Merge tag 'clk-imx-fixes-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes

Pull i.MX clock fixes for 4.16 from Shawn Guo:

 - Update i.MX5 clock driver to register UART4/5 clock only on i.MX50
   and i.MX53.  It fixes a kernel warning seen on i.MX53, caused by
   commit 59dc3d8c8673 ("clk: imx51: uart4, uart5 gates only exist on
   imx50, imx53").

* tag 'clk-imx-fixes-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx51-imx53: Fix UART4/5 registration on i.MX50 and i.MX53

1 files changed, 17 insertions, 3 deletions

diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c
index c864992e6983..caa8bd40692c 100644
--- a/drivers/clk/imx/clk-imx51-imx53.c
+++ b/drivers/clk/imx/clk-imx51-imx53.c
@@ -131,7 +131,17 @@ static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_
 static struct clk *clk[IMX5_CLK_END];
 static struct clk_onecell_data clk_data;
 
-static struct clk ** const uart_clks[] __initconst = {
+static struct clk ** const uart_clks_mx51[] __initconst = {
+        &clk[IMX5_CLK_UART1_IPG_GATE],
+        &clk[IMX5_CLK_UART1_PER_GATE],
+        &clk[IMX5_CLK_UART2_IPG_GATE],
+        &clk[IMX5_CLK_UART2_PER_GATE],
+        &clk[IMX5_CLK_UART3_IPG_GATE],
+        &clk[IMX5_CLK_UART3_PER_GATE],
+        NULL
+};
+
+static struct clk ** const uart_clks_mx50_mx53[] __initconst = {
         &clk[IMX5_CLK_UART1_IPG_GATE],
         &clk[IMX5_CLK_UART1_PER_GATE],
         &clk[IMX5_CLK_UART2_IPG_GATE],
@@ -321,8 +331,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
         clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
         clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
         clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
-
-        imx_register_uart_clocks(uart_clks);
 }
 
 static void __init mx50_clocks_init(struct device_node *np)
@@ -388,6 +396,8 @@ static void __init mx50_clocks_init(struct device_node *np)
 
         r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
         clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
+
+        imx_register_uart_clocks(uart_clks_mx50_mx53);
 }
 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
 
@@ -477,6 +487,8 @@ static void __init mx51_clocks_init(struct device_node *np)
         val = readl(MXC_CCM_CLPCR);
         val |= 1 << 23;
         writel(val, MXC_CCM_CLPCR);
+
+        imx_register_uart_clocks(uart_clks_mx51);
 }
 CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
 
@@ -606,5 +618,7 @@ static void __init mx53_clocks_init(struct device_node *np)
 
         r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
         clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
+
+        imx_register_uart_clocks(uart_clks_mx50_mx53);
 }
 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);