aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2017-12-11 20:05:33 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2017-12-11 20:05:33 -0500
commita83cb7e6ada140f8b932c223511f1063c4150870 (patch)
treeaad8f7095b9fe2dc8194a17c46b46c10cef3febf
parentbfb529ee790f5c3b1efd892d48c0b8d1449849f4 (diff)
parent2dc0b46b5ea30f169b0b272253ea846a5a281731 (diff)
Merge branch 'for-4.15-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata fixes from Tejun Heo: "Nothing too interesting. David Milburn improved a corner case misbehavior during hotplug. Other than that, minor driver-specific fixes" * 'for-4.15-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: libata: sata_down_spd_limit should return if driver has not recorded sstatus speed ahci: mtk: Change driver name to ahci-mtk ahci: qoriq: refine port register configuration pata_pdc2027x : make pdc2027x_*_timing structures const pata_pdc2027x: Remove unnecessary error check ata: mediatek: Fix typo in module description
-rw-r--r--drivers/ata/ahci_mtk.c6
-rw-r--r--drivers/ata/ahci_qoriq.c12
-rw-r--r--drivers/ata/libata-core.c12
-rw-r--r--drivers/ata/pata_pdc2027x.c16
4 files changed, 30 insertions, 16 deletions
diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c
index 80854f71559a..0ae6971c2a4c 100644
--- a/drivers/ata/ahci_mtk.c
+++ b/drivers/ata/ahci_mtk.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * MeidaTek AHCI SATA driver 2 * MediaTek AHCI SATA driver
3 * 3 *
4 * Copyright (c) 2017 MediaTek Inc. 4 * Copyright (c) 2017 MediaTek Inc.
5 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Author: Ryder Lee <ryder.lee@mediatek.com>
@@ -25,7 +25,7 @@
25#include <linux/reset.h> 25#include <linux/reset.h>
26#include "ahci.h" 26#include "ahci.h"
27 27
28#define DRV_NAME "ahci" 28#define DRV_NAME "ahci-mtk"
29 29
30#define SYS_CFG 0x14 30#define SYS_CFG 0x14
31#define SYS_CFG_SATA_MSK GENMASK(31, 30) 31#define SYS_CFG_SATA_MSK GENMASK(31, 30)
@@ -192,5 +192,5 @@ static struct platform_driver mtk_ahci_driver = {
192}; 192};
193module_platform_driver(mtk_ahci_driver); 193module_platform_driver(mtk_ahci_driver);
194 194
195MODULE_DESCRIPTION("MeidaTek SATA AHCI Driver"); 195MODULE_DESCRIPTION("MediaTek SATA AHCI Driver");
196MODULE_LICENSE("GPL v2"); 196MODULE_LICENSE("GPL v2");
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index b6b0bf76dfc7..2685f28160f7 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -35,6 +35,8 @@
35 35
36/* port register default value */ 36/* port register default value */
37#define AHCI_PORT_PHY_1_CFG 0xa003fffe 37#define AHCI_PORT_PHY_1_CFG 0xa003fffe
38#define AHCI_PORT_PHY2_CFG 0x28184d1f
39#define AHCI_PORT_PHY3_CFG 0x0e081509
38#define AHCI_PORT_TRANS_CFG 0x08000029 40#define AHCI_PORT_TRANS_CFG 0x08000029
39#define AHCI_PORT_AXICC_CFG 0x3fffffff 41#define AHCI_PORT_AXICC_CFG 0x3fffffff
40 42
@@ -183,6 +185,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
183 writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, 185 writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
184 qpriv->ecc_addr); 186 qpriv->ecc_addr);
185 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 187 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
188 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
189 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
186 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 190 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
187 if (qpriv->is_dmacoherent) 191 if (qpriv->is_dmacoherent)
188 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); 192 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -190,6 +194,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
190 194
191 case AHCI_LS2080A: 195 case AHCI_LS2080A:
192 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 196 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
197 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
198 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
193 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 199 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
194 if (qpriv->is_dmacoherent) 200 if (qpriv->is_dmacoherent)
195 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); 201 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -201,6 +207,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
201 writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, 207 writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
202 qpriv->ecc_addr); 208 qpriv->ecc_addr);
203 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 209 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
210 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
211 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
204 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 212 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
205 if (qpriv->is_dmacoherent) 213 if (qpriv->is_dmacoherent)
206 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); 214 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -212,6 +220,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
212 writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A, 220 writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
213 qpriv->ecc_addr); 221 qpriv->ecc_addr);
214 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 222 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
223 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
224 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
215 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 225 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
216 if (qpriv->is_dmacoherent) 226 if (qpriv->is_dmacoherent)
217 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); 227 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -219,6 +229,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
219 229
220 case AHCI_LS2088A: 230 case AHCI_LS2088A:
221 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 231 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
232 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
233 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
222 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 234 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
223 if (qpriv->is_dmacoherent) 235 if (qpriv->is_dmacoherent)
224 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); 236 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 2a882929de4a..8193b38a1cae 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -3082,13 +3082,19 @@ int sata_down_spd_limit(struct ata_link *link, u32 spd_limit)
3082 bit = fls(mask) - 1; 3082 bit = fls(mask) - 1;
3083 mask &= ~(1 << bit); 3083 mask &= ~(1 << bit);
3084 3084
3085 /* Mask off all speeds higher than or equal to the current 3085 /*
3086 * one. Force 1.5Gbps if current SPD is not available. 3086 * Mask off all speeds higher than or equal to the current one. At
3087 * this point, if current SPD is not available and we previously
3088 * recorded the link speed from SStatus, the driver has already
3089 * masked off the highest bit so mask should already be 1 or 0.
3090 * Otherwise, we should not force 1.5Gbps on a link where we have
3091 * not previously recorded speed from SStatus. Just return in this
3092 * case.
3087 */ 3093 */
3088 if (spd > 1) 3094 if (spd > 1)
3089 mask &= (1 << (spd - 1)) - 1; 3095 mask &= (1 << (spd - 1)) - 1;
3090 else 3096 else
3091 mask &= 1; 3097 return -EINVAL;
3092 3098
3093 /* were we already at the bottom? */ 3099 /* were we already at the bottom? */
3094 if (!mask) 3100 if (!mask)
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index ffd8d33c6e0f..6db2e34bd52f 100644
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -82,7 +82,7 @@ static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed
82 * is issued to the device. However, if the controller clock is 133MHz, 82 * is issued to the device. However, if the controller clock is 133MHz,
83 * the following tables must be used. 83 * the following tables must be used.
84 */ 84 */
85static struct pdc2027x_pio_timing { 85static const struct pdc2027x_pio_timing {
86 u8 value0, value1, value2; 86 u8 value0, value1, value2;
87} pdc2027x_pio_timing_tbl[] = { 87} pdc2027x_pio_timing_tbl[] = {
88 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ 88 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
@@ -92,7 +92,7 @@ static struct pdc2027x_pio_timing {
92 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ 92 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
93}; 93};
94 94
95static struct pdc2027x_mdma_timing { 95static const struct pdc2027x_mdma_timing {
96 u8 value0, value1; 96 u8 value0, value1;
97} pdc2027x_mdma_timing_tbl[] = { 97} pdc2027x_mdma_timing_tbl[] = {
98 { 0xdf, 0x5f }, /* MDMA mode 0 */ 98 { 0xdf, 0x5f }, /* MDMA mode 0 */
@@ -100,7 +100,7 @@ static struct pdc2027x_mdma_timing {
100 { 0x69, 0x25 }, /* MDMA mode 2 */ 100 { 0x69, 0x25 }, /* MDMA mode 2 */
101}; 101};
102 102
103static struct pdc2027x_udma_timing { 103static const struct pdc2027x_udma_timing {
104 u8 value0, value1, value2; 104 u8 value0, value1, value2;
105} pdc2027x_udma_timing_tbl[] = { 105} pdc2027x_udma_timing_tbl[] = {
106 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ 106 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
@@ -649,7 +649,7 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
649 * @host: target ATA host 649 * @host: target ATA host
650 * @board_idx: board identifier 650 * @board_idx: board identifier
651 */ 651 */
652static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx) 652static void pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
653{ 653{
654 long pll_clock; 654 long pll_clock;
655 655
@@ -665,8 +665,6 @@ static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
665 665
666 /* Adjust PLL control register */ 666 /* Adjust PLL control register */
667 pdc_adjust_pll(host, pll_clock, board_idx); 667 pdc_adjust_pll(host, pll_clock, board_idx);
668
669 return 0;
670} 668}
671 669
672/** 670/**
@@ -753,8 +751,7 @@ static int pdc2027x_init_one(struct pci_dev *pdev,
753 //pci_enable_intx(pdev); 751 //pci_enable_intx(pdev);
754 752
755 /* initialize adapter */ 753 /* initialize adapter */
756 if (pdc_hardware_init(host, board_idx) != 0) 754 pdc_hardware_init(host, board_idx);
757 return -EIO;
758 755
759 pci_set_master(pdev); 756 pci_set_master(pdev);
760 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 757 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
@@ -778,8 +775,7 @@ static int pdc2027x_reinit_one(struct pci_dev *pdev)
778 else 775 else
779 board_idx = PDC_UDMA_133; 776 board_idx = PDC_UDMA_133;
780 777
781 if (pdc_hardware_init(host, board_idx)) 778 pdc_hardware_init(host, board_idx);
782 return -EIO;
783 779
784 ata_host_resume(host); 780 ata_host_resume(host);
785 return 0; 781 return 0;