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authorRussell King <rmk+kernel@armlinux.org.uk>2018-02-27 11:01:57 -0500
committerGregory CLEMENT <gregory.clement@bootlin.com>2018-03-05 11:33:42 -0500
commita83aeb3836b1cd65770b20eafefbef7467972fa2 (patch)
tree548590248138484d17ebf38dc0f8cff93fdd9445
parente662e70fa41985d258ba82f47bb248d2433c52e0 (diff)
ARM: dts: armada388-clearfog: increase speed of i2c0 to 400kHz
All the devices on I2C0 support fast mode, so increase the bus speed to match. The Armada 388 is known to have a timing issue when in standard mode, which we believe causes the ficticious device at 0x64 to appear. [gregory.clement@bootlin.com: Note that since the commit fbffee74986c ("ARM: dts: Fix I2C repeated start issue on Armada-38x") in 4.14, the timing issue is managed for the Armada 38x SoCs.] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
-rw-r--r--arch/arm/boot/dts/armada-388-clearfog.dtsi7
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 68acfc968706..0e3b1f140e6d 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -143,8 +143,7 @@
143}; 143};
144 144
145&i2c0 { 145&i2c0 {
146 /* Is there anything on this? */ 146 clock-frequency = <400000>;
147 clock-frequency = <100000>;
148 pinctrl-0 = <&i2c0_pins>; 147 pinctrl-0 = <&i2c0_pins>;
149 pinctrl-names = "default"; 148 pinctrl-names = "default";
150 status = "okay"; 149 status = "okay";
@@ -239,13 +238,11 @@
239 }; 238 };
240 }; 239 };
241 240
242 /* The MCP3021 is 100kHz clock only */ 241 /* The MCP3021 supports standard and fast modes */
243 mikrobus_adc: mcp3021@4c { 242 mikrobus_adc: mcp3021@4c {
244 compatible = "microchip,mcp3021"; 243 compatible = "microchip,mcp3021";
245 reg = <0x4c>; 244 reg = <0x4c>;
246 }; 245 };
247
248 /* Also something at 0x64 */
249}; 246};
250 247
251&i2c1 { 248&i2c1 {