ARM: dts: r8a7793: Add SYSC PM Domains

Add a device node for the System Controller.
Hook up the first Cortex-A15 CPU core and the Cortex-A15 L2 cache/SCU to
their respective PM Domains.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

1 files changed, 9 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 6186179fd66d..53e235e3279d 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/r8a7793-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7793-sysc.h>
 
 / {
         compatible = "renesas,r8a7793";
@@ -43,6 +44,7 @@
                         voltage-tolerance = <1>; /* 1% */
                         clocks = <&cpg_clocks R8A7793_CLK_Z>;
                         clock-latency = <300000>; /* 300 us */
+                        power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
 
                         /* kHz - uV - OPPs unknown yet */
                         operating-points = <1500000 1000000>,
@@ -76,6 +78,7 @@
 
         L2_CA15: cache-controller@0 {
                 compatible = "cache";
+                power-domains = <&sysc R8A7793_PD_CA15_SCU>;
                 cache-unified;
                 cache-level = <2>;
         };
@@ -1223,6 +1226,12 @@
                 };
         };
 
+        sysc: system-controller@e6180000 {
+                compatible = "renesas,r8a7793-sysc";
+                reg = <0 0xe6180000 0 0x0200>;
+                #power-domain-cells = <1>;
+        };
+
         ipmmu_sy0: mmu@e6280000 {
                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
                 reg = <0 0xe6280000 0 0x1000>;