aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMurali Karicheri <m-karicheri2@ti.com>2017-01-04 14:32:30 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-01-10 09:43:24 -0500
commita782b5f986c3fa1cfa7f2b57941200c6a5809242 (patch)
tree6daa542c4e59cd3900912bb109726c00f5ec11f8
parent7ce7d89f48834cefece7804d38fc5d85382edf77 (diff)
PCI: designware: Check for iATU unroll only on platforms that use ATU
Previously we checked for iATU unroll support by reading PCIE_ATU_VIEWPORT even on platforms, e.g., Keystone, that do not have ATU ports. This can cause bad behavior such as asynchronous external aborts: OF: PCI: MEM 0x60000000..0x6fffffff -> 0x60000000 Unhandled fault: asynchronous external abort (0x1211) at 0x00000000 pgd = c0003000 [00000000] *pgd=80000800004003, *pmd=00000000 Internal error: : 1211 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-00009-g6ff59d2-dirty #7 Hardware name: Keystone task: eb878000 task.stack: eb866000 PC is at dw_pcie_setup_rc+0x24/0x380 LR is at ks_pcie_host_init+0x10/0x170 Move the dw_pcie_iatu_unroll_enabled() check so we only call it on platforms that do not use the ATU. These platforms supply their own ->rd_other_conf() and ->wr_other_conf() methods. [bhelgaas: changelog] Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature") Fixes: 416379f9ebde ("PCI: designware: Check for iATU unroll support after initializing host") Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Joao Pinto <jpinto@synopsys.com> CC: stable@vger.kernel.org # v4.9+
-rw-r--r--drivers/pci/host/pcie-designware.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index bed19994c1e9..af8f6e92e885 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -807,11 +807,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
807{ 807{
808 u32 val; 808 u32 val;
809 809
810 /* get iATU unroll support */
811 pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
812 dev_dbg(pp->dev, "iATU unroll: %s\n",
813 pp->iatu_unroll_enabled ? "enabled" : "disabled");
814
815 /* set the number of lanes */ 810 /* set the number of lanes */
816 val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL); 811 val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);
817 val &= ~PORT_LINK_MODE_MASK; 812 val &= ~PORT_LINK_MODE_MASK;
@@ -882,6 +877,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
882 * we should not program the ATU here. 877 * we should not program the ATU here.
883 */ 878 */
884 if (!pp->ops->rd_other_conf) { 879 if (!pp->ops->rd_other_conf) {
880 /* get iATU unroll support */
881 pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
882 dev_dbg(pp->dev, "iATU unroll: %s\n",
883 pp->iatu_unroll_enabled ? "enabled" : "disabled");
884
885 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, 885 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
886 PCIE_ATU_TYPE_MEM, pp->mem_base, 886 PCIE_ATU_TYPE_MEM, pp->mem_base,
887 pp->mem_bus_addr, pp->mem_size); 887 pp->mem_bus_addr, pp->mem_size);