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authorFabio Estevam <fabio.estevam@nxp.com>2016-08-15 12:47:34 -0400
committerShawn Guo <shawnguo@kernel.org>2016-08-17 10:34:34 -0400
commita7311c0c9a338d18f4a6d21dfad34c66053c9225 (patch)
tree738aff13fc08a1ce07006736810d795243efa3d6
parent44e645faffa7428502712cc6062a92a07ae09679 (diff)
ARM: dts: imx7s-warp: Use WDOG_B pin reset
imx7s-warpd has WDOG1_B pin connected to the PMIC. Pass the 'fsl,ext-reset-output' property so that the watchdog can trigger a system POR reset via the PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm/boot/dts/imx7s-warp.dts13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index 4d4959c856a9..92d9c8570716 100644
--- a/arch/arm/boot/dts/imx7s-warp.dts
+++ b/arch/arm/boot/dts/imx7s-warp.dts
@@ -257,6 +257,13 @@
257 status = "okay"; 257 status = "okay";
258}; 258};
259 259
260&wdog1 {
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_wdog>;
263 fsl,ext-reset-output;
264 status = "okay";
265};
266
260&iomuxc { 267&iomuxc {
261 pinctrl_brcm_reg: brcmreggrp { 268 pinctrl_brcm_reg: brcmreggrp {
262 fsl,pins = < 269 fsl,pins = <
@@ -354,4 +361,10 @@
354 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b 361 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
355 >; 362 >;
356 }; 363 };
364
365 pinctrl_wdog: wdoggrp {
366 fsl,pins = <
367 MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
368 >;
369 };
357}; 370};