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authorEmily Deng <Emily.Deng@amd.com>2016-08-07 23:37:50 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-08-08 14:33:28 -0400
commita6be7570518f85ce94ca9d6540543e00725828d3 (patch)
treed817a1b9d03ccddbcbdea5a44e50c33d386fb378
parente443059d0f41fcc07f0fb6b3b8ae96dc3d2364c7 (diff)
drm/amdgpu: Set ip_blocks according variable amdgpu_virtual_display.
For virtual display feature, if user set the option "amdgpu.virtual_display=1" when load amdgpu.ko. Then need to set the ip_blocks with virtual display ip blocks. And when enable virtual display, the amdgpu_dal need to be set to zero. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c77
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c84
3 files changed, 113 insertions, 50 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 72d5d094965d..4bf9bd96a46e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1185,6 +1185,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
1185{ 1185{
1186 int i, r; 1186 int i, r;
1187 1187
1188 DRM_INFO("virtual display enabled:%d\n", amdgpu_virtual_display);
1189
1188 switch (adev->asic_type) { 1190 switch (adev->asic_type) {
1189 case CHIP_TOPAZ: 1191 case CHIP_TOPAZ:
1190 case CHIP_TONGA: 1192 case CHIP_TONGA:
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index edcc14287d2d..15200b1b77d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2323,30 +2323,59 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] =
2323 2323
2324int cik_set_ip_blocks(struct amdgpu_device *adev) 2324int cik_set_ip_blocks(struct amdgpu_device *adev)
2325{ 2325{
2326 switch (adev->asic_type) { 2326 if (amdgpu_virtual_display) {
2327 case CHIP_BONAIRE: 2327 adev->mode_info.vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
2328 adev->ip_blocks = bonaire_ip_blocks; 2328 switch (adev->asic_type) {
2329 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks); 2329 case CHIP_BONAIRE:
2330 break; 2330 adev->ip_blocks = bonaire_ip_blocks_vd;
2331 case CHIP_HAWAII: 2331 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_vd);
2332 adev->ip_blocks = hawaii_ip_blocks; 2332 break;
2333 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks); 2333 case CHIP_HAWAII:
2334 break; 2334 adev->ip_blocks = hawaii_ip_blocks_vd;
2335 case CHIP_KAVERI: 2335 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_vd);
2336 adev->ip_blocks = kaveri_ip_blocks; 2336 break;
2337 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks); 2337 case CHIP_KAVERI:
2338 break; 2338 adev->ip_blocks = kaveri_ip_blocks_vd;
2339 case CHIP_KABINI: 2339 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks_vd);
2340 adev->ip_blocks = kabini_ip_blocks; 2340 break;
2341 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks); 2341 case CHIP_KABINI:
2342 break; 2342 adev->ip_blocks = kabini_ip_blocks_vd;
2343 case CHIP_MULLINS: 2343 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks_vd);
2344 adev->ip_blocks = mullins_ip_blocks; 2344 break;
2345 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks); 2345 case CHIP_MULLINS:
2346 break; 2346 adev->ip_blocks = mullins_ip_blocks_vd;
2347 default: 2347 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks_vd);
2348 /* FIXME: not supported yet */ 2348 break;
2349 return -EINVAL; 2349 default:
2350 /* FIXME: not supported yet */
2351 return -EINVAL;
2352 }
2353 } else {
2354 switch (adev->asic_type) {
2355 case CHIP_BONAIRE:
2356 adev->ip_blocks = bonaire_ip_blocks;
2357 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
2358 break;
2359 case CHIP_HAWAII:
2360 adev->ip_blocks = hawaii_ip_blocks;
2361 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
2362 break;
2363 case CHIP_KAVERI:
2364 adev->ip_blocks = kaveri_ip_blocks;
2365 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
2366 break;
2367 case CHIP_KABINI:
2368 adev->ip_blocks = kabini_ip_blocks;
2369 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
2370 break;
2371 case CHIP_MULLINS:
2372 adev->ip_blocks = mullins_ip_blocks;
2373 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
2374 break;
2375 default:
2376 /* FIXME: not supported yet */
2377 return -EINVAL;
2378 }
2350 } 2379 }
2351 2380
2352 return 0; 2381 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index ff78b5a36143..064291771d79 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1387,32 +1387,64 @@ static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] =
1387 1387
1388int vi_set_ip_blocks(struct amdgpu_device *adev) 1388int vi_set_ip_blocks(struct amdgpu_device *adev)
1389{ 1389{
1390 switch (adev->asic_type) { 1390 if (amdgpu_virtual_display) {
1391 case CHIP_TOPAZ: 1391 adev->mode_info.vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
1392 adev->ip_blocks = topaz_ip_blocks; 1392 switch (adev->asic_type) {
1393 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks); 1393 case CHIP_TOPAZ:
1394 break; 1394 adev->ip_blocks = topaz_ip_blocks;
1395 case CHIP_FIJI: 1395 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1396 adev->ip_blocks = fiji_ip_blocks; 1396 break;
1397 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks); 1397 case CHIP_FIJI:
1398 break; 1398 adev->ip_blocks = fiji_ip_blocks_vd;
1399 case CHIP_TONGA: 1399 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_vd);
1400 adev->ip_blocks = tonga_ip_blocks; 1400 break;
1401 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); 1401 case CHIP_TONGA:
1402 break; 1402 adev->ip_blocks = tonga_ip_blocks_vd;
1403 case CHIP_POLARIS11: 1403 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_vd);
1404 case CHIP_POLARIS10: 1404 break;
1405 adev->ip_blocks = polaris11_ip_blocks; 1405 case CHIP_POLARIS11:
1406 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks); 1406 case CHIP_POLARIS10:
1407 break; 1407 adev->ip_blocks = polaris11_ip_blocks_vd;
1408 case CHIP_CARRIZO: 1408 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_vd);
1409 case CHIP_STONEY: 1409 break;
1410 adev->ip_blocks = cz_ip_blocks; 1410
1411 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks); 1411 case CHIP_CARRIZO:
1412 break; 1412 case CHIP_STONEY:
1413 default: 1413 adev->ip_blocks = cz_ip_blocks_vd;
1414 /* FIXME: not supported yet */ 1414 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_vd);
1415 return -EINVAL; 1415 break;
1416 default:
1417 /* FIXME: not supported yet */
1418 return -EINVAL;
1419 }
1420 } else {
1421 switch (adev->asic_type) {
1422 case CHIP_TOPAZ:
1423 adev->ip_blocks = topaz_ip_blocks;
1424 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1425 break;
1426 case CHIP_FIJI:
1427 adev->ip_blocks = fiji_ip_blocks;
1428 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
1429 break;
1430 case CHIP_TONGA:
1431 adev->ip_blocks = tonga_ip_blocks;
1432 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1433 break;
1434 case CHIP_POLARIS11:
1435 case CHIP_POLARIS10:
1436 adev->ip_blocks = polaris11_ip_blocks;
1437 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
1438 break;
1439 case CHIP_CARRIZO:
1440 case CHIP_STONEY:
1441 adev->ip_blocks = cz_ip_blocks;
1442 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1443 break;
1444 default:
1445 /* FIXME: not supported yet */
1446 return -EINVAL;
1447 }
1416 } 1448 }
1417 1449
1418 return 0; 1450 return 0;