diff options
author | Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> | 2017-11-10 08:58:49 -0500 |
---|---|---|
committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-11-28 04:43:12 -0500 |
commit | a678abfee7ab5d2dcfc2079158ec799c7f4cf204 (patch) | |
tree | 5ddbb66559dcdbea5176e6e2f74248b4ea753cec | |
parent | 3f35221842305e82494e10fcfc1f5750c8bc682a (diff) |
pinctrl: sh-pfc: r8a7795: Add CAN support
This patch adds CAN[0-1] pinmux support for R-Car H3 ES2.0. The pin
config is identical to H3 ES1.*.
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index d1cec6d12e81..59249a990cef 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c | |||
@@ -1781,6 +1781,38 @@ static const unsigned int avb_avtp_capture_b_mux[] = { | |||
1781 | AVB_AVTP_CAPTURE_B_MARK, | 1781 | AVB_AVTP_CAPTURE_B_MARK, |
1782 | }; | 1782 | }; |
1783 | 1783 | ||
1784 | /* - CAN ------------------------------------------------------------------ */ | ||
1785 | static const unsigned int can0_data_a_pins[] = { | ||
1786 | /* TX, RX */ | ||
1787 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), | ||
1788 | }; | ||
1789 | static const unsigned int can0_data_a_mux[] = { | ||
1790 | CAN0_TX_A_MARK, CAN0_RX_A_MARK, | ||
1791 | }; | ||
1792 | static const unsigned int can0_data_b_pins[] = { | ||
1793 | /* TX, RX */ | ||
1794 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
1795 | }; | ||
1796 | static const unsigned int can0_data_b_mux[] = { | ||
1797 | CAN0_TX_B_MARK, CAN0_RX_B_MARK, | ||
1798 | }; | ||
1799 | static const unsigned int can1_data_pins[] = { | ||
1800 | /* TX, RX */ | ||
1801 | RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), | ||
1802 | }; | ||
1803 | static const unsigned int can1_data_mux[] = { | ||
1804 | CAN1_TX_MARK, CAN1_RX_MARK, | ||
1805 | }; | ||
1806 | |||
1807 | /* - CAN Clock -------------------------------------------------------------- */ | ||
1808 | static const unsigned int can_clk_pins[] = { | ||
1809 | /* CLK */ | ||
1810 | RCAR_GP_PIN(1, 25), | ||
1811 | }; | ||
1812 | static const unsigned int can_clk_mux[] = { | ||
1813 | CAN_CLK_MARK, | ||
1814 | }; | ||
1815 | |||
1784 | /* - DRIF0 --------------------------------------------------------------- */ | 1816 | /* - DRIF0 --------------------------------------------------------------- */ |
1785 | static const unsigned int drif0_ctrl_a_pins[] = { | 1817 | static const unsigned int drif0_ctrl_a_pins[] = { |
1786 | /* CLK, SYNC */ | 1818 | /* CLK, SYNC */ |
@@ -3843,6 +3875,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { | |||
3843 | SH_PFC_PIN_GROUP(avb_avtp_capture_a), | 3875 | SH_PFC_PIN_GROUP(avb_avtp_capture_a), |
3844 | SH_PFC_PIN_GROUP(avb_avtp_match_b), | 3876 | SH_PFC_PIN_GROUP(avb_avtp_match_b), |
3845 | SH_PFC_PIN_GROUP(avb_avtp_capture_b), | 3877 | SH_PFC_PIN_GROUP(avb_avtp_capture_b), |
3878 | SH_PFC_PIN_GROUP(can0_data_a), | ||
3879 | SH_PFC_PIN_GROUP(can0_data_b), | ||
3880 | SH_PFC_PIN_GROUP(can1_data), | ||
3881 | SH_PFC_PIN_GROUP(can_clk), | ||
3846 | SH_PFC_PIN_GROUP(drif0_ctrl_a), | 3882 | SH_PFC_PIN_GROUP(drif0_ctrl_a), |
3847 | SH_PFC_PIN_GROUP(drif0_data0_a), | 3883 | SH_PFC_PIN_GROUP(drif0_data0_a), |
3848 | SH_PFC_PIN_GROUP(drif0_data1_a), | 3884 | SH_PFC_PIN_GROUP(drif0_data1_a), |
@@ -4154,6 +4190,19 @@ static const char * const avb_groups[] = { | |||
4154 | "avb_avtp_capture_b", | 4190 | "avb_avtp_capture_b", |
4155 | }; | 4191 | }; |
4156 | 4192 | ||
4193 | static const char * const can0_groups[] = { | ||
4194 | "can0_data_a", | ||
4195 | "can0_data_b", | ||
4196 | }; | ||
4197 | |||
4198 | static const char * const can1_groups[] = { | ||
4199 | "can1_data", | ||
4200 | }; | ||
4201 | |||
4202 | static const char * const can_clk_groups[] = { | ||
4203 | "can_clk", | ||
4204 | }; | ||
4205 | |||
4157 | static const char * const drif0_groups[] = { | 4206 | static const char * const drif0_groups[] = { |
4158 | "drif0_ctrl_a", | 4207 | "drif0_ctrl_a", |
4159 | "drif0_data0_a", | 4208 | "drif0_data0_a", |
@@ -4559,6 +4608,9 @@ static const char * const usb30_groups[] = { | |||
4559 | static const struct sh_pfc_function pinmux_functions[] = { | 4608 | static const struct sh_pfc_function pinmux_functions[] = { |
4560 | SH_PFC_FUNCTION(audio_clk), | 4609 | SH_PFC_FUNCTION(audio_clk), |
4561 | SH_PFC_FUNCTION(avb), | 4610 | SH_PFC_FUNCTION(avb), |
4611 | SH_PFC_FUNCTION(can0), | ||
4612 | SH_PFC_FUNCTION(can1), | ||
4613 | SH_PFC_FUNCTION(can_clk), | ||
4562 | SH_PFC_FUNCTION(drif0), | 4614 | SH_PFC_FUNCTION(drif0), |
4563 | SH_PFC_FUNCTION(drif1), | 4615 | SH_PFC_FUNCTION(drif1), |
4564 | SH_PFC_FUNCTION(drif2), | 4616 | SH_PFC_FUNCTION(drif2), |