MIPS: ralink: Fix booting on MT7621

Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621 has
not been able to boot.

This commit caused mips_cm_probe() to be called before
mt7621.c::proc_soc_init().

prom_soc_init() has a comment explaining that mips_cm_probe() "wipes out
the bootloader config" and means that configuration registers are no
longer available. It has some code to re-enable this config.

Before this re-enable code is run, the sysc register cannot be read, so
when SYSC_REG_CHIP_NAME0 is read, a garbage value is returned and
panic() is called.

If we move the config-repair code to the top of prom_soc_init(), the
registers can be read and boot can proceed.

Very occasionally, the first register read after the reconfiguration
returns garbage, so add a call to __sync().

Fixes: 3af5a67c86a3 ("MIPS: Fix early CM probing")
Signed-off-by: NeilBrown <neil@brown.name>
Reviewed-by: Matt Redfearn <matt.redfearn@mips.com>
Cc: John Crispin <john@phrozen.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.5+
Patchwork: https://patchwork.linux-mips.org/patch/18859/
Signed-off-by: James Hogan <jhogan@kernel.org>

1 files changed, 22 insertions, 20 deletions

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index 1b274742077d..d2718de60b9b 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -170,6 +170,28 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
         u32 n1;
         u32 rev;
 
+        /* Early detection of CMP support */
+        mips_cm_probe();
+        mips_cpc_probe();
+
+        if (mips_cps_numiocu(0)) {
+                /*
+                 * mips_cm_probe() wipes out bootloader
+                 * config for CM regions and we have to configure them
+                 * again. This SoC cannot talk to pamlbus devices
+                 * witout proper iocu region set up.
+                 *
+                 * FIXME: it would be better to do this with values
+                 * from DT, but we need this very early because
+                 * without this we cannot talk to pretty much anything
+                 * including serial.
+                 */
+                write_gcr_reg0_base(MT7621_PALMBUS_BASE);
+                write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
+                                    CM_GCR_REGn_MASK_CMTGT_IOCU0);
+                __sync();
+        }
+
         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 
@@ -194,26 +216,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
         rt2880_pinmux_data = mt7621_pinmux_data;
 
-        /* Early detection of CMP support */
-        mips_cm_probe();
-        mips_cpc_probe();
-
-        if (mips_cps_numiocu(0)) {
-                /*
-                 * mips_cm_probe() wipes out bootloader
-                 * config for CM regions and we have to configure them
-                 * again. This SoC cannot talk to pamlbus devices
-                 * witout proper iocu region set up.
-                 *
-                 * FIXME: it would be better to do this with values
-                 * from DT, but we need this very early because
-                 * without this we cannot talk to pretty much anything
-                 * including serial.
-                 */
-                write_gcr_reg0_base(MT7621_PALMBUS_BASE);
-                write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
-                                    CM_GCR_REGn_MASK_CMTGT_IOCU0);
-        }
 
         if (!register_cps_smp_ops())
                 return;