aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2014-10-28 12:25:01 -0400
committerMark Brown <broonie@kernel.org>2014-10-28 18:40:38 -0400
commita5c2db964d3eb26b41bd7abc1b13486f732b3aa2 (patch)
treec1ac9e5491f7c46ca33f56fba0fed223d35aee7b
parentb7a40242c82cd73cfcea305f23e67d068dd8401a (diff)
spi: dw-mid: refactor to use helpers
This patch splits few helpers, namely dw_spi_dma_prepare_rx(), dw_spi_dma_prepare_tx(), and dw_spi_dma_setup() which will be useful for the consequent improvements. There is no functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--drivers/spi/spi-dw-mid.c69
1 files changed, 48 insertions, 21 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 46c6d58e1fda..c8319ab0bbdf 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -111,28 +111,11 @@ static void dw_spi_dma_done(void *arg)
111 dw_spi_xfer_done(dws); 111 dw_spi_xfer_done(dws);
112} 112}
113 113
114static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change) 114static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
115{ 115{
116 struct dma_async_tx_descriptor *txdesc, *rxdesc; 116 struct dma_slave_config txconf;
117 struct dma_slave_config txconf, rxconf; 117 struct dma_async_tx_descriptor *txdesc;
118 u16 dma_ctrl = 0;
119
120 /* 1. setup DMA related registers */
121 if (cs_change) {
122 spi_enable_chip(dws, 0);
123 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
124 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
125 if (dws->tx_dma)
126 dma_ctrl |= SPI_DMA_TDMAE;
127 if (dws->rx_dma)
128 dma_ctrl |= SPI_DMA_RDMAE;
129 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
130 spi_enable_chip(dws, 1);
131 }
132 118
133 dws->dma_chan_done = 0;
134
135 /* 2. Prepare the TX dma transfer */
136 txconf.direction = DMA_MEM_TO_DEV; 119 txconf.direction = DMA_MEM_TO_DEV;
137 txconf.dst_addr = dws->dma_addr; 120 txconf.dst_addr = dws->dma_addr;
138 txconf.dst_maxburst = LNW_DMA_MSIZE_16; 121 txconf.dst_maxburst = LNW_DMA_MSIZE_16;
@@ -154,7 +137,14 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
154 txdesc->callback = dw_spi_dma_done; 137 txdesc->callback = dw_spi_dma_done;
155 txdesc->callback_param = dws; 138 txdesc->callback_param = dws;
156 139
157 /* 3. Prepare the RX dma transfer */ 140 return txdesc;
141}
142
143static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
144{
145 struct dma_slave_config rxconf;
146 struct dma_async_tx_descriptor *rxdesc;
147
158 rxconf.direction = DMA_DEV_TO_MEM; 148 rxconf.direction = DMA_DEV_TO_MEM;
159 rxconf.src_addr = dws->dma_addr; 149 rxconf.src_addr = dws->dma_addr;
160 rxconf.src_maxburst = LNW_DMA_MSIZE_16; 150 rxconf.src_maxburst = LNW_DMA_MSIZE_16;
@@ -176,6 +166,43 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
176 rxdesc->callback = dw_spi_dma_done; 166 rxdesc->callback = dw_spi_dma_done;
177 rxdesc->callback_param = dws; 167 rxdesc->callback_param = dws;
178 168
169 return rxdesc;
170}
171
172static void dw_spi_dma_setup(struct dw_spi *dws)
173{
174 u16 dma_ctrl = 0;
175
176 spi_enable_chip(dws, 0);
177
178 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
179 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
180
181 if (dws->tx_dma)
182 dma_ctrl |= SPI_DMA_TDMAE;
183 if (dws->rx_dma)
184 dma_ctrl |= SPI_DMA_RDMAE;
185 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
186
187 spi_enable_chip(dws, 1);
188}
189
190static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
191{
192 struct dma_async_tx_descriptor *txdesc, *rxdesc;
193
194 /* 1. setup DMA related registers */
195 if (cs_change)
196 dw_spi_dma_setup(dws);
197
198 dws->dma_chan_done = 0;
199
200 /* 2. Prepare the TX dma transfer */
201 txdesc = dw_spi_dma_prepare_tx(dws);
202
203 /* 3. Prepare the RX dma transfer */
204 rxdesc = dw_spi_dma_prepare_rx(dws);
205
179 /* rx must be started before tx due to spi instinct */ 206 /* rx must be started before tx due to spi instinct */
180 dmaengine_submit(rxdesc); 207 dmaengine_submit(rxdesc);
181 dma_async_issue_pending(dws->rxchan); 208 dma_async_issue_pending(dws->rxchan);