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authorPeter De Schrijver <pdeschrijver@nvidia.com>2013-09-02 08:09:08 -0400
committerPeter De Schrijver <pdeschrijver@nvidia.com>2013-11-26 11:46:22 -0500
commita59ba9565ee20d162e858de03b9eebc0b9dbd8b6 (patch)
tree94514e5d7ffe55148e44a795658cf91f3eb6a0fc
parentebe142b2ad35d5656caae35d5deefdbebe847d3b (diff)
clk: tegra: add header for common tegra clock IDs
Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat
-rw-r--r--drivers/clk/tegra/clk-id.h213
1 files changed, 213 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
new file mode 100644
index 000000000000..22e2e8e67b2f
--- /dev/null
+++ b/drivers/clk/tegra/clk-id.h
@@ -0,0 +1,213 @@
1/*
2 * This header provides IDs for clocks common between several Tegra SoCs
3 */
4#ifndef _TEGRA_CLK_ID_H
5#define _TEGRA_CLK_ID_H
6
7enum clk_id {
8 tegra_clk_actmon,
9 tegra_clk_adx,
10 tegra_clk_afi,
11 tegra_clk_amx,
12 tegra_clk_apbdma,
13 tegra_clk_apbif,
14 tegra_clk_audio0,
15 tegra_clk_audio0_2x,
16 tegra_clk_audio0_mux,
17 tegra_clk_audio1,
18 tegra_clk_audio1_2x,
19 tegra_clk_audio1_mux,
20 tegra_clk_audio2,
21 tegra_clk_audio2_2x,
22 tegra_clk_audio2_mux,
23 tegra_clk_audio3,
24 tegra_clk_audio3_2x,
25 tegra_clk_audio3_mux,
26 tegra_clk_audio4,
27 tegra_clk_audio4_2x,
28 tegra_clk_audio4_mux,
29 tegra_clk_blink,
30 tegra_clk_bsea,
31 tegra_clk_bsev,
32 tegra_clk_cclk_g,
33 tegra_clk_cclk_lp,
34 tegra_clk_cilab,
35 tegra_clk_cilcd,
36 tegra_clk_cile,
37 tegra_clk_clk_32k,
38 tegra_clk_clk_m,
39 tegra_clk_clk_m_div2,
40 tegra_clk_clk_m_div4,
41 tegra_clk_clk_out_1,
42 tegra_clk_clk_out_1_mux,
43 tegra_clk_clk_out_2,
44 tegra_clk_clk_out_2_mux,
45 tegra_clk_clk_out_3,
46 tegra_clk_clk_out_3_mux,
47 tegra_clk_csi,
48 tegra_clk_csite,
49 tegra_clk_csus,
50 tegra_clk_cve,
51 tegra_clk_dam0,
52 tegra_clk_dam1,
53 tegra_clk_dam2,
54 tegra_clk_d_audio,
55 tegra_clk_dds,
56 tegra_clk_dfll_ref,
57 tegra_clk_dfll_soc,
58 tegra_clk_disp1,
59 tegra_clk_disp2,
60 tegra_clk_dp2,
61 tegra_clk_dsia,
62 tegra_clk_dsialp,
63 tegra_clk_dsia_mux,
64 tegra_clk_dsib,
65 tegra_clk_dsiblp,
66 tegra_clk_dsib_mux,
67 tegra_clk_dtv,
68 tegra_clk_emc,
69 tegra_clk_epp,
70 tegra_clk_epp_8,
71 tegra_clk_extern1,
72 tegra_clk_extern2,
73 tegra_clk_extern3,
74 tegra_clk_fuse,
75 tegra_clk_fuse_burn,
76 tegra_clk_gr2d,
77 tegra_clk_gr2d_8,
78 tegra_clk_gr3d,
79 tegra_clk_gr3d_8,
80 tegra_clk_hclk,
81 tegra_clk_hda,
82 tegra_clk_hda2codec_2x,
83 tegra_clk_hda2hdmi,
84 tegra_clk_hdmi,
85 tegra_clk_host1x,
86 tegra_clk_host1x_8,
87 tegra_clk_i2c1,
88 tegra_clk_i2c2,
89 tegra_clk_i2c3,
90 tegra_clk_i2c4,
91 tegra_clk_i2c5,
92 tegra_clk_i2cslow,
93 tegra_clk_i2s0,
94 tegra_clk_i2s0_sync,
95 tegra_clk_i2s1,
96 tegra_clk_i2s1_sync,
97 tegra_clk_i2s2,
98 tegra_clk_i2s2_sync,
99 tegra_clk_i2s3,
100 tegra_clk_i2s3_sync,
101 tegra_clk_i2s4,
102 tegra_clk_i2s4_sync,
103 tegra_clk_isp,
104 tegra_clk_kbc,
105 tegra_clk_kfuse,
106 tegra_clk_la,
107 tegra_clk_mipi,
108 tegra_clk_mipi_cal,
109 tegra_clk_mpe,
110 tegra_clk_mselect,
111 tegra_clk_msenc,
112 tegra_clk_ndflash,
113 tegra_clk_ndflash_8,
114 tegra_clk_ndspeed,
115 tegra_clk_ndspeed_8,
116 tegra_clk_nor,
117 tegra_clk_owr,
118 tegra_clk_pclk,
119 tegra_clk_pll_a,
120 tegra_clk_pll_a_out0,
121 tegra_clk_pll_c,
122 tegra_clk_pll_c2,
123 tegra_clk_pll_c3,
124 tegra_clk_pll_c_out1,
125 tegra_clk_pll_d,
126 tegra_clk_pll_d2,
127 tegra_clk_pll_d2_out0,
128 tegra_clk_pll_d_out0,
129 tegra_clk_pll_e_out0,
130 tegra_clk_pll_m,
131 tegra_clk_pll_m_out1,
132 tegra_clk_pll_p,
133 tegra_clk_pll_p_out1,
134 tegra_clk_pll_p_out2,
135 tegra_clk_pll_p_out2_int,
136 tegra_clk_pll_p_out3,
137 tegra_clk_pll_p_out4,
138 tegra_clk_pll_ref,
139 tegra_clk_pll_re_out,
140 tegra_clk_pll_re_vco,
141 tegra_clk_pll_u,
142 tegra_clk_pll_u_12m,
143 tegra_clk_pll_u_480m,
144 tegra_clk_pll_u_48m,
145 tegra_clk_pll_u_60m,
146 tegra_clk_pll_x,
147 tegra_clk_pll_x_out0,
148 tegra_clk_pwm,
149 tegra_clk_rtc,
150 tegra_clk_sata,
151 tegra_clk_sata_cold,
152 tegra_clk_sata_oob,
153 tegra_clk_sbc1,
154 tegra_clk_sbc1_8,
155 tegra_clk_sbc2,
156 tegra_clk_sbc2_8,
157 tegra_clk_sbc3,
158 tegra_clk_sbc3_8,
159 tegra_clk_sbc4,
160 tegra_clk_sbc4_8,
161 tegra_clk_sbc5,
162 tegra_clk_sbc5_8,
163 tegra_clk_sbc6,
164 tegra_clk_sbc6_8,
165 tegra_clk_sclk,
166 tegra_clk_sdmmc1,
167 tegra_clk_sdmmc2,
168 tegra_clk_sdmmc3,
169 tegra_clk_sdmmc4,
170 tegra_clk_se,
171 tegra_clk_soc_therm,
172 tegra_clk_spdif,
173 tegra_clk_spdif_2x,
174 tegra_clk_spdif_in,
175 tegra_clk_spdif_in_sync,
176 tegra_clk_spdif_mux,
177 tegra_clk_spdif_out,
178 tegra_clk_timer,
179 tegra_clk_trace,
180 tegra_clk_tsec,
181 tegra_clk_tsensor,
182 tegra_clk_tvdac,
183 tegra_clk_tvo,
184 tegra_clk_uarta,
185 tegra_clk_uartb,
186 tegra_clk_uartc,
187 tegra_clk_uartd,
188 tegra_clk_uarte,
189 tegra_clk_usb2,
190 tegra_clk_usb3,
191 tegra_clk_usbd,
192 tegra_clk_vcp,
193 tegra_clk_vde,
194 tegra_clk_vde_8,
195 tegra_clk_vfir,
196 tegra_clk_vi,
197 tegra_clk_vi_8,
198 tegra_clk_vimclk_sync,
199 tegra_clk_vi_sensor,
200 tegra_clk_vi_sensor_8,
201 tegra_clk_xusb_dev,
202 tegra_clk_xusb_dev_src,
203 tegra_clk_xusb_falcon_src,
204 tegra_clk_xusb_fs_src,
205 tegra_clk_xusb_host,
206 tegra_clk_xusb_host_src,
207 tegra_clk_xusb_hs_src,
208 tegra_clk_xusb_ss,
209 tegra_clk_xusb_ss_src,
210 tegra_clk_max,
211};
212
213#endif /* _TEGRA_CLK_ID_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-14 22:20:59 -0400