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authorThomas Bogendoerfer <tbogendoerfer@suse.de>2019-05-07 17:09:13 -0400
committerPaul Burton <paul.burton@mips.com>2019-05-09 19:39:27 -0400
commita57140e9a850582ddafdd8f115b78713baaf0d00 (patch)
tree5bef10f17e75eb4b9168d7562856cfc9144e12c0
parent8041edb5920902adc9b28f2fcd9ccce395434ead (diff)
MIPS: SGI-IP27: use generic PCI driver
Converted bridge code to a platform driver using the PCI generic driver framework and use adding platform devices during xtalk scan. This allows easier sharing bridge driver for other SGI platforms like IP30 (Octane) and IP35 (Origin 3k, Fuel, Tezro). Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> [paul.burton@mips.com: - Leave __phys_to_dma(), __dma_to_phys() & pcibus_to_node() in arch/mips/pci/pci-ip27.c since the motivation for moving them disappeared when the driver stopped being moved to drivers/pci.] Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
Diffstat
-rw-r--r--arch/mips/Kconfig5
-rw-r--r--arch/mips/include/asm/mach-ip27/topology.h11
-rw-r--r--arch/mips/include/asm/pci/bridge.h11
-rw-r--r--arch/mips/include/asm/xtalk/xtalk.h9
-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/pci-ip27.c181
-rw-r--r--arch/mips/pci/pci-xtalk-bridge.c (renamed from arch/mips/pci/ops-bridge.c)258
-rw-r--r--arch/mips/sgi-ip27/ip27-init.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-xtalk.c61
-rw-r--r--include/linux/platform_data/xtalk-bridge.h22
10 files changed, 288 insertions, 275 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fb8a39d53168..0e7a48598b26 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -676,6 +676,8 @@ config SGI_IP27
676 select HAVE_PCI 676 select HAVE_PCI
677 select IRQ_MIPS_CPU 677 select IRQ_MIPS_CPU
678 select NR_CPUS_DEFAULT_64 678 select NR_CPUS_DEFAULT_64
679 select PCI_DRIVERS_GENERIC
680 select PCI_XTALK_BRIDGE
679 select SYS_HAS_CPU_R10000 681 select SYS_HAS_CPU_R10000
680 select SYS_SUPPORTS_64BIT_KERNEL 682 select SYS_SUPPORTS_64BIT_KERNEL
681 select SYS_SUPPORTS_BIG_ENDIAN 683 select SYS_SUPPORTS_BIG_ENDIAN
@@ -1249,6 +1251,9 @@ config IRQ_GT641XX
1249config PCI_GT64XXX_PCI0 1251config PCI_GT64XXX_PCI0
1250 bool 1252 bool
1251 1253
1254config PCI_XTALK_BRIDGE
1255 bool
1256
1252config NO_EXCEPT_FILL 1257config NO_EXCEPT_FILL
1253 bool 1258 bool
1254 1259
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index 42ea1313626c..965f0793a5f9 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -7,18 +7,9 @@
7#include <asm/mmzone.h> 7#include <asm/mmzone.h>
8 8
9struct cpuinfo_ip27 { 9struct cpuinfo_ip27 {
10// cpuid_t p_cpuid; /* PROM assigned cpuid */
11 cnodeid_t p_nodeid; /* my node ID in compact-id-space */ 10 cnodeid_t p_nodeid; /* my node ID in compact-id-space */
12 nasid_t p_nasid; /* my node ID in numa-as-id-space */ 11 nasid_t p_nasid; /* my node ID in numa-as-id-space */
13 unsigned char p_slice; /* Physical position on node board */ 12 unsigned char p_slice; /* Physical position on node board */
14#if 0
15 unsigned long loops_per_sec;
16 unsigned long ipi_count;
17 unsigned long irq_attempt[NR_IRQS];
18 unsigned long smp_local_irq_count;
19 unsigned long prof_multiplier;
20 unsigned long prof_counter;
21#endif
22}; 13};
23 14
24extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; 15extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
@@ -30,7 +21,7 @@ extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
30struct pci_bus; 21struct pci_bus;
31extern int pcibus_to_node(struct pci_bus *); 22extern int pcibus_to_node(struct pci_bus *);
32 23
33#define cpumask_of_pcibus(bus) (cpu_online_mask) 24#define cpumask_of_pcibus(bus) (cpumask_of_node(pcibus_to_node(bus)))
34 25
35extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; 26extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
36 27
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index 23574c27eb40..d42b27c97c23 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -801,15 +801,12 @@ struct bridge_err_cmdword {
801#define PCI64_ATTR_RMF_SHFT 48 801#define PCI64_ATTR_RMF_SHFT 48
802 802
803struct bridge_controller { 803struct bridge_controller {
804 struct pci_controller pc;
805 struct resource mem;
806 struct resource io;
807 struct resource busn; 804 struct resource busn;
808 struct bridge_regs *base; 805 struct bridge_regs *base;
809 nasid_t nasid; 806 unsigned long baddr;
810 unsigned int widget_id; 807 unsigned long intr_addr;
811 u64 baddr;
812 unsigned int pci_int[8]; 808 unsigned int pci_int[8];
809 nasid_t nasid;
813}; 810};
814 811
815#define BRIDGE_CONTROLLER(bus) \ 812#define BRIDGE_CONTROLLER(bus) \
@@ -824,6 +821,4 @@ struct bridge_controller {
824 821
825extern int request_bridge_irq(struct bridge_controller *bc, int pin); 822extern int request_bridge_irq(struct bridge_controller *bc, int pin);
826 823
827extern struct pci_ops bridge_pci_ops;
828
829#endif /* _ASM_PCI_BRIDGE_H */ 824#endif /* _ASM_PCI_BRIDGE_H */
diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
index 26d2ed1fa917..680e7efebbaf 100644
--- a/arch/mips/include/asm/xtalk/xtalk.h
+++ b/arch/mips/include/asm/xtalk/xtalk.h
@@ -47,15 +47,6 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) 47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) 48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
49 49
50#ifdef CONFIG_PCI
51extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
52#else
53static inline int bridge_probe(nasid_t nasid, int widget, int masterwid)
54{
55 return 0;
56}
57#endif
58
59#endif /* !__ASSEMBLY__ */ 50#endif /* !__ASSEMBLY__ */
60 51
61#endif /* _ASM_XTALK_XTALK_H */ 52#endif /* _ASM_XTALK_XTALK_H */
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c4f976593061..d6de4cb2e31c 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
26obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o 26obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
27obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o 27obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
28obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o 28obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
29obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xtalk-bridge.o
29# 30#
30# These are still pretty much in the old state, watch, go blind. 31# These are still pretty much in the old state, watch, go blind.
31# 32#
@@ -39,7 +40,7 @@ obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o
39obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 40obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
40obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 41obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
41obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o 42obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
42obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o 43obj-$(CONFIG_SGI_IP27) += pci-ip27.o
43obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o 44obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
44obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o 45obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
45obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o 46obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 3c177b4d0609..441eb9383b20 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -7,162 +7,7 @@
7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */ 9 */
10#include <linux/kernel.h>
11#include <linux/export.h>
12#include <linux/pci.h>
13#include <linux/smp.h>
14#include <linux/dma-direct.h>
15#include <asm/sn/arch.h>
16#include <asm/pci/bridge.h> 10#include <asm/pci/bridge.h>
17#include <asm/paccess.h>
18#include <asm/sn/intr.h>
19#include <asm/sn/sn0/hub.h>
20
21/*
22 * Max #PCI busses we can handle; ie, max #PCI bridges.
23 */
24#define MAX_PCI_BUSSES 40
25
26/*
27 * XXX: No kmalloc available when we do our crosstalk scan,
28 * we should try to move it later in the boot process.
29 */
30static struct bridge_controller bridges[MAX_PCI_BUSSES];
31
32extern struct pci_ops bridge_pci_ops;
33
34int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
35{
36 unsigned long offset = NODE_OFFSET(nasid);
37 struct bridge_controller *bc;
38 static int num_bridges = 0;
39 int slot;
40
41 pci_set_flags(PCI_PROBE_ONLY);
42
43 printk("a bridge\n");
44
45 /* XXX: kludge alert.. */
46 if (!num_bridges)
47 ioport_resource.end = ~0UL;
48
49 bc = &bridges[num_bridges];
50
51 bc->pc.pci_ops = &bridge_pci_ops;
52 bc->pc.mem_resource = &bc->mem;
53 bc->pc.io_resource = &bc->io;
54
55 bc->pc.index = num_bridges;
56
57 bc->mem.name = "Bridge PCI MEM";
58 bc->pc.mem_offset = offset;
59 bc->mem.start = 0;
60 bc->mem.end = ~0UL;
61 bc->mem.flags = IORESOURCE_MEM;
62
63 bc->io.name = "Bridge IO MEM";
64 bc->pc.io_offset = offset;
65 bc->io.start = 0UL;
66 bc->io.end = ~0UL;
67 bc->io.flags = IORESOURCE_IO;
68
69 bc->widget_id = widget_id;
70 bc->nasid = nasid;
71
72 bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
73
74 /*
75 * point to this bridge
76 */
77 bc->base = (struct bridge_regs *)RAW_NODE_SWIN_BASE(nasid, widget_id);
78
79 /*
80 * Clear all pending interrupts.
81 */
82 bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
83
84 /*
85 * Until otherwise set up, assume all interrupts are from slot 0
86 */
87 bridge_write(bc, b_int_device, 0x0);
88
89 /*
90 * swap pio's to pci mem and io space (big windows)
91 */
92 bridge_set(bc, b_wid_control, BRIDGE_CTRL_IO_SWAP |
93 BRIDGE_CTRL_MEM_SWAP);
94#ifdef CONFIG_PAGE_SIZE_4KB
95 bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
96#else /* 16kB or larger */
97 bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
98#endif
99
100 /*
101 * Hmm... IRIX sets additional bits in the address which
102 * are documented as reserved in the bridge docs.
103 */
104 bridge_write(bc, b_wid_int_upper, 0x8000 | (masterwid << 16));
105 bridge_write(bc, b_wid_int_lower, 0x01800090); /* PI_INT_PEND_MOD off*/
106 bridge_write(bc, b_dir_map, (masterwid << 20)); /* DMA */
107 bridge_write(bc, b_int_enable, 0);
108
109 for (slot = 0; slot < 8; slot ++) {
110 bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
111 bc->pci_int[slot] = -1;
112 }
113 bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
114
115 register_pci_controller(&bc->pc);
116
117 num_bridges++;
118
119 return 0;
120}
121
122/*
123 * All observed requests have pin == 1. We could have a global here, that
124 * gets incremented and returned every time - unfortunately, pci_map_irq
125 * may be called on the same device over and over, and need to return the
126 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
127 *
128 * A given PCI device, in general, should be able to intr any of the cpus
129 * on any one of the hubs connected to its xbow.
130 */
131int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
132{
133 return 0;
134}
135
136static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev)
137{
138 while (dev->bus->parent) {
139 /* Move up the chain of bridges. */
140 dev = dev->bus->self;
141 }
142
143 return dev;
144}
145
146/* Do platform specific device initialization at pci_enable_device() time */
147int pcibios_plat_dev_init(struct pci_dev *dev)
148{
149 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
150 struct pci_dev *rdev = bridge_root_dev(dev);
151 int slot = PCI_SLOT(rdev->devfn);
152 int irq;
153
154 irq = bc->pci_int[slot];
155 if (irq == -1) {
156 irq = request_bridge_irq(bc, slot);
157 if (irq < 0)
158 return irq;
159
160 bc->pci_int[slot] = irq;
161 }
162 dev->irq = irq;
163
164 return 0;
165}
166 11
167dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) 12dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
168{ 13{
@@ -177,29 +22,6 @@ phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
177 return dma_addr & ~(0xffUL << 56); 22 return dma_addr & ~(0xffUL << 56);
178} 23}
179 24
180/*
181 * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
182 * to find the slot number in sense of the bridge device register.
183 * XXX This also means multiple devices might rely on conflicting bridge
184 * settings.
185 */
186
187static inline void pci_disable_swapping(struct pci_dev *dev)
188{
189 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
190 struct bridge_regs *bridge = bc->base;
191 int slot = PCI_SLOT(dev->devfn);
192
193 /* Turn off byte swapping */
194 bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
195 bridge->b_widget.w_tflush; /* Flush */
196}
197
198static void pci_fixup_ioc3(struct pci_dev *d)
199{
200 pci_disable_swapping(d);
201}
202
203#ifdef CONFIG_NUMA 25#ifdef CONFIG_NUMA
204int pcibus_to_node(struct pci_bus *bus) 26int pcibus_to_node(struct pci_bus *bus)
205{ 27{
@@ -209,6 +31,3 @@ int pcibus_to_node(struct pci_bus *bus)
209} 31}
210EXPORT_SYMBOL(pcibus_to_node); 32EXPORT_SYMBOL(pcibus_to_node);
211#endif /* CONFIG_NUMA */ 33#endif /* CONFIG_NUMA */
212
213DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
214 pci_fixup_ioc3);
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/pci-xtalk-bridge.c
index df95b0da08f2..8f481984ab6e 100644
--- a/arch/mips/pci/ops-bridge.c
+++ b/arch/mips/pci/pci-xtalk-bridge.c
@@ -1,17 +1,20 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * This file is subject to the terms and conditions of the GNU General Public 3 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
3 * License. See the file "COPYING" in the main directory of this archive 4 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
4 * for more details.
5 *
6 * Copyright (C) 1999, 2000, 04, 06 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */ 6 */
7#include <linux/kernel.h>
8#include <linux/export.h>
9#include <linux/pci.h> 9#include <linux/pci.h>
10#include <asm/paccess.h> 10#include <linux/smp.h>
11#include <linux/dma-direct.h>
12#include <linux/platform_device.h>
13#include <linux/platform_data/xtalk-bridge.h>
14
11#include <asm/pci/bridge.h> 15#include <asm/pci/bridge.h>
12#include <asm/sn/arch.h> 16#include <asm/paccess.h>
13#include <asm/sn/intr.h> 17#include <asm/sn/intr.h>
14#include <asm/sn/sn0/hub.h>
15 18
16/* 19/*
17 * Most of the IOC3 PCI config register aren't present 20 * Most of the IOC3 PCI config register aren't present
@@ -29,6 +32,20 @@ static u32 emulate_ioc3_cfg(int where, int size)
29 return 0; 32 return 0;
30} 33}
31 34
35static void bridge_disable_swapping(struct pci_dev *dev)
36{
37 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
38 int slot = PCI_SLOT(dev->devfn);
39
40 /* Turn off byte swapping */
41 bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
42 bridge_read(bc, b_widget.w_tflush); /* Flush */
43}
44
45DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
46 bridge_disable_swapping);
47
48
32/* 49/*
33 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is 50 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
34 * not really documented, so right now I can't write code which uses it. 51 * not really documented, so right now I can't write code which uses it.
@@ -39,20 +56,19 @@ static u32 emulate_ioc3_cfg(int where, int size)
39 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI 56 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
40 * accesses and does only decode parts of it's address space. 57 * accesses and does only decode parts of it's address space.
41 */ 58 */
42
43static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, 59static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
44 int where, int size, u32 * value) 60 int where, int size, u32 *value)
45{ 61{
46 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 62 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
47 struct bridge_regs *bridge = bc->base; 63 struct bridge_regs *bridge = bc->base;
48 int slot = PCI_SLOT(devfn); 64 int slot = PCI_SLOT(devfn);
49 int fn = PCI_FUNC(devfn); 65 int fn = PCI_FUNC(devfn);
50 volatile void *addr; 66 void *addr;
51 u32 cf, shift, mask; 67 u32 cf, shift, mask;
52 int res; 68 int res;
53 69
54 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; 70 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
55 if (get_dbe(cf, (u32 *) addr)) 71 if (get_dbe(cf, (u32 *)addr))
56 return PCIBIOS_DEVICE_NOT_FOUND; 72 return PCIBIOS_DEVICE_NOT_FOUND;
57 73
58 /* 74 /*
@@ -65,11 +81,11 @@ static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
65 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 81 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
66 82
67 if (size == 1) 83 if (size == 1)
68 res = get_dbe(*value, (u8 *) addr); 84 res = get_dbe(*value, (u8 *)addr);
69 else if (size == 2) 85 else if (size == 2)
70 res = get_dbe(*value, (u16 *) addr); 86 res = get_dbe(*value, (u16 *)addr);
71 else 87 else
72 res = get_dbe(*value, (u32 *) addr); 88 res = get_dbe(*value, (u32 *)addr);
73 89
74 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 90 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
75 91
@@ -84,8 +100,7 @@ is_ioc3:
84 } 100 }
85 101
86 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 102 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
87 103 if (get_dbe(cf, (u32 *)addr))
88 if (get_dbe(cf, (u32 *) addr))
89 return PCIBIOS_DEVICE_NOT_FOUND; 104 return PCIBIOS_DEVICE_NOT_FOUND;
90 105
91 shift = ((where & 3) << 3); 106 shift = ((where & 3) << 3);
@@ -96,20 +111,20 @@ is_ioc3:
96} 111}
97 112
98static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn, 113static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
99 int where, int size, u32 * value) 114 int where, int size, u32 *value)
100{ 115{
101 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 116 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
102 struct bridge_regs *bridge = bc->base; 117 struct bridge_regs *bridge = bc->base;
103 int busno = bus->number; 118 int busno = bus->number;
104 int slot = PCI_SLOT(devfn); 119 int slot = PCI_SLOT(devfn);
105 int fn = PCI_FUNC(devfn); 120 int fn = PCI_FUNC(devfn);
106 volatile void *addr; 121 void *addr;
107 u32 cf, shift, mask; 122 u32 cf, shift, mask;
108 int res; 123 int res;
109 124
110 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 125 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
111 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 126 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
112 if (get_dbe(cf, (u32 *) addr)) 127 if (get_dbe(cf, (u32 *)addr))
113 return PCIBIOS_DEVICE_NOT_FOUND; 128 return PCIBIOS_DEVICE_NOT_FOUND;
114 129
115 /* 130 /*
@@ -119,15 +134,14 @@ static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
119 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 134 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
120 goto is_ioc3; 135 goto is_ioc3;
121 136
122 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
123 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 137 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
124 138
125 if (size == 1) 139 if (size == 1)
126 res = get_dbe(*value, (u8 *) addr); 140 res = get_dbe(*value, (u8 *)addr);
127 else if (size == 2) 141 else if (size == 2)
128 res = get_dbe(*value, (u16 *) addr); 142 res = get_dbe(*value, (u16 *)addr);
129 else 143 else
130 res = get_dbe(*value, (u32 *) addr); 144 res = get_dbe(*value, (u32 *)addr);
131 145
132 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 146 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
133 147
@@ -141,10 +155,8 @@ is_ioc3:
141 return PCIBIOS_SUCCESSFUL; 155 return PCIBIOS_SUCCESSFUL;
142 } 156 }
143 157
144 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
145 addr = &bridge->b_type1_cfg.c[(fn << 8) | where]; 158 addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
146 159 if (get_dbe(cf, (u32 *)addr))
147 if (get_dbe(cf, (u32 *) addr))
148 return PCIBIOS_DEVICE_NOT_FOUND; 160 return PCIBIOS_DEVICE_NOT_FOUND;
149 161
150 shift = ((where & 3) << 3); 162 shift = ((where & 3) << 3);
@@ -155,7 +167,7 @@ is_ioc3:
155} 167}
156 168
157static int pci_read_config(struct pci_bus *bus, unsigned int devfn, 169static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
158 int where, int size, u32 * value) 170 int where, int size, u32 *value)
159{ 171{
160 if (!pci_is_root_bus(bus)) 172 if (!pci_is_root_bus(bus))
161 return pci_conf1_read_config(bus, devfn, where, size, value); 173 return pci_conf1_read_config(bus, devfn, where, size, value);
@@ -170,12 +182,12 @@ static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
170 struct bridge_regs *bridge = bc->base; 182 struct bridge_regs *bridge = bc->base;
171 int slot = PCI_SLOT(devfn); 183 int slot = PCI_SLOT(devfn);
172 int fn = PCI_FUNC(devfn); 184 int fn = PCI_FUNC(devfn);
173 volatile void *addr; 185 void *addr;
174 u32 cf, shift, mask, smask; 186 u32 cf, shift, mask, smask;
175 int res; 187 int res;
176 188
177 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; 189 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
178 if (get_dbe(cf, (u32 *) addr)) 190 if (get_dbe(cf, (u32 *)addr))
179 return PCIBIOS_DEVICE_NOT_FOUND; 191 return PCIBIOS_DEVICE_NOT_FOUND;
180 192
181 /* 193 /*
@@ -187,13 +199,12 @@ static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
187 199
188 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 200 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
189 201
190 if (size == 1) { 202 if (size == 1)
191 res = put_dbe(value, (u8 *) addr); 203 res = put_dbe(value, (u8 *)addr);
192 } else if (size == 2) { 204 else if (size == 2)
193 res = put_dbe(value, (u16 *) addr); 205 res = put_dbe(value, (u16 *)addr);
194 } else { 206 else
195 res = put_dbe(value, (u32 *) addr); 207 res = put_dbe(value, (u32 *)addr);
196 }
197 208
198 if (res) 209 if (res)
199 return PCIBIOS_DEVICE_NOT_FOUND; 210 return PCIBIOS_DEVICE_NOT_FOUND;
@@ -210,7 +221,7 @@ is_ioc3:
210 221
211 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 222 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
212 223
213 if (get_dbe(cf, (u32 *) addr)) 224 if (get_dbe(cf, (u32 *)addr))
214 return PCIBIOS_DEVICE_NOT_FOUND; 225 return PCIBIOS_DEVICE_NOT_FOUND;
215 226
216 shift = ((where & 3) << 3); 227 shift = ((where & 3) << 3);
@@ -218,7 +229,7 @@ is_ioc3:
218 smask = mask << shift; 229 smask = mask << shift;
219 230
220 cf = (cf & ~smask) | ((value & mask) << shift); 231 cf = (cf & ~smask) | ((value & mask) << shift);
221 if (put_dbe(cf, (u32 *) addr)) 232 if (put_dbe(cf, (u32 *)addr))
222 return PCIBIOS_DEVICE_NOT_FOUND; 233 return PCIBIOS_DEVICE_NOT_FOUND;
223 234
224 return PCIBIOS_SUCCESSFUL; 235 return PCIBIOS_SUCCESSFUL;
@@ -232,13 +243,13 @@ static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
232 int slot = PCI_SLOT(devfn); 243 int slot = PCI_SLOT(devfn);
233 int fn = PCI_FUNC(devfn); 244 int fn = PCI_FUNC(devfn);
234 int busno = bus->number; 245 int busno = bus->number;
235 volatile void *addr; 246 void *addr;
236 u32 cf, shift, mask, smask; 247 u32 cf, shift, mask, smask;
237 int res; 248 int res;
238 249
239 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 250 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
240 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 251 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
241 if (get_dbe(cf, (u32 *) addr)) 252 if (get_dbe(cf, (u32 *)addr))
242 return PCIBIOS_DEVICE_NOT_FOUND; 253 return PCIBIOS_DEVICE_NOT_FOUND;
243 254
244 /* 255 /*
@@ -250,13 +261,12 @@ static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
250 261
251 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 262 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
252 263
253 if (size == 1) { 264 if (size == 1)
254 res = put_dbe(value, (u8 *) addr); 265 res = put_dbe(value, (u8 *)addr);
255 } else if (size == 2) { 266 else if (size == 2)
256 res = put_dbe(value, (u16 *) addr); 267 res = put_dbe(value, (u16 *)addr);
257 } else { 268 else
258 res = put_dbe(value, (u32 *) addr); 269 res = put_dbe(value, (u32 *)addr);
259 }
260 270
261 if (res) 271 if (res)
262 return PCIBIOS_DEVICE_NOT_FOUND; 272 return PCIBIOS_DEVICE_NOT_FOUND;
@@ -272,8 +282,7 @@ is_ioc3:
272 return PCIBIOS_SUCCESSFUL; 282 return PCIBIOS_SUCCESSFUL;
273 283
274 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 284 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
275 285 if (get_dbe(cf, (u32 *)addr))
276 if (get_dbe(cf, (u32 *) addr))
277 return PCIBIOS_DEVICE_NOT_FOUND; 286 return PCIBIOS_DEVICE_NOT_FOUND;
278 287
279 shift = ((where & 3) << 3); 288 shift = ((where & 3) << 3);
@@ -281,7 +290,7 @@ is_ioc3:
281 smask = mask << shift; 290 smask = mask << shift;
282 291
283 cf = (cf & ~smask) | ((value & mask) << shift); 292 cf = (cf & ~smask) | ((value & mask) << shift);
284 if (put_dbe(cf, (u32 *) addr)) 293 if (put_dbe(cf, (u32 *)addr))
285 return PCIBIOS_DEVICE_NOT_FOUND; 294 return PCIBIOS_DEVICE_NOT_FOUND;
286 295
287 return PCIBIOS_SUCCESSFUL; 296 return PCIBIOS_SUCCESSFUL;
@@ -296,7 +305,148 @@ static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
296 return pci_conf0_write_config(bus, devfn, where, size, value); 305 return pci_conf0_write_config(bus, devfn, where, size, value);
297} 306}
298 307
299struct pci_ops bridge_pci_ops = { 308static struct pci_ops bridge_pci_ops = {
300 .read = pci_read_config, 309 .read = pci_read_config,
301 .write = pci_write_config, 310 .write = pci_write_config,
311};
312
313/*
314 * All observed requests have pin == 1. We could have a global here, that
315 * gets incremented and returned every time - unfortunately, pci_map_irq
316 * may be called on the same device over and over, and need to return the
317 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
318 *
319 * A given PCI device, in general, should be able to intr any of the cpus
320 * on any one of the hubs connected to its xbow.
321 */
322static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
323{
324 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
325 int irq;
326
327 irq = bc->pci_int[slot];
328 if (irq == -1) {
329 irq = request_bridge_irq(bc, slot);
330 if (irq < 0)
331 return irq;
332
333 bc->pci_int[slot] = irq;
334 }
335 return irq;
336}
337
338static int bridge_probe(struct platform_device *pdev)
339{
340 struct device *dev = &pdev->dev;
341 struct bridge_controller *bc;
342 struct pci_host_bridge *host;
343 int slot;
344 int err;
345 struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
346
347 pci_set_flags(PCI_PROBE_ONLY);
348
349 host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
350 if (!host)
351 return -ENOMEM;
352
353 bc = pci_host_bridge_priv(host);
354
355 bc->busn.name = "Bridge PCI busn";
356 bc->busn.start = 0;
357 bc->busn.end = 0xff;
358 bc->busn.flags = IORESOURCE_BUS;
359
360 pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
361 pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
362 pci_add_resource(&host->windows, &bc->busn);
363
364 err = devm_request_pci_bus_resources(dev, &host->windows);
365 if (err < 0) {
366 pci_free_resource_list(&host->windows);
367 return err;
368 }
369
370 bc->nasid = bd->nasid;
371
372 bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
373 bc->base = (struct bridge_regs *)bd->bridge_addr;
374 bc->intr_addr = bd->intr_addr;
375
376 /*
377 * Clear all pending interrupts.
378 */
379 bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
380
381 /*
382 * Until otherwise set up, assume all interrupts are from slot 0
383 */
384 bridge_write(bc, b_int_device, 0x0);
385
386 /*
387 * disable swapping for big windows
388 */
389 bridge_clr(bc, b_wid_control,
390 BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
391#ifdef CONFIG_PAGE_SIZE_4KB
392 bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
393#else /* 16kB or larger */
394 bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
395#endif
396
397 /*
398 * Hmm... IRIX sets additional bits in the address which
399 * are documented as reserved in the bridge docs.
400 */
401 bridge_write(bc, b_wid_int_upper,
402 ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
403 bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
404 bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */
405 bridge_write(bc, b_int_enable, 0);
406
407 for (slot = 0; slot < 8; slot++) {
408 bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
409 bc->pci_int[slot] = -1;
410 }
411 bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
412
413 host->dev.parent = dev;
414 host->sysdata = bc;
415 host->busnr = 0;
416 host->ops = &bridge_pci_ops;
417 host->map_irq = bridge_map_irq;
418 host->swizzle_irq = pci_common_swizzle;
419
420 err = pci_scan_root_bus_bridge(host);
421 if (err < 0)
422 return err;
423
424 pci_bus_claim_resources(host->bus);
425 pci_bus_add_devices(host->bus);
426
427 platform_set_drvdata(pdev, host->bus);
428
429 return 0;
430}
431
432static int bridge_remove(struct platform_device *pdev)
433{
434 struct pci_bus *bus = platform_get_drvdata(pdev);
435
436 pci_lock_rescan_remove();
437 pci_stop_root_bus(bus);
438 pci_remove_root_bus(bus);
439 pci_unlock_rescan_remove();
440
441 return 0;
442}
443
444static struct platform_driver bridge_driver = {
445 .probe = bridge_probe,
446 .remove = bridge_remove,
447 .driver = {
448 .name = "xtalk-bridge",
449 }
302}; 450};
451
452builtin_platform_driver(bridge_driver);
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 6074efeff894..066b33f50bcc 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -184,5 +184,7 @@ void __init plat_mem_setup(void)
184 184
185 ioc3_eth_init(); 185 ioc3_eth_init();
186 186
187 ioport_resource.start = 0;
188 ioport_resource.end = ~0UL;
187 set_io_port_base(IO_BASE); 189 set_io_port_base(IO_BASE);
188} 190}
diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
index ce06aaa115ae..bd5cb855c6e5 100644
--- a/arch/mips/sgi-ip27/ip27-xtalk.c
+++ b/arch/mips/sgi-ip27/ip27-xtalk.c
@@ -9,6 +9,9 @@
9 9
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/smp.h> 11#include <linux/smp.h>
12#include <linux/platform_device.h>
13#include <linux/platform_data/xtalk-bridge.h>
14#include <asm/sn/addrs.h>
12#include <asm/sn/types.h> 15#include <asm/sn/types.h>
13#include <asm/sn/klconfig.h> 16#include <asm/sn/klconfig.h>
14#include <asm/sn/hub.h> 17#include <asm/sn/hub.h>
@@ -20,7 +23,48 @@
20#define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbow in Xbridge */ 23#define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbow in Xbridge */
21#define BASE_XBOW_PORT 8 /* Lowest external port */ 24#define BASE_XBOW_PORT 8 /* Lowest external port */
22 25
23extern int bridge_probe(nasid_t nasid, int widget, int masterwid); 26static void bridge_platform_create(nasid_t nasid, int widget, int masterwid)
27{
28 struct xtalk_bridge_platform_data *bd;
29 struct platform_device *pdev;
30 unsigned long offset;
31
32 bd = kzalloc(sizeof(*bd), GFP_KERNEL);
33 if (!bd)
34 goto no_mem;
35 pdev = platform_device_alloc("xtalk-bridge", PLATFORM_DEVID_AUTO);
36 if (!pdev) {
37 kfree(bd);
38 goto no_mem;
39 }
40
41 offset = NODE_OFFSET(nasid);
42
43 bd->bridge_addr = RAW_NODE_SWIN_BASE(nasid, widget);
44 bd->intr_addr = BIT_ULL(47) + 0x01800000 + PI_INT_PEND_MOD;
45 bd->nasid = nasid;
46 bd->masterwid = masterwid;
47
48 bd->mem.name = "Bridge PCI MEM";
49 bd->mem.start = offset + (widget << SWIN_SIZE_BITS);
50 bd->mem.end = bd->mem.start + SWIN_SIZE - 1;
51 bd->mem.flags = IORESOURCE_MEM;
52 bd->mem_offset = offset;
53
54 bd->io.name = "Bridge PCI IO";
55 bd->io.start = offset + (widget << SWIN_SIZE_BITS);
56 bd->io.end = bd->io.start + SWIN_SIZE - 1;
57 bd->io.flags = IORESOURCE_IO;
58 bd->io_offset = offset;
59
60 platform_device_add_data(pdev, bd, sizeof(*bd));
61 platform_device_add(pdev);
62 pr_info("xtalk:n%d/%x bridge widget\n", nasid, widget);
63 return;
64
65no_mem:
66 pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget);
67}
24 68
25static int probe_one_port(nasid_t nasid, int widget, int masterwid) 69static int probe_one_port(nasid_t nasid, int widget, int masterwid)
26{ 70{
@@ -31,13 +75,10 @@ static int probe_one_port(nasid_t nasid, int widget, int masterwid)
31 (RAW_NODE_SWIN_BASE(nasid, widget) + WIDGET_ID); 75 (RAW_NODE_SWIN_BASE(nasid, widget) + WIDGET_ID);
32 partnum = XWIDGET_PART_NUM(widget_id); 76 partnum = XWIDGET_PART_NUM(widget_id);
33 77
34 printk(KERN_INFO "Cpu %d, Nasid 0x%x, widget 0x%x (partnum 0x%x) is ",
35 smp_processor_id(), nasid, widget, partnum);
36
37 switch (partnum) { 78 switch (partnum) {
38 case BRIDGE_WIDGET_PART_NUM: 79 case BRIDGE_WIDGET_PART_NUM:
39 case XBRIDGE_WIDGET_PART_NUM: 80 case XBRIDGE_WIDGET_PART_NUM:
40 bridge_probe(nasid, widget, masterwid); 81 bridge_platform_create(nasid, widget, masterwid);
41 break; 82 break;
42 default: 83 default:
43 break; 84 break;
@@ -52,8 +93,6 @@ static int xbow_probe(nasid_t nasid)
52 klxbow_t *xbow_p; 93 klxbow_t *xbow_p;
53 unsigned masterwid, i; 94 unsigned masterwid, i;
54 95
55 printk("is xbow\n");
56
57 /* 96 /*
58 * found xbow, so may have multiple bridges 97 * found xbow, so may have multiple bridges
59 * need to probe xbow 98 * need to probe xbow
@@ -117,19 +156,17 @@ static void xtalk_probe_node(cnodeid_t nid)
117 (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID); 156 (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID);
118 partnum = XWIDGET_PART_NUM(widget_id); 157 partnum = XWIDGET_PART_NUM(widget_id);
119 158
120 printk(KERN_INFO "Cpu %d, Nasid 0x%x: partnum 0x%x is ",
121 smp_processor_id(), nasid, partnum);
122
123 switch (partnum) { 159 switch (partnum) {
124 case BRIDGE_WIDGET_PART_NUM: 160 case BRIDGE_WIDGET_PART_NUM:
125 bridge_probe(nasid, 0x8, 0xa); 161 bridge_platform_create(nasid, 0x8, 0xa);
126 break; 162 break;
127 case XBOW_WIDGET_PART_NUM: 163 case XBOW_WIDGET_PART_NUM:
128 case XXBOW_WIDGET_PART_NUM: 164 case XXBOW_WIDGET_PART_NUM:
165 pr_info("xtalk:n%d/0 xbow widget\n", nasid);
129 xbow_probe(nasid); 166 xbow_probe(nasid);
130 break; 167 break;
131 default: 168 default:
132 printk(" unknown widget??\n"); 169 pr_info("xtalk:n%d/0 unknown widget (0x%x)\n", nasid, partnum);
133 break; 170 break;
134 } 171 }
135} 172}
diff --git a/include/linux/platform_data/xtalk-bridge.h b/include/linux/platform_data/xtalk-bridge.h
new file mode 100644
index 000000000000..51e5001f2c05
--- /dev/null
+++ b/include/linux/platform_data/xtalk-bridge.h
@@ -0,0 +1,22 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * SGI PCI Xtalk Bridge
4 */
5
6#ifndef PLATFORM_DATA_XTALK_BRIDGE_H
7#define PLATFORM_DATA_XTALK_BRIDGE_H
8
9#include <asm/sn/types.h>
10
11struct xtalk_bridge_platform_data {
12 struct resource mem;
13 struct resource io;
14 unsigned long bridge_addr;
15 unsigned long intr_addr;
16 unsigned long mem_offset;
17 unsigned long io_offset;
18 nasid_t nasid;
19 int masterwid;
20};
21
22#endif /* PLATFORM_DATA_XTALK_BRIDGE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 14:15:42 -0400