Merge tag 'gvt-fixes-2018-09-18' of https://github.com/intel/gvt-linux into drm-intel-fixes

gvt-fixes-2018-09-18

- Fix initial DPIO PHY register state for BXT (Colin)
- BXT untracked GEN9_CLKGATE_DIS_4 warning fix (Colin)
- Fix srcu lock for GFN valid check (Weinan)
- Should clear GGTT entry value after vGPU destroy (Zhipeng)

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180918073349.GQ20737@zhen-hp.sh.intel.com

4 files changed, 36 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 72afa518edd9..94c1089ecf59 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3210,6 +3210,7 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
         MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
 
         MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
+        MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
 
         MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
         MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index c7afee37b2b8..9ad89e38f6c0 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1833,6 +1833,8 @@ static bool kvmgt_is_valid_gfn(unsigned long handle, unsigned long gfn)
 {
         struct kvmgt_guest_info *info;
         struct kvm *kvm;
+        int idx;
+        bool ret;
 
         if (!handle_valid(handle))
                 return false;
@@ -1840,8 +1842,11 @@ static bool kvmgt_is_valid_gfn(unsigned long handle, unsigned long gfn)
         info = (struct kvmgt_guest_info *)handle;
         kvm = info->kvm;
 
-        return kvm_is_visible_gfn(kvm, gfn);
+        idx = srcu_read_lock(&kvm->srcu);
+        ret = kvm_is_visible_gfn(kvm, gfn);
+        srcu_read_unlock(&kvm->srcu, idx);
 
+        return ret;
 }
 
 struct intel_gvt_mpt kvmgt_mpt = {
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 994366035364..9bb9a85c992c 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -244,6 +244,34 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
 
                 /* set the bit 0:2(Core C-State ) to C0 */
                 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
+
+                if (IS_BROXTON(vgpu->gvt->dev_priv)) {
+                        vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
+                                    ~(BIT(0) | BIT(1));
+                        vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
+                                    ~PHY_POWER_GOOD;
+                        vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
+                                    ~PHY_POWER_GOOD;
+                        vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
+                                    ~BIT(30);
+                        vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
+                                    ~BIT(30);
+                        vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
+                                    ~BXT_PHY_LANE_ENABLED;
+                        vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
+                                    BXT_PHY_CMNLANE_POWERDOWN_ACK |
+                                    BXT_PHY_LANE_POWERDOWN_ACK;
+                        vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
+                                    ~BXT_PHY_LANE_ENABLED;
+                        vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
+                                    BXT_PHY_CMNLANE_POWERDOWN_ACK |
+                                    BXT_PHY_LANE_POWERDOWN_ACK;
+                        vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
+                                    ~BXT_PHY_LANE_ENABLED;
+                        vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
+                                    BXT_PHY_CMNLANE_POWERDOWN_ACK |
+                                    BXT_PHY_LANE_POWERDOWN_ACK;
+                }
         } else {
 #define GVT_GEN8_MMIO_RESET_OFFSET              (0x44200)
                 /* only reset the engine related, so starting with 0x44200
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index a4e8e3cf74fd..c628be05fbfe 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -281,6 +281,7 @@ void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
         intel_vgpu_clean_submission(vgpu);
         intel_vgpu_clean_display(vgpu);
         intel_vgpu_clean_opregion(vgpu);
+        intel_vgpu_reset_ggtt(vgpu, true);
         intel_vgpu_clean_gtt(vgpu);
         intel_gvt_hypervisor_detach_vgpu(vgpu);
         intel_vgpu_free_resource(vgpu);