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authorYongqiang Sun <yongqiang.sun@amd.com>2017-11-08 14:50:06 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-12-06 12:47:44 -0500
commita4e6d14ebe80ee53e295540c51dfb1352d7069a8 (patch)
tree455c4b3c8eee420848565aadf1231f05964f5065
parent105f6ab86cc26eaa3ee9b4845d90c8b6a0571534 (diff)
drm/amd/display: Optimize front end programming.
for video scaling changes, Reduce reg access count from 1044 to 447, duration time from 4.6ms to 3ms. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c219
1 files changed, 111 insertions, 108 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d0f46e13efca..30f458701f9c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1453,6 +1453,89 @@ static void dcn10_enable_per_frame_crtc_position_reset(
1453} 1453}
1454*/ 1454*/
1455 1455
1456static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1457 struct vm_system_aperture_param *apt,
1458 struct dce_hwseq *hws)
1459{
1460 PHYSICAL_ADDRESS_LOC physical_page_number;
1461 uint32_t logical_addr_low;
1462 uint32_t logical_addr_high;
1463
1464 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1465 PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1466 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1467 PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1468
1469 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1470 LOGICAL_ADDR, &logical_addr_low);
1471
1472 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1473 LOGICAL_ADDR, &logical_addr_high);
1474
1475 apt->sys_default.quad_part = physical_page_number.quad_part << 12;
1476 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
1477 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
1478}
1479
1480/* Temporary read settings, future will get values from kmd directly */
1481static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1482 struct vm_context0_param *vm0,
1483 struct dce_hwseq *hws)
1484{
1485 PHYSICAL_ADDRESS_LOC fb_base;
1486 PHYSICAL_ADDRESS_LOC fb_offset;
1487 uint32_t fb_base_value;
1488 uint32_t fb_offset_value;
1489
1490 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1491 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1492
1493 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1494 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1495 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1496 PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1497
1498 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1499 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1500 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1501 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1502
1503 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1504 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1505 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1506 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1507
1508 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1509 PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1510 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1511 PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1512
1513 /*
1514 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1515 * Therefore we need to do
1516 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1517 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1518 */
1519 fb_base.quad_part = (uint64_t)fb_base_value << 24;
1520 fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1521 vm0->pte_base.quad_part += fb_base.quad_part;
1522 vm0->pte_base.quad_part -= fb_offset.quad_part;
1523}
1524
1525
1526static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1527{
1528 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1529 struct vm_system_aperture_param apt = { {{ 0 } } };
1530 struct vm_context0_param vm0 = { { { 0 } } };
1531
1532 mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1533 mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1534
1535 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1536 hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1537}
1538
1456static void dcn10_enable_plane( 1539static void dcn10_enable_plane(
1457 struct dc *dc, 1540 struct dc *dc,
1458 struct pipe_ctx *pipe_ctx, 1541 struct pipe_ctx *pipe_ctx,
@@ -1515,6 +1598,8 @@ static void dcn10_enable_plane(
1515 print_rq_dlg_ttu(dc, pipe_ctx); 1598 print_rq_dlg_ttu(dc, pipe_ctx);
1516 } 1599 }
1517*/ 1600*/
1601 if (dc->config.gpu_vm_support)
1602 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1518 1603
1519 if (dc->debug.sanity_checks) { 1604 if (dc->debug.sanity_checks) {
1520 dcn10_verify_allow_pstate_change_high(dc); 1605 dcn10_verify_allow_pstate_change_high(dc);
@@ -1737,93 +1822,6 @@ void build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
1737 } 1822 }
1738} 1823}
1739 1824
1740static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1741 struct vm_system_aperture_param *apt,
1742 struct dce_hwseq *hws)
1743{
1744 PHYSICAL_ADDRESS_LOC physical_page_number;
1745 uint32_t logical_addr_low;
1746 uint32_t logical_addr_high;
1747
1748 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1749 PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1750 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1751 PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1752
1753 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1754 LOGICAL_ADDR, &logical_addr_low);
1755
1756 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1757 LOGICAL_ADDR, &logical_addr_high);
1758
1759 apt->sys_default.quad_part = physical_page_number.quad_part << 12;
1760 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
1761 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
1762}
1763
1764/* Temporary read settings, future will get values from kmd directly */
1765static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1766 struct vm_context0_param *vm0,
1767 struct dce_hwseq *hws)
1768{
1769 PHYSICAL_ADDRESS_LOC fb_base;
1770 PHYSICAL_ADDRESS_LOC fb_offset;
1771 uint32_t fb_base_value;
1772 uint32_t fb_offset_value;
1773
1774 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1775 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1776
1777 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1778 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1779 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1780 PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1781
1782 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1783 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1784 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1785 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1786
1787 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1788 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1789 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1790 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1791
1792 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1793 PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1794 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1795 PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1796
1797 /*
1798 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1799 * Therefore we need to do
1800 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1801 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1802 */
1803 fb_base.quad_part = (uint64_t)fb_base_value << 24;
1804 fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1805 vm0->pte_base.quad_part += fb_base.quad_part;
1806 vm0->pte_base.quad_part -= fb_offset.quad_part;
1807}
1808
1809static void dcn10_program_pte_vm(struct hubp *hubp,
1810 enum surface_pixel_format format,
1811 union dc_tiling_info *tiling_info,
1812 enum dc_rotation_angle rotation,
1813 struct dce_hwseq *hws)
1814{
1815 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1816 struct vm_system_aperture_param apt = { {{ 0 } } };
1817 struct vm_context0_param vm0 = { { { 0 } } };
1818
1819
1820 mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1821 mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1822
1823 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1824 hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1825}
1826
1827static void update_dchubp_dpp( 1825static void update_dchubp_dpp(
1828 struct dc *dc, 1826 struct dc *dc,
1829 struct pipe_ctx *pipe_ctx, 1827 struct pipe_ctx *pipe_ctx,
@@ -1865,15 +1863,6 @@ static void update_dchubp_dpp(
1865 1863
1866 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1864 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1867 1865
1868 if (dc->config.gpu_vm_support)
1869 dcn10_program_pte_vm(
1870 pipe_ctx->plane_res.hubp,
1871 plane_state->format,
1872 &plane_state->tiling_info,
1873 plane_state->rotation,
1874 hws
1875 );
1876
1877 // program the input csc 1866 // program the input csc
1878 dpp->funcs->dpp_setup(dpp, 1867 dpp->funcs->dpp_setup(dpp,
1879 plane_state->format, 1868 plane_state->format,
@@ -1970,18 +1959,11 @@ static void program_all_pipe_in_tree(
1970 struct pipe_ctx *cur_pipe_ctx = 1959 struct pipe_ctx *cur_pipe_ctx =
1971 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1960 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1972 1961
1973 dcn10_enable_plane(dc, pipe_ctx, context); 1962 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1963 dcn10_enable_plane(dc, pipe_ctx, context);
1974 1964
1975 update_dchubp_dpp(dc, pipe_ctx, context); 1965 if (pipe_ctx->plane_state->update_flags.raw != 0)
1976 1966 update_dchubp_dpp(dc, pipe_ctx, context);
1977 /* TODO: this is a hack w/a for switching from mpo to pipe split */
1978 if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1979 struct dc_cursor_position position = { 0 };
1980
1981 dc_stream_set_cursor_position(pipe_ctx->stream, &position);
1982 dc_stream_set_cursor_attributes(pipe_ctx->stream,
1983 &pipe_ctx->stream->cursor_attributes);
1984 }
1985 1967
1986 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { 1968 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
1987 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); 1969 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
@@ -2141,9 +2123,30 @@ static void dcn10_apply_ctx_for_surface(
2141 } 2123 }
2142 } 2124 }
2143 2125
2144 if (num_planes > 0) 2126 if (num_planes > 0) {
2127 struct dc_stream_state *stream_for_cursor;
2128
2145 program_all_pipe_in_tree(dc, top_pipe_to_program, context); 2129 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2146 2130
2131 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2132 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2133
2134 if (stream == pipe_ctx->stream) {
2135 stream_for_cursor = pipe_ctx->stream;
2136 break;
2137 }
2138 }
2139
2140 /* TODO: this is a hack w/a for switching from mpo to pipe split */
2141 if (stream_for_cursor->cursor_attributes.address.quad_part != 0) {
2142 struct dc_cursor_position position = { 0 };
2143
2144 dc_stream_set_cursor_position(stream_for_cursor, &position);
2145 dc_stream_set_cursor_attributes(stream_for_cursor,
2146 &stream_for_cursor->cursor_attributes);
2147 }
2148 }
2149
2147 tg->funcs->unlock(tg); 2150 tg->funcs->unlock(tg);
2148 2151
2149 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2152 for (i = 0; i < dc->res_pool->pipe_count; i++) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 01:02:46 -0400