drm/amd/pp: Print out voltage/clock range in sysfs

when user cat pp_od_clk_voltage
add display info about the sclk/mclk/vddc range that user can overdrive
output as:
OD_SCLK:
0:        300MHz        900mV
1:        400MHz        912mV
2:        500MHz        925mV
3:        600MHz        937mV
4:        700MHz        950mV
5:        800MHz        975mV
6:        900MHz        987mV
7:       1000MHz       1000mV
OD_MCLK:
0:        300MHz        900mV
1:       1500MHz        912mV
OD_RANGE:
SCLK:     300MHz       1200MHz
MCLK:     300MHz       1500MHz
VDDC:     700mV        1200mV

also
1. remove unnecessary whitespace before a quoted newline
2. change unit of frequency Mhz to MHz

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3 files changed, 22 insertions, 6 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index ce8be467608d..27d8dd77860d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -555,6 +555,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
         if (adev->powerplay.pp_funcs->print_clock_levels) {
                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
+                size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
                 return size;
         } else {
                 return snprintf(buf, PAGE_SIZE, "\n");
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 01969b135ab4..06f08f34a110 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -94,6 +94,7 @@ enum pp_clock_type {
         PP_PCIE,
         OD_SCLK,
         OD_MCLK,
+        OD_RANGE,
 };
 
 enum amd_pp_sensors {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index e1196372a6ba..232ea6fc30f4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4335,22 +4335,36 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
                 break;
         case OD_SCLK:
                 if (hwmgr->od_enabled) {
-                        size = sprintf(buf, "%s: \n", "OD_SCLK");
+                        size = sprintf(buf, "%s:\n", "OD_SCLK");
                         for (i = 0; i < odn_sclk_table->num_of_pl; i++)
-                                size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
-                                        i, odn_sclk_table->entries[i].clock / 100,
+                                size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
+                                        i, odn_sclk_table->entries[i].clock/100,
                                         odn_sclk_table->entries[i].vddc);
                 }
                 break;
         case OD_MCLK:
                 if (hwmgr->od_enabled) {
-                        size = sprintf(buf, "%s: \n", "OD_MCLK");
+                        size = sprintf(buf, "%s:\n", "OD_MCLK");
                         for (i = 0; i < odn_mclk_table->num_of_pl; i++)
-                                size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
-                                        i, odn_mclk_table->entries[i].clock / 100,
+                                size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
+                                        i, odn_mclk_table->entries[i].clock/100,
                                         odn_mclk_table->entries[i].vddc);
                 }
                 break;
+        case OD_RANGE:
+                if (hwmgr->od_enabled) {
+                        size = sprintf(buf, "%s:\n", "OD_RANGE");
+                        size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
+                                data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
+                                hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
+                        size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
+                                data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
+                                hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
+                        size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
+                                data->odn_dpm_table.min_vddc,
+                                data->odn_dpm_table.max_vddc);
+                }
+                break;
         default:
                 break;
         }