diff options
author | Jitendra Bhivare <jitendra.bhivare@broadcom.com> | 2016-08-19 05:50:10 -0400 |
---|---|---|
committer | Martin K. Petersen <martin.petersen@oracle.com> | 2016-08-23 22:42:43 -0400 |
commit | a30950161954a046421b26fbf55a873ae27b1e25 (patch) | |
tree | 15667456bdc2b2f478485c0876a5e3e646c989e6 | |
parent | 1f5e847acbda0c46f66a7571bd62a9970a248b27 (diff) |
scsi: be2iscsi: Remove isr_lock and dead code
todo_mcc_cq is not needed as only MCC work is queued.
todo_cq is not used at all.
Rename functions to be consistent.
Signed-off-by: Jitendra Bhivare <jitendra.bhivare@broadcom.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
-rw-r--r-- | drivers/scsi/be2iscsi/be.h | 2 | ||||
-rw-r--r-- | drivers/scsi/be2iscsi/be_main.c | 132 | ||||
-rw-r--r-- | drivers/scsi/be2iscsi/be_main.h | 2 |
3 files changed, 49 insertions, 87 deletions
diff --git a/drivers/scsi/be2iscsi/be.h b/drivers/scsi/be2iscsi/be.h index ee5ace873535..621291ab0214 100644 --- a/drivers/scsi/be2iscsi/be.h +++ b/drivers/scsi/be2iscsi/be.h | |||
@@ -100,7 +100,7 @@ struct be_eq_obj { | |||
100 | struct be_queue_info q; | 100 | struct be_queue_info q; |
101 | struct beiscsi_hba *phba; | 101 | struct beiscsi_hba *phba; |
102 | struct be_queue_info *cq; | 102 | struct be_queue_info *cq; |
103 | struct work_struct work_cqs; /* Work Item */ | 103 | struct work_struct mcc_work; /* Work Item */ |
104 | struct irq_poll iopoll; | 104 | struct irq_poll iopoll; |
105 | }; | 105 | }; |
106 | 106 | ||
diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c index 0fbb80d3e090..6179c4e512a6 100644 --- a/drivers/scsi/be2iscsi/be_main.c +++ b/drivers/scsi/be2iscsi/be_main.c | |||
@@ -832,12 +832,11 @@ static void hwi_ring_eq_db(struct beiscsi_hba *phba, | |||
832 | static irqreturn_t be_isr_mcc(int irq, void *dev_id) | 832 | static irqreturn_t be_isr_mcc(int irq, void *dev_id) |
833 | { | 833 | { |
834 | struct beiscsi_hba *phba; | 834 | struct beiscsi_hba *phba; |
835 | struct be_eq_entry *eqe = NULL; | 835 | struct be_eq_entry *eqe; |
836 | struct be_queue_info *eq; | 836 | struct be_queue_info *eq; |
837 | struct be_queue_info *mcc; | 837 | struct be_queue_info *mcc; |
838 | unsigned int num_eq_processed; | 838 | unsigned int mcc_events; |
839 | struct be_eq_obj *pbe_eq; | 839 | struct be_eq_obj *pbe_eq; |
840 | unsigned long flags; | ||
841 | 840 | ||
842 | pbe_eq = dev_id; | 841 | pbe_eq = dev_id; |
843 | eq = &pbe_eq->q; | 842 | eq = &pbe_eq->q; |
@@ -845,27 +844,23 @@ static irqreturn_t be_isr_mcc(int irq, void *dev_id) | |||
845 | mcc = &phba->ctrl.mcc_obj.cq; | 844 | mcc = &phba->ctrl.mcc_obj.cq; |
846 | eqe = queue_tail_node(eq); | 845 | eqe = queue_tail_node(eq); |
847 | 846 | ||
848 | num_eq_processed = 0; | 847 | mcc_events = 0; |
849 | |||
850 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] | 848 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] |
851 | & EQE_VALID_MASK) { | 849 | & EQE_VALID_MASK) { |
852 | if (((eqe->dw[offsetof(struct amap_eq_entry, | 850 | if (((eqe->dw[offsetof(struct amap_eq_entry, |
853 | resource_id) / 32] & | 851 | resource_id) / 32] & |
854 | EQE_RESID_MASK) >> 16) == mcc->id) { | 852 | EQE_RESID_MASK) >> 16) == mcc->id) { |
855 | spin_lock_irqsave(&phba->isr_lock, flags); | 853 | mcc_events++; |
856 | pbe_eq->todo_mcc_cq = true; | ||
857 | spin_unlock_irqrestore(&phba->isr_lock, flags); | ||
858 | } | 854 | } |
859 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); | 855 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); |
860 | queue_tail_inc(eq); | 856 | queue_tail_inc(eq); |
861 | eqe = queue_tail_node(eq); | 857 | eqe = queue_tail_node(eq); |
862 | num_eq_processed++; | ||
863 | } | 858 | } |
864 | if (pbe_eq->todo_mcc_cq) | ||
865 | queue_work(phba->wq, &pbe_eq->work_cqs); | ||
866 | if (num_eq_processed) | ||
867 | hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1); | ||
868 | 859 | ||
860 | if (mcc_events) { | ||
861 | queue_work(phba->wq, &pbe_eq->mcc_work); | ||
862 | hwi_ring_eq_db(phba, eq->id, 1, mcc_events, 1, 1); | ||
863 | } | ||
869 | return IRQ_HANDLED; | 864 | return IRQ_HANDLED; |
870 | } | 865 | } |
871 | 866 | ||
@@ -884,7 +879,6 @@ static irqreturn_t be_isr_msix(int irq, void *dev_id) | |||
884 | eq = &pbe_eq->q; | 879 | eq = &pbe_eq->q; |
885 | 880 | ||
886 | phba = pbe_eq->phba; | 881 | phba = pbe_eq->phba; |
887 | |||
888 | /* disable interrupt till iopoll completes */ | 882 | /* disable interrupt till iopoll completes */ |
889 | hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1); | 883 | hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1); |
890 | irq_poll_sched(&pbe_eq->iopoll); | 884 | irq_poll_sched(&pbe_eq->iopoll); |
@@ -902,14 +896,13 @@ static irqreturn_t be_isr(int irq, void *dev_id) | |||
902 | struct beiscsi_hba *phba; | 896 | struct beiscsi_hba *phba; |
903 | struct hwi_controller *phwi_ctrlr; | 897 | struct hwi_controller *phwi_ctrlr; |
904 | struct hwi_context_memory *phwi_context; | 898 | struct hwi_context_memory *phwi_context; |
905 | struct be_eq_entry *eqe = NULL; | 899 | struct be_eq_entry *eqe; |
906 | struct be_queue_info *eq; | 900 | struct be_queue_info *eq; |
907 | struct be_queue_info *mcc; | 901 | struct be_queue_info *mcc; |
908 | unsigned long flags, index; | 902 | unsigned int mcc_events, io_events; |
909 | unsigned int num_mcceq_processed, num_ioeq_processed; | ||
910 | struct be_ctrl_info *ctrl; | 903 | struct be_ctrl_info *ctrl; |
911 | struct be_eq_obj *pbe_eq; | 904 | struct be_eq_obj *pbe_eq; |
912 | int isr; | 905 | int isr, rearm; |
913 | 906 | ||
914 | phba = dev_id; | 907 | phba = dev_id; |
915 | ctrl = &phba->ctrl; | 908 | ctrl = &phba->ctrl; |
@@ -924,44 +917,35 @@ static irqreturn_t be_isr(int irq, void *dev_id) | |||
924 | 917 | ||
925 | eq = &phwi_context->be_eq[0].q; | 918 | eq = &phwi_context->be_eq[0].q; |
926 | mcc = &phba->ctrl.mcc_obj.cq; | 919 | mcc = &phba->ctrl.mcc_obj.cq; |
927 | index = 0; | ||
928 | eqe = queue_tail_node(eq); | 920 | eqe = queue_tail_node(eq); |
929 | 921 | ||
930 | num_ioeq_processed = 0; | 922 | io_events = 0; |
931 | num_mcceq_processed = 0; | 923 | mcc_events = 0; |
932 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] | 924 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] |
933 | & EQE_VALID_MASK) { | 925 | & EQE_VALID_MASK) { |
934 | if (((eqe->dw[offsetof(struct amap_eq_entry, | 926 | if (((eqe->dw[offsetof(struct amap_eq_entry, |
935 | resource_id) / 32] & | 927 | resource_id) / 32] & EQE_RESID_MASK) >> 16) == mcc->id) |
936 | EQE_RESID_MASK) >> 16) == mcc->id) { | 928 | mcc_events++; |
937 | spin_lock_irqsave(&phba->isr_lock, flags); | 929 | else |
938 | pbe_eq->todo_mcc_cq = true; | 930 | io_events++; |
939 | spin_unlock_irqrestore(&phba->isr_lock, flags); | ||
940 | num_mcceq_processed++; | ||
941 | } else { | ||
942 | irq_poll_sched(&pbe_eq->iopoll); | ||
943 | num_ioeq_processed++; | ||
944 | } | ||
945 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); | 931 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); |
946 | queue_tail_inc(eq); | 932 | queue_tail_inc(eq); |
947 | eqe = queue_tail_node(eq); | 933 | eqe = queue_tail_node(eq); |
948 | } | 934 | } |
949 | if (num_ioeq_processed || num_mcceq_processed) { | 935 | if (!io_events && !mcc_events) |
950 | if (pbe_eq->todo_mcc_cq) | ||
951 | queue_work(phba->wq, &pbe_eq->work_cqs); | ||
952 | |||
953 | if ((num_mcceq_processed) && (!num_ioeq_processed)) | ||
954 | hwi_ring_eq_db(phba, eq->id, 0, | ||
955 | (num_ioeq_processed + | ||
956 | num_mcceq_processed) , 1, 1); | ||
957 | else | ||
958 | hwi_ring_eq_db(phba, eq->id, 0, | ||
959 | (num_ioeq_processed + | ||
960 | num_mcceq_processed), 0, 1); | ||
961 | |||
962 | return IRQ_HANDLED; | ||
963 | } else | ||
964 | return IRQ_NONE; | 936 | return IRQ_NONE; |
937 | |||
938 | /* no need to rearm if interrupt is only for IOs */ | ||
939 | rearm = 0; | ||
940 | if (mcc_events) { | ||
941 | queue_work(phba->wq, &pbe_eq->mcc_work); | ||
942 | /* rearm for MCCQ */ | ||
943 | rearm = 1; | ||
944 | } | ||
945 | if (io_events) | ||
946 | irq_poll_sched(&pbe_eq->iopoll); | ||
947 | hwi_ring_eq_db(phba, eq->id, 0, (io_events + mcc_events), rearm, 1); | ||
948 | return IRQ_HANDLED; | ||
965 | } | 949 | } |
966 | 950 | ||
967 | 951 | ||
@@ -2055,6 +2039,18 @@ void beiscsi_process_mcc_cq(struct beiscsi_hba *phba) | |||
2055 | hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1); | 2039 | hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1); |
2056 | } | 2040 | } |
2057 | 2041 | ||
2042 | static void beiscsi_mcc_work(struct work_struct *work) | ||
2043 | { | ||
2044 | struct be_eq_obj *pbe_eq; | ||
2045 | struct beiscsi_hba *phba; | ||
2046 | |||
2047 | pbe_eq = container_of(work, struct be_eq_obj, mcc_work); | ||
2048 | phba = pbe_eq->phba; | ||
2049 | beiscsi_process_mcc_cq(phba); | ||
2050 | /* rearm EQ for further interrupts */ | ||
2051 | hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); | ||
2052 | } | ||
2053 | |||
2058 | /** | 2054 | /** |
2059 | * beiscsi_process_cq()- Process the Completion Queue | 2055 | * beiscsi_process_cq()- Process the Completion Queue |
2060 | * @pbe_eq: Event Q on which the Completion has come | 2056 | * @pbe_eq: Event Q on which the Completion has come |
@@ -2244,46 +2240,15 @@ proc_next_cqe: | |||
2244 | return total; | 2240 | return total; |
2245 | } | 2241 | } |
2246 | 2242 | ||
2247 | void beiscsi_process_all_cqs(struct work_struct *work) | ||
2248 | { | ||
2249 | unsigned long flags; | ||
2250 | struct hwi_controller *phwi_ctrlr; | ||
2251 | struct hwi_context_memory *phwi_context; | ||
2252 | struct beiscsi_hba *phba; | ||
2253 | struct be_eq_obj *pbe_eq = | ||
2254 | container_of(work, struct be_eq_obj, work_cqs); | ||
2255 | |||
2256 | phba = pbe_eq->phba; | ||
2257 | phwi_ctrlr = phba->phwi_ctrlr; | ||
2258 | phwi_context = phwi_ctrlr->phwi_ctxt; | ||
2259 | |||
2260 | if (pbe_eq->todo_mcc_cq) { | ||
2261 | spin_lock_irqsave(&phba->isr_lock, flags); | ||
2262 | pbe_eq->todo_mcc_cq = false; | ||
2263 | spin_unlock_irqrestore(&phba->isr_lock, flags); | ||
2264 | beiscsi_process_mcc_cq(phba); | ||
2265 | } | ||
2266 | |||
2267 | if (pbe_eq->todo_cq) { | ||
2268 | spin_lock_irqsave(&phba->isr_lock, flags); | ||
2269 | pbe_eq->todo_cq = false; | ||
2270 | spin_unlock_irqrestore(&phba->isr_lock, flags); | ||
2271 | beiscsi_process_cq(pbe_eq, BE2_MAX_NUM_CQ_PROC); | ||
2272 | } | ||
2273 | |||
2274 | /* rearm EQ for further interrupts */ | ||
2275 | hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); | ||
2276 | } | ||
2277 | |||
2278 | static int be_iopoll(struct irq_poll *iop, int budget) | 2243 | static int be_iopoll(struct irq_poll *iop, int budget) |
2279 | { | 2244 | { |
2280 | unsigned int ret, num_eq_processed; | 2245 | unsigned int ret, io_events; |
2281 | struct beiscsi_hba *phba; | 2246 | struct beiscsi_hba *phba; |
2282 | struct be_eq_obj *pbe_eq; | 2247 | struct be_eq_obj *pbe_eq; |
2283 | struct be_eq_entry *eqe = NULL; | 2248 | struct be_eq_entry *eqe = NULL; |
2284 | struct be_queue_info *eq; | 2249 | struct be_queue_info *eq; |
2285 | 2250 | ||
2286 | num_eq_processed = 0; | 2251 | io_events = 0; |
2287 | pbe_eq = container_of(iop, struct be_eq_obj, iopoll); | 2252 | pbe_eq = container_of(iop, struct be_eq_obj, iopoll); |
2288 | phba = pbe_eq->phba; | 2253 | phba = pbe_eq->phba; |
2289 | eq = &pbe_eq->q; | 2254 | eq = &pbe_eq->q; |
@@ -2294,10 +2259,10 @@ static int be_iopoll(struct irq_poll *iop, int budget) | |||
2294 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); | 2259 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); |
2295 | queue_tail_inc(eq); | 2260 | queue_tail_inc(eq); |
2296 | eqe = queue_tail_node(eq); | 2261 | eqe = queue_tail_node(eq); |
2297 | num_eq_processed++; | 2262 | io_events++; |
2298 | } | 2263 | } |
2299 | 2264 | ||
2300 | hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1); | 2265 | hwi_ring_eq_db(phba, eq->id, 1, io_events, 0, 1); |
2301 | 2266 | ||
2302 | ret = beiscsi_process_cq(pbe_eq, budget); | 2267 | ret = beiscsi_process_cq(pbe_eq, budget); |
2303 | pbe_eq->cq_count += ret; | 2268 | pbe_eq->cq_count += ret; |
@@ -5578,7 +5543,7 @@ static void beiscsi_eeh_resume(struct pci_dev *pdev) | |||
5578 | i = (phba->msix_enabled) ? i : 0; | 5543 | i = (phba->msix_enabled) ? i : 0; |
5579 | /* Work item for MCC handling */ | 5544 | /* Work item for MCC handling */ |
5580 | pbe_eq = &phwi_context->be_eq[i]; | 5545 | pbe_eq = &phwi_context->be_eq[i]; |
5581 | INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs); | 5546 | INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work); |
5582 | 5547 | ||
5583 | ret = beiscsi_init_irqs(phba); | 5548 | ret = beiscsi_init_irqs(phba); |
5584 | if (ret < 0) { | 5549 | if (ret < 0) { |
@@ -5682,7 +5647,6 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev, | |||
5682 | 5647 | ||
5683 | spin_lock_init(&phba->io_sgl_lock); | 5648 | spin_lock_init(&phba->io_sgl_lock); |
5684 | spin_lock_init(&phba->mgmt_sgl_lock); | 5649 | spin_lock_init(&phba->mgmt_sgl_lock); |
5685 | spin_lock_init(&phba->isr_lock); | ||
5686 | spin_lock_init(&phba->async_pdu_lock); | 5650 | spin_lock_init(&phba->async_pdu_lock); |
5687 | ret = mgmt_get_fw_config(&phba->ctrl, phba); | 5651 | ret = mgmt_get_fw_config(&phba->ctrl, phba); |
5688 | if (ret != 0) { | 5652 | if (ret != 0) { |
@@ -5754,7 +5718,7 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev, | |||
5754 | i = (phba->msix_enabled) ? i : 0; | 5718 | i = (phba->msix_enabled) ? i : 0; |
5755 | /* Work item for MCC handling */ | 5719 | /* Work item for MCC handling */ |
5756 | pbe_eq = &phwi_context->be_eq[i]; | 5720 | pbe_eq = &phwi_context->be_eq[i]; |
5757 | INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs); | 5721 | INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work); |
5758 | 5722 | ||
5759 | ret = beiscsi_init_irqs(phba); | 5723 | ret = beiscsi_init_irqs(phba); |
5760 | if (ret < 0) { | 5724 | if (ret < 0) { |
diff --git a/drivers/scsi/be2iscsi/be_main.h b/drivers/scsi/be2iscsi/be_main.h index 30a4606d9a3b..90cdc10c01fb 100644 --- a/drivers/scsi/be2iscsi/be_main.h +++ b/drivers/scsi/be2iscsi/be_main.h | |||
@@ -378,7 +378,6 @@ struct beiscsi_hba { | |||
378 | struct sgl_handle **eh_sgl_hndl_base; | 378 | struct sgl_handle **eh_sgl_hndl_base; |
379 | spinlock_t io_sgl_lock; | 379 | spinlock_t io_sgl_lock; |
380 | spinlock_t mgmt_sgl_lock; | 380 | spinlock_t mgmt_sgl_lock; |
381 | spinlock_t isr_lock; | ||
382 | spinlock_t async_pdu_lock; | 381 | spinlock_t async_pdu_lock; |
383 | unsigned int age; | 382 | unsigned int age; |
384 | struct list_head hba_queue; | 383 | struct list_head hba_queue; |
@@ -845,7 +844,6 @@ struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid, | |||
845 | void | 844 | void |
846 | free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle); | 845 | free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle); |
847 | 846 | ||
848 | void beiscsi_process_all_cqs(struct work_struct *work); | ||
849 | void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, | 847 | void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, |
850 | struct iscsi_task *task); | 848 | struct iscsi_task *task); |
851 | 849 | ||