aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLucile Quirion <lucile.quirion@savoirfairelinux.com>2016-08-09 11:15:44 -0400
committerShawn Guo <shawnguo@kernel.org>2016-08-15 09:28:47 -0400
commita2f11455316420c749151da3fcb2a89f3cfb51bb (patch)
tree7a931dcdbc63d8cd919370f616c2fa8cf5123a7b
parent1a7723b1ec42767396ce5001a63cf89e11201598 (diff)
ARM: dts: TS-4900: add basic device tree
These device trees add support for TS-4900 by Technologic Systems. More details here: http://wiki.embeddedarm.com/wiki/TS-4900 Signed-off-by: Lucile Quirion <lucile.quirion@savoirfairelinux.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/imx6dl-ts4900.dts49
-rw-r--r--arch/arm/boot/dts/imx6q-ts4900.dts53
-rw-r--r--arch/arm/boot/dts/imx6qdl-ts4900.dtsi481
4 files changed, 585 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index dbd6a35b2a92..606a8b632d27 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -340,6 +340,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
340 imx6dl-sabreauto.dtb \ 340 imx6dl-sabreauto.dtb \
341 imx6dl-sabrelite.dtb \ 341 imx6dl-sabrelite.dtb \
342 imx6dl-sabresd.dtb \ 342 imx6dl-sabresd.dtb \
343 imx6dl-ts4900.dtb \
343 imx6dl-tx6dl-comtft.dtb \ 344 imx6dl-tx6dl-comtft.dtb \
344 imx6dl-tx6s-8034.dtb \ 345 imx6dl-tx6s-8034.dtb \
345 imx6dl-tx6s-8035.dtb \ 346 imx6dl-tx6s-8035.dtb \
@@ -384,6 +385,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
384 imx6q-sabresd.dtb \ 385 imx6q-sabresd.dtb \
385 imx6q-sbc6x.dtb \ 386 imx6q-sbc6x.dtb \
386 imx6q-tbs2910.dtb \ 387 imx6q-tbs2910.dtb \
388 imx6q-ts4900.dtb \
387 imx6q-tx6q-1010.dtb \ 389 imx6q-tx6q-1010.dtb \
388 imx6q-tx6q-1010-comtft.dtb \ 390 imx6q-tx6q-1010-comtft.dtb \
389 imx6q-tx6q-1020.dtb \ 391 imx6q-tx6q-1020.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/imx6dl-ts4900.dts
new file mode 100644
index 000000000000..85eddeb30e21
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-ts4900.dts
@@ -0,0 +1,49 @@
1/*
2 * Copyright 2015 Technologic Systems
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6dl.dtsi"
44#include "imx6qdl-ts4900.dtsi"
45
46/ {
47 model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)";
48 compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl";
49};
diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/imx6q-ts4900.dts
new file mode 100644
index 000000000000..9b81ebc8b0d4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-ts4900.dts
@@ -0,0 +1,53 @@
1/*
2 * Copyright 2015 Technologic Systems
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6q.dtsi"
44#include "imx6qdl-ts4900.dtsi"
45
46/ {
47 model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)";
48 compatible = "technologic,imx6q-ts4900", "fsl,imx6q";
49};
50
51&sata {
52 status = "okay";
53};
diff --git a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi
new file mode 100644
index 000000000000..5c26b26e851a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi
@@ -0,0 +1,481 @@
1/*
2 * Copyright 2015 Technologic Systems
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/interrupt-controller/irq.h>
44
45/ {
46 aliases {
47 ethernet0 = &fec;
48 };
49
50 leds {
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_leds1>;
53 compatible = "gpio-leds";
54
55 green-led {
56 label = "green-led";
57 gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
58 default-state = "on";
59 };
60
61 red-led {
62 label = "red-led";
63 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
64 default-state = "off";
65 };
66 };
67
68 reg_3p3v: regulator-3p3v {
69 compatible = "regulator-fixed";
70 regulator-name = "3p3v";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 };
74
75 reg_usb_otg_vbus: regulator-usb-otg-vbus {
76 compatible = "regulator-fixed";
77 regulator-name = "usb_otg_vbus";
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
81 enable-active-high;
82 };
83};
84
85&can1 {
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_flexcan1>;
88 status = "okay";
89};
90
91&can2 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_flexcan2>;
94 status = "okay";
95};
96
97&ecspi1 {
98 fsl,spi-num-chipselects = <1>;
99 cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_ecspi1>;
102 status = "okay";
103
104 n25q064: flash@0 {
105 compatible = "micron,n25q064", "jedec,spi-nor";
106 reg = <0>;
107 spi-max-frequency = <20000000>;
108 };
109};
110
111&ecspi2 {
112 fsl,spi-num-chipselects = <1>;
113 cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_ecspi2>;
116 status = "okay";
117};
118
119&fec {
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_enet>;
122 phy-mode = "rgmii";
123 status = "okay";
124};
125
126&i2c1 {
127 clock-frequency = <100000>;
128 pinctrl-names = "default", "gpio";
129 pinctrl-0 = <&pinctrl_i2c1>;
130 pinctrl-1 = <&pinctrl_i2c1_gpio>;
131 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
132 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
133 status = "okay";
134
135 isl12022: rtc@6f {
136 compatible = "isil,isl12022";
137 reg = <0x6f>;
138 };
139
140 gpio8: gpio@28 {
141 compatible = "technologic,ts4900-gpio";
142 reg = <0x28>;
143 #gpio-cells = <2>;
144 gpio-controller;
145 ngpio = <32>;
146 };
147};
148
149&i2c2 {
150 clock-frequency = <100000>;
151 pinctrl-names = "default", "gpio";
152 pinctrl-0 = <&pinctrl_i2c2>;
153 pinctrl-1 = <&pinctrl_i2c2_gpio>;
154 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
155 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
156 status = "okay";
157};
158
159&iomuxc {
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_hog>;
162
163 pinctrl_ecspi1: ecspi1grp {
164 fsl,pins = <
165 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
166 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
167 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
168 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */
169 >;
170 };
171
172 pinctrl_ecspi2: ecspi2grp {
173 fsl,pins = <
174 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
175 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
176 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
177 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */
178 MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */
179 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */
180 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */
181 MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */
182 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */
183 >;
184 };
185
186 pinctrl_enet: enetgrp {
187 fsl,pins = <
188 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
189 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
190 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
191 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
192 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
193 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
194 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
195 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
196 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
197 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
198 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
199 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
200 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
201 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
202 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8
203 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
204 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */
205 >;
206 };
207
208 pinctrl_flexcan1: flexcan1grp {
209 fsl,pins = <
210 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
211 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
212 >;
213 };
214
215 pinctrl_flexcan2: flexcan2grp {
216 fsl,pins = <
217 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1
218 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1
219 >;
220 };
221
222 pinctrl_hog: hoggrp {
223 fsl,pins = <
224 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */
225 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */
226 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */
227 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */
228 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */
229 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */
230 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */
231 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */
232 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */
233 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */
234 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */
235 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */
236 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */
237 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */
238 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */
239 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */
240 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */
241 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */
242 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */
243 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */
244 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */
245 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */
246 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */
247 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */
248 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */
249 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */
250 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */
251 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */
252 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */
253 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */
254 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */
255 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */
256 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */
257 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */
258 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */
259 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */
260 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */
261 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */
262 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */
263 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */
264 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */
265 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */
266 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */
267 MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */
268 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */
269 MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */
270 MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */
271 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */
272 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */
273 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */
274 MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */
275 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1
276 MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1
277 MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1
278 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1
279 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
280 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1
281 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1
282 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1
283 MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1
284 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1
285 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1
286 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1
287 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1
288 MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1
289 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1
290 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1
291 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1
292 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1
293 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1
294 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1
295 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1
296 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1
297 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1
298 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1
299 >;
300 };
301
302 pinctrl_i2c1: i2c1grp {
303 fsl,pins = <
304 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
305 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
306 >;
307 };
308
309 pinctrl_i2c1_gpio: i2c1gpiogrp {
310 fsl,pins = <
311 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
312 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
313 >;
314 };
315
316 pinctrl_i2c2: i2c2grp {
317 fsl,pins = <
318 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
319 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
320 >;
321 };
322
323 pinctrl_i2c2_gpio: i2c2gpiogrp {
324 fsl,pins = <
325 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
326 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
327 >;
328 };
329
330 pinctrl_leds1: leds1grp {
331 fsl,pins = <
332 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */
333 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */
334 >;
335 };
336
337 pinctrl_uart1: uart1grp {
338 fsl,pins = <
339 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
340 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
341 >;
342 };
343
344 pinctrl_uart2: uart2grp {
345 fsl,pins = <
346 MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
347 MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
348 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
349 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
350 >;
351 };
352
353 pinctrl_uart3: uart3grp {
354 fsl,pins = <
355 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
356 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
357 >;
358 };
359
360 pinctrl_uart4: uart4grp {
361 fsl,pins = <
362 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
363 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
364 >;
365 };
366
367 pinctrl_uart5: uart5grp {
368 fsl,pins = <
369 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
370 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
371 >;
372 };
373
374 pinctrl_usbotg: usbotggrp {
375 fsl,pins = <
376 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
377 >;
378 };
379
380 pinctrl_usdhc1: usdhc1grp {
381 fsl,pins = <
382 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
383 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
384 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
385 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
386 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
387 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
388 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */
389 >;
390 };
391
392 pinctrl_usdhc2: usdhc2grp {
393 fsl,pins = <
394 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
395 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
396 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
397 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
398 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
399 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
400 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */
401 >;
402 };
403
404 pinctrl_usdhc3: usdhc3grp {
405 fsl,pins = <
406 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
407 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
408 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
409 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
410 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
411 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
412 >;
413 };
414};
415
416&pcie {
417 status = "okay";
418};
419
420&uart1 {
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_uart1>;
423 status = "okay";
424};
425
426&uart2 {
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_uart2>;
429 uart-has-rtscts;
430 status = "okay";
431};
432
433&uart3 {
434 pinctrl-names = "default";
435 pinctrl-0 = <&pinctrl_uart3>;
436 status = "okay";
437};
438
439&uart4 {
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_uart4>;
442 status = "okay";
443};
444
445&uart5 {
446 pinctrl-names = "default";
447 pinctrl-0 = <&pinctrl_uart5>;
448 status = "okay";
449};
450
451&usbh1 {
452 status = "okay";
453};
454
455&usbotg {
456 vbus-supply = <&reg_usb_otg_vbus>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_usbotg>;
459 disable-over-current;
460 status = "okay";
461};
462
463/* SD */
464&usdhc2 {
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_usdhc2>;
467 vmmc-supply = <&reg_3p3v>;
468 bus-width = <4>;
469 fsl,wp-controller;
470 status = "okay";
471};
472
473/* eMMC */
474&usdhc3 {
475 pinctrl-names = "default";
476 pinctrl-0 = <&pinctrl_usdhc3>;
477 vmmc-supply = <&reg_3p3v>;
478 bus-width = <4>;
479 non-removable;
480 status = "okay";
481};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-17 22:00:41 -0400