drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number

The number of GFXHUB/MMHUB may be expanded in later ASICs.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

16 files changed, 46 insertions, 46 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 24c3c05e2fb7..4726b5176417 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -3060,12 +3060,12 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
         switch (args->in.op) {
         case AMDGPU_VM_OP_RESERVE_VMID:
                 /* current, we only have requirement to reserve vmid from gfxhub */
-                r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
+                r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
                 if (r)
                         return r;
                 break;
         case AMDGPU_VM_OP_UNRESERVE_VMID:
-                amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
+                amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
                 break;
         default:
                 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 489a162ca620..8e78b81d0a05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -101,8 +101,8 @@ struct amdgpu_bo_list_entry;
 
 /* max number of VMHUB */
 #define AMDGPU_MAX_VMHUBS                       2
-#define AMDGPU_GFXHUB                           0
-#define AMDGPU_MMHUB                            1
+#define AMDGPU_GFXHUB_0                         0
+#define AMDGPU_MMHUB_0                          1
 
 /* hardcode that limit for now */
 #define AMDGPU_VA_RESERVED_SIZE                 (1ULL << 20)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ec11bfded772..5b5ea9b41c12 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1603,7 +1603,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
         /* XXX SH_MEM regs */
         /* where to put LDS, scratch, GPUVM in FSA64 space */
         mutex_lock(&adev->srbm_mutex);
-        for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
+        for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
                 nv_grbm_select(adev, 0, 0, 0, i);
                 /* CP and shaders */
                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
@@ -5005,7 +5005,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
         .align_mask = 0xff,
         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
         .support_64bit_ptrs = true,
-        .vmhub = AMDGPU_GFXHUB,
+        .vmhub = AMDGPU_GFXHUB_0,
         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
@@ -5056,7 +5056,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
         .align_mask = 0xff,
         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
         .support_64bit_ptrs = true,
-        .vmhub = AMDGPU_GFXHUB,
+        .vmhub = AMDGPU_GFXHUB_0,
         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
@@ -5089,7 +5089,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
         .align_mask = 0xff,
         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
         .support_64bit_ptrs = true,
-        .vmhub = AMDGPU_GFXHUB,
+        .vmhub = AMDGPU_GFXHUB_0,
         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index f4c4eea62526..eca9ea779649 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1936,7 +1936,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
         /* XXX SH_MEM regs */
         /* where to put LDS, scratch, GPUVM in FSA64 space */
         mutex_lock(&adev->srbm_mutex);
-        for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
+        for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
                 soc15_grbm_select(adev, 0, 0, 0, i);
                 /* CP and shaders */
                 if (i == 0) {
@@ -5174,7 +5174,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
         .align_mask = 0xff,
         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
         .support_64bit_ptrs = true,
-        .vmhub = AMDGPU_GFXHUB,
+        .vmhub = AMDGPU_GFXHUB_0,
         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
@@ -5225,7 +5225,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
         .align_mask = 0xff,
         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
         .support_64bit_ptrs = true,
-        .vmhub = AMDGPU_GFXHUB,
+        .vmhub = AMDGPU_GFXHUB_0,
         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
@@ -5260,7 +5260,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
         .align_mask = 0xff,
         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
         .support_64bit_ptrs = true,
-        .vmhub = AMDGPU_GFXHUB,
+        .vmhub = AMDGPU_GFXHUB_0,
         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 15986748f59f..6ce37ce77d14 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -357,7 +357,7 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 
 void gfxhub_v1_0_init(struct amdgpu_device *adev)
 {
-        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
+        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 
         hub->ctx0_ptb_addr_lo32 =
                 SOC15_REG_OFFSET(GC, 0,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index d605b4963f8a..8ce5bf5feb45 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -333,7 +333,7 @@ void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
 
 void gfxhub_v2_0_init(struct amdgpu_device *adev)
 {
-        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
+        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 
         hub->ctx0_ptb_addr_lo32 =
                 SOC15_REG_OFFSET(GC, 0,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 8a1e23c6eee6..f52823ffc7fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -62,7 +62,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
         struct amdgpu_vmhub *hub;
         u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
 
-        bits[AMDGPU_GFXHUB] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+        bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
                 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
                 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
                 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
@@ -70,7 +70,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
                 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 
-        bits[AMDGPU_MMHUB] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+        bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
@@ -81,39 +81,39 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
         switch (state) {
         case AMDGPU_IRQ_STATE_DISABLE:
                 /* MM HUB */
-                hub = &adev->vmhub[AMDGPU_MMHUB];
+                hub = &adev->vmhub[AMDGPU_MMHUB_0];
                 for (i = 0; i < 16; i++) {
                         reg = hub->vm_context0_cntl + i;
                         tmp = RREG32(reg);
-                        tmp &= ~bits[AMDGPU_MMHUB];
+                        tmp &= ~bits[AMDGPU_MMHUB_0];
                         WREG32(reg, tmp);
                 }
 
                 /* GFX HUB */
-                hub = &adev->vmhub[AMDGPU_GFXHUB];
+                hub = &adev->vmhub[AMDGPU_GFXHUB_0];
                 for (i = 0; i < 16; i++) {
                         reg = hub->vm_context0_cntl + i;
                         tmp = RREG32(reg);
-                        tmp &= ~bits[AMDGPU_GFXHUB];
+                        tmp &= ~bits[AMDGPU_GFXHUB_0];
                         WREG32(reg, tmp);
                 }
                 break;
         case AMDGPU_IRQ_STATE_ENABLE:
                 /* MM HUB */
-                hub = &adev->vmhub[AMDGPU_MMHUB];
+                hub = &adev->vmhub[AMDGPU_MMHUB_0];
                 for (i = 0; i < 16; i++) {
                         reg = hub->vm_context0_cntl + i;
                         tmp = RREG32(reg);
-                        tmp |= bits[AMDGPU_MMHUB];
+                        tmp |= bits[AMDGPU_MMHUB_0];
                         WREG32(reg, tmp);
                 }
 
                 /* GFX HUB */
-                hub = &adev->vmhub[AMDGPU_GFXHUB];
+                hub = &adev->vmhub[AMDGPU_GFXHUB_0];
                 for (i = 0; i < 16; i++) {
                         reg = hub->vm_context0_cntl + i;
                         tmp = RREG32(reg);
-                        tmp |= bits[AMDGPU_GFXHUB];
+                        tmp |= bits[AMDGPU_GFXHUB_0];
                         WREG32(reg, tmp);
                 }
                 break;
@@ -244,11 +244,11 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev,
 
         mutex_lock(&adev->mman.gtt_window_lock);
 
-        gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0);
+        gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
         if (!adev->mman.buffer_funcs_enabled ||
             !adev->ib_pool_ready ||
             adev->in_gpu_reset) {
-                gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0);
+                gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
                 mutex_unlock(&adev->mman.gtt_window_lock);
                 return;
         }
@@ -313,7 +313,7 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid
         struct amdgpu_device *adev = ring->adev;
         uint32_t reg;
 
-        if (ring->funcs->vmhub == AMDGPU_GFXHUB)
+        if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
         else
                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
@@ -682,8 +682,8 @@ static int gmc_v10_0_sw_init(void *handle)
          * amdgpu graphics/compute will use VMIDs 1-7
          * amdkfd will use VMIDs 8-15
          */
-        adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
-        adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
+        adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
+        adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
 
         amdgpu_vm_manager_init(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index d1ede86cbdb0..ad45d633b147 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -480,7 +480,7 @@ static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
         struct amdgpu_device *adev = ring->adev;
         uint32_t reg;
 
-        if (ring->funcs->vmhub == AMDGPU_GFXHUB)
+        if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
         else
                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
@@ -1082,8 +1082,8 @@ static int gmc_v9_0_sw_init(void *handle)
          * amdgpu graphics/compute will use VMIDs 1-7
          * amdkfd will use VMIDs 8-15
          */
-        adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
-        adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
+        adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
+        adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
 
         amdgpu_vm_manager_init(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index dc5ce03034d3..3abd02bd5222 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -407,7 +407,7 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 
 void mmhub_v1_0_init(struct amdgpu_device *adev)
 {
-        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
+        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 
         hub->ctx0_ptb_addr_lo32 =
                 SOC15_REG_OFFSET(MMHUB, 0,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index a5c7ed1f37eb..d2f4775299c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -324,7 +324,7 @@ void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 
 void mmhub_v2_0_init(struct amdgpu_device *adev)
 {
-        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
+        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 
         hub->ctx0_ptb_addr_lo32 =
                 SOC15_REG_OFFSET(MMHUB, 0,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 4428018672d3..4654846fb580 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2133,7 +2133,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
         .align_mask = 0xf,
         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
         .support_64bit_ptrs = true,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = sdma_v4_0_ring_get_rptr,
         .get_wptr = sdma_v4_0_ring_get_wptr,
         .set_wptr = sdma_v4_0_ring_set_wptr,
@@ -2165,7 +2165,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
         .align_mask = 0xf,
         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
         .support_64bit_ptrs = true,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = sdma_v4_0_ring_get_rptr,
         .get_wptr = sdma_v4_0_page_ring_get_wptr,
         .set_wptr = sdma_v4_0_page_ring_set_wptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 89893261f145..3e536140bfd6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1554,7 +1554,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
         .align_mask = 0xf,
         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
         .support_64bit_ptrs = true,
-        .vmhub = AMDGPU_GFXHUB,
+        .vmhub = AMDGPU_GFXHUB_0,
         .get_rptr = sdma_v5_0_ring_get_rptr,
         .get_wptr = sdma_v5_0_ring_get_wptr,
         .set_wptr = sdma_v5_0_ring_set_wptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index a6bfe7651d07..01f658fa72c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1763,7 +1763,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
         .align_mask = 0xf,
         .support_64bit_ptrs = false,
         .no_user_fence = true,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = uvd_v7_0_ring_get_rptr,
         .get_wptr = uvd_v7_0_ring_get_wptr,
         .set_wptr = uvd_v7_0_ring_set_wptr,
@@ -1796,7 +1796,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
         .nop = HEVC_ENC_CMD_NO_OP,
         .support_64bit_ptrs = false,
         .no_user_fence = true,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index eafbe8d8248d..683701cf7270 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -1070,7 +1070,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {
         .nop = VCE_CMD_NO_OP,
         .support_64bit_ptrs = false,
         .no_user_fence = true,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = vce_v4_0_ring_get_rptr,
         .get_wptr = vce_v4_0_ring_get_wptr,
         .set_wptr = vce_v4_0_ring_set_wptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index dde22b7d140d..916e32533c1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -2198,7 +2198,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
         .align_mask = 0xf,
         .support_64bit_ptrs = false,
         .no_user_fence = true,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
@@ -2232,7 +2232,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
         .nop = VCN_ENC_CMD_NO_OP,
         .support_64bit_ptrs = false,
         .no_user_fence = true,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
@@ -2264,7 +2264,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
         .nop = PACKET0(0x81ff, 0),
         .support_64bit_ptrs = false,
         .no_user_fence = true,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .extra_dw = 64,
         .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
         .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 988c0adaca91..c701868dd57f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -2131,7 +2131,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
         .type = AMDGPU_RING_TYPE_VCN_DEC,
         .align_mask = 0xf,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = vcn_v2_0_dec_ring_get_rptr,
         .get_wptr = vcn_v2_0_dec_ring_get_wptr,
         .set_wptr = vcn_v2_0_dec_ring_set_wptr,
@@ -2162,7 +2162,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
         .type = AMDGPU_RING_TYPE_VCN_ENC,
         .align_mask = 0x3f,
         .nop = VCN_ENC_CMD_NO_OP,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = vcn_v2_0_enc_ring_get_rptr,
         .get_wptr = vcn_v2_0_enc_ring_get_wptr,
         .set_wptr = vcn_v2_0_enc_ring_set_wptr,
@@ -2191,7 +2191,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
 static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = {
         .type = AMDGPU_RING_TYPE_VCN_JPEG,
         .align_mask = 0xf,
-        .vmhub = AMDGPU_MMHUB,
+        .vmhub = AMDGPU_MMHUB_0,
         .get_rptr = vcn_v2_0_jpeg_ring_get_rptr,
         .get_wptr = vcn_v2_0_jpeg_ring_get_wptr,
         .set_wptr = vcn_v2_0_jpeg_ring_set_wptr,