MIPS: BMIPS: Use interrupt-controller node name

Changes node names of the interrupt-controller device nodes to interrupt-controller instead of label strings. Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jonas Gorski <jonas.gorski@gmail.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: MIPS Mailing List <linux-mips@linux-mips.org> Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14004/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
author: Jaedon Shin <jaedon.shin@gmail.com> 2016-08-18 22:52:30 -0400
committer: Ralf Baechle <ralf@linux-mips.org> 2016-10-06 11:31:02 -0400
commit: a2c510a2d0418ce15cd739d0a177ce53b06e5695 (patch)
tree: e9fe7512d66b8b1e31d352a1cbe9eec9fdc119cb
parent: cfc8be04c36a1a6546b6f9cb8f02fd9f215c9d38 (diff)
8 files changed, 38 insertions, 38 deletions
diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi
index 746ed06c85de..bbd00f65ce39 100644
--- a/arch/mips/boot/dts/brcm/bcm7125.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
@@ -26,7 +26,7 @@
                uart0 = &uart0;
        };
-        cpu_intc: cpu_intc {
+        cpu_intc: interrupt-controller {
                #address-cells = <0>;
                compatible = "mti,cpu-interrupt-controller";
@@ -55,7 +55,7 @@
                compatible = "simple-bus";
                ranges = <0 0x10000000 0x01000000>;
-                periph_intc: periph_intc@441400 {
+                periph_intc: interrupt-controller@441400 {
                        compatible = "brcm,bcm7038-l1-intc";
                        reg = <0x441400 0x30>, <0x441600 0x30>;
@@ -66,7 +66,7 @@
                        interrupts = <2>, <3>;
                };
-                sun_l2_intc: sun_l2_intc@401800 {
+                sun_l2_intc: interrupt-controller@401800 {
                        compatible = "brcm,l2-intc";
                        reg = <0x401800 0x30>;
                        interrupt-controller;
@@ -87,7 +87,7 @@
                                                     "avd_0", "jtag_0";
                };
-                upg_irq0_intc: upg_irq0_intc@406780 {
+                upg_irq0_intc: interrupt-controller@406780 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x406780 0x8>;
diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi
index 72d9cffa8927..4bbcc95f1c15 100644
--- a/arch/mips/boot/dts/brcm/bcm7346.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -26,7 +26,7 @@
                uart0 = &uart0;
        };
-        cpu_intc: cpu_intc {
+        cpu_intc: interrupt-controller {
                #address-cells = <0>;
                compatible = "mti,cpu-interrupt-controller";
@@ -55,7 +55,7 @@
                compatible = "simple-bus";
                ranges = <0 0x10000000 0x01000000>;
-                periph_intc: periph_intc@411400 {
+                periph_intc: interrupt-controller@411400 {
                        compatible = "brcm,bcm7038-l1-intc";
                        reg = <0x411400 0x30>, <0x411600 0x30>;
@@ -66,7 +66,7 @@
                        interrupts = <2>, <3>;
                };
-                sun_l2_intc: sun_l2_intc@403000 {
+                sun_l2_intc: interrupt-controller@403000 {
                        compatible = "brcm,l2-intc";
                        reg = <0x403000 0x30>;
                        interrupt-controller;
@@ -87,7 +87,7 @@
                                                     "jtag_0", "svd_0";
                };
-                upg_irq0_intc: upg_irq0_intc@406780 {
+                upg_irq0_intc: interrupt-controller@406780 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x406780 0x8>;
@@ -102,7 +102,7 @@
                        interrupt-names = "upg_main", "upg_bsc";
                };
-                upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
+                upg_aon_irq0_intc: interrupt-controller@408b80 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x408b80 0x8>;
diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi
index 7f78bfab164b..3e42535c8d29 100644
--- a/arch/mips/boot/dts/brcm/bcm7358.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi
@@ -20,7 +20,7 @@
                uart0 = &uart0;
        };
-        cpu_intc: cpu_intc {
+        cpu_intc: interrupt-controller {
                #address-cells = <0>;
                compatible = "mti,cpu-interrupt-controller";
@@ -49,7 +49,7 @@
                compatible = "simple-bus";
                ranges = <0 0x10000000 0x01000000>;
-                periph_intc: periph_intc@411400 {
+                periph_intc: interrupt-controller@411400 {
                        compatible = "brcm,bcm7038-l1-intc";
                        reg = <0x411400 0x30>;
@@ -60,7 +60,7 @@
                        interrupts = <2>;
                };
-                sun_l2_intc: sun_l2_intc@403000 {
+                sun_l2_intc: interrupt-controller@403000 {
                        compatible = "brcm,l2-intc";
                        reg = <0x403000 0x30>;
                        interrupt-controller;
@@ -81,7 +81,7 @@
                                                     "avd_0", "jtag_0";
                };
-                upg_irq0_intc: upg_irq0_intc@406600 {
+                upg_irq0_intc: interrupt-controller@406600 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x406600 0x8>;
@@ -96,7 +96,7 @@
                        interrupt-names = "upg_main", "upg_bsc";
                };
-                upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
+                upg_aon_irq0_intc: interrupt-controller@408b80 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x408b80 0x8>;
diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi
index 64b9fd90941d..112a5571c596 100644
--- a/arch/mips/boot/dts/brcm/bcm7360.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
@@ -20,7 +20,7 @@
                uart0 = &uart0;
        };
-        cpu_intc: cpu_intc {
+        cpu_intc: interrupt-controller {
                #address-cells = <0>;
                compatible = "mti,cpu-interrupt-controller";
@@ -49,7 +49,7 @@
                compatible = "simple-bus";
                ranges = <0 0x10000000 0x01000000>;
-                periph_intc: periph_intc@411400 {
+                periph_intc: interrupt-controller@411400 {
                        compatible = "brcm,bcm7038-l1-intc";
                        reg = <0x411400 0x30>;
@@ -60,7 +60,7 @@
                        interrupts = <2>;
                };
-                sun_l2_intc: sun_l2_intc@403000 {
+                sun_l2_intc: interrupt-controller@403000 {
                        compatible = "brcm,l2-intc";
                        reg = <0x403000 0x30>;
                        interrupt-controller;
@@ -81,7 +81,7 @@
                                                     "avd_0", "jtag_0";
                };
-                upg_irq0_intc: upg_irq0_intc@406600 {
+                upg_irq0_intc: interrupt-controller@406600 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x406600 0x8>;
@@ -96,7 +96,7 @@
                        interrupt-names = "upg_main", "upg_bsc";
                };
-                upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
+                upg_aon_irq0_intc: interrupt-controller@408b80 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x408b80 0x8>;
diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi
index 784d58725227..34abfb0b07e7 100644
--- a/arch/mips/boot/dts/brcm/bcm7362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -26,7 +26,7 @@
                uart0 = &uart0;
        };
-        cpu_intc: cpu_intc {
+        cpu_intc: interrupt-controller {
                #address-cells = <0>;
                compatible = "mti,cpu-interrupt-controller";
@@ -55,7 +55,7 @@
                compatible = "simple-bus";
                ranges = <0 0x10000000 0x01000000>;
-                periph_intc: periph_intc@411400 {
+                periph_intc: interrupt-controller@411400 {
                        compatible = "brcm,bcm7038-l1-intc";
                        reg = <0x411400 0x30>, <0x411600 0x30>;
@@ -66,7 +66,7 @@
                        interrupts = <2>, <3>;
                };
-                sun_l2_intc: sun_l2_intc@403000 {
+                sun_l2_intc: interrupt-controller@403000 {
                        compatible = "brcm,l2-intc";
                        reg = <0x403000 0x30>;
                        interrupt-controller;
@@ -87,7 +87,7 @@
                                                     "avd_0", "jtag_0";
                };
-                upg_irq0_intc: upg_irq0_intc@406600 {
+                upg_irq0_intc: interrupt-controller@406600 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x406600 0x8>;
@@ -102,7 +102,7 @@
                        interrupt-names = "upg_main", "upg_bsc";
                };
-                upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
+                upg_aon_irq0_intc: interrupt-controller@408b80 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x408b80 0x8>;
diff --git a/arch/mips/boot/dts/brcm/bcm7420.dtsi b/arch/mips/boot/dts/brcm/bcm7420.dtsi
index 0d391d77c780..b143723c674e 100644
--- a/arch/mips/boot/dts/brcm/bcm7420.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7420.dtsi
@@ -26,7 +26,7 @@
                uart0 = &uart0;
        };
-        cpu_intc: cpu_intc {
+        cpu_intc: interrupt-controller {
                #address-cells = <0>;
                compatible = "mti,cpu-interrupt-controller";
@@ -55,7 +55,7 @@
                compatible = "simple-bus";
                ranges = <0 0x10000000 0x01000000>;
-                periph_intc: periph_intc@441400 {
+                periph_intc: interrupt-controller@441400 {
                        compatible = "brcm,bcm7038-l1-intc";
                        reg = <0x441400 0x30>, <0x441600 0x30>;
@@ -66,7 +66,7 @@
                        interrupts = <2>, <3>;
                };
-                sun_l2_intc: sun_l2_intc@401800 {
+                sun_l2_intc: interrupt-controller@401800 {
                        compatible = "brcm,l2-intc";
                        reg = <0x401800 0x30>;
                        interrupt-controller;
@@ -88,7 +88,7 @@
                                                     "jtag_0";
                };
-                upg_irq0_intc: upg_irq0_intc@406780 {
+                upg_irq0_intc: interrupt-controller@406780 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x406780 0x8>;
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index 7124c9822479..2488d2f61f60 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -26,7 +26,7 @@
                uart0 = &uart0;
        };
-        cpu_intc: cpu_intc {
+        cpu_intc: interrupt-controller {
                #address-cells = <0>;
                compatible = "mti,cpu-interrupt-controller";
@@ -55,7 +55,7 @@
                compatible = "simple-bus";
                ranges = <0 0x10000000 0x01000000>;
-                periph_intc: periph_intc@41a400 {
+                periph_intc: interrupt-controller@41a400 {
                        compatible = "brcm,bcm7038-l1-intc";
                        reg = <0x41a400 0x30>, <0x41a600 0x30>;
@@ -66,7 +66,7 @@
                        interrupts = <2>, <3>;
                };
-                sun_l2_intc: sun_l2_intc@403000 {
+                sun_l2_intc: interrupt-controller@403000 {
                        compatible = "brcm,l2-intc";
                        reg = <0x403000 0x30>;
                        interrupt-controller;
@@ -89,7 +89,7 @@
                                                     "vice_0";
                };
-                upg_irq0_intc: upg_irq0_intc@406780 {
+                upg_irq0_intc: interrupt-controller@406780 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x406780 0x8>;
@@ -104,7 +104,7 @@
                        interrupt-names = "upg_main", "upg_bsc";
                };
-                upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {
+                upg_aon_irq0_intc: interrupt-controller@409480 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x409480 0x8>;
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index a3648964be3a..19fa259b968b 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -38,7 +38,7 @@
                uart0 = &uart0;
        };
-        cpu_intc: cpu_intc {
+        cpu_intc: interrupt-controller {
                #address-cells = <0>;
                compatible = "mti,cpu-interrupt-controller";
@@ -67,7 +67,7 @@
                compatible = "simple-bus";
                ranges = <0 0x10000000 0x01000000>;
-                periph_intc: periph_intc@41b500 {
+                periph_intc: interrupt-controller@41b500 {
                        compatible = "brcm,bcm7038-l1-intc";
                        reg = <0x41b500 0x40>, <0x41b600 0x40>,
                                <0x41b700 0x40>, <0x41b800 0x40>;
@@ -79,7 +79,7 @@
                        interrupts = <2>, <3>, <2>, <3>;
                };
-                sun_l2_intc: sun_l2_intc@403000 {
+                sun_l2_intc: interrupt-controller@403000 {
                        compatible = "brcm,l2-intc";
                        reg = <0x403000 0x30>;
                        interrupt-controller;
@@ -104,7 +104,7 @@
                                                     "scpu";
                };
-                upg_irq0_intc: upg_irq0_intc@406780 {
+                upg_irq0_intc: interrupt-controller@406780 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x406780 0x8>;
@@ -119,7 +119,7 @@
                        interrupt-names = "upg_main", "upg_bsc";
                };
-                upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {
+                upg_aon_irq0_intc: interrupt-controller@409480 {
                        compatible = "brcm,bcm7120-l2-intc";
                        reg = <0x409480 0x8>;
author	Jaedon Shin <jaedon.shin@gmail.com>	2016-08-18 22:52:30 -0400
committer	Ralf Baechle <ralf@linux-mips.org>	2016-10-06 11:31:02 -0400
commit	a2c510a2d0418ce15cd739d0a177ce53b06e5695 (patch)
tree	e9fe7512d66b8b1e31d352a1cbe9eec9fdc119cb
parent	cfc8be04c36a1a6546b6f9cb8f02fd9f215c9d38 (diff)

diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi index 746ed06c85de..bbd00f65ce39 100644 --- a/arch/mips/boot/dts/brcm/bcm7125.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
@@ -26,7 +26,7 @@
26	uart0 = &uart0;	26	uart0 = &uart0;
27	};	27	};
28		28
29	cpu_intc: cpu_intc {	29	cpu_intc: interrupt-controller {
30	#address-cells = <0>;	30	#address-cells = <0>;
31	compatible = "mti,cpu-interrupt-controller";	31	compatible = "mti,cpu-interrupt-controller";
32		32
@@ -55,7 +55,7 @@
55	compatible = "simple-bus";	55	compatible = "simple-bus";
56	ranges = <0 0x10000000 0x01000000>;	56	ranges = <0 0x10000000 0x01000000>;
57		57
58	periph_intc: periph_intc@441400 {	58	periph_intc: interrupt-controller@441400 {
59	compatible = "brcm,bcm7038-l1-intc";	59	compatible = "brcm,bcm7038-l1-intc";
60	reg = <0x441400 0x30>, <0x441600 0x30>;	60	reg = <0x441400 0x30>, <0x441600 0x30>;
61		61
@@ -66,7 +66,7 @@
66	interrupts = <2>, <3>;	66	interrupts = <2>, <3>;
67	};	67	};
68		68
69	sun_l2_intc: sun_l2_intc@401800 {	69	sun_l2_intc: interrupt-controller@401800 {
70	compatible = "brcm,l2-intc";	70	compatible = "brcm,l2-intc";
71	reg = <0x401800 0x30>;	71	reg = <0x401800 0x30>;
72	interrupt-controller;	72	interrupt-controller;
@@ -87,7 +87,7 @@
87	"avd_0", "jtag_0";	87	"avd_0", "jtag_0";
88	};	88	};
89		89
90	upg_irq0_intc: upg_irq0_intc@406780 {	90	upg_irq0_intc: interrupt-controller@406780 {
91	compatible = "brcm,bcm7120-l2-intc";	91	compatible = "brcm,bcm7120-l2-intc";
92	reg = <0x406780 0x8>;	92	reg = <0x406780 0x8>;
93		93


diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi index 72d9cffa8927..4bbcc95f1c15 100644 --- a/arch/mips/boot/dts/brcm/bcm7346.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -26,7 +26,7 @@
26	uart0 = &uart0;	26	uart0 = &uart0;
27	};	27	};
28		28
29	cpu_intc: cpu_intc {	29	cpu_intc: interrupt-controller {
30	#address-cells = <0>;	30	#address-cells = <0>;
31	compatible = "mti,cpu-interrupt-controller";	31	compatible = "mti,cpu-interrupt-controller";
32		32
@@ -55,7 +55,7 @@
55	compatible = "simple-bus";	55	compatible = "simple-bus";
56	ranges = <0 0x10000000 0x01000000>;	56	ranges = <0 0x10000000 0x01000000>;
57		57
58	periph_intc: periph_intc@411400 {	58	periph_intc: interrupt-controller@411400 {
59	compatible = "brcm,bcm7038-l1-intc";	59	compatible = "brcm,bcm7038-l1-intc";
60	reg = <0x411400 0x30>, <0x411600 0x30>;	60	reg = <0x411400 0x30>, <0x411600 0x30>;
61		61
@@ -66,7 +66,7 @@
66	interrupts = <2>, <3>;	66	interrupts = <2>, <3>;
67	};	67	};
68		68
69	sun_l2_intc: sun_l2_intc@403000 {	69	sun_l2_intc: interrupt-controller@403000 {
70	compatible = "brcm,l2-intc";	70	compatible = "brcm,l2-intc";
71	reg = <0x403000 0x30>;	71	reg = <0x403000 0x30>;
72	interrupt-controller;	72	interrupt-controller;
@@ -87,7 +87,7 @@
87	"jtag_0", "svd_0";	87	"jtag_0", "svd_0";
88	};	88	};
89		89
90	upg_irq0_intc: upg_irq0_intc@406780 {	90	upg_irq0_intc: interrupt-controller@406780 {
91	compatible = "brcm,bcm7120-l2-intc";	91	compatible = "brcm,bcm7120-l2-intc";
92	reg = <0x406780 0x8>;	92	reg = <0x406780 0x8>;
93		93
@@ -102,7 +102,7 @@
102	interrupt-names = "upg_main", "upg_bsc";	102	interrupt-names = "upg_main", "upg_bsc";
103	};	103	};
104		104
105	upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {	105	upg_aon_irq0_intc: interrupt-controller@408b80 {
106	compatible = "brcm,bcm7120-l2-intc";	106	compatible = "brcm,bcm7120-l2-intc";
107	reg = <0x408b80 0x8>;	107	reg = <0x408b80 0x8>;
108		108


diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi index 7f78bfab164b..3e42535c8d29 100644 --- a/arch/mips/boot/dts/brcm/bcm7358.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi
@@ -20,7 +20,7 @@
20	uart0 = &uart0;	20	uart0 = &uart0;
21	};	21	};
22		22
23	cpu_intc: cpu_intc {	23	cpu_intc: interrupt-controller {
24	#address-cells = <0>;	24	#address-cells = <0>;
25	compatible = "mti,cpu-interrupt-controller";	25	compatible = "mti,cpu-interrupt-controller";
26		26
@@ -49,7 +49,7 @@
49	compatible = "simple-bus";	49	compatible = "simple-bus";
50	ranges = <0 0x10000000 0x01000000>;	50	ranges = <0 0x10000000 0x01000000>;
51		51
52	periph_intc: periph_intc@411400 {	52	periph_intc: interrupt-controller@411400 {
53	compatible = "brcm,bcm7038-l1-intc";	53	compatible = "brcm,bcm7038-l1-intc";
54	reg = <0x411400 0x30>;	54	reg = <0x411400 0x30>;
55		55
@@ -60,7 +60,7 @@
60	interrupts = <2>;	60	interrupts = <2>;
61	};	61	};
62		62
63	sun_l2_intc: sun_l2_intc@403000 {	63	sun_l2_intc: interrupt-controller@403000 {
64	compatible = "brcm,l2-intc";	64	compatible = "brcm,l2-intc";
65	reg = <0x403000 0x30>;	65	reg = <0x403000 0x30>;
66	interrupt-controller;	66	interrupt-controller;
@@ -81,7 +81,7 @@
81	"avd_0", "jtag_0";	81	"avd_0", "jtag_0";
82	};	82	};
83		83
84	upg_irq0_intc: upg_irq0_intc@406600 {	84	upg_irq0_intc: interrupt-controller@406600 {
85	compatible = "brcm,bcm7120-l2-intc";	85	compatible = "brcm,bcm7120-l2-intc";
86	reg = <0x406600 0x8>;	86	reg = <0x406600 0x8>;
87		87
@@ -96,7 +96,7 @@
96	interrupt-names = "upg_main", "upg_bsc";	96	interrupt-names = "upg_main", "upg_bsc";
97	};	97	};
98		98
99	upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {	99	upg_aon_irq0_intc: interrupt-controller@408b80 {
100	compatible = "brcm,bcm7120-l2-intc";	100	compatible = "brcm,bcm7120-l2-intc";
101	reg = <0x408b80 0x8>;	101	reg = <0x408b80 0x8>;
102		102


diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi index 64b9fd90941d..112a5571c596 100644 --- a/arch/mips/boot/dts/brcm/bcm7360.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
@@ -20,7 +20,7 @@
20	uart0 = &uart0;	20	uart0 = &uart0;
21	};	21	};
22		22
23	cpu_intc: cpu_intc {	23	cpu_intc: interrupt-controller {
24	#address-cells = <0>;	24	#address-cells = <0>;
25	compatible = "mti,cpu-interrupt-controller";	25	compatible = "mti,cpu-interrupt-controller";
26		26
@@ -49,7 +49,7 @@
49	compatible = "simple-bus";	49	compatible = "simple-bus";
50	ranges = <0 0x10000000 0x01000000>;	50	ranges = <0 0x10000000 0x01000000>;
51		51
52	periph_intc: periph_intc@411400 {	52	periph_intc: interrupt-controller@411400 {
53	compatible = "brcm,bcm7038-l1-intc";	53	compatible = "brcm,bcm7038-l1-intc";
54	reg = <0x411400 0x30>;	54	reg = <0x411400 0x30>;
55		55
@@ -60,7 +60,7 @@
60	interrupts = <2>;	60	interrupts = <2>;
61	};	61	};
62		62
63	sun_l2_intc: sun_l2_intc@403000 {	63	sun_l2_intc: interrupt-controller@403000 {
64	compatible = "brcm,l2-intc";	64	compatible = "brcm,l2-intc";
65	reg = <0x403000 0x30>;	65	reg = <0x403000 0x30>;
66	interrupt-controller;	66	interrupt-controller;
@@ -81,7 +81,7 @@
81	"avd_0", "jtag_0";	81	"avd_0", "jtag_0";
82	};	82	};
83		83
84	upg_irq0_intc: upg_irq0_intc@406600 {	84	upg_irq0_intc: interrupt-controller@406600 {
85	compatible = "brcm,bcm7120-l2-intc";	85	compatible = "brcm,bcm7120-l2-intc";
86	reg = <0x406600 0x8>;	86	reg = <0x406600 0x8>;
87		87
@@ -96,7 +96,7 @@
96	interrupt-names = "upg_main", "upg_bsc";	96	interrupt-names = "upg_main", "upg_bsc";
97	};	97	};
98		98
99	upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {	99	upg_aon_irq0_intc: interrupt-controller@408b80 {
100	compatible = "brcm,bcm7120-l2-intc";	100	compatible = "brcm,bcm7120-l2-intc";
101	reg = <0x408b80 0x8>;	101	reg = <0x408b80 0x8>;
102		102


diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi index 784d58725227..34abfb0b07e7 100644 --- a/arch/mips/boot/dts/brcm/bcm7362.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -26,7 +26,7 @@
26	uart0 = &uart0;	26	uart0 = &uart0;
27	};	27	};
28		28
29	cpu_intc: cpu_intc {	29	cpu_intc: interrupt-controller {
30	#address-cells = <0>;	30	#address-cells = <0>;
31	compatible = "mti,cpu-interrupt-controller";	31	compatible = "mti,cpu-interrupt-controller";
32		32
@@ -55,7 +55,7 @@
55	compatible = "simple-bus";	55	compatible = "simple-bus";
56	ranges = <0 0x10000000 0x01000000>;	56	ranges = <0 0x10000000 0x01000000>;
57		57
58	periph_intc: periph_intc@411400 {	58	periph_intc: interrupt-controller@411400 {
59	compatible = "brcm,bcm7038-l1-intc";	59	compatible = "brcm,bcm7038-l1-intc";
60	reg = <0x411400 0x30>, <0x411600 0x30>;	60	reg = <0x411400 0x30>, <0x411600 0x30>;
61		61
@@ -66,7 +66,7 @@
66	interrupts = <2>, <3>;	66	interrupts = <2>, <3>;
67	};	67	};
68		68
69	sun_l2_intc: sun_l2_intc@403000 {	69	sun_l2_intc: interrupt-controller@403000 {
70	compatible = "brcm,l2-intc";	70	compatible = "brcm,l2-intc";
71	reg = <0x403000 0x30>;	71	reg = <0x403000 0x30>;
72	interrupt-controller;	72	interrupt-controller;
@@ -87,7 +87,7 @@
87	"avd_0", "jtag_0";	87	"avd_0", "jtag_0";
88	};	88	};
89		89
90	upg_irq0_intc: upg_irq0_intc@406600 {	90	upg_irq0_intc: interrupt-controller@406600 {
91	compatible = "brcm,bcm7120-l2-intc";	91	compatible = "brcm,bcm7120-l2-intc";
92	reg = <0x406600 0x8>;	92	reg = <0x406600 0x8>;
93		93
@@ -102,7 +102,7 @@
102	interrupt-names = "upg_main", "upg_bsc";	102	interrupt-names = "upg_main", "upg_bsc";
103	};	103	};
104		104
105	upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {	105	upg_aon_irq0_intc: interrupt-controller@408b80 {
106	compatible = "brcm,bcm7120-l2-intc";	106	compatible = "brcm,bcm7120-l2-intc";
107	reg = <0x408b80 0x8>;	107	reg = <0x408b80 0x8>;
108		108


diff --git a/arch/mips/boot/dts/brcm/bcm7420.dtsi b/arch/mips/boot/dts/brcm/bcm7420.dtsi index 0d391d77c780..b143723c674e 100644 --- a/arch/mips/boot/dts/brcm/bcm7420.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7420.dtsi
@@ -26,7 +26,7 @@
26	uart0 = &uart0;	26	uart0 = &uart0;
27	};	27	};
28		28
29	cpu_intc: cpu_intc {	29	cpu_intc: interrupt-controller {
30	#address-cells = <0>;	30	#address-cells = <0>;
31	compatible = "mti,cpu-interrupt-controller";	31	compatible = "mti,cpu-interrupt-controller";
32		32
@@ -55,7 +55,7 @@
55	compatible = "simple-bus";	55	compatible = "simple-bus";
56	ranges = <0 0x10000000 0x01000000>;	56	ranges = <0 0x10000000 0x01000000>;
57		57
58	periph_intc: periph_intc@441400 {	58	periph_intc: interrupt-controller@441400 {
59	compatible = "brcm,bcm7038-l1-intc";	59	compatible = "brcm,bcm7038-l1-intc";
60	reg = <0x441400 0x30>, <0x441600 0x30>;	60	reg = <0x441400 0x30>, <0x441600 0x30>;
61		61
@@ -66,7 +66,7 @@
66	interrupts = <2>, <3>;	66	interrupts = <2>, <3>;
67	};	67	};
68		68
69	sun_l2_intc: sun_l2_intc@401800 {	69	sun_l2_intc: interrupt-controller@401800 {
70	compatible = "brcm,l2-intc";	70	compatible = "brcm,l2-intc";
71	reg = <0x401800 0x30>;	71	reg = <0x401800 0x30>;
72	interrupt-controller;	72	interrupt-controller;
@@ -88,7 +88,7 @@
88	"jtag_0";	88	"jtag_0";
89	};	89	};
90		90
91	upg_irq0_intc: upg_irq0_intc@406780 {	91	upg_irq0_intc: interrupt-controller@406780 {
92	compatible = "brcm,bcm7120-l2-intc";	92	compatible = "brcm,bcm7120-l2-intc";
93	reg = <0x406780 0x8>;	93	reg = <0x406780 0x8>;
94		94


diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi index 7124c9822479..2488d2f61f60 100644 --- a/arch/mips/boot/dts/brcm/bcm7425.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -26,7 +26,7 @@
26	uart0 = &uart0;	26	uart0 = &uart0;
27	};	27	};
28		28
29	cpu_intc: cpu_intc {	29	cpu_intc: interrupt-controller {
30	#address-cells = <0>;	30	#address-cells = <0>;
31	compatible = "mti,cpu-interrupt-controller";	31	compatible = "mti,cpu-interrupt-controller";
32		32
@@ -55,7 +55,7 @@
55	compatible = "simple-bus";	55	compatible = "simple-bus";
56	ranges = <0 0x10000000 0x01000000>;	56	ranges = <0 0x10000000 0x01000000>;
57		57
58	periph_intc: periph_intc@41a400 {	58	periph_intc: interrupt-controller@41a400 {
59	compatible = "brcm,bcm7038-l1-intc";	59	compatible = "brcm,bcm7038-l1-intc";
60	reg = <0x41a400 0x30>, <0x41a600 0x30>;	60	reg = <0x41a400 0x30>, <0x41a600 0x30>;
61		61
@@ -66,7 +66,7 @@
66	interrupts = <2>, <3>;	66	interrupts = <2>, <3>;
67	};	67	};
68		68
69	sun_l2_intc: sun_l2_intc@403000 {	69	sun_l2_intc: interrupt-controller@403000 {
70	compatible = "brcm,l2-intc";	70	compatible = "brcm,l2-intc";
71	reg = <0x403000 0x30>;	71	reg = <0x403000 0x30>;
72	interrupt-controller;	72	interrupt-controller;
@@ -89,7 +89,7 @@
89	"vice_0";	89	"vice_0";
90	};	90	};
91		91
92	upg_irq0_intc: upg_irq0_intc@406780 {	92	upg_irq0_intc: interrupt-controller@406780 {
93	compatible = "brcm,bcm7120-l2-intc";	93	compatible = "brcm,bcm7120-l2-intc";
94	reg = <0x406780 0x8>;	94	reg = <0x406780 0x8>;
95		95
@@ -104,7 +104,7 @@
104	interrupt-names = "upg_main", "upg_bsc";	104	interrupt-names = "upg_main", "upg_bsc";
105	};	105	};
106		106
107	upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {	107	upg_aon_irq0_intc: interrupt-controller@409480 {
108	compatible = "brcm,bcm7120-l2-intc";	108	compatible = "brcm,bcm7120-l2-intc";
109	reg = <0x409480 0x8>;	109	reg = <0x409480 0x8>;
110		110


diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi index a3648964be3a..19fa259b968b 100644 --- a/arch/mips/boot/dts/brcm/bcm7435.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -38,7 +38,7 @@
38	uart0 = &uart0;	38	uart0 = &uart0;
39	};	39	};
40		40
41	cpu_intc: cpu_intc {	41	cpu_intc: interrupt-controller {
42	#address-cells = <0>;	42	#address-cells = <0>;
43	compatible = "mti,cpu-interrupt-controller";	43	compatible = "mti,cpu-interrupt-controller";
44		44
@@ -67,7 +67,7 @@
67	compatible = "simple-bus";	67	compatible = "simple-bus";
68	ranges = <0 0x10000000 0x01000000>;	68	ranges = <0 0x10000000 0x01000000>;
69		69
70	periph_intc: periph_intc@41b500 {	70	periph_intc: interrupt-controller@41b500 {
71	compatible = "brcm,bcm7038-l1-intc";	71	compatible = "brcm,bcm7038-l1-intc";
72	reg = <0x41b500 0x40>, <0x41b600 0x40>,	72	reg = <0x41b500 0x40>, <0x41b600 0x40>,
73	<0x41b700 0x40>, <0x41b800 0x40>;	73	<0x41b700 0x40>, <0x41b800 0x40>;
@@ -79,7 +79,7 @@
79	interrupts = <2>, <3>, <2>, <3>;	79	interrupts = <2>, <3>, <2>, <3>;
80	};	80	};
81		81
82	sun_l2_intc: sun_l2_intc@403000 {	82	sun_l2_intc: interrupt-controller@403000 {
83	compatible = "brcm,l2-intc";	83	compatible = "brcm,l2-intc";
84	reg = <0x403000 0x30>;	84	reg = <0x403000 0x30>;
85	interrupt-controller;	85	interrupt-controller;
@@ -104,7 +104,7 @@
104	"scpu";	104	"scpu";
105	};	105	};
106		106
107	upg_irq0_intc: upg_irq0_intc@406780 {	107	upg_irq0_intc: interrupt-controller@406780 {
108	compatible = "brcm,bcm7120-l2-intc";	108	compatible = "brcm,bcm7120-l2-intc";
109	reg = <0x406780 0x8>;	109	reg = <0x406780 0x8>;
110		110
@@ -119,7 +119,7 @@
119	interrupt-names = "upg_main", "upg_bsc";	119	interrupt-names = "upg_main", "upg_bsc";
120	};	120	};
121		121
122	upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {	122	upg_aon_irq0_intc: interrupt-controller@409480 {
123	compatible = "brcm,bcm7120-l2-intc";	123	compatible = "brcm,bcm7120-l2-intc";
124	reg = <0x409480 0x8>;	124	reg = <0x409480 0x8>;
125		125