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authorTony Lindgren <tony@atomide.com>2016-09-14 19:27:28 -0400
committerTony Lindgren <tony@atomide.com>2016-09-14 19:27:28 -0400
commita2a2b8215621536a7620e31f36bede81bb86680b (patch)
tree94b2bcedaac82c999041e1e7b281ce46ed9f429f
parent3868b42f367d7a8d4246db03388fddc1d4db428f (diff)
parenta8dc7cb3e310a7ca4d4e06fe020d1b24b7f7ee3c (diff)
Merge branch 'am335x-cpufreq-regression' into omap-for-v4.9/dt-v2
Diffstat
-rw-r--r--arch/arm/boot/dts/am335x-boneblack.dts11
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi88
-rw-r--r--arch/arm/boot/dts/dra7.dtsi26
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi1
4 files changed, 18 insertions, 108 deletions
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index ca721670bd91..55c0e954b146 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -33,17 +33,6 @@
33 status = "okay"; 33 status = "okay";
34}; 34};
35 35
36&cpu0_opp_table {
37 /*
38 * All PG 2.0 silicon may not support 1GHz but some of the early
39 * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
40 * to support 1GHz OPP so enable it for PG 2.0 on this board.
41 */
42 oppnitro@1000000000 {
43 opp-supported-hw = <0x06 0x0100>;
44 };
45};
46
47&am33xx_pinmux { 36&am33xx_pinmux {
48 nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { 37 nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
49 pinctrl-single,pins = < 38 pinctrl-single,pins = <
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index eeef6bc8e410..194d884c9de1 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -45,9 +45,19 @@
45 device_type = "cpu"; 45 device_type = "cpu";
46 reg = <0>; 46 reg = <0>;
47 47
48 operating-points-v2 = <&cpu0_opp_table>; 48 /*
49 ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>; 49 * To consider voltage drop between PMIC and SoC,
50 ti,syscon-rev = <&scm_conf 0x600>; 50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
51 61
52 clocks = <&dpll_mpu_ck>; 62 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu"; 63 clock-names = "cpu";
@@ -56,78 +66,6 @@
56 }; 66 };
57 }; 67 };
58 68
59 cpu0_opp_table: opp_table0 {
60 compatible = "operating-points-v2";
61
62 /*
63 * The three following nodes are marked with opp-suspend
64 * because the can not be enabled simultaneously on a
65 * single SoC.
66 */
67 opp50@300000000 {
68 opp-hz = /bits/ 64 <300000000>;
69 opp-microvolt = <950000 931000 969000>;
70 opp-supported-hw = <0x06 0x0010>;
71 opp-suspend;
72 };
73
74 opp100@275000000 {
75 opp-hz = /bits/ 64 <275000000>;
76 opp-microvolt = <1100000 1078000 1122000>;
77 opp-supported-hw = <0x01 0x00FF>;
78 opp-suspend;
79 };
80
81 opp100@300000000 {
82 opp-hz = /bits/ 64 <300000000>;
83 opp-microvolt = <1100000 1078000 1122000>;
84 opp-supported-hw = <0x06 0x0020>;
85 opp-suspend;
86 };
87
88 opp100@500000000 {
89 opp-hz = /bits/ 64 <500000000>;
90 opp-microvolt = <1100000 1078000 1122000>;
91 opp-supported-hw = <0x01 0xFFFF>;
92 };
93
94 opp100@600000000 {
95 opp-hz = /bits/ 64 <600000000>;
96 opp-microvolt = <1100000 1078000 1122000>;
97 opp-supported-hw = <0x06 0x0040>;
98 };
99
100 opp120@600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <1200000 1176000 1224000>;
103 opp-supported-hw = <0x01 0xFFFF>;
104 };
105
106 opp120@720000000 {
107 opp-hz = /bits/ 64 <720000000>;
108 opp-microvolt = <1200000 1176000 1224000>;
109 opp-supported-hw = <0x06 0x0080>;
110 };
111
112 oppturbo@720000000 {
113 opp-hz = /bits/ 64 <720000000>;
114 opp-microvolt = <1260000 1234800 1285200>;
115 opp-supported-hw = <0x01 0xFFFF>;
116 };
117
118 oppturbo@800000000 {
119 opp-hz = /bits/ 64 <800000000>;
120 opp-microvolt = <1260000 1234800 1285200>;
121 opp-supported-hw = <0x06 0x0100>;
122 };
123
124 oppnitro@1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <1325000 1298500 1351500>;
127 opp-supported-hw = <0x04 0x0200>;
128 };
129 };
130
131 pmu { 69 pmu {
132 compatible = "arm,cortex-a8-pmu"; 70 compatible = "arm,cortex-a8-pmu";
133 interrupts = <3>; 71 interrupts = <3>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 147df90d2126..d4fcd68f6349 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -80,9 +80,11 @@
80 compatible = "arm,cortex-a15"; 80 compatible = "arm,cortex-a15";
81 reg = <0>; 81 reg = <0>;
82 82
83 operating-points-v2 = <&cpu0_opp_table>; 83 operating-points = <
84 ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>; 84 /* kHz uV */
85 ti,syscon-rev = <&scm_wkup 0x204>; 85 1000000 1060000
86 1176000 1160000
87 >;
86 88
87 clocks = <&dpll_mpu_ck>; 89 clocks = <&dpll_mpu_ck>;
88 clock-names = "cpu"; 90 clock-names = "cpu";
@@ -96,24 +98,6 @@
96 }; 98 };
97 }; 99 };
98 100
99 cpu0_opp_table: opp_table0 {
100 compatible = "operating-points-v2";
101 opp-shared;
102
103 opp_nom@1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <1060000 850000 1150000>;
106 opp-supported-hw = <0xFF 0x01>;
107 opp-suspend;
108 };
109
110 opp_od@1176000000 {
111 opp-hz = /bits/ 64 <1176000000>;
112 opp-microvolt = <1160000 885000 1160000>;
113 opp-supported-hw = <0xFF 0x02>;
114 };
115 };
116
117 /* 101 /*
118 * The soc node represents the soc top level view. It is used for IPs 102 * The soc node represents the soc top level view. It is used for IPs
119 * that are not memory mapped in the MPU view or for the MPU itself. 103 * that are not memory mapped in the MPU view or for the MPU itself.
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 8987b3e180a1..0a78347e6615 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -17,7 +17,6 @@
17 device_type = "cpu"; 17 device_type = "cpu";
18 compatible = "arm,cortex-a15"; 18 compatible = "arm,cortex-a15";
19 reg = <1>; 19 reg = <1>;
20 operating-points-v2 = <&cpu0_opp_table>;
21 }; 20 };
22 }; 21 };
23 22
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