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authorRob Clark <robdclark@gmail.com>2016-11-07 14:53:49 -0500
committerRob Clark <robdclark@gmail.com>2016-11-28 15:14:10 -0500
commita26ae754b0ac086151b84a2e8db10b3e98096f2d (patch)
treeab2e825b0508f266968c08a8e0b34331b9c3a81b
parent398efc46f80f312ef6414bc366ae141945869028 (diff)
drm/msm: update generated headers
Pull in a5xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat
-rw-r--r--drivers/gpu/drm/msm/adreno/a2xx.xml.h27
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx.xml.h38
-rw-r--r--drivers/gpu/drm/msm/adreno/a4xx.xml.h111
-rw-r--r--drivers/gpu/drm/msm/adreno/a5xx.xml.h3757
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_common.xml.h21
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h300
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi.xml.h2
-rw-r--r--drivers/gpu/drm/msm/dsi/mmss_cc.xml.h2
-rw-r--r--drivers/gpu/drm/msm/dsi/sfpb.xml.h2
-rw-r--r--drivers/gpu/drm/msm/edp/edp.xml.h2
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.xml.h2
-rw-r--r--drivers/gpu/drm/msm/hdmi/qfprom.xml.h2
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h2
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h14
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp_common.xml.h2
15 files changed, 4177 insertions, 107 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
index fee24297fb92..4be092f911f9 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -8,16 +8,17 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19 20
20Copyright (C) 2013-2015 by the following authors: 21Copyright (C) 2013-2016 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark) 22- Rob Clark <robdclark@gmail.com> (robclark)
22- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 23- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
23 24
@@ -206,12 +207,12 @@ enum a2xx_rb_copy_sample_select {
206}; 207};
207 208
208enum a2xx_rb_blend_opcode { 209enum a2xx_rb_blend_opcode {
209 BLEND_DST_PLUS_SRC = 0, 210 BLEND2_DST_PLUS_SRC = 0,
210 BLEND_SRC_MINUS_DST = 1, 211 BLEND2_SRC_MINUS_DST = 1,
211 BLEND_MIN_DST_SRC = 2, 212 BLEND2_MIN_DST_SRC = 2,
212 BLEND_MAX_DST_SRC = 3, 213 BLEND2_MAX_DST_SRC = 3,
213 BLEND_DST_MINUS_SRC = 4, 214 BLEND2_DST_MINUS_SRC = 4,
214 BLEND_DST_PLUS_SRC_BIAS = 5, 215 BLEND2_DST_PLUS_SRC_BIAS = 5,
215}; 216};
216 217
217enum adreno_mmu_clnt_beh { 218enum adreno_mmu_clnt_beh {
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
index 27dabd5e57fb..a066c8b9eccd 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19 20
20Copyright (C) 2013-2016 by the following authors: 21Copyright (C) 2013-2016 by the following authors:
@@ -129,10 +130,14 @@ enum a3xx_tex_fmt {
129 TFMT_Z16_UNORM = 9, 130 TFMT_Z16_UNORM = 9,
130 TFMT_X8Z24_UNORM = 10, 131 TFMT_X8Z24_UNORM = 10,
131 TFMT_Z32_FLOAT = 11, 132 TFMT_Z32_FLOAT = 11,
132 TFMT_NV12_UV_TILED = 17, 133 TFMT_UV_64X32 = 16,
133 TFMT_NV12_Y_TILED = 19, 134 TFMT_VU_64X32 = 17,
134 TFMT_NV12_UV = 21, 135 TFMT_Y_64X32 = 18,
135 TFMT_NV12_Y = 23, 136 TFMT_NV12_64X32 = 19,
137 TFMT_UV_LINEAR = 20,
138 TFMT_VU_LINEAR = 21,
139 TFMT_Y_LINEAR = 22,
140 TFMT_NV12_LINEAR = 23,
136 TFMT_I420_Y = 24, 141 TFMT_I420_Y = 24,
137 TFMT_I420_U = 26, 142 TFMT_I420_U = 26,
138 TFMT_I420_V = 27, 143 TFMT_I420_V = 27,
@@ -525,14 +530,6 @@ enum a3xx_uche_perfcounter_select {
525 UCHE_UCHEPERF_ACTIVE_CYCLES = 20, 530 UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
526}; 531};
527 532
528enum a3xx_rb_blend_opcode {
529 BLEND_DST_PLUS_SRC = 0,
530 BLEND_SRC_MINUS_DST = 1,
531 BLEND_DST_MINUS_SRC = 2,
532 BLEND_MIN_DST_SRC = 3,
533 BLEND_MAX_DST_SRC = 4,
534};
535
536enum a3xx_intp_mode { 533enum a3xx_intp_mode {
537 SMOOTH = 0, 534 SMOOTH = 0,
538 FLAT = 1, 535 FLAT = 1,
@@ -1393,13 +1390,14 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mod
1393{ 1390{
1394 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 1391 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
1395} 1392}
1393#define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE 0x00000080
1396#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1394#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
1397#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1395#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
1398static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1396static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1399{ 1397{
1400 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1398 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1401} 1399}
1402#define A3XX_RB_COPY_CONTROL_UNK12 0x00001000 1400#define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE 0x00001000
1403#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1401#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
1404#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1402#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
1405static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1403static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
@@ -1472,7 +1470,7 @@ static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1472{ 1470{
1473 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1471 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1474} 1472}
1475#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1473#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
1476#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1474#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1477 1475
1478#define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 1476#define REG_A3XX_RB_DEPTH_CLEAR 0x00002101
diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h
index 3220b91f559a..4ce21b902779 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19 20
20Copyright (C) 2013-2016 by the following authors: 21Copyright (C) 2013-2016 by the following authors:
@@ -46,6 +47,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46enum a4xx_color_fmt { 47enum a4xx_color_fmt {
47 RB4_A8_UNORM = 1, 48 RB4_A8_UNORM = 1,
48 RB4_R8_UNORM = 2, 49 RB4_R8_UNORM = 2,
50 RB4_R8_SNORM = 3,
51 RB4_R8_UINT = 4,
52 RB4_R8_SINT = 5,
49 RB4_R4G4B4A4_UNORM = 8, 53 RB4_R4G4B4A4_UNORM = 8,
50 RB4_R5G5B5A1_UNORM = 10, 54 RB4_R5G5B5A1_UNORM = 10,
51 RB4_R5G6B5_UNORM = 14, 55 RB4_R5G6B5_UNORM = 14,
@@ -89,17 +93,10 @@ enum a4xx_color_fmt {
89 93
90enum a4xx_tile_mode { 94enum a4xx_tile_mode {
91 TILE4_LINEAR = 0, 95 TILE4_LINEAR = 0,
96 TILE4_2 = 2,
92 TILE4_3 = 3, 97 TILE4_3 = 3,
93}; 98};
94 99
95enum a4xx_rb_blend_opcode {
96 BLEND_DST_PLUS_SRC = 0,
97 BLEND_SRC_MINUS_DST = 1,
98 BLEND_DST_MINUS_SRC = 2,
99 BLEND_MIN_DST_SRC = 3,
100 BLEND_MAX_DST_SRC = 4,
101};
102
103enum a4xx_vtx_fmt { 100enum a4xx_vtx_fmt {
104 VFMT4_32_FLOAT = 1, 101 VFMT4_32_FLOAT = 1,
105 VFMT4_32_32_FLOAT = 2, 102 VFMT4_32_32_FLOAT = 2,
@@ -940,6 +937,7 @@ static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
940{ 937{
941 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 938 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
942} 939}
940#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000
943 941
944#define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 942#define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
945#define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 943#define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
@@ -1043,7 +1041,7 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_b
1043} 1041}
1044#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1042#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
1045#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1043#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
1046static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 1044static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1047{ 1045{
1048 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1046 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1049} 1047}
@@ -1061,7 +1059,7 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb
1061} 1059}
1062#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1060#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
1063#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1061#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
1064static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 1062static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1065{ 1063{
1066 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1064 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1067} 1065}
@@ -1073,12 +1071,18 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r
1073} 1071}
1074 1072
1075#define REG_A4XX_RB_BLEND_RED 0x000020f0 1073#define REG_A4XX_RB_BLEND_RED 0x000020f0
1076#define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff 1074#define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff
1077#define A4XX_RB_BLEND_RED_UINT__SHIFT 0 1075#define A4XX_RB_BLEND_RED_UINT__SHIFT 0
1078static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 1076static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
1079{ 1077{
1080 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 1078 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
1081} 1079}
1080#define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
1081#define A4XX_RB_BLEND_RED_SINT__SHIFT 8
1082static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
1083{
1084 return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;
1085}
1082#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 1086#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1083#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 1087#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
1084static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 1088static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
@@ -1095,12 +1099,18 @@ static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1095} 1099}
1096 1100
1097#define REG_A4XX_RB_BLEND_GREEN 0x000020f2 1101#define REG_A4XX_RB_BLEND_GREEN 0x000020f2
1098#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff 1102#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
1099#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 1103#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
1100static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 1104static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
1101{ 1105{
1102 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 1106 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
1103} 1107}
1108#define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
1109#define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8
1110static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
1111{
1112 return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;
1113}
1104#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 1114#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1105#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 1115#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1106static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 1116static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
@@ -1117,12 +1127,18 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1117} 1127}
1118 1128
1119#define REG_A4XX_RB_BLEND_BLUE 0x000020f4 1129#define REG_A4XX_RB_BLEND_BLUE 0x000020f4
1120#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff 1130#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
1121#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 1131#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
1122static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 1132static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
1123{ 1133{
1124 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 1134 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
1125} 1135}
1136#define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
1137#define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8
1138static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
1139{
1140 return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;
1141}
1126#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 1142#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1127#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 1143#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1128static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 1144static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
@@ -1139,12 +1155,18 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1139} 1155}
1140 1156
1141#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 1157#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
1142#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff 1158#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
1143#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 1159#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
1144static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 1160static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1145{ 1161{
1146 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 1162 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
1147} 1163}
1164#define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
1165#define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8
1166static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
1167{
1168 return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;
1169}
1148#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 1170#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1149#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 1171#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1150static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 1172static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
@@ -1348,7 +1370,7 @@ static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1348{ 1370{
1349 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1371 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1350} 1372}
1351#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1373#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
1352#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 1374#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
1353#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000 1375#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
1354#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1376#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
@@ -2177,11 +2199,23 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)
2177 2199
2178#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 2200#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
2179 2201
2180#define REG_A4XX_CP_PROTECT_REG_0 0x00000240
2181
2182static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2202static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2183 2203
2184static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2204static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2205#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
2206#define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
2207static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
2208{
2209 return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK;
2210}
2211#define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
2212#define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
2213static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
2214{
2215 return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;
2216}
2217#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
2218#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000
2185 2219
2186#define REG_A4XX_CP_PROTECT_CTRL 0x00000250 2220#define REG_A4XX_CP_PROTECT_CTRL 0x00000250
2187 2221
@@ -2272,7 +2306,7 @@ static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2272{ 2306{
2273 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2307 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2274} 2308}
2275#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 2309#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2276#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2310#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2277static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2311static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2278{ 2312{
@@ -2420,7 +2454,7 @@ static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2420{ 2454{
2421 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2455 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2422} 2456}
2423#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 2457#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2424#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2458#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2425static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2459static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2426{ 2460{
@@ -3117,6 +3151,8 @@ static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
3117 3151
3118#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 3152#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
3119#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000 3153#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
3154#define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000
3155#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
3120#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 3156#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
3121 3157
3122#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 3158#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
@@ -3253,6 +3289,7 @@ static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
3253 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 3289 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
3254} 3290}
3255#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 3291#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
3292#define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000
3256#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 3293#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
3257 3294
3258#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 3295#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
@@ -3670,6 +3707,8 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3670#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 3707#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
3671#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 3708#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
3672 3709
3710#define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08
3711
3673#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 3712#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
3674 3713
3675#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 3714#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
@@ -3690,6 +3729,20 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3690 3729
3691#define REG_A4XX_PC_BIN_BASE 0x000021c0 3730#define REG_A4XX_PC_BIN_BASE 0x000021c0
3692 3731
3732#define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2
3733#define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
3734#define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
3735static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
3736{
3737 return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK;
3738}
3739#define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
3740#define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22
3741static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)
3742{
3743 return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK;
3744}
3745
3693#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 3746#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
3694#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f 3747#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
3695#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 3748#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
@@ -3752,12 +3805,8 @@ static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3752{ 3805{
3753 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; 3806 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
3754} 3807}
3755#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000 3808#define A4XX_PC_HS_PARAM_CW 0x00800000
3756#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23 3809#define A4XX_PC_HS_PARAM_CONNECTED 0x01000000
3757static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3758{
3759 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
3760}
3761 3810
3762#define REG_A4XX_VBIF_VERSION 0x00003000 3811#define REG_A4XX_VBIF_VERSION 0x00003000
3763 3812
diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h
new file mode 100644
index 000000000000..b6fe763ddf34
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h
@@ -0,0 +1,3757 @@
1#ifndef A5XX_XML
2#define A5XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
19- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
20
21Copyright (C) 2013-2016 by the following authors:
22- Rob Clark <robdclark@gmail.com> (robclark)
23- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24
25Permission is hereby granted, free of charge, to any person obtaining
26a copy of this software and associated documentation files (the
27"Software"), to deal in the Software without restriction, including
28without limitation the rights to use, copy, modify, merge, publish,
29distribute, sublicense, and/or sell copies of the Software, and to
30permit persons to whom the Software is furnished to do so, subject to
31the following conditions:
32
33The above copyright notice and this permission notice (including the
34next paragraph) shall be included in all copies or substantial
35portions of the Software.
36
37THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44*/
45
46
47enum a5xx_color_fmt {
48 RB5_R8_UNORM = 3,
49 RB5_R4G4B4A4_UNORM = 8,
50 RB5_R5G5B5A1_UNORM = 10,
51 RB5_R5G6B5_UNORM = 14,
52 RB5_R16_FLOAT = 23,
53 RB5_R8G8B8A8_UNORM = 48,
54 RB5_R8G8B8_UNORM = 49,
55 RB5_R8G8B8A8_UINT = 51,
56 RB5_R10G10B10A2_UINT = 58,
57 RB5_R16G16_FLOAT = 69,
58 RB5_R32_FLOAT = 74,
59 RB5_R16G16B16A16_FLOAT = 98,
60 RB5_R32G32_FLOAT = 103,
61 RB5_R32G32B32A32_FLOAT = 130,
62};
63
64enum a5xx_tile_mode {
65 TILE5_LINEAR = 0,
66 TILE5_2 = 2,
67 TILE5_3 = 3,
68};
69
70enum a5xx_vtx_fmt {
71 VFMT5_8_UNORM = 3,
72 VFMT5_8_SNORM = 4,
73 VFMT5_8_UINT = 5,
74 VFMT5_8_SINT = 6,
75 VFMT5_8_8_UNORM = 15,
76 VFMT5_8_8_SNORM = 16,
77 VFMT5_8_8_UINT = 17,
78 VFMT5_8_8_SINT = 18,
79 VFMT5_16_UNORM = 21,
80 VFMT5_16_SNORM = 22,
81 VFMT5_16_FLOAT = 23,
82 VFMT5_16_UINT = 24,
83 VFMT5_16_SINT = 25,
84 VFMT5_8_8_8_UNORM = 33,
85 VFMT5_8_8_8_SNORM = 34,
86 VFMT5_8_8_8_UINT = 35,
87 VFMT5_8_8_8_SINT = 36,
88 VFMT5_8_8_8_8_UNORM = 48,
89 VFMT5_8_8_8_8_SNORM = 50,
90 VFMT5_8_8_8_8_UINT = 51,
91 VFMT5_8_8_8_8_SINT = 52,
92 VFMT5_16_16_UNORM = 67,
93 VFMT5_16_16_SNORM = 68,
94 VFMT5_16_16_FLOAT = 69,
95 VFMT5_16_16_UINT = 70,
96 VFMT5_16_16_SINT = 71,
97 VFMT5_32_UNORM = 72,
98 VFMT5_32_SNORM = 73,
99 VFMT5_32_FLOAT = 74,
100 VFMT5_32_UINT = 75,
101 VFMT5_32_SINT = 76,
102 VFMT5_32_FIXED = 77,
103 VFMT5_16_16_16_UNORM = 88,
104 VFMT5_16_16_16_SNORM = 89,
105 VFMT5_16_16_16_FLOAT = 90,
106 VFMT5_16_16_16_UINT = 91,
107 VFMT5_16_16_16_SINT = 92,
108 VFMT5_16_16_16_16_UNORM = 96,
109 VFMT5_16_16_16_16_SNORM = 97,
110 VFMT5_16_16_16_16_FLOAT = 98,
111 VFMT5_16_16_16_16_UINT = 99,
112 VFMT5_16_16_16_16_SINT = 100,
113 VFMT5_32_32_UNORM = 101,
114 VFMT5_32_32_SNORM = 102,
115 VFMT5_32_32_FLOAT = 103,
116 VFMT5_32_32_UINT = 104,
117 VFMT5_32_32_SINT = 105,
118 VFMT5_32_32_FIXED = 106,
119 VFMT5_32_32_32_UNORM = 112,
120 VFMT5_32_32_32_SNORM = 113,
121 VFMT5_32_32_32_UINT = 114,
122 VFMT5_32_32_32_SINT = 115,
123 VFMT5_32_32_32_FLOAT = 116,
124 VFMT5_32_32_32_FIXED = 117,
125 VFMT5_32_32_32_32_UNORM = 128,
126 VFMT5_32_32_32_32_SNORM = 129,
127 VFMT5_32_32_32_32_FLOAT = 130,
128 VFMT5_32_32_32_32_UINT = 131,
129 VFMT5_32_32_32_32_SINT = 132,
130 VFMT5_32_32_32_32_FIXED = 133,
131};
132
133enum a5xx_tex_fmt {
134 TFMT5_A8_UNORM = 2,
135 TFMT5_8_UNORM = 3,
136 TFMT5_4_4_4_4_UNORM = 8,
137 TFMT5_5_5_5_1_UNORM = 10,
138 TFMT5_5_6_5_UNORM = 14,
139 TFMT5_8_8_UNORM = 15,
140 TFMT5_8_8_SNORM = 16,
141 TFMT5_L8_A8_UNORM = 19,
142 TFMT5_16_FLOAT = 23,
143 TFMT5_8_8_8_8_UNORM = 48,
144 TFMT5_8_8_8_UNORM = 49,
145 TFMT5_8_8_8_SNORM = 50,
146 TFMT5_9_9_9_E5_FLOAT = 53,
147 TFMT5_10_10_10_2_UNORM = 54,
148 TFMT5_11_11_10_FLOAT = 66,
149 TFMT5_16_16_FLOAT = 69,
150 TFMT5_32_FLOAT = 74,
151 TFMT5_16_16_16_16_FLOAT = 98,
152 TFMT5_32_32_FLOAT = 103,
153 TFMT5_32_32_32_32_FLOAT = 130,
154 TFMT5_X8Z24_UNORM = 160,
155};
156
157enum a5xx_tex_fetchsize {
158 TFETCH5_1_BYTE = 0,
159 TFETCH5_2_BYTE = 1,
160 TFETCH5_4_BYTE = 2,
161 TFETCH5_8_BYTE = 3,
162 TFETCH5_16_BYTE = 4,
163};
164
165enum a5xx_depth_format {
166 DEPTH5_NONE = 0,
167 DEPTH5_16 = 1,
168 DEPTH5_24_8 = 2,
169 DEPTH5_32 = 4,
170};
171
172enum a5xx_blit_buf {
173 BLIT_MRT0 = 0,
174 BLIT_MRT1 = 1,
175 BLIT_MRT2 = 2,
176 BLIT_MRT3 = 3,
177 BLIT_MRT4 = 4,
178 BLIT_MRT5 = 5,
179 BLIT_MRT6 = 6,
180 BLIT_MRT7 = 7,
181 BLIT_ZS = 8,
182 BLIT_Z32 = 9,
183};
184
185enum a5xx_tex_filter {
186 A5XX_TEX_NEAREST = 0,
187 A5XX_TEX_LINEAR = 1,
188 A5XX_TEX_ANISO = 2,
189};
190
191enum a5xx_tex_clamp {
192 A5XX_TEX_REPEAT = 0,
193 A5XX_TEX_CLAMP_TO_EDGE = 1,
194 A5XX_TEX_MIRROR_REPEAT = 2,
195 A5XX_TEX_CLAMP_TO_BORDER = 3,
196 A5XX_TEX_MIRROR_CLAMP = 4,
197};
198
199enum a5xx_tex_aniso {
200 A5XX_TEX_ANISO_1 = 0,
201 A5XX_TEX_ANISO_2 = 1,
202 A5XX_TEX_ANISO_4 = 2,
203 A5XX_TEX_ANISO_8 = 3,
204 A5XX_TEX_ANISO_16 = 4,
205};
206
207enum a5xx_tex_swiz {
208 A5XX_TEX_X = 0,
209 A5XX_TEX_Y = 1,
210 A5XX_TEX_Z = 2,
211 A5XX_TEX_W = 3,
212 A5XX_TEX_ZERO = 4,
213 A5XX_TEX_ONE = 5,
214};
215
216enum a5xx_tex_type {
217 A5XX_TEX_1D = 0,
218 A5XX_TEX_2D = 1,
219 A5XX_TEX_CUBE = 2,
220 A5XX_TEX_3D = 3,
221};
222
223#define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
224#define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
225#define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
226#define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
227#define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
228#define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
229#define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
230#define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
231#define A5XX_INT0_CP_SW 0x00000100
232#define A5XX_INT0_CP_HW_ERROR 0x00000200
233#define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
234#define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
235#define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
236#define A5XX_INT0_CP_IB2 0x00002000
237#define A5XX_INT0_CP_IB1 0x00004000
238#define A5XX_INT0_CP_RB 0x00008000
239#define A5XX_INT0_CP_UNUSED_1 0x00010000
240#define A5XX_INT0_CP_RB_DONE_TS 0x00020000
241#define A5XX_INT0_CP_WT_DONE_TS 0x00040000
242#define A5XX_INT0_UNKNOWN_1 0x00080000
243#define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
244#define A5XX_INT0_UNUSED_2 0x00200000
245#define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
246#define A5XX_INT0_MISC_HANG_DETECT 0x00800000
247#define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
248#define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
249#define A5XX_INT0_DEBBUS_INTR_0 0x04000000
250#define A5XX_INT0_DEBBUS_INTR_1 0x08000000
251#define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
252#define A5XX_INT0_GPMU_FIRMWARE 0x20000000
253#define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
254#define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
255#define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
256#define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
257#define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
258#define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
259#define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
260#define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
261#define REG_A5XX_CP_RB_BASE 0x00000800
262
263#define REG_A5XX_CP_RB_BASE_HI 0x00000801
264
265#define REG_A5XX_CP_RB_CNTL 0x00000802
266
267#define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
268
269#define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
270
271#define REG_A5XX_CP_RB_RPTR 0x00000806
272
273#define REG_A5XX_CP_RB_WPTR 0x00000807
274
275#define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
276
277#define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
278
279#define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
280
281#define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
282
283#define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
284
285#define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
286
287#define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
288
289#define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
290
291#define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
292
293#define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
294
295#define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
296
297#define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
298
299#define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
300
301#define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
302
303#define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
304
305#define REG_A5XX_CP_MERCIU_SIZE 0x00000826
306
307#define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
308
309#define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
310
311#define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
312
313#define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
314
315#define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
316
317#define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
318
319#define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
320
321#define REG_A5XX_CP_CNTL 0x00000831
322
323#define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
324
325#define REG_A5XX_CP_CHICKEN_DBG 0x00000833
326
327#define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
328
329#define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
330
331#define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
332
333#define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
334
335#define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
336
337#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
338
339#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
340
341#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
342
343#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
344
345#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
346
347#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
348
349#define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
350
351#define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
352
353#define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
354
355#define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
356
357#define REG_A5XX_CP_HW_FAULT 0x00000b1a
358
359#define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
360
361#define REG_A5XX_CP_IB1_BASE 0x00000b1f
362
363#define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
364
365#define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
366
367#define REG_A5XX_CP_IB2_BASE 0x00000b22
368
369#define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
370
371#define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
372
373static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
374
375static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
376
377static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
378
379static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
380#define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
381#define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
382static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
383{
384 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
385}
386#define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
387#define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
388static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
389{
390 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
391}
392#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
393#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
394
395#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
396
397#define REG_A5XX_CP_AHB_FAULT 0x00000b1b
398
399#define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
400
401#define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
402
403#define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
404
405#define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
406
407#define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
408
409#define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
410
411#define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
412
413#define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
414
415#define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
416
417#define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
418
419#define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
420
421#define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
422
423#define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
424
425#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
426
427#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
428
429#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
430
431#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
432
433#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
434
435#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
436
437#define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
438
439#define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
440
441#define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
442
443#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
444
445#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
446
447#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
448
449#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
450
451#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
452
453#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
454
455#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
456
457#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
458
459#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
460
461#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
462
463#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
464
465#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
466
467#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
468
469#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
470
471#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
472
473#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
474
475#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
476
477#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
478
479#define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
480
481#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
482
483#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
484
485#define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
486
487#define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
488
489#define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
490
491#define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
492
493#define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
494
495#define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
496
497#define REG_A5XX_RBBM_INT_0_MASK 0x00000038
498#define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
499#define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
500#define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
501#define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
502#define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
503#define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
504#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
505#define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
506#define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
507#define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
508#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
509#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
510#define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
511#define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
512#define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
513#define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
514#define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
515#define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
516#define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
517#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
518#define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
519#define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
520#define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
521#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
522#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
523#define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
524#define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
525#define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
526#define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
527
528#define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
529
530#define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
531
532#define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
533
534#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
535
536#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
537
538#define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
539
540#define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
541
542#define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
543
544#define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
545
546#define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
547
548#define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
549
550#define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
551
552#define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
553
554#define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
555
556#define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
557
558#define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
559
560#define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
561
562#define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
563
564#define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
565
566#define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
567
568#define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
569
570#define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
571
572#define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
573
574#define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
575
576#define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
577
578#define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
579
580#define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
581
582#define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
583
584#define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
585
586#define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
587
588#define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
589
590#define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
591
592#define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
593
594#define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
595
596#define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
597
598#define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
599
600#define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
601
602#define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
603
604#define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
605
606#define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
607
608#define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
609
610#define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
611
612#define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
613
614#define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
615
616#define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
617
618#define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
619
620#define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
621
622#define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
623
624#define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
625
626#define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
627
628#define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
629
630#define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
631
632#define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
633
634#define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
635
636#define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
637
638#define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
639
640#define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
641
642#define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
643
644#define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
645
646#define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
647
648#define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
649
650#define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
651
652#define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
653
654#define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
655
656#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
657
658#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
659
660#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
661
662#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
663
664#define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
665
666#define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
667
668#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
669
670#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
671
672#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
673
674#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
675
676#define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
677
678#define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
679
680#define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
681
682#define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
683
684#define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
685
686#define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
687
688#define REG_A5XX_RBBM_AHB_CMD 0x00000096
689
690#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
691
692#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
693
694#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
695
696#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
697
698#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
699
700#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
701
702#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
703
704#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
705
706#define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
707
708#define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
709
710#define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
711
712#define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
713
714#define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
715
716#define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
717
718#define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
719
720#define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
721
722#define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
723
724#define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
725
726#define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
727
728#define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
729
730#define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
731
732#define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
733
734#define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
735
736#define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
737
738#define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
739
740#define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
741
742#define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
743
744#define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
745
746#define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
747
748#define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
749
750#define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
751
752#define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
753
754#define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
755
756#define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
757
758#define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
759
760#define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
761
762#define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
763
764#define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
765
766#define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
767
768#define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
769
770#define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
771
772#define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
773
774#define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
775
776#define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
777
778#define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
779
780#define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
781
782#define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
783
784#define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
785
786#define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
787
788#define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
789
790#define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
791
792#define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
793
794#define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
795
796#define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
797
798#define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
799
800#define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
801
802#define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
803
804#define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
805
806#define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
807
808#define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
809
810#define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
811
812#define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
813
814#define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
815
816#define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
817
818#define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
819
820#define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
821
822#define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
823
824#define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
825
826#define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
827
828#define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
829
830#define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
831
832#define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
833
834#define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
835
836#define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
837
838#define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
839
840#define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
841
842#define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
843
844#define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
845
846#define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
847
848#define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
849
850#define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
851
852#define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
853
854#define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
855
856#define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
857
858#define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
859
860#define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
861
862#define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
863
864#define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
865
866#define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
867
868#define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
869
870#define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
871
872#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
873
874#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
875
876#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
877
878#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
879
880#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
881
882#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
883
884#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
885
886#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
887
888#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
889
890#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
891
892#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
893
894#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
895
896#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
897
898#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
899
900#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
901
902#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
903
904#define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
905
906#define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
907
908#define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
909
910#define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
911
912#define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
913
914#define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
915
916#define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
917
918#define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
919
920#define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
921
922#define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
923
924#define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
925
926#define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
927
928#define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
929
930#define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
931
932#define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
933
934#define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
935
936#define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
937
938#define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
939
940#define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
941
942#define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
943
944#define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
945
946#define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
947
948#define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
949
950#define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
951
952#define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
953
954#define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
955
956#define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
957
958#define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
959
960#define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
961
962#define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
963
964#define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
965
966#define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
967
968#define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
969
970#define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
971
972#define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
973
974#define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
975
976#define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
977
978#define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
979
980#define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
981
982#define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
983
984#define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
985
986#define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
987
988#define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
989
990#define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
991
992#define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
993
994#define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
995
996#define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
997
998#define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
999
1000#define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
1001
1002#define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
1003
1004#define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
1005
1006#define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
1007
1008#define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
1009
1010#define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
1011
1012#define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
1013
1014#define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
1015
1016#define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
1017
1018#define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
1019
1020#define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
1021
1022#define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
1023
1024#define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
1025
1026#define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
1027
1028#define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
1029
1030#define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
1031
1032#define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
1033
1034#define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
1035
1036#define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
1037
1038#define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
1039
1040#define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
1041
1042#define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
1043
1044#define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
1045
1046#define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
1047
1048#define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
1049
1050#define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
1051
1052#define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
1053
1054#define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
1055
1056#define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
1057
1058#define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
1059
1060#define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
1061
1062#define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
1063
1064#define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
1065
1066#define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
1067
1068#define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
1069
1070#define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
1071
1072#define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
1073
1074#define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
1075
1076#define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
1077
1078#define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
1079
1080#define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
1081
1082#define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
1083
1084#define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
1085
1086#define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
1087
1088#define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
1089
1090#define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
1091
1092#define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
1093
1094#define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
1095
1096#define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
1097
1098#define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
1099
1100#define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
1101
1102#define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
1103
1104#define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
1105
1106#define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
1107
1108#define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
1109
1110#define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
1111
1112#define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
1113
1114#define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
1115
1116#define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
1117
1118#define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
1119
1120#define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
1121
1122#define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
1123
1124#define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
1125
1126#define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
1127
1128#define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
1129
1130#define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
1131
1132#define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
1133
1134#define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
1135
1136#define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
1137
1138#define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
1139
1140#define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
1141
1142#define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
1143
1144#define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
1145
1146#define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
1147
1148#define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
1149
1150#define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
1151
1152#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1153
1154#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1155
1156#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1157
1158#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1159
1160#define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
1161
1162#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
1163
1164#define REG_A5XX_RBBM_STATUS 0x000004f5
1165#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
1166#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
1167#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1168#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
1169#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
1170#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
1171#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
1172#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
1173#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
1174#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
1175#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
1176#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1177#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1178#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
1179#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
1180#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
1181#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
1182#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
1183#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
1184#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
1185#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
1186#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
1187#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
1188#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
1189#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
1190#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
1191#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
1192#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
1193#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
1194#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1195#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1196#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
1197
1198#define REG_A5XX_RBBM_STATUS3 0x00000530
1199
1200#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
1201
1202#define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
1203
1204#define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
1205
1206#define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
1207
1208#define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
1209
1210#define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
1211
1212#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
1213
1214#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
1215
1216#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
1217
1218#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
1219
1220#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
1221
1222#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
1223
1224#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1225
1226#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1227
1228#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1229
1230#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1231
1232#define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
1233
1234#define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
1235
1236#define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
1237
1238#define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
1239
1240#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
1241
1242#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
1243
1244#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
1245
1246#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
1247
1248#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
1249
1250#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
1251
1252#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
1253
1254#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
1255
1256#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
1257
1258#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
1259
1260#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
1261
1262#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
1263
1264#define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
1265
1266#define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
1267
1268#define REG_A5XX_RBBM_ISDB_CNT 0x00000533
1269
1270#define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
1271
1272#define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1273
1274#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1275
1276#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1277
1278#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1279
1280#define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1281
1282#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
1283
1284#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
1285
1286#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
1287
1288#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
1289
1290#define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1291
1292#define REG_A5XX_VSC_PIPE_DATA_LENGTH_0 0x00000c00
1293
1294#define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
1295
1296#define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
1297
1298#define REG_A5XX_VSC_BIN_SIZE 0x00000cdd
1299#define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE 0x80000000
1300#define A5XX_VSC_BIN_SIZE_X__MASK 0x00007fff
1301#define A5XX_VSC_BIN_SIZE_X__SHIFT 0
1302static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val)
1303{
1304 return ((val) << A5XX_VSC_BIN_SIZE_X__SHIFT) & A5XX_VSC_BIN_SIZE_X__MASK;
1305}
1306#define A5XX_VSC_BIN_SIZE_Y__MASK 0x7fff0000
1307#define A5XX_VSC_BIN_SIZE_Y__SHIFT 16
1308static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
1309{
1310 return ((val) << A5XX_VSC_BIN_SIZE_Y__SHIFT) & A5XX_VSC_BIN_SIZE_Y__MASK;
1311}
1312
1313#define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
1314
1315#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
1316
1317#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
1318
1319#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
1320
1321#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
1322
1323#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
1324
1325#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
1326
1327#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
1328
1329#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
1330
1331#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
1332
1333#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
1334
1335#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
1336
1337#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
1338
1339#define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
1340
1341#define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
1342
1343#define REG_A5XX_RB_MODE_CNTL 0x00000cc6
1344
1345#define REG_A5XX_RB_CCU_CNTL 0x00000cc7
1346
1347#define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
1348
1349#define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
1350
1351#define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
1352
1353#define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
1354
1355#define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
1356
1357#define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
1358
1359#define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
1360
1361#define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
1362
1363#define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
1364
1365#define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
1366
1367#define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
1368
1369#define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
1370
1371#define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
1372
1373#define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
1374
1375#define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
1376
1377#define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
1378
1379#define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
1380
1381#define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
1382
1383#define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
1384
1385#define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
1386
1387#define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
1388
1389#define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
1390
1391#define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
1392#define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
1393
1394#define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
1395
1396#define REG_A5XX_PC_MODE_CNTL 0x00000d02
1397
1398#define REG_A5XX_UNKNOWN_0D08 0x00000d08
1399
1400#define REG_A5XX_UNKNOWN_0D09 0x00000d09
1401
1402#define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
1403
1404#define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
1405
1406#define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
1407
1408#define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
1409
1410#define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
1411
1412#define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
1413
1414#define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
1415
1416#define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
1417
1418#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
1419
1420#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
1421
1422#define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
1423
1424#define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
1425
1426#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
1427
1428#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
1429
1430#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
1431
1432#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
1433
1434#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
1435
1436#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
1437
1438#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
1439
1440#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
1441
1442#define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
1443
1444#define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
1445
1446#define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
1447
1448#define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
1449
1450#define REG_A5XX_VFD_MODE_CNTL 0x00000e42
1451
1452#define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
1453
1454#define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
1455
1456#define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
1457
1458#define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
1459
1460#define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
1461
1462#define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
1463
1464#define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
1465
1466#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
1467
1468#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
1469
1470#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
1471
1472#define REG_A5XX_VPC_MODE_CNTL 0x00000e62
1473
1474#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
1475
1476#define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
1477
1478#define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
1479
1480#define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
1481
1482#define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
1483
1484#define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
1485
1486#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
1487
1488#define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
1489
1490#define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
1491
1492#define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
1493
1494#define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
1495
1496#define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
1497
1498#define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
1499
1500#define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
1501
1502#define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
1503
1504#define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
1505
1506#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
1507
1508#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
1509
1510#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
1511
1512#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
1513
1514#define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
1515
1516#define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
1517
1518#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
1519
1520#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
1521
1522#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
1523
1524#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
1525
1526#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
1527
1528#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
1529
1530#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
1531
1532#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
1533
1534#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
1535
1536#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
1537
1538#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
1539
1540#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
1541
1542#define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
1543
1544#define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
1545
1546#define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
1547
1548#define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
1549
1550#define REG_A5XX_SP_MODE_CNTL 0x00000ec2
1551
1552#define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
1553
1554#define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
1555
1556#define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
1557
1558#define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
1559
1560#define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
1561
1562#define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
1563
1564#define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
1565
1566#define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
1567
1568#define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
1569
1570#define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
1571
1572#define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
1573
1574#define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
1575
1576#define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
1577
1578#define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
1579
1580#define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
1581
1582#define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
1583
1584#define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
1585
1586#define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
1587
1588#define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
1589
1590#define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
1591
1592#define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
1593
1594#define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
1595
1596#define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
1597
1598#define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
1599
1600#define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
1601
1602#define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
1603
1604#define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
1605
1606#define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
1607
1608#define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
1609
1610#define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
1611
1612#define REG_A5XX_VBIF_VERSION 0x00003000
1613
1614#define REG_A5XX_VBIF_CLKON 0x00003001
1615
1616#define REG_A5XX_VBIF_ABIT_SORT 0x00003028
1617
1618#define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
1619
1620#define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
1621
1622#define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1623
1624#define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
1625
1626#define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
1627
1628#define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
1629
1630#define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
1631
1632#define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
1633
1634#define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
1635
1636#define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
1637
1638#define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
1639
1640#define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
1641
1642#define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
1643
1644#define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
1645
1646#define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
1647
1648#define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
1649
1650#define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
1651
1652#define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
1653
1654#define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
1655
1656#define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
1657
1658#define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
1659
1660#define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
1661
1662#define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
1663
1664#define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
1665
1666#define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
1667
1668#define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
1669
1670#define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
1671
1672#define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
1673
1674#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
1675
1676#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
1677
1678#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
1679
1680#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
1681
1682#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
1683
1684#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
1685
1686#define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
1687
1688#define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
1689
1690#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
1691
1692#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
1693
1694#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
1695
1696#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
1697#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
1698
1699#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
1700#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
1701
1702#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
1703
1704#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
1705
1706#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
1707
1708#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
1709
1710#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
1711
1712#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
1713
1714#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
1715
1716#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
1717
1718#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
1719
1720#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
1721
1722#define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
1723
1724#define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
1725
1726#define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
1727
1728#define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
1729
1730#define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
1731
1732#define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
1733
1734#define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
1735
1736#define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
1737
1738#define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
1739
1740#define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
1741
1742#define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
1743
1744#define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
1745
1746#define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
1747
1748#define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
1749
1750#define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
1751
1752#define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
1753
1754#define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
1755
1756#define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
1757
1758#define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
1759
1760#define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
1761
1762#define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
1763
1764#define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
1765
1766#define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
1767
1768#define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
1769
1770#define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
1771
1772#define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
1773
1774#define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
1775
1776#define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
1777
1778#define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
1779
1780#define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
1781
1782#define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
1783
1784#define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
1785
1786#define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
1787
1788#define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
1789
1790#define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
1791
1792#define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
1793
1794#define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
1795
1796#define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
1797
1798#define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
1799
1800#define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
1801
1802#define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
1803
1804#define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
1805
1806#define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
1807
1808#define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
1809
1810#define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
1811
1812#define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
1813
1814#define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
1815
1816#define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
1817
1818#define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
1819
1820#define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
1821
1822#define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
1823
1824#define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
1825
1826#define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
1827
1828#define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
1829
1830#define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
1831
1832#define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
1833
1834#define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
1835
1836#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
1837
1838#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
1839
1840#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
1841
1842#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
1843
1844#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
1845
1846#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
1847
1848#define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
1849
1850#define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
1851
1852#define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
1853
1854#define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
1855
1856#define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
1857
1858#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
1859
1860#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
1861
1862#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
1863
1864#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
1865
1866#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
1867
1868#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
1869
1870#define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
1871
1872#define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
1873
1874#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
1875
1876#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
1877
1878#define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
1879
1880#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
1881
1882#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
1883
1884#define REG_A5XX_GDPM_CONFIG1 0x0000b80c
1885
1886#define REG_A5XX_GDPM_CONFIG2 0x0000b80d
1887
1888#define REG_A5XX_GDPM_INT_EN 0x0000b80f
1889
1890#define REG_A5XX_GDPM_INT_MASK 0x0000b811
1891
1892#define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
1893
1894#define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
1895
1896#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
1897
1898#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
1899
1900#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
1901
1902#define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
1903
1904#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
1905
1906#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
1907
1908#define REG_A5XX_UNKNOWN_E001 0x0000e001
1909
1910#define REG_A5XX_UNKNOWN_E004 0x0000e004
1911
1912#define REG_A5XX_GRAS_CNTL 0x0000e005
1913#define A5XX_GRAS_CNTL_VARYING 0x00000001
1914
1915#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
1916#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
1917#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
1918static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
1919{
1920 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
1921}
1922#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
1923#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
1924static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
1925{
1926 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
1927}
1928
1929#define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
1930#define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
1931#define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
1932static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
1933{
1934 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
1935}
1936
1937#define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
1938#define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
1939#define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
1940static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
1941{
1942 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
1943}
1944
1945#define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
1946#define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
1947#define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
1948static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
1949{
1950 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
1951}
1952
1953#define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
1954#define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
1955#define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
1956static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
1957{
1958 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
1959}
1960
1961#define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
1962#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
1963#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
1964static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
1965{
1966 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
1967}
1968
1969#define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
1970#define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
1971#define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
1972static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
1973{
1974 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
1975}
1976
1977#define REG_A5XX_GRAS_SU_CNTL 0x0000e090
1978#define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
1979#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
1980#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
1981static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
1982{
1983 return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
1984}
1985#define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
1986#define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
1987
1988#define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
1989#define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
1990#define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
1991static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
1992{
1993 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
1994}
1995#define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
1996#define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
1997static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
1998{
1999 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2000}
2001
2002#define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
2003#define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2004#define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
2005static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
2006{
2007 return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
2008}
2009
2010#define REG_A5XX_UNKNOWN_E093 0x0000e093
2011
2012#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
2013#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_ALPHA_TEST_ENABLE 0x00000001
2014
2015#define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
2016#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2017#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2018static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2019{
2020 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2021}
2022
2023#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
2024#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2025#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2026static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2027{
2028 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2029}
2030
2031#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
2032#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2033#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2034static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2035{
2036 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2037}
2038
2039#define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
2040#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2041#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2042static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2043{
2044 return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2045}
2046
2047#define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
2048
2049#define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
2050#define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
2051
2052#define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
2053
2054#define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
2055#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2056#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2057static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2058{
2059 return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
2060}
2061
2062#define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
2063#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2064#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2065static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2066{
2067 return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
2068}
2069#define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2070
2071#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
2072
2073#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
2074#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2075#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2076#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2077static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2078{
2079 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2080}
2081#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2082#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2083static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2084{
2085 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2086}
2087
2088#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
2089#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2090#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
2091#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
2092static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2093{
2094 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2095}
2096#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
2097#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
2098static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2099{
2100 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2101}
2102
2103#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
2104#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2105#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
2106#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
2107static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2108{
2109 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2110}
2111#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
2112#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
2113static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2114{
2115 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2116}
2117
2118#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
2119#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2120#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
2121#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
2122static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2123{
2124 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2125}
2126#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
2127#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
2128static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2129{
2130 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2131}
2132
2133#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
2134#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2135#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2136#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2137static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2138{
2139 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2140}
2141#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2142#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2143static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2144{
2145 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2146}
2147
2148#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
2149#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2150#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2151#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2152static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2153{
2154 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2155}
2156#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2157#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2158static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2159{
2160 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2161}
2162
2163#define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
2164
2165#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
2166
2167#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
2168
2169#define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
2170
2171#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
2172
2173#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
2174
2175#define REG_A5XX_RB_CNTL 0x0000e140
2176#define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
2177#define A5XX_RB_CNTL_WIDTH__SHIFT 0
2178static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
2179{
2180 return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
2181}
2182#define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
2183#define A5XX_RB_CNTL_HEIGHT__SHIFT 9
2184static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
2185{
2186 return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
2187}
2188#define A5XX_RB_CNTL_BYPASS 0x00020000
2189
2190#define REG_A5XX_RB_RENDER_CNTL 0x0000e141
2191#define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
2192#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
2193#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
2194#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
2195#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
2196static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
2197{
2198 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
2199}
2200#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
2201#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
2202static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
2203{
2204 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
2205}
2206
2207#define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
2208#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2209#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2210static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2211{
2212 return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
2213}
2214
2215#define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
2216#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2217#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2218static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2219{
2220 return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
2221}
2222#define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2223
2224#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
2225#define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
2226#define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
2227#define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
2228#define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
2229#define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
2230
2231#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
2232#define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
2233
2234#define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
2235#define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
2236#define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
2237static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
2238{
2239 return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
2240}
2241#define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
2242
2243#define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
2244#define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
2245#define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
2246static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
2247{
2248 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
2249}
2250#define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
2251#define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
2252static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
2253{
2254 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
2255}
2256#define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
2257#define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
2258static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
2259{
2260 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
2261}
2262#define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
2263#define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
2264static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
2265{
2266 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
2267}
2268#define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
2269#define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
2270static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
2271{
2272 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
2273}
2274#define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
2275#define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
2276static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
2277{
2278 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
2279}
2280#define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
2281#define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
2282static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
2283{
2284 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
2285}
2286#define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
2287#define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
2288static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
2289{
2290 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
2291}
2292
2293static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
2294
2295static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
2296#define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
2297#define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
2298#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
2299#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
2300static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
2301{
2302 return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
2303}
2304
2305static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
2306#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
2307#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
2308static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
2309{
2310 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
2311}
2312#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
2313#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
2314static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
2315{
2316 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
2317}
2318#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
2319#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
2320static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
2321{
2322 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
2323}
2324#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
2325#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
2326static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
2327{
2328 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
2329}
2330#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
2331#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
2332static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
2333{
2334 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
2335}
2336#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
2337#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
2338static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
2339{
2340 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
2341}
2342
2343static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
2344#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
2345#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
2346static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
2347{
2348 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
2349}
2350#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
2351#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
2352static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
2353{
2354 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
2355}
2356#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
2357#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
2358static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
2359{
2360 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
2361}
2362#define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
2363
2364static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
2365#define A5XX_RB_MRT_PITCH__MASK 0xffffffff
2366#define A5XX_RB_MRT_PITCH__SHIFT 0
2367static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
2368{
2369 return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
2370}
2371
2372static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
2373#define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
2374#define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
2375static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
2376{
2377 return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
2378}
2379
2380static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
2381
2382static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
2383
2384#define REG_A5XX_RB_BLEND_RED 0x0000e1a0
2385#define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
2386#define A5XX_RB_BLEND_RED_UINT__SHIFT 0
2387static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
2388{
2389 return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
2390}
2391#define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
2392#define A5XX_RB_BLEND_RED_SINT__SHIFT 8
2393static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
2394{
2395 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
2396}
2397#define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
2398#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
2399static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
2400{
2401 return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
2402}
2403
2404#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
2405#define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
2406#define A5XX_RB_BLEND_RED_F32__SHIFT 0
2407static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
2408{
2409 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
2410}
2411
2412#define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
2413#define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
2414#define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
2415static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
2416{
2417 return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
2418}
2419#define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
2420#define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
2421static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
2422{
2423 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
2424}
2425#define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
2426#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
2427static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
2428{
2429 return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
2430}
2431
2432#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
2433#define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
2434#define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
2435static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
2436{
2437 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
2438}
2439
2440#define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
2441#define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
2442#define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
2443static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
2444{
2445 return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
2446}
2447#define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
2448#define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
2449static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
2450{
2451 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
2452}
2453#define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
2454#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
2455static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
2456{
2457 return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
2458}
2459
2460#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
2461#define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
2462#define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
2463static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
2464{
2465 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
2466}
2467
2468#define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
2469#define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
2470#define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
2471static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
2472{
2473 return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
2474}
2475#define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
2476#define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
2477static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
2478{
2479 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
2480}
2481#define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
2482#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
2483static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
2484{
2485 return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
2486}
2487
2488#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
2489#define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
2490#define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
2491static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
2492{
2493 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
2494}
2495
2496#define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
2497#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
2498#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
2499static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
2500{
2501 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
2502}
2503#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
2504#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
2505#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
2506static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
2507{
2508 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
2509}
2510
2511#define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
2512#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
2513#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
2514static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
2515{
2516 return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
2517}
2518#define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
2519#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
2520#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
2521static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
2522{
2523 return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
2524}
2525
2526#define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
2527#define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2528
2529#define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
2530#define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
2531#define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
2532#define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
2533#define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
2534static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
2535{
2536 return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
2537}
2538#define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
2539
2540#define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
2541#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2542#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2543static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2544{
2545 return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2546}
2547
2548#define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
2549
2550#define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
2551
2552#define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
2553#define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
2554#define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
2555static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
2556{
2557 return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
2558}
2559
2560#define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
2561#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
2562#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
2563static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
2564{
2565 return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
2566}
2567
2568#define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
2569#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
2570#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
2571#define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
2572#define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
2573#define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
2574static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
2575{
2576 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
2577}
2578#define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
2579#define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
2580static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
2581{
2582 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
2583}
2584#define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
2585#define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
2586static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
2587{
2588 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
2589}
2590#define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
2591#define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
2592static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
2593{
2594 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
2595}
2596#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
2597#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
2598static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
2599{
2600 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
2601}
2602#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
2603#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
2604static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
2605{
2606 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
2607}
2608#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
2609#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
2610static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
2611{
2612 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
2613}
2614#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
2615#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
2616static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
2617{
2618 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
2619}
2620
2621#define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
2622#define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
2623
2624#define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
2625
2626#define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
2627
2628#define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
2629#define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
2630#define A5XX_RB_STENCIL_PITCH__SHIFT 0
2631static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
2632{
2633 return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
2634}
2635
2636#define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
2637#define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
2638#define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
2639static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
2640{
2641 return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
2642}
2643
2644#define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
2645#define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
2646#define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
2647static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
2648{
2649 return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
2650}
2651#define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
2652#define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
2653static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
2654{
2655 return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
2656}
2657#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
2658#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
2659static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
2660{
2661 return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
2662}
2663
2664#define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7
2665
2666#define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
2667#define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2668#define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
2669#define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
2670static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
2671{
2672 return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
2673}
2674#define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
2675#define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
2676static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
2677{
2678 return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
2679}
2680
2681#define REG_A5XX_RB_BLIT_CNTL 0x0000e210
2682#define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000003f
2683#define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
2684static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
2685{
2686 return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
2687}
2688
2689#define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
2690#define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
2691#define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
2692#define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
2693static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
2694{
2695 return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
2696}
2697#define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
2698#define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
2699static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
2700{
2701 return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
2702}
2703
2704#define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
2705#define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
2706#define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
2707#define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
2708static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
2709{
2710 return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
2711}
2712#define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
2713#define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
2714static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
2715{
2716 return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
2717}
2718
2719#define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
2720
2721#define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
2722
2723#define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
2724
2725#define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
2726#define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
2727#define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
2728static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
2729{
2730 return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
2731}
2732
2733#define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
2734#define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
2735#define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
2736static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
2737{
2738 return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
2739}
2740
2741#define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
2742
2743#define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
2744
2745#define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
2746
2747#define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
2748
2749#define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
2750#define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
2751#define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
2752#define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
2753static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
2754{
2755 return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
2756}
2757
2758#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
2759
2760#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
2761
2762#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
2763
2764static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
2765
2766static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
2767
2768static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
2769
2770static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
2771#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
2772#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
2773static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
2774{
2775 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
2776}
2777
2778static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
2779#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
2780#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
2781static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
2782{
2783 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
2784}
2785
2786#define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
2787
2788#define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
2789
2790#define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
2791#define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
2792#define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
2793static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
2794{
2795 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
2796}
2797
2798#define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
2799#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
2800#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
2801static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
2802{
2803 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
2804}
2805
2806#define REG_A5XX_VPC_CNTL_0 0x0000e280
2807#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
2808#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
2809static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
2810{
2811 return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
2812}
2813#define A5XX_VPC_CNTL_0_VARYING 0x00000800
2814
2815static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
2816
2817static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
2818
2819static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
2820
2821static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
2822
2823#define REG_A5XX_UNKNOWN_E292 0x0000e292
2824
2825#define REG_A5XX_UNKNOWN_E293 0x0000e293
2826
2827static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
2828
2829static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
2830
2831#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
2832
2833#define REG_A5XX_UNKNOWN_E29A 0x0000e29a
2834
2835#define REG_A5XX_VPC_PACK 0x0000e29d
2836#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
2837#define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
2838static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
2839{
2840 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
2841}
2842
2843#define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
2844
2845#define REG_A5XX_UNKNOWN_E2A1 0x0000e2a1
2846
2847#define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
2848
2849#define REG_A5XX_VPC_SO_BUFFER_BASE_LO_0 0x0000e2a7
2850
2851#define REG_A5XX_VPC_SO_BUFFER_BASE_HI_0 0x0000e2a8
2852
2853#define REG_A5XX_VPC_SO_BUFFER_SIZE_0 0x0000e2a9
2854
2855#define REG_A5XX_UNKNOWN_E2AB 0x0000e2ab
2856
2857#define REG_A5XX_VPC_SO_FLUSH_BASE_LO_0 0x0000e2ac
2858
2859#define REG_A5XX_VPC_SO_FLUSH_BASE_HI_0 0x0000e2ad
2860
2861#define REG_A5XX_UNKNOWN_E2AE 0x0000e2ae
2862
2863#define REG_A5XX_UNKNOWN_E2B2 0x0000e2b2
2864
2865#define REG_A5XX_UNKNOWN_E2B9 0x0000e2b9
2866
2867#define REG_A5XX_UNKNOWN_E2C0 0x0000e2c0
2868
2869#define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
2870#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
2871#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
2872static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
2873{
2874 return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
2875}
2876
2877#define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
2878#define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
2879
2880#define REG_A5XX_PC_RASTER_CNTL 0x0000e388
2881
2882#define REG_A5XX_UNKNOWN_E389 0x0000e389
2883
2884#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
2885
2886#define REG_A5XX_UNKNOWN_E38D 0x0000e38d
2887
2888#define REG_A5XX_PC_GS_PARAM 0x0000e38e
2889
2890#define REG_A5XX_PC_HS_PARAM 0x0000e38f
2891
2892#define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
2893
2894#define REG_A5XX_VFD_CONTROL_0 0x0000e400
2895#define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
2896#define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
2897static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
2898{
2899 return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
2900}
2901
2902#define REG_A5XX_VFD_CONTROL_1 0x0000e401
2903#define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
2904#define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
2905static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
2906{
2907 return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
2908}
2909#define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
2910#define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
2911static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
2912{
2913 return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
2914}
2915
2916#define REG_A5XX_VFD_CONTROL_2 0x0000e402
2917
2918#define REG_A5XX_VFD_CONTROL_3 0x0000e403
2919
2920#define REG_A5XX_VFD_CONTROL_4 0x0000e404
2921
2922#define REG_A5XX_VFD_CONTROL_5 0x0000e405
2923
2924#define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
2925
2926#define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
2927
2928static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
2929
2930static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
2931
2932static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
2933
2934static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
2935
2936static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
2937
2938static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
2939
2940static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
2941#define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
2942#define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
2943static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
2944{
2945 return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
2946}
2947#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000
2948#define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
2949static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
2950{
2951 return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
2952}
2953#define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0xc0000000
2954#define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 30
2955static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
2956{
2957 return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
2958}
2959
2960static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
2961
2962static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
2963
2964static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
2965#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
2966#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
2967static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
2968{
2969 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
2970}
2971#define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
2972#define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
2973static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
2974{
2975 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
2976}
2977
2978#define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
2979
2980#define REG_A5XX_SP_SP_CNTL 0x0000e580
2981
2982#define REG_A5XX_SP_VS_CONTROL_REG 0x0000e584
2983#define A5XX_SP_VS_CONTROL_REG_ENABLED 0x00000001
2984#define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
2985#define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
2986static inline uint32_t A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2987{
2988 return ((val) << A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2989}
2990#define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
2991#define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
2992static inline uint32_t A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2993{
2994 return ((val) << A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2995}
2996
2997#define REG_A5XX_SP_FS_CONTROL_REG 0x0000e585
2998#define A5XX_SP_FS_CONTROL_REG_ENABLED 0x00000001
2999#define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3000#define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3001static inline uint32_t A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3002{
3003 return ((val) << A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3004}
3005#define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3006#define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3007static inline uint32_t A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3008{
3009 return ((val) << A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3010}
3011
3012#define REG_A5XX_SP_HS_CONTROL_REG 0x0000e586
3013#define A5XX_SP_HS_CONTROL_REG_ENABLED 0x00000001
3014#define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3015#define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3016static inline uint32_t A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3017{
3018 return ((val) << A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3019}
3020#define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3021#define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3022static inline uint32_t A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3023{
3024 return ((val) << A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3025}
3026
3027#define REG_A5XX_SP_DS_CONTROL_REG 0x0000e587
3028#define A5XX_SP_DS_CONTROL_REG_ENABLED 0x00000001
3029#define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3030#define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3031static inline uint32_t A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3032{
3033 return ((val) << A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3034}
3035#define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3036#define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3037static inline uint32_t A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3038{
3039 return ((val) << A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3040}
3041
3042#define REG_A5XX_SP_GS_CONTROL_REG 0x0000e588
3043#define A5XX_SP_GS_CONTROL_REG_ENABLED 0x00000001
3044#define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3045#define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3046static inline uint32_t A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3047{
3048 return ((val) << A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3049}
3050#define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3051#define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3052static inline uint32_t A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3053{
3054 return ((val) << A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3055}
3056
3057#define REG_A5XX_SP_CS_CONFIG 0x0000e589
3058
3059#define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
3060
3061#define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
3062
3063#define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
3064#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3065#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3066static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3067{
3068 return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3069}
3070#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3071#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3072static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3073{
3074 return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3075}
3076#define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
3077#define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
3078
3079#define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
3080#define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000001f
3081#define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
3082static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
3083{
3084 return ((val >> 2) << A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
3085}
3086
3087static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
3088
3089static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
3090#define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
3091#define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
3092static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
3093{
3094 return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
3095}
3096#define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
3097#define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
3098static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
3099{
3100 return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
3101}
3102#define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
3103#define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
3104static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
3105{
3106 return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
3107}
3108#define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
3109#define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
3110static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
3111{
3112 return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
3113}
3114
3115static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
3116
3117static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
3118#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
3119#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
3120static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
3121{
3122 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
3123}
3124#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
3125#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
3126static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
3127{
3128 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
3129}
3130#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
3131#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
3132static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
3133{
3134 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
3135}
3136#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
3137#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
3138static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
3139{
3140 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
3141}
3142
3143#define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
3144
3145#define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
3146
3147#define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
3148
3149#define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
3150#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3151#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3152static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3153{
3154 return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3155}
3156#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3157#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3158static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3159{
3160 return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3161}
3162#define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
3163#define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
3164
3165#define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
3166
3167#define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
3168
3169#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
3170
3171#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
3172
3173#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
3174#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
3175#define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
3176static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
3177{
3178 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
3179}
3180#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
3181#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
3182static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
3183{
3184 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
3185}
3186#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
3187#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
3188static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
3189{
3190 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
3191}
3192
3193static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
3194
3195static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
3196#define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
3197#define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
3198static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
3199{
3200 return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
3201}
3202#define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
3203
3204static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
3205
3206static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
3207#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
3208#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
3209static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
3210{
3211 return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
3212}
3213
3214#define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
3215
3216#define REG_A5XX_SP_CS_CNTL_0 0x0000e5f0
3217
3218#define REG_A5XX_UNKNOWN_E600 0x0000e600
3219
3220#define REG_A5XX_UNKNOWN_E640 0x0000e640
3221
3222#define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
3223#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3224#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
3225static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3226{
3227 return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
3228}
3229
3230#define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
3231#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3232#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
3233static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3234{
3235 return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
3236}
3237#define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3238
3239#define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
3240
3241#define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
3242
3243#define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
3244
3245#define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
3246
3247#define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
3248
3249#define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
3250
3251#define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
3252
3253#define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
3254
3255#define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
3256
3257#define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
3258
3259#define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
3260
3261#define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
3262
3263#define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
3264#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
3265#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
3266static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
3267{
3268 return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
3269}
3270
3271#define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
3272#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
3273#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
3274static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
3275{
3276 return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
3277}
3278
3279#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
3280#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
3281#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
3282static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
3283{
3284 return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
3285}
3286
3287#define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
3288#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
3289#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
3290static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
3291{
3292 return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
3293}
3294#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
3295#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
3296static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
3297{
3298 return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
3299}
3300
3301#define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
3302
3303#define REG_A5XX_HLSQ_VS_CONTROL_REG 0x0000e78b
3304#define A5XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00000001
3305#define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3306#define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3307static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3308{
3309 return ((val) << A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3310}
3311#define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3312#define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3313static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3314{
3315 return ((val) << A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3316}
3317
3318#define REG_A5XX_HLSQ_FS_CONTROL_REG 0x0000e78c
3319#define A5XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00000001
3320#define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3321#define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3322static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3323{
3324 return ((val) << A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3325}
3326#define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3327#define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3328static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3329{
3330 return ((val) << A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3331}
3332
3333#define REG_A5XX_HLSQ_HS_CONTROL_REG 0x0000e78d
3334#define A5XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00000001
3335#define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3336#define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3337static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3338{
3339 return ((val) << A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3340}
3341#define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3342#define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3343static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3344{
3345 return ((val) << A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3346}
3347
3348#define REG_A5XX_HLSQ_DS_CONTROL_REG 0x0000e78e
3349#define A5XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00000001
3350#define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3351#define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3352static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3353{
3354 return ((val) << A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3355}
3356#define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3357#define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3358static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3359{
3360 return ((val) << A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3361}
3362
3363#define REG_A5XX_HLSQ_GS_CONTROL_REG 0x0000e78f
3364#define A5XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00000001
3365#define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3366#define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3367static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3368{
3369 return ((val) << A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3370}
3371#define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3372#define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3373static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3374{
3375 return ((val) << A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3376}
3377
3378#define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
3379
3380#define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
3381#define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
3382#define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
3383static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
3384{
3385 return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
3386}
3387
3388#define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
3389#define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
3390#define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
3391static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
3392{
3393 return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
3394}
3395
3396#define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
3397#define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
3398#define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
3399static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
3400{
3401 return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
3402}
3403
3404#define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
3405#define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
3406#define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
3407static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
3408{
3409 return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
3410}
3411
3412#define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
3413#define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
3414#define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
3415static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
3416{
3417 return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
3418}
3419
3420#define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
3421#define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
3422#define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
3423static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
3424{
3425 return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
3426}
3427
3428#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
3429
3430#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
3431
3432#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
3433
3434#define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
3435
3436#define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
3437
3438#define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
3439
3440#define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
3441
3442#define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
3443
3444#define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
3445
3446#define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
3447
3448#define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
3449
3450#define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
3451
3452#define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
3453
3454#define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
3455
3456#define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
3457
3458#define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
3459
3460#define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
3461
3462#define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
3463
3464#define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
3465
3466#define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
3467
3468#define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
3469
3470#define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
3471
3472#define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
3473
3474#define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
3475
3476#define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
3477
3478#define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
3479
3480#define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
3481
3482#define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
3483
3484#define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3 0x0000e7dc
3485
3486#define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_4 0x0000e7dd
3487
3488#define REG_A5XX_RB_2D_DST_FILL 0x00002101
3489
3490#define REG_A5XX_RB_2D_SRC_INFO 0x00002107
3491#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
3492#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
3493static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3494{
3495 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
3496}
3497#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
3498#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
3499static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3500{
3501 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
3502}
3503
3504#define REG_A5XX_RB_2D_SRC_LO 0x00002108
3505
3506#define REG_A5XX_RB_2D_SRC_HI 0x00002109
3507
3508#define REG_A5XX_RB_2D_DST_INFO 0x00002110
3509#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3510#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3511static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3512{
3513 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
3514}
3515#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3516#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3517static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3518{
3519 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
3520}
3521
3522#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
3523
3524#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
3525
3526#define REG_A5XX_RB_2D_DST_LO 0x00002111
3527
3528#define REG_A5XX_RB_2D_DST_HI 0x00002112
3529
3530#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
3531
3532#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
3533
3534#define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
3535#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
3536#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
3537static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3538{
3539 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
3540}
3541#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
3542#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
3543static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3544{
3545 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
3546}
3547
3548#define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
3549#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3550#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3551static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3552{
3553 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
3554}
3555#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3556#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3557static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3558{
3559 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
3560}
3561
3562#define REG_A5XX_TEX_SAMP_0 0x00000000
3563#define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
3564#define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
3565#define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
3566static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
3567{
3568 return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
3569}
3570#define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
3571#define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
3572static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
3573{
3574 return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
3575}
3576#define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
3577#define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
3578static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
3579{
3580 return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
3581}
3582#define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
3583#define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
3584static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
3585{
3586 return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
3587}
3588#define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
3589#define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
3590static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
3591{
3592 return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
3593}
3594#define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
3595#define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
3596static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
3597{
3598 return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
3599}
3600#define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
3601#define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
3602static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
3603{
3604 return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
3605}
3606
3607#define REG_A5XX_TEX_SAMP_1 0x00000001
3608#define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
3609#define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
3610static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
3611{
3612 return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
3613}
3614#define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
3615#define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
3616#define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
3617#define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
3618#define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
3619static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
3620{
3621 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
3622}
3623#define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
3624#define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
3625static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
3626{
3627 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
3628}
3629
3630#define REG_A5XX_TEX_SAMP_2 0x00000002
3631
3632#define REG_A5XX_TEX_SAMP_3 0x00000003
3633
3634#define REG_A5XX_TEX_CONST_0 0x00000000
3635#define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
3636#define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
3637static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
3638{
3639 return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
3640}
3641#define A5XX_TEX_CONST_0_SRGB 0x00000004
3642#define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
3643#define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
3644static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
3645{
3646 return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
3647}
3648#define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
3649#define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
3650static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
3651{
3652 return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
3653}
3654#define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
3655#define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
3656static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
3657{
3658 return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
3659}
3660#define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
3661#define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
3662static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
3663{
3664 return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
3665}
3666#define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
3667#define A5XX_TEX_CONST_0_FMT__SHIFT 22
3668static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
3669{
3670 return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
3671}
3672#define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
3673#define A5XX_TEX_CONST_0_SWAP__SHIFT 30
3674static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
3675{
3676 return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
3677}
3678
3679#define REG_A5XX_TEX_CONST_1 0x00000001
3680#define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
3681#define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
3682static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
3683{
3684 return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
3685}
3686#define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
3687#define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
3688static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
3689{
3690 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
3691}
3692
3693#define REG_A5XX_TEX_CONST_2 0x00000002
3694#define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
3695#define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
3696static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val)
3697{
3698 return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK;
3699}
3700#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
3701#define A5XX_TEX_CONST_2_PITCH__SHIFT 7
3702static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
3703{
3704 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
3705}
3706#define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
3707#define A5XX_TEX_CONST_2_TYPE__SHIFT 29
3708static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
3709{
3710 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
3711}
3712
3713#define REG_A5XX_TEX_CONST_3 0x00000003
3714#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
3715#define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
3716static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
3717{
3718 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
3719}
3720#define A5XX_TEX_CONST_3_FLAG 0x10000000
3721
3722#define REG_A5XX_TEX_CONST_4 0x00000004
3723#define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
3724#define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
3725static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
3726{
3727 return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
3728}
3729
3730#define REG_A5XX_TEX_CONST_5 0x00000005
3731#define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
3732#define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
3733static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
3734{
3735 return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
3736}
3737#define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
3738#define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
3739static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
3740{
3741 return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
3742}
3743
3744#define REG_A5XX_TEX_CONST_6 0x00000006
3745
3746#define REG_A5XX_TEX_CONST_7 0x00000007
3747
3748#define REG_A5XX_TEX_CONST_8 0x00000008
3749
3750#define REG_A5XX_TEX_CONST_9 0x00000009
3751
3752#define REG_A5XX_TEX_CONST_10 0x0000000a
3753
3754#define REG_A5XX_TEX_CONST_11 0x0000000b
3755
3756
3757#endif /* A5XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
index e81481d1b7df..4a33ba6f1244 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19 20
20Copyright (C) 2013-2016 by the following authors: 21Copyright (C) 2013-2016 by the following authors:
@@ -172,6 +173,14 @@ enum a3xx_color_swap {
172 XYZW = 3, 173 XYZW = 3,
173}; 174};
174 175
176enum a3xx_rb_blend_opcode {
177 BLEND_DST_PLUS_SRC = 0,
178 BLEND_SRC_MINUS_DST = 1,
179 BLEND_DST_MINUS_SRC = 2,
180 BLEND_MIN_DST_SRC = 3,
181 BLEND_MAX_DST_SRC = 4,
182};
183
175#define REG_AXXX_CP_RB_BASE 0x000001c0 184#define REG_AXXX_CP_RB_BASE 0x000001c0
176 185
177#define REG_AXXX_CP_RB_CNTL 0x000001c1 186#define REG_AXXX_CP_RB_CNTL 0x000001c1
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index d7477ff867c9..6a2930e75503 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19 20
20Copyright (C) 2013-2016 by the following authors: 21Copyright (C) 2013-2016 by the following authors:
@@ -58,6 +59,7 @@ enum vgt_event_type {
58 RST_PIX_CNT = 13, 59 RST_PIX_CNT = 13,
59 RST_VTX_CNT = 14, 60 RST_VTX_CNT = 14,
60 TILE_FLUSH = 15, 61 TILE_FLUSH = 15,
62 STAT_EVENT = 16,
61 CACHE_FLUSH_AND_INV_TS_EVENT = 20, 63 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
62 ZPASS_DONE = 21, 64 ZPASS_DONE = 21,
63 CACHE_FLUSH_AND_INV_EVENT = 22, 65 CACHE_FLUSH_AND_INV_EVENT = 22,
@@ -65,6 +67,10 @@ enum vgt_event_type {
65 PERFCOUNTER_STOP = 24, 67 PERFCOUNTER_STOP = 24,
66 VS_FETCH_DONE = 27, 68 VS_FETCH_DONE = 27,
67 FACENESS_FLUSH = 28, 69 FACENESS_FLUSH = 28,
70 UNK_1C = 28,
71 UNK_1D = 29,
72 BLIT = 30,
73 UNK_26 = 38,
68}; 74};
69 75
70enum pc_di_primtype { 76enum pc_di_primtype {
@@ -82,7 +88,6 @@ enum pc_di_primtype {
82 DI_PT_LINESTRIP_ADJ = 11, 88 DI_PT_LINESTRIP_ADJ = 11,
83 DI_PT_TRI_ADJ = 12, 89 DI_PT_TRI_ADJ = 12,
84 DI_PT_TRISTRIP_ADJ = 13, 90 DI_PT_TRISTRIP_ADJ = 13,
85 DI_PT_PATCHES = 34,
86}; 91};
87 92
88enum pc_di_src_sel { 93enum pc_di_src_sel {
@@ -110,11 +115,15 @@ enum adreno_pm4_packet_type {
110 CP_TYPE1_PKT = 0x40000000, 115 CP_TYPE1_PKT = 0x40000000,
111 CP_TYPE2_PKT = 0x80000000, 116 CP_TYPE2_PKT = 0x80000000,
112 CP_TYPE3_PKT = 0xc0000000, 117 CP_TYPE3_PKT = 0xc0000000,
118 CP_TYPE4_PKT = 0x40000000,
119 CP_TYPE7_PKT = 0x70000000,
113}; 120};
114 121
115enum adreno_pm4_type3_packets { 122enum adreno_pm4_type3_packets {
116 CP_ME_INIT = 72, 123 CP_ME_INIT = 72,
117 CP_NOP = 16, 124 CP_NOP = 16,
125 CP_PREEMPT_ENABLE = 28,
126 CP_PREEMPT_TOKEN = 30,
118 CP_INDIRECT_BUFFER = 63, 127 CP_INDIRECT_BUFFER = 63,
119 CP_INDIRECT_BUFFER_PFD = 55, 128 CP_INDIRECT_BUFFER_PFD = 55,
120 CP_WAIT_FOR_IDLE = 38, 129 CP_WAIT_FOR_IDLE = 38,
@@ -163,6 +172,7 @@ enum adreno_pm4_type3_packets {
163 CP_TEST_TWO_MEMS = 113, 172 CP_TEST_TWO_MEMS = 113,
164 CP_REG_WR_NO_CTXT = 120, 173 CP_REG_WR_NO_CTXT = 120,
165 CP_RECORD_PFP_TIMESTAMP = 17, 174 CP_RECORD_PFP_TIMESTAMP = 17,
175 CP_SET_SECURE_MODE = 102,
166 CP_WAIT_FOR_ME = 19, 176 CP_WAIT_FOR_ME = 19,
167 CP_SET_DRAW_STATE = 67, 177 CP_SET_DRAW_STATE = 67,
168 CP_DRAW_INDX_OFFSET = 56, 178 CP_DRAW_INDX_OFFSET = 56,
@@ -178,6 +188,22 @@ enum adreno_pm4_type3_packets {
178 CP_WAIT_MEM_WRITES = 18, 188 CP_WAIT_MEM_WRITES = 18,
179 CP_COND_REG_EXEC = 71, 189 CP_COND_REG_EXEC = 71,
180 CP_MEM_TO_REG = 66, 190 CP_MEM_TO_REG = 66,
191 CP_EXEC_CS = 51,
192 CP_PERFCOUNTER_ACTION = 80,
193 CP_SMMU_TABLE_UPDATE = 83,
194 CP_CONTEXT_REG_BUNCH = 92,
195 CP_YIELD_ENABLE = 28,
196 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
197 CP_SKIP_IB2_ENABLE_LOCAL = 35,
198 CP_SET_SUBDRAW_SIZE = 53,
199 CP_SET_VISIBILITY_OVERRIDE = 100,
200 CP_PREEMPT_ENABLE_GLOBAL = 105,
201 CP_PREEMPT_ENABLE_LOCAL = 106,
202 CP_CONTEXT_SWITCH_YIELD = 107,
203 CP_SET_RENDER_MODE = 108,
204 CP_COMPUTE_CHECKPOINT = 110,
205 CP_MEM_TO_MEM = 115,
206 CP_BLIT = 44,
181 IN_IB_PREFETCH_END = 23, 207 IN_IB_PREFETCH_END = 23,
182 IN_SUBBLK_PREFETCH = 31, 208 IN_SUBBLK_PREFETCH = 31,
183 IN_INSTR_PREFETCH = 32, 209 IN_INSTR_PREFETCH = 32,
@@ -196,6 +222,7 @@ enum adreno_state_block {
196 SB_VERT_SHADER = 4, 222 SB_VERT_SHADER = 4,
197 SB_GEOM_SHADER = 5, 223 SB_GEOM_SHADER = 5,
198 SB_FRAG_SHADER = 6, 224 SB_FRAG_SHADER = 6,
225 SB_COMPUTE_SHADER = 7,
199}; 226};
200 227
201enum adreno_state_type { 228enum adreno_state_type {
@@ -218,6 +245,17 @@ enum a4xx_index_size {
218 INDEX4_SIZE_32_BIT = 2, 245 INDEX4_SIZE_32_BIT = 2,
219}; 246};
220 247
248enum render_mode_cmd {
249 BYPASS = 1,
250 GMEM = 3,
251 BLIT2D = 5,
252};
253
254enum cp_blit_cmd {
255 BLIT_OP_FILL = 0,
256 BLIT_OP_BLIT = 1,
257};
258
221#define REG_CP_LOAD_STATE_0 0x00000000 259#define REG_CP_LOAD_STATE_0 0x00000000
222#define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff 260#define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
223#define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 261#define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
@@ -258,6 +296,14 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
258 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 296 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
259} 297}
260 298
299#define REG_CP_LOAD_STATE_2 0x00000002
300#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
301#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT 0
302static inline uint32_t CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val)
303{
304 return ((val) << CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK;
305}
306
261#define REG_CP_DRAW_INDX_0 0x00000000 307#define REG_CP_DRAW_INDX_0 0x00000000
262#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff 308#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
263#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 309#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
@@ -389,7 +435,12 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va
389{ 435{
390 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; 436 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
391} 437}
392#define CP_DRAW_INDX_OFFSET_0_TESSELLATE 0x00000100 438#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
439#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
440static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
441{
442 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
443}
393#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 444#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
394#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 445#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
395static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) 446static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
@@ -437,30 +488,40 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
437 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; 488 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
438} 489}
439 490
440#define REG_CP_SET_DRAW_STATE_0 0x00000000 491static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
441#define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff 492
442#define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0 493static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
443static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val) 494#define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
495#define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
496static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
444{ 497{
445 return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK; 498 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
446} 499}
447#define CP_SET_DRAW_STATE_0_DIRTY 0x00010000 500#define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
448#define CP_SET_DRAW_STATE_0_DISABLE 0x00020000 501#define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
449#define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000 502#define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
450#define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000 503#define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
451#define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000 504#define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
452#define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24 505#define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
453static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val) 506static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
454{ 507{
455 return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK; 508 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
456} 509}
457 510
458#define REG_CP_SET_DRAW_STATE_1 0x00000001 511static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
459#define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff 512#define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
460#define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0 513#define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
461static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val) 514static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
462{ 515{
463 return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK; 516 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
517}
518
519static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
520#define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
521#define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
522static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
523{
524 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
464} 525}
465 526
466#define REG_CP_SET_BIN_0 0x00000000 527#define REG_CP_SET_BIN_0 0x00000000
@@ -533,5 +594,192 @@ static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
533 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; 594 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
534} 595}
535 596
597#define REG_CP_DISPATCH_COMPUTE_0 0x00000000
598
599#define REG_CP_DISPATCH_COMPUTE_1 0x00000001
600#define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
601#define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
602static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
603{
604 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
605}
606
607#define REG_CP_DISPATCH_COMPUTE_2 0x00000002
608#define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
609#define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
610static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
611{
612 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
613}
614
615#define REG_CP_DISPATCH_COMPUTE_3 0x00000003
616#define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
617#define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
618static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
619{
620 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
621}
622
623#define REG_CP_SET_RENDER_MODE_0 0x00000000
624#define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
625#define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
626static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
627{
628 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
629}
630
631#define REG_CP_SET_RENDER_MODE_1 0x00000001
632#define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
633#define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
634static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
635{
636 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
637}
638
639#define REG_CP_SET_RENDER_MODE_2 0x00000002
640#define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
641#define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
642static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
643{
644 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
645}
646
647#define REG_CP_SET_RENDER_MODE_3 0x00000003
648#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
649
650#define REG_CP_SET_RENDER_MODE_4 0x00000004
651
652#define REG_CP_SET_RENDER_MODE_5 0x00000005
653#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
654#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
655static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
656{
657 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
658}
659
660#define REG_CP_SET_RENDER_MODE_6 0x00000006
661#define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
662#define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
663static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
664{
665 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
666}
667
668#define REG_CP_SET_RENDER_MODE_7 0x00000007
669#define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
670#define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
671static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
672{
673 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
674}
675
676#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
677
678#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
679#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
680#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
681static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
682{
683 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
684}
685
686#define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
687#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
688#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
689static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
690{
691 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
692}
693
694#define REG_CP_EVENT_WRITE_0 0x00000000
695#define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
696#define CP_EVENT_WRITE_0_EVENT__SHIFT 0
697static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
698{
699 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
700}
701
702#define REG_CP_EVENT_WRITE_1 0x00000001
703#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
704#define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
705static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
706{
707 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
708}
709
710#define REG_CP_EVENT_WRITE_2 0x00000002
711#define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
712#define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
713static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
714{
715 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
716}
717
718#define REG_CP_EVENT_WRITE_3 0x00000003
719
720#define REG_CP_BLIT_0 0x00000000
721#define CP_BLIT_0_OP__MASK 0x0000000f
722#define CP_BLIT_0_OP__SHIFT 0
723static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
724{
725 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
726}
727
728#define REG_CP_BLIT_1 0x00000001
729#define CP_BLIT_1_SRC_X1__MASK 0x0000ffff
730#define CP_BLIT_1_SRC_X1__SHIFT 0
731static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
732{
733 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
734}
735#define CP_BLIT_1_SRC_Y1__MASK 0xffff0000
736#define CP_BLIT_1_SRC_Y1__SHIFT 16
737static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
738{
739 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
740}
741
742#define REG_CP_BLIT_2 0x00000002
743#define CP_BLIT_2_SRC_X2__MASK 0x0000ffff
744#define CP_BLIT_2_SRC_X2__SHIFT 0
745static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
746{
747 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
748}
749#define CP_BLIT_2_SRC_Y2__MASK 0xffff0000
750#define CP_BLIT_2_SRC_Y2__SHIFT 16
751static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
752{
753 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
754}
755
756#define REG_CP_BLIT_3 0x00000003
757#define CP_BLIT_3_DST_X1__MASK 0x0000ffff
758#define CP_BLIT_3_DST_X1__SHIFT 0
759static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
760{
761 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
762}
763#define CP_BLIT_3_DST_Y1__MASK 0xffff0000
764#define CP_BLIT_3_DST_Y1__SHIFT 16
765static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
766{
767 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
768}
769
770#define REG_CP_BLIT_4 0x00000004
771#define CP_BLIT_4_DST_X2__MASK 0x0000ffff
772#define CP_BLIT_4_DST_X2__SHIFT 0
773static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
774{
775 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
776}
777#define CP_BLIT_4_DST_Y2__MASK 0xffff0000
778#define CP_BLIT_4_DST_Y2__SHIFT 16
779static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
780{
781 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
782}
783
536 784
537#endif /* ADRENO_PM4_XML */ 785#endif /* ADRENO_PM4_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 4958594d5266..39dff7d5e89b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
index 2d999494cdea..8b9f3ebaeba7 100644
--- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
+++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
@@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
index 506434fac993..3fcbb30dc241 100644
--- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h
+++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
@@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
diff --git a/drivers/gpu/drm/msm/edp/edp.xml.h b/drivers/gpu/drm/msm/edp/edp.xml.h
index f1072c18c81e..d7bf3232dc88 100644
--- a/drivers/gpu/drm/msm/edp/edp.xml.h
+++ b/drivers/gpu/drm/msm/edp/edp.xml.h
@@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 34c7df6549c1..0a97ff75ed6f 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
index 6eab7d0cf6b5..1b996ede7a65 100644
--- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
@@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
index 6688e79cc88e..88037889589b 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
@@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index ca6ca30650a0..27d5371acee0 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,9 +8,17 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-05-10 05:06:30) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /local/mnt/workspace/source_trees/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2016-01-07 08:45:55) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
21- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
14 22
15Copyright (C) 2013-2016 by the following authors: 23Copyright (C) 2013-2016 by the following authors:
16- Rob Clark <robdclark@gmail.com> (robclark) 24- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
index 452e3518f98b..8994c365e218 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
@@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-04 21:35:13 -0400