diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2018-05-16 16:34:19 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-05-18 17:08:19 -0400 |
commit | a1a0c40664fbd0bd1a9fa53e14ccab539005e2ca (patch) | |
tree | 4963361677294b0d367328721ce110bca09994c8 | |
parent | b4b9f944e4ee3d1a268d96d7de2d519b491e8ea5 (diff) |
drm/amdgpu/display: fix vega12/20 handling in dal_asic_id.h
- Remove unused ASICREV_IS_VEGA12_p() macro
- Fix ASICREV_IS_VEGA12_P() macro to properly check against vega20
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/include/dal_asic_id.h | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index cac069dd2a0e..25029ed42d89 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h | |||
@@ -115,19 +115,17 @@ | |||
115 | /* DCE12 */ | 115 | /* DCE12 */ |
116 | #define AI_UNKNOWN 0xFF | 116 | #define AI_UNKNOWN 0xFF |
117 | 117 | ||
118 | #define AI_VEGA20_P_A0 40 | ||
119 | #define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN)) | ||
120 | |||
121 | #define AI_GREENLAND_P_A0 1 | 118 | #define AI_GREENLAND_P_A0 1 |
122 | #define AI_GREENLAND_P_A1 2 | 119 | #define AI_GREENLAND_P_A1 2 |
123 | #define AI_UNKNOWN 0xFF | 120 | #define AI_UNKNOWN 0xFF |
124 | 121 | ||
125 | #define AI_VEGA12_P_A0 20 | 122 | #define AI_VEGA12_P_A0 20 |
123 | #define AI_VEGA20_P_A0 40 | ||
126 | #define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0) | 124 | #define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0) |
127 | #define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0) | 125 | #define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0) |
128 | 126 | ||
129 | #define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN)) | 127 | #define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_VEGA20_P_A0)) |
130 | #define ASICREV_IS_VEGA12_p(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN)) | 128 | #define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN)) |
131 | 129 | ||
132 | /* DCN1_0 */ | 130 | /* DCN1_0 */ |
133 | #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ | 131 | #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ |