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authorArnd Bergmann <arnd@arndb.de>2016-07-14 09:39:27 -0400
committerArnd Bergmann <arnd@arndb.de>2016-07-14 09:39:27 -0400
commita185c8639fe5888fadcba78b430a412e4324198f (patch)
tree5b803cba2a19cb84772142e8f01e78f092c2cd14
parent2869576d0f531757f0dc6897f5f6578b3ad7c6c1 (diff)
parent85afd20e4bccc39f4eae01cb50e435ca45aef912 (diff)
Merge tag 'tegra-for-4.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
Merge "ARM: tegra: Device tree changes for v4.8-rc1" from Thierry Reding: Some cleanups to existing device tree sources and add Toradex Apalis TK1 support. * tag 'tegra-for-4.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Initial support for Apalis TK1 ARM: tegra: Remove commas from unit addresses on Tegra124 ARM: tegra: Import latest Jetson TK1 spreadsheet ARM: tegra: Add spaces around = in properties ARM: tegra: Fix a couple of DTC warnings
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts2
-rw-r--r--arch/arm/boot/dts/tegra114-roth.dts4
-rw-r--r--arch/arm/boot/dts/tegra114-tn7.dts2
-rw-r--r--arch/arm/boot/dts/tegra124-apalis-emc.dtsi1502
-rw-r--r--arch/arm/boot/dts/tegra124-apalis-eval.dts284
-rw-r--r--arch/arm/boot/dts/tegra124-apalis.dtsi2100
-rw-r--r--arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi6
-rw-r--r--arch/arm/boot/dts/tegra124-jetson-tk1.dts88
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi6
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-big.dts4
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi6
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-blaze.dts2
-rw-r--r--arch/arm/boot/dts/tegra124-nyan.dtsi60
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts70
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi125
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts2
-rw-r--r--arch/arm/boot/dts/tegra30-apalis.dtsi7
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts2
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra30-colibri-eval-v3.dts2
-rw-r--r--arch/arm/boot/dts/tegra30-colibri.dtsi2
29 files changed, 4091 insertions, 202 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3cc5f0841c00..b25cc6af35c8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -816,6 +816,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
816 tegra114-roth.dtb \ 816 tegra114-roth.dtb \
817 tegra114-tn7.dtb 817 tegra114-tn7.dtb
818dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ 818dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
819 tegra124-apalis-eval.dtb \
819 tegra124-jetson-tk1.dtb \ 820 tegra124-jetson-tk1.dtb \
820 tegra124-nyan-big.dtb \ 821 tegra124-nyan-big.dtb \
821 tegra124-nyan-blaze.dtb \ 822 tegra124-nyan-blaze.dtb \
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index c970bf65c74c..1dfc492cc004 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1149,7 +1149,7 @@
1149 1149
1150 clk32k_in: clock@0 { 1150 clk32k_in: clock@0 {
1151 compatible = "fixed-clock"; 1151 compatible = "fixed-clock";
1152 reg=<0>; 1152 reg = <0>;
1153 #clock-cells = <0>; 1153 #clock-cells = <0>;
1154 clock-frequency = <32768>; 1154 clock-frequency = <32768>;
1155 }; 1155 };
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
index 9d868af97b8e..70cf40996c3f 100644
--- a/arch/arm/boot/dts/tegra114-roth.dts
+++ b/arch/arm/boot/dts/tegra114-roth.dts
@@ -1020,9 +1020,9 @@
1020 #address-cells = <1>; 1020 #address-cells = <1>;
1021 #size-cells = <0>; 1021 #size-cells = <0>;
1022 1022
1023 clk32k_in: clock { 1023 clk32k_in: clock@0 {
1024 compatible = "fixed-clock"; 1024 compatible = "fixed-clock";
1025 reg=<0>; 1025 reg = <0>;
1026 #clock-cells = <0>; 1026 #clock-cells = <0>;
1027 clock-frequency = <32768>; 1027 clock-frequency = <32768>;
1028 }; 1028 };
diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts
index 89047edb5c5f..17dd14545862 100644
--- a/arch/arm/boot/dts/tegra114-tn7.dts
+++ b/arch/arm/boot/dts/tegra114-tn7.dts
@@ -277,7 +277,7 @@
277 #address-cells = <1>; 277 #address-cells = <1>;
278 #size-cells = <0>; 278 #size-cells = <0>;
279 279
280 clk32k_in: clock { 280 clk32k_in: clock@0 {
281 compatible = "fixed-clock"; 281 compatible = "fixed-clock";
282 reg = <0>; 282 reg = <0>;
283 #clock-cells = <0>; 283 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
new file mode 100644
index 000000000000..ca2c3a557895
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
@@ -0,0 +1,1502 @@
1/*
2 * Copyright 2016 Toradex AG
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/ {
43 clock@60006000 {
44 emc-timings-1 {
45 nvidia,ram-code = <1>;
46
47 timing-12750000 {
48 clock-frequency = <12750000>;
49 nvidia,parent-clock-frequency = <408000000>;
50 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
51 clock-names = "emc-parent";
52 };
53 timing-20400000 {
54 clock-frequency = <20400000>;
55 nvidia,parent-clock-frequency = <408000000>;
56 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
57 clock-names = "emc-parent";
58 };
59 timing-40800000 {
60 clock-frequency = <40800000>;
61 nvidia,parent-clock-frequency = <408000000>;
62 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
63 clock-names = "emc-parent";
64 };
65 timing-68000000 {
66 clock-frequency = <68000000>;
67 nvidia,parent-clock-frequency = <408000000>;
68 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
69 clock-names = "emc-parent";
70 };
71 timing-102000000 {
72 clock-frequency = <102000000>;
73 nvidia,parent-clock-frequency = <408000000>;
74 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
75 clock-names = "emc-parent";
76 };
77 timing-204000000 {
78 clock-frequency = <204000000>;
79 nvidia,parent-clock-frequency = <408000000>;
80 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
81 clock-names = "emc-parent";
82 };
83 timing-300000000 {
84 clock-frequency = <300000000>;
85 nvidia,parent-clock-frequency = <600000000>;
86 clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
87 clock-names = "emc-parent";
88 };
89 timing-396000000 {
90 clock-frequency = <396000000>;
91 nvidia,parent-clock-frequency = <792000000>;
92 clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
93 clock-names = "emc-parent";
94 };
95 timing-528000000 {
96 clock-frequency = <528000000>;
97 nvidia,parent-clock-frequency = <528000000>;
98 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
99 clock-names = "emc-parent";
100 };
101 timing-600000000 {
102 clock-frequency = <600000000>;
103 nvidia,parent-clock-frequency = <600000000>;
104 clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
105 clock-names = "emc-parent";
106 };
107 timing-792000000 {
108 clock-frequency = <792000000>;
109 nvidia,parent-clock-frequency = <792000000>;
110 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
111 clock-names = "emc-parent";
112 };
113 timing-924000000 {
114 clock-frequency = <924000000>;
115 nvidia,parent-clock-frequency = <924000000>;
116 clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
117 clock-names = "emc-parent";
118 };
119 };
120 };
121
122 emc@7001b000 {
123 emc-timings-1 {
124 nvidia,ram-code = <1>;
125
126 timing-12750000 {
127 clock-frequency = <12750000>;
128
129 nvidia,emc-auto-cal-config = <0xa1430000>;
130 nvidia,emc-auto-cal-config2 = <0x00000000>;
131 nvidia,emc-auto-cal-config3 = <0x00000000>;
132 nvidia,emc-auto-cal-interval = <0x001fffff>;
133 nvidia,emc-bgbias-ctl0 = <0x00000008>;
134 nvidia,emc-cfg = <0x73240000>;
135 nvidia,emc-cfg-2 = <0x000008c5>;
136 nvidia,emc-ctt-term-ctrl = <0x00000802>;
137 nvidia,emc-mode-1 = <0x80100003>;
138 nvidia,emc-mode-2 = <0x80200008>;
139 nvidia,emc-mode-4 = <0x00000000>;
140 nvidia,emc-mode-reset = <0x80001221>;
141 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
142 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
143 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
144 nvidia,emc-zcal-cnt-long = <0x00000042>;
145 nvidia,emc-zcal-interval = <0x00000000>;
146
147 nvidia,emc-configuration = <
148 0x00000000 0x00000003
149 0x00000000 0x00000000
150 0x00000000 0x00000004
151 0x0000000a 0x00000005
152 0x0000000b 0x00000000
153 0x00000000 0x00000003
154 0x00000003 0x00000000
155 0x00000006 0x00000006
156 0x00000006 0x00000002
157 0x00000000 0x00000005
158 0x00000005 0x00010000
159 0x00000003 0x00000000
160 0x00000000 0x00000000
161 0x00000000 0x00000004
162 0x0000000c 0x0000000d
163 0x0000000f 0x00000060
164 0x00000000 0x00000018
165 0x00000002 0x00000002
166 0x00000001 0x00000000
167 0x00000007 0x0000000f
168 0x00000005 0x00000005
169 0x00000004 0x00000005
170 0x00000004 0x00000000
171 0x00000000 0x00000005
172 0x00000005 0x00000064
173 0x00000000 0x00000000
174 0x00000000 0x106aa298
175 0x002c00a0 0x00008000
176 0x00080000 0x00080000
177 0x00080000 0x00080000
178 0x00080000 0x00080000
179 0x00080000 0x00080000
180 0x00080000 0x00080000
181 0x00080000 0x00080000
182 0x00080000 0x00080000
183 0x00080000 0x00080000
184 0x00000000 0x00000000
185 0x00000000 0x00000000
186 0x00000000 0x00000000
187 0x00000000 0x00000000
188 0x00000000 0x00000000
189 0x00000000 0x00000000
190 0x00000000 0x00000000
191 0x00000000 0x00000000
192 0x00000000 0x00000000
193 0x00000000 0x00000000
194 0x00000000 0x00000000
195 0x00000000 0x00000000
196 0x00000000 0x00000000
197 0x00000000 0x00000000
198 0x00000000 0x00000000
199 0x00000000 0x00000000
200 0x00000000 0x00000000
201 0x00000000 0x00000000
202 0x00000000 0x00000000
203 0x000fc000 0x000fc000
204 0x000fc000 0x000fc000
205 0x0000fc00 0x0000fc00
206 0x0000fc00 0x0000fc00
207 0x10000280 0x00000000
208 0x00111111 0x00000000
209 0x00000000 0x77ffc081
210 0x00000e0e 0x81f1f108
211 0x07070004 0x0000003f
212 0x016eeeee 0x51451400
213 0x00514514 0x00514514
214 0x51451400 0x0000003f
215 0x00000007 0x00000000
216 0x00000042 0x000e000e
217 0x00000000 0x00000003
218 0x0000f2f3 0x800001c5
219 0x0000000a
220 >;
221 };
222
223 timing-20400000 {
224 clock-frequency = <20400000>;
225
226 nvidia,emc-auto-cal-config = <0xa1430000>;
227 nvidia,emc-auto-cal-config2 = <0x00000000>;
228 nvidia,emc-auto-cal-config3 = <0x00000000>;
229 nvidia,emc-auto-cal-interval = <0x001fffff>;
230 nvidia,emc-bgbias-ctl0 = <0x00000008>;
231 nvidia,emc-cfg = <0x73240000>;
232 nvidia,emc-cfg-2 = <0x000008c5>;
233 nvidia,emc-ctt-term-ctrl = <0x00000802>;
234 nvidia,emc-mode-1 = <0x80100003>;
235 nvidia,emc-mode-2 = <0x80200008>;
236 nvidia,emc-mode-4 = <0x00000000>;
237 nvidia,emc-mode-reset = <0x80001221>;
238 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
239 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
240 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
241 nvidia,emc-zcal-cnt-long = <0x00000042>;
242 nvidia,emc-zcal-interval = <0x00000000>;
243
244 nvidia,emc-configuration = <
245 0x00000000 0x00000005
246 0x00000000 0x00000000
247 0x00000000 0x00000004
248 0x0000000a 0x00000005
249 0x0000000b 0x00000000
250 0x00000000 0x00000003
251 0x00000003 0x00000000
252 0x00000006 0x00000006
253 0x00000006 0x00000002
254 0x00000000 0x00000005
255 0x00000005 0x00010000
256 0x00000003 0x00000000
257 0x00000000 0x00000000
258 0x00000000 0x00000004
259 0x0000000c 0x0000000d
260 0x0000000f 0x0000009a
261 0x00000000 0x00000026
262 0x00000002 0x00000002
263 0x00000001 0x00000000
264 0x00000007 0x0000000f
265 0x00000006 0x00000006
266 0x00000004 0x00000005
267 0x00000004 0x00000000
268 0x00000000 0x00000005
269 0x00000005 0x000000a0
270 0x00000000 0x00000000
271 0x00000000 0x106aa298
272 0x002c00a0 0x00008000
273 0x00080000 0x00080000
274 0x00080000 0x00080000
275 0x00080000 0x00080000
276 0x00080000 0x00080000
277 0x00080000 0x00080000
278 0x00080000 0x00080000
279 0x00080000 0x00080000
280 0x00080000 0x00080000
281 0x00000000 0x00000000
282 0x00000000 0x00000000
283 0x00000000 0x00000000
284 0x00000000 0x00000000
285 0x00000000 0x00000000
286 0x00000000 0x00000000
287 0x00000000 0x00000000
288 0x00000000 0x00000000
289 0x00000000 0x00000000
290 0x00000000 0x00000000
291 0x00000000 0x00000000
292 0x00000000 0x00000000
293 0x00000000 0x00000000
294 0x00000000 0x00000000
295 0x00000000 0x00000000
296 0x00000000 0x00000000
297 0x00000000 0x00000000
298 0x00000000 0x00000000
299 0x00000000 0x00000000
300 0x000fc000 0x000fc000
301 0x000fc000 0x000fc000
302 0x0000fc00 0x0000fc00
303 0x0000fc00 0x0000fc00
304 0x10000280 0x00000000
305 0x00111111 0x00000000
306 0x00000000 0x77ffc081
307 0x00000e0e 0x81f1f108
308 0x07070004 0x0000003f
309 0x016eeeee 0x51451400
310 0x00514514 0x00514514
311 0x51451400 0x0000003f
312 0x0000000b 0x00000000
313 0x00000042 0x000e000e
314 0x00000000 0x00000003
315 0x0000f2f3 0x8000023a
316 0x0000000a
317 >;
318 };
319
320 timing-40800000 {
321 clock-frequency = <40800000>;
322
323 nvidia,emc-auto-cal-config = <0xa1430000>;
324 nvidia,emc-auto-cal-config2 = <0x00000000>;
325 nvidia,emc-auto-cal-config3 = <0x00000000>;
326 nvidia,emc-auto-cal-interval = <0x001fffff>;
327 nvidia,emc-bgbias-ctl0 = <0x00000008>;
328 nvidia,emc-cfg = <0x73240000>;
329 nvidia,emc-cfg-2 = <0x000008c5>;
330 nvidia,emc-ctt-term-ctrl = <0x00000802>;
331 nvidia,emc-mode-1 = <0x80100003>;
332 nvidia,emc-mode-2 = <0x80200008>;
333 nvidia,emc-mode-4 = <0x00000000>;
334 nvidia,emc-mode-reset = <0x80001221>;
335 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
336 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
337 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
338 nvidia,emc-zcal-cnt-long = <0x00000042>;
339 nvidia,emc-zcal-interval = <0x00000000>;
340
341 nvidia,emc-configuration = <
342 0x00000001 0x0000000a
343 0x00000000 0x00000001
344 0x00000000 0x00000004
345 0x0000000a 0x00000005
346 0x0000000b 0x00000000
347 0x00000000 0x00000003
348 0x00000003 0x00000000
349 0x00000006 0x00000006
350 0x00000006 0x00000002
351 0x00000000 0x00000005
352 0x00000005 0x00010000
353 0x00000003 0x00000000
354 0x00000000 0x00000000
355 0x00000000 0x00000004
356 0x0000000c 0x0000000d
357 0x0000000f 0x00000134
358 0x00000000 0x0000004d
359 0x00000002 0x00000002
360 0x00000001 0x00000000
361 0x00000008 0x0000000f
362 0x0000000c 0x0000000c
363 0x00000004 0x00000005
364 0x00000004 0x00000000
365 0x00000000 0x00000005
366 0x00000005 0x0000013f
367 0x00000000 0x00000000
368 0x00000000 0x106aa298
369 0x002c00a0 0x00008000
370 0x00080000 0x00080000
371 0x00080000 0x00080000
372 0x00080000 0x00080000
373 0x00080000 0x00080000
374 0x00080000 0x00080000
375 0x00080000 0x00080000
376 0x00080000 0x00080000
377 0x00080000 0x00080000
378 0x00000000 0x00000000
379 0x00000000 0x00000000
380 0x00000000 0x00000000
381 0x00000000 0x00000000
382 0x00000000 0x00000000
383 0x00000000 0x00000000
384 0x00000000 0x00000000
385 0x00000000 0x00000000
386 0x00000000 0x00000000
387 0x00000000 0x00000000
388 0x00000000 0x00000000
389 0x00000000 0x00000000
390 0x00000000 0x00000000
391 0x00000000 0x00000000
392 0x00000000 0x00000000
393 0x00000000 0x00000000
394 0x00000000 0x00000000
395 0x00000000 0x00000000
396 0x00000000 0x00000000
397 0x000fc000 0x000fc000
398 0x000fc000 0x000fc000
399 0x0000fc00 0x0000fc00
400 0x0000fc00 0x0000fc00
401 0x10000280 0x00000000
402 0x00111111 0x00000000
403 0x00000000 0x77ffc081
404 0x00000e0e 0x81f1f108
405 0x07070004 0x0000003f
406 0x016eeeee 0x51451400
407 0x00514514 0x00514514
408 0x51451400 0x0000003f
409 0x00000015 0x00000000
410 0x00000042 0x000e000e
411 0x00000000 0x00000003
412 0x0000f2f3 0x80000370
413 0x0000000a
414 >;
415 };
416
417 timing-68000000 {
418 clock-frequency = <68000000>;
419
420 nvidia,emc-auto-cal-config = <0xa1430000>;
421 nvidia,emc-auto-cal-config2 = <0x00000000>;
422 nvidia,emc-auto-cal-config3 = <0x00000000>;
423 nvidia,emc-auto-cal-interval = <0x001fffff>;
424 nvidia,emc-bgbias-ctl0 = <0x00000008>;
425 nvidia,emc-cfg = <0x73240000>;
426 nvidia,emc-cfg-2 = <0x000008c5>;
427 nvidia,emc-ctt-term-ctrl = <0x00000802>;
428 nvidia,emc-mode-1 = <0x80100003>;
429 nvidia,emc-mode-2 = <0x80200008>;
430 nvidia,emc-mode-4 = <0x00000000>;
431 nvidia,emc-mode-reset = <0x80001221>;
432 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
433 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
434 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
435 nvidia,emc-zcal-cnt-long = <0x00000042>;
436 nvidia,emc-zcal-interval = <0x00000000>;
437
438 nvidia,emc-configuration = <
439 0x00000003 0x00000011
440 0x00000000 0x00000002
441 0x00000000 0x00000004
442 0x0000000a 0x00000005
443 0x0000000b 0x00000000
444 0x00000000 0x00000003
445 0x00000003 0x00000000
446 0x00000006 0x00000006
447 0x00000006 0x00000002
448 0x00000000 0x00000005
449 0x00000005 0x00010000
450 0x00000003 0x00000000
451 0x00000000 0x00000000
452 0x00000000 0x00000004
453 0x0000000c 0x0000000d
454 0x0000000f 0x00000202
455 0x00000000 0x00000080
456 0x00000002 0x00000002
457 0x00000001 0x00000000
458 0x0000000f 0x0000000f
459 0x00000013 0x00000013
460 0x00000004 0x00000005
461 0x00000004 0x00000001
462 0x00000000 0x00000005
463 0x00000005 0x00000213
464 0x00000000 0x00000000
465 0x00000000 0x106aa298
466 0x002c00a0 0x00008000
467 0x00080000 0x00080000
468 0x00080000 0x00080000
469 0x00080000 0x00080000
470 0x00080000 0x00080000
471 0x00080000 0x00080000
472 0x00080000 0x00080000
473 0x00080000 0x00080000
474 0x00080000 0x00080000
475 0x00000000 0x00000000
476 0x00000000 0x00000000
477 0x00000000 0x00000000
478 0x00000000 0x00000000
479 0x00000000 0x00000000
480 0x00000000 0x00000000
481 0x00000000 0x00000000
482 0x00000000 0x00000000
483 0x00000000 0x00000000
484 0x00000000 0x00000000
485 0x00000000 0x00000000
486 0x00000000 0x00000000
487 0x00000000 0x00000000
488 0x00000000 0x00000000
489 0x00000000 0x00000000
490 0x00000000 0x00000000
491 0x00000000 0x00000000
492 0x00000000 0x00000000
493 0x00000000 0x00000000
494 0x000fc000 0x000fc000
495 0x000fc000 0x000fc000
496 0x0000fc00 0x0000fc00
497 0x0000fc00 0x0000fc00
498 0x10000280 0x00000000
499 0x00111111 0x00000000
500 0x00000000 0x77ffc081
501 0x00000e0e 0x81f1f108
502 0x07070004 0x0000003f
503 0x016eeeee 0x51451400
504 0x00514514 0x00514514
505 0x51451400 0x0000003f
506 0x00000022 0x00000000
507 0x00000042 0x000e000e
508 0x00000000 0x00000003
509 0x0000f2f3 0x8000050e
510 0x0000000a
511 >;
512 };
513
514 timing-102000000 {
515 clock-frequency = <102000000>;
516
517 nvidia,emc-auto-cal-config = <0xa1430000>;
518 nvidia,emc-auto-cal-config2 = <0x00000000>;
519 nvidia,emc-auto-cal-config3 = <0x00000000>;
520 nvidia,emc-auto-cal-interval = <0x001fffff>;
521 nvidia,emc-bgbias-ctl0 = <0x00000008>;
522 nvidia,emc-cfg = <0x73240000>;
523 nvidia,emc-cfg-2 = <0x000008c5>;
524 nvidia,emc-ctt-term-ctrl = <0x00000802>;
525 nvidia,emc-mode-1 = <0x80100003>;
526 nvidia,emc-mode-2 = <0x80200008>;
527 nvidia,emc-mode-4 = <0x00000000>;
528 nvidia,emc-mode-reset = <0x80001221>;
529 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
530 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
531 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
532 nvidia,emc-zcal-cnt-long = <0x00000042>;
533 nvidia,emc-zcal-interval = <0x00000000>;
534
535 nvidia,emc-configuration = <
536 0x00000004 0x0000001a
537 0x00000000 0x00000003
538 0x00000001 0x00000004
539 0x0000000a 0x00000005
540 0x0000000b 0x00000001
541 0x00000001 0x00000003
542 0x00000003 0x00000000
543 0x00000006 0x00000006
544 0x00000006 0x00000002
545 0x00000000 0x00000005
546 0x00000005 0x00010000
547 0x00000003 0x00000000
548 0x00000000 0x00000000
549 0x00000000 0x00000004
550 0x0000000c 0x0000000d
551 0x0000000f 0x00000304
552 0x00000000 0x000000c1
553 0x00000002 0x00000002
554 0x00000001 0x00000000
555 0x00000018 0x0000000f
556 0x0000001c 0x0000001c
557 0x00000004 0x00000005
558 0x00000004 0x00000002
559 0x00000000 0x00000005
560 0x00000005 0x0000031c
561 0x00000000 0x00000000
562 0x00000000 0x106aa298
563 0x002c00a0 0x00008000
564 0x00080000 0x00080000
565 0x00080000 0x00080000
566 0x00080000 0x00080000
567 0x00080000 0x00080000
568 0x00080000 0x00080000
569 0x00080000 0x00080000
570 0x00080000 0x00080000
571 0x00080000 0x00080000
572 0x00000000 0x00000000
573 0x00000000 0x00000000
574 0x00000000 0x00000000
575 0x00000000 0x00000000
576 0x00000000 0x00000000
577 0x00000000 0x00000000
578 0x00000000 0x00000000
579 0x00000000 0x00000000
580 0x00000000 0x00000000
581 0x00000000 0x00000000
582 0x00000000 0x00000000
583 0x00000000 0x00000000
584 0x00000000 0x00000000
585 0x00000000 0x00000000
586 0x00000000 0x00000000
587 0x00000000 0x00000000
588 0x00000000 0x00000000
589 0x00000000 0x00000000
590 0x00000000 0x00000000
591 0x000fc000 0x000fc000
592 0x000fc000 0x000fc000
593 0x0000fc00 0x0000fc00
594 0x0000fc00 0x0000fc00
595 0x10000280 0x00000000
596 0x00111111 0x00000000
597 0x00000000 0x77ffc081
598 0x00000e0e 0x81f1f108
599 0x07070004 0x0000003f
600 0x016eeeee 0x51451400
601 0x00514514 0x00514514
602 0x51451400 0x0000003f
603 0x00000033 0x00000000
604 0x00000042 0x000e000e
605 0x00000000 0x00000003
606 0x0000f2f3 0x80000713
607 0x0000000a
608 >;
609 };
610
611 timing-204000000 {
612 clock-frequency = <204000000>;
613
614 nvidia,emc-auto-cal-config = <0xa1430000>;
615 nvidia,emc-auto-cal-config2 = <0x00000000>;
616 nvidia,emc-auto-cal-config3 = <0x00000000>;
617 nvidia,emc-auto-cal-interval = <0x001fffff>;
618 nvidia,emc-bgbias-ctl0 = <0x00000008>;
619 nvidia,emc-cfg = <0x73240000>;
620 nvidia,emc-cfg-2 = <0x000008cd>;
621 nvidia,emc-ctt-term-ctrl = <0x00000802>;
622 nvidia,emc-mode-1 = <0x80100003>;
623 nvidia,emc-mode-2 = <0x80200008>;
624 nvidia,emc-mode-4 = <0x00000000>;
625 nvidia,emc-mode-reset = <0x80001221>;
626 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
627 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
628 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
629 nvidia,emc-zcal-cnt-long = <0x00000042>;
630 nvidia,emc-zcal-interval = <0x00020000>;
631
632 nvidia,emc-configuration = <
633 0x00000009 0x00000035
634 0x00000000 0x00000006
635 0x00000002 0x00000005
636 0x0000000a 0x00000005
637 0x0000000b 0x00000002
638 0x00000002 0x00000003
639 0x00000003 0x00000000
640 0x00000005 0x00000005
641 0x00000006 0x00000002
642 0x00000000 0x00000004
643 0x00000006 0x00010000
644 0x00000003 0x00000000
645 0x00000000 0x00000000
646 0x00000000 0x00000003
647 0x0000000d 0x0000000f
648 0x00000011 0x00000607
649 0x00000000 0x00000181
650 0x00000002 0x00000002
651 0x00000001 0x00000000
652 0x00000032 0x0000000f
653 0x00000038 0x00000038
654 0x00000004 0x00000005
655 0x00000004 0x00000006
656 0x00000000 0x00000005
657 0x00000005 0x00000638
658 0x00000000 0x00000000
659 0x00000000 0x106aa298
660 0x002c00a0 0x00008000
661 0x00080000 0x00080000
662 0x00080000 0x00080000
663 0x00080000 0x00080000
664 0x00080000 0x00080000
665 0x00080000 0x00080000
666 0x00080000 0x00080000
667 0x00080000 0x00080000
668 0x00080000 0x00080000
669 0x00000000 0x00000000
670 0x00000000 0x00000000
671 0x00000000 0x00000000
672 0x00000000 0x00000000
673 0x00000000 0x00000000
674 0x00008000 0x00000000
675 0x00000000 0x00008000
676 0x00000000 0x00000000
677 0x00000000 0x00000000
678 0x00000000 0x00000000
679 0x00000000 0x00000000
680 0x00000000 0x00000000
681 0x00000000 0x00000000
682 0x00000000 0x00000000
683 0x00000000 0x00000000
684 0x00000000 0x00000000
685 0x00000000 0x00000000
686 0x00000000 0x00000000
687 0x00000000 0x00000000
688 0x00090000 0x00090000
689 0x00090000 0x00090000
690 0x00009000 0x00009000
691 0x00009000 0x00009000
692 0x10000280 0x00000000
693 0x00111111 0x00000000
694 0x00000000 0x77ffc081
695 0x00000707 0x81f1f108
696 0x07070004 0x0000003f
697 0x016eeeee 0x51451400
698 0x00514514 0x00514514
699 0x51451400 0x0000003f
700 0x00000066 0x00000000
701 0x00000100 0x000e000e
702 0x00000000 0x00000003
703 0x0000d2b3 0x80000d22
704 0x0000000a
705 >;
706 };
707
708 timing-300000000 {
709 clock-frequency = <300000000>;
710
711 nvidia,emc-auto-cal-config = <0xa1430000>;
712 nvidia,emc-auto-cal-config2 = <0x00000000>;
713 nvidia,emc-auto-cal-config3 = <0x00000000>;
714 nvidia,emc-auto-cal-interval = <0x001fffff>;
715 nvidia,emc-bgbias-ctl0 = <0x00000000>;
716 nvidia,emc-cfg = <0x73340000>;
717 nvidia,emc-cfg-2 = <0x000008d5>;
718 nvidia,emc-ctt-term-ctrl = <0x00000802>;
719 nvidia,emc-mode-1 = <0x80100002>;
720 nvidia,emc-mode-2 = <0x80200000>;
721 nvidia,emc-mode-4 = <0x00000000>;
722 nvidia,emc-mode-reset = <0x80000321>;
723 nvidia,emc-mrs-wait-cnt = <0x0173000e>;
724 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
725 nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
726 nvidia,emc-zcal-cnt-long = <0x00000042>;
727 nvidia,emc-zcal-interval = <0x00020000>;
728
729 nvidia,emc-configuration = <
730 0x0000000d 0x0000004d
731 0x00000000 0x00000009
732 0x00000003 0x00000004
733 0x00000008 0x00000002
734 0x00000009 0x00000003
735 0x00000003 0x00000002
736 0x00000002 0x00000000
737 0x00000003 0x00000003
738 0x00000005 0x00000002
739 0x00000000 0x00000002
740 0x00000007 0x00020000
741 0x00000003 0x00000000
742 0x00000000 0x00000000
743 0x00000000 0x00000001
744 0x0000000e 0x00000010
745 0x00000012 0x000008e4
746 0x00000000 0x00000239
747 0x00000001 0x00000008
748 0x00000001 0x00000000
749 0x0000004b 0x0000000e
750 0x00000052 0x00000200
751 0x00000004 0x00000005
752 0x00000004 0x00000008
753 0x00000000 0x00000005
754 0x00000005 0x00000924
755 0x00000000 0x00000000
756 0x00000000 0x104ab098
757 0x002c00a0 0x00008000
758 0x00030000 0x00030000
759 0x00030000 0x00030000
760 0x00030000 0x00030000
761 0x00030000 0x00030000
762 0x00030000 0x00030000
763 0x00030000 0x00030000
764 0x00030000 0x00030000
765 0x00030000 0x00030000
766 0x00000000 0x00000000
767 0x00000000 0x00000000
768 0x00000000 0x00000000
769 0x00000000 0x00000000
770 0x00098000 0x00098000
771 0x00000000 0x00098000
772 0x00098000 0x00000000
773 0x00000000 0x00000000
774 0x00000000 0x00000000
775 0x00000000 0x00000000
776 0x00000000 0x00000000
777 0x00000000 0x00000000
778 0x00000000 0x00000000
779 0x00000000 0x00000000
780 0x00000000 0x00000000
781 0x00000000 0x00000000
782 0x00000000 0x00000000
783 0x00000000 0x00000000
784 0x00000000 0x00000000
785 0x00050000 0x00050000
786 0x00050000 0x00050000
787 0x00005000 0x00005000
788 0x00005000 0x00005000
789 0x10000280 0x00000000
790 0x00111111 0x00000000
791 0x00000000 0x77ffc081
792 0x00000505 0x81f1f108
793 0x07070004 0x00000000
794 0x016eeeee 0x51451420
795 0x00514514 0x00514514
796 0x51451400 0x0000003f
797 0x00000096 0x00000000
798 0x00000100 0x0173000e
799 0x00000000 0x00000003
800 0x000052a3 0x800012d7
801 0x00000009
802 >;
803 };
804
805 timing-396000000 {
806 clock-frequency = <396000000>;
807
808 nvidia,emc-auto-cal-config = <0xa1430000>;
809 nvidia,emc-auto-cal-config2 = <0x00000000>;
810 nvidia,emc-auto-cal-config3 = <0x00000000>;
811 nvidia,emc-auto-cal-interval = <0x001fffff>;
812 nvidia,emc-bgbias-ctl0 = <0x00000000>;
813 nvidia,emc-cfg = <0x73340000>;
814 nvidia,emc-cfg-2 = <0x00000895>;
815 nvidia,emc-ctt-term-ctrl = <0x00000802>;
816 nvidia,emc-mode-1 = <0x80100002>;
817 nvidia,emc-mode-2 = <0x80200000>;
818 nvidia,emc-mode-4 = <0x00000000>;
819 nvidia,emc-mode-reset = <0x80000521>;
820 nvidia,emc-mrs-wait-cnt = <0x015b000e>;
821 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
822 nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
823 nvidia,emc-zcal-cnt-long = <0x00000042>;
824 nvidia,emc-zcal-interval = <0x00020000>;
825
826 nvidia,emc-configuration = <
827 0x00000011 0x00000066
828 0x00000000 0x0000000c
829 0x00000004 0x00000004
830 0x00000008 0x00000002
831 0x0000000a 0x00000004
832 0x00000004 0x00000002
833 0x00000002 0x00000000
834 0x00000003 0x00000003
835 0x00000005 0x00000002
836 0x00000000 0x00000001
837 0x00000008 0x00020000
838 0x00000003 0x00000000
839 0x00000000 0x00000000
840 0x00000000 0x00000000
841 0x0000000f 0x00000010
842 0x00000012 0x00000bd1
843 0x00000000 0x000002f4
844 0x00000001 0x00000008
845 0x00000001 0x00000000
846 0x00000063 0x0000000f
847 0x0000006c 0x00000200
848 0x00000004 0x00000005
849 0x00000004 0x0000000b
850 0x00000000 0x00000005
851 0x00000005 0x00000c11
852 0x00000000 0x00000000
853 0x00000000 0x104ab098
854 0x002c00a0 0x00008000
855 0x00030000 0x00030000
856 0x00030000 0x00030000
857 0x00030000 0x00030000
858 0x00030000 0x00030000
859 0x00030000 0x00030000
860 0x00030000 0x00030000
861 0x00030000 0x00030000
862 0x00030000 0x00030000
863 0x00000000 0x00000000
864 0x00000000 0x00000000
865 0x00000000 0x00000000
866 0x00000000 0x00000000
867 0x00070000 0x00070000
868 0x00000000 0x00070000
869 0x00070000 0x00000000
870 0x00000000 0x00000000
871 0x00000000 0x00000000
872 0x00000000 0x00000000
873 0x00000000 0x00000000
874 0x00000000 0x00000000
875 0x00000000 0x00000000
876 0x00000000 0x00000000
877 0x00000000 0x00000000
878 0x00000000 0x00000000
879 0x00000000 0x00000000
880 0x00000000 0x00000000
881 0x00000000 0x00000000
882 0x00038000 0x00038000
883 0x00038000 0x00038000
884 0x00003800 0x00003800
885 0x00003800 0x00003800
886 0x10000280 0x00000000
887 0x00111111 0x00000000
888 0x00000000 0x77ffc081
889 0x00000505 0x81f1f108
890 0x07070004 0x00000000
891 0x016eeeee 0x51451420
892 0x00514514 0x00514514
893 0x51451400 0x0000003f
894 0x000000c6 0x00000000
895 0x00000100 0x015b000e
896 0x00000000 0x00000003
897 0x000052a3 0x8000188b
898 0x00000009
899 >;
900 };
901
902 timing-528000000 {
903 clock-frequency = <528000000>;
904
905 nvidia,emc-auto-cal-config = <0xa1430000>;
906 nvidia,emc-auto-cal-config2 = <0x00000000>;
907 nvidia,emc-auto-cal-config3 = <0x00000000>;
908 nvidia,emc-auto-cal-interval = <0x001fffff>;
909 nvidia,emc-bgbias-ctl0 = <0x00000000>;
910 nvidia,emc-cfg = <0x73300000>;
911 nvidia,emc-cfg-2 = <0x0000089d>;
912 nvidia,emc-ctt-term-ctrl = <0x00000802>;
913 nvidia,emc-mode-1 = <0x80100002>;
914 nvidia,emc-mode-2 = <0x80200008>;
915 nvidia,emc-mode-4 = <0x00000000>;
916 nvidia,emc-mode-reset = <0x80000941>;
917 nvidia,emc-mrs-wait-cnt = <0x0139000e>;
918 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
919 nvidia,emc-xm2dqspadctrl2 = <0x0123133d>;
920 nvidia,emc-zcal-cnt-long = <0x00000042>;
921 nvidia,emc-zcal-interval = <0x00020000>;
922
923 nvidia,emc-configuration = <
924 0x00000018 0x00000088
925 0x00000000 0x00000010
926 0x00000006 0x00000006
927 0x00000009 0x00000002
928 0x0000000d 0x00000006
929 0x00000006 0x00000002
930 0x00000002 0x00000000
931 0x00000003 0x00000003
932 0x00000006 0x00000002
933 0x00000000 0x00000001
934 0x00000009 0x00030000
935 0x00000003 0x00000000
936 0x00000000 0x00000000
937 0x00000000 0x00000000
938 0x00000010 0x00000012
939 0x00000014 0x00000fd6
940 0x00000000 0x000003f5
941 0x00000002 0x0000000b
942 0x00000001 0x00000000
943 0x00000085 0x00000012
944 0x00000090 0x00000200
945 0x00000004 0x00000005
946 0x00000004 0x00000010
947 0x00000000 0x00000006
948 0x00000006 0x00001017
949 0x00000000 0x00000000
950 0x00000000 0x104ab098
951 0xe01200b1 0x00008000
952 0x0000000a 0x0000000a
953 0x0000000a 0x0000000a
954 0x0000000a 0x0000000a
955 0x0000000a 0x0000000a
956 0x0000000a 0x0000000a
957 0x0000000a 0x0000000a
958 0x0000000a 0x0000000a
959 0x0000000a 0x0000000a
960 0x00000000 0x00000000
961 0x00000000 0x00000000
962 0x00000000 0x00000000
963 0x00000000 0x00000000
964 0x00054000 0x00054000
965 0x00000000 0x00054000
966 0x00054000 0x00000000
967 0x00000000 0x00000000
968 0x00000000 0x00000000
969 0x00000000 0x00000000
970 0x00000000 0x00000000
971 0x00000000 0x00000000
972 0x00000000 0x00000000
973 0x00000000 0x00000000
974 0x00000000 0x00000000
975 0x00000000 0x00000000
976 0x00000000 0x00000000
977 0x00000000 0x00000000
978 0x00000000 0x00000000
979 0x0000000c 0x0000000c
980 0x0000000c 0x0000000c
981 0x0000000c 0x0000000c
982 0x0000000c 0x0000000c
983 0x100002a0 0x00000000
984 0x00111111 0x00000000
985 0x00000000 0x77ffc085
986 0x00000505 0x81f1f108
987 0x07070004 0x00000000
988 0x016eeeee 0x51451420
989 0x00514514 0x00514514
990 0x51451400 0x0606003f
991 0x00000000 0x00000000
992 0x00000100 0x0139000e
993 0x00000000 0x00000003
994 0x000042a0 0x80002062
995 0x0000000a
996 >;
997 };
998
999 timing-600000000 {
1000 clock-frequency = <600000000>;
1001
1002 nvidia,emc-auto-cal-config = <0xa1430000>;
1003 nvidia,emc-auto-cal-config2 = <0x00000000>;
1004 nvidia,emc-auto-cal-config3 = <0x00000000>;
1005 nvidia,emc-auto-cal-interval = <0x001fffff>;
1006 nvidia,emc-bgbias-ctl0 = <0x00000000>;
1007 nvidia,emc-cfg = <0x73300000>;
1008 nvidia,emc-cfg-2 = <0x0000089d>;
1009 nvidia,emc-ctt-term-ctrl = <0x00000802>;
1010 nvidia,emc-mode-1 = <0x80100002>;
1011 nvidia,emc-mode-2 = <0x80200010>;
1012 nvidia,emc-mode-4 = <0x00000000>;
1013 nvidia,emc-mode-reset = <0x80000b61>;
1014 nvidia,emc-mrs-wait-cnt = <0x0127000e>;
1015 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1016 nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
1017 nvidia,emc-zcal-cnt-long = <0x00000042>;
1018 nvidia,emc-zcal-interval = <0x00020000>;
1019
1020 nvidia,emc-configuration = <
1021 0x0000001b 0x0000009b
1022 0x00000000 0x00000013
1023 0x00000007 0x00000007
1024 0x0000000b 0x00000003
1025 0x00000010 0x00000007
1026 0x00000007 0x00000002
1027 0x00000002 0x00000000
1028 0x00000005 0x00000005
1029 0x0000000a 0x00000002
1030 0x00000000 0x00000003
1031 0x0000000b 0x00070000
1032 0x00000003 0x00000000
1033 0x00000000 0x00000000
1034 0x00000000 0x00000002
1035 0x00000012 0x00000016
1036 0x00000018 0x00001208
1037 0x00000000 0x00000482
1038 0x00000002 0x0000000d
1039 0x00000001 0x00000000
1040 0x00000097 0x00000015
1041 0x000000a3 0x00000200
1042 0x00000004 0x00000005
1043 0x00000004 0x00000013
1044 0x00000000 0x00000006
1045 0x00000006 0x00001248
1046 0x00000000 0x00000000
1047 0x00000000 0x104ab098
1048 0xe00e00b1 0x00008000
1049 0x0000000a 0x0000000a
1050 0x0000000a 0x0000000a
1051 0x0000000a 0x0000000a
1052 0x0000000a 0x0000000a
1053 0x0000000a 0x0000000a
1054 0x0000000a 0x0000000a
1055 0x0000000a 0x0000000a
1056 0x0000000a 0x0000000a
1057 0x00000000 0x00000000
1058 0x00000000 0x00000000
1059 0x00000000 0x00000000
1060 0x00000000 0x00000000
1061 0x00048000 0x00048000
1062 0x00000000 0x00048000
1063 0x00048000 0x00000000
1064 0x00000000 0x00000000
1065 0x00000000 0x00000000
1066 0x00000000 0x00000000
1067 0x00000000 0x00000000
1068 0x00000000 0x00000000
1069 0x00000000 0x00000000
1070 0x00000000 0x00000000
1071 0x00000000 0x00000000
1072 0x00000000 0x00000000
1073 0x00000000 0x00000000
1074 0x00000000 0x00000000
1075 0x00000000 0x00000000
1076 0x0000000d 0x0000000d
1077 0x0000000d 0x0000000d
1078 0x0000000d 0x0000000d
1079 0x0000000d 0x0000000d
1080 0x100002a0 0x00000000
1081 0x00111111 0x00000000
1082 0x00000000 0x77ffc085
1083 0x00000505 0x81f1f108
1084 0x07070004 0x00000000
1085 0x016eeeee 0x51451420
1086 0x00514514 0x00514514
1087 0x51451400 0x0606003f
1088 0x00000000 0x00000000
1089 0x00000100 0x0127000e
1090 0x00000000 0x00000003
1091 0x000040a0 0x800024aa
1092 0x0000000e
1093 >;
1094 };
1095
1096 timing-792000000 {
1097 clock-frequency = <792000000>;
1098
1099 nvidia,emc-auto-cal-config = <0xa1430000>;
1100 nvidia,emc-auto-cal-config2 = <0x00000000>;
1101 nvidia,emc-auto-cal-config3 = <0x00000000>;
1102 nvidia,emc-auto-cal-interval = <0x001fffff>;
1103 nvidia,emc-bgbias-ctl0 = <0x00000000>;
1104 nvidia,emc-cfg = <0x73300000>;
1105 nvidia,emc-cfg-2 = <0x0000089d>;
1106 nvidia,emc-ctt-term-ctrl = <0x00000802>;
1107 nvidia,emc-mode-1 = <0x80100002>;
1108 nvidia,emc-mode-2 = <0x80200018>;
1109 nvidia,emc-mode-4 = <0x00000000>;
1110 nvidia,emc-mode-reset = <0x80000d71>;
1111 nvidia,emc-mrs-wait-cnt = <0x00f7000e>;
1112 nvidia,emc-sel-dpd-ctrl = <0x00040000>;
1113 nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
1114 nvidia,emc-zcal-cnt-long = <0x00000042>;
1115 nvidia,emc-zcal-interval = <0x00020000>;
1116
1117 nvidia,emc-configuration = <
1118 0x00000024 0x000000cd
1119 0x00000000 0x00000019
1120 0x0000000a 0x00000008
1121 0x0000000d 0x00000004
1122 0x00000013 0x0000000a
1123 0x0000000a 0x00000004
1124 0x00000002 0x00000000
1125 0x00000006 0x00000006
1126 0x0000000b 0x00000002
1127 0x00000000 0x00000002
1128 0x0000000d 0x00080000
1129 0x00000004 0x00000000
1130 0x00000000 0x00000000
1131 0x00000000 0x00000001
1132 0x00000014 0x00000018
1133 0x0000001a 0x000017e2
1134 0x00000000 0x000005f8
1135 0x00000003 0x00000011
1136 0x00000001 0x00000000
1137 0x000000c7 0x00000018
1138 0x000000d7 0x00000200
1139 0x00000005 0x00000006
1140 0x00000005 0x00000019
1141 0x00000000 0x00000008
1142 0x00000008 0x00001822
1143 0x00000000 0x00000000
1144 0x00000000 0x104ab098
1145 0xe00700b1 0x00008000
1146 0x007fc008 0x007fc008
1147 0x007fc008 0x007fc008
1148 0x007fc008 0x007fc008
1149 0x007fc008 0x007fc008
1150 0x007fc008 0x007fc008
1151 0x007fc008 0x007fc008
1152 0x007fc008 0x007fc008
1153 0x007fc008 0x007fc008
1154 0x00000000 0x00000000
1155 0x00000000 0x00000000
1156 0x00000000 0x00000000
1157 0x00000000 0x00000000
1158 0x00034000 0x00034000
1159 0x00000000 0x00034000
1160 0x00034000 0x00000000
1161 0x00000000 0x00000000
1162 0x00000000 0x00000000
1163 0x00000000 0x00000000
1164 0x00000000 0x00000000
1165 0x00000005 0x00000005
1166 0x00000005 0x00000005
1167 0x00000005 0x00000005
1168 0x00000005 0x00000005
1169 0x00000005 0x00000005
1170 0x00000005 0x00000005
1171 0x00000005 0x00000005
1172 0x00000005 0x00000005
1173 0x0000000a 0x0000000a
1174 0x0000000a 0x0000000a
1175 0x0000000a 0x0000000a
1176 0x0000000a 0x0000000a
1177 0x100002a0 0x00000000
1178 0x00111111 0x00000000
1179 0x00000000 0x77ffc085
1180 0x00000000 0x81f1f108
1181 0x07070004 0x00000000
1182 0x016eeeee 0x61861820
1183 0x00514514 0x00514514
1184 0x61861800 0x0606003f
1185 0x00000000 0x00000000
1186 0x00000100 0x00f7000e
1187 0x00000000 0x00000004
1188 0x00004080 0x80003012
1189 0x0000000f
1190 >;
1191 };
1192
1193 timing-924000000 {
1194 clock-frequency = <924000000>;
1195
1196 nvidia,emc-auto-cal-config = <0xa1430303>;
1197 nvidia,emc-auto-cal-config2 = <0x00000000>;
1198 nvidia,emc-auto-cal-config3 = <0x00000000>;
1199 nvidia,emc-auto-cal-interval = <0x001fffff>;
1200 nvidia,emc-bgbias-ctl0 = <0x00000000>;
1201 nvidia,emc-cfg = <0x73300000>;
1202 nvidia,emc-cfg-2 = <0x0000089d>;
1203 nvidia,emc-ctt-term-ctrl = <0x00000802>;
1204 nvidia,emc-mode-1 = <0x80100002>;
1205 nvidia,emc-mode-2 = <0x80200020>;
1206 nvidia,emc-mode-4 = <0x00000000>;
1207 nvidia,emc-mode-reset = <0x80000f15>;
1208 nvidia,emc-mrs-wait-cnt = <0x00cd000e>;
1209 nvidia,emc-sel-dpd-ctrl = <0x00040000>;
1210 nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
1211 nvidia,emc-zcal-cnt-long = <0x0000004c>;
1212 nvidia,emc-zcal-interval = <0x00020000>;
1213
1214 nvidia,emc-configuration = <
1215 0x0000002b 0x000000f0
1216 0x00000000 0x0000001e
1217 0x0000000b 0x00000009
1218 0x0000000f 0x00000005
1219 0x00000016 0x0000000b
1220 0x0000000b 0x00000004
1221 0x00000002 0x00000000
1222 0x00000007 0x00000007
1223 0x0000000d 0x00000002
1224 0x00000000 0x00000002
1225 0x0000000f 0x000a0000
1226 0x00000004 0x00000000
1227 0x00000000 0x00000000
1228 0x00000000 0x00000001
1229 0x00000016 0x0000001a
1230 0x0000001c 0x00001be7
1231 0x00000000 0x000006f9
1232 0x00000004 0x00000015
1233 0x00000001 0x00000000
1234 0x000000e7 0x0000001b
1235 0x000000fb 0x00000200
1236 0x00000006 0x00000007
1237 0x00000006 0x0000001e
1238 0x00000000 0x0000000a
1239 0x0000000a 0x00001c28
1240 0x00000000 0x00000000
1241 0x00000000 0x104ab898
1242 0xe00400b1 0x00008000
1243 0x007f800a 0x007f800a
1244 0x007f800a 0x007f800a
1245 0x007f800a 0x007f800a
1246 0x007f800a 0x007f800a
1247 0x007f800a 0x007f800a
1248 0x007f800a 0x007f800a
1249 0x007f800a 0x007f800a
1250 0x007f800a 0x007f800a
1251 0x00000000 0x00000000
1252 0x00000000 0x00000000
1253 0x00000000 0x00000000
1254 0x00000000 0x00000000
1255 0x0002c000 0x0002c000
1256 0x00000000 0x0002c000
1257 0x0002c000 0x00000000
1258 0x00000000 0x00000000
1259 0x00000000 0x00000000
1260 0x00000000 0x00000000
1261 0x00000000 0x00000000
1262 0x00000004 0x00000004
1263 0x00000004 0x00000004
1264 0x00000004 0x00000004
1265 0x00000004 0x00000004
1266 0x00000004 0x00000004
1267 0x00000004 0x00000004
1268 0x00000004 0x00000004
1269 0x00000004 0x00000004
1270 0x00000008 0x00000008
1271 0x00000008 0x00000008
1272 0x00000008 0x00000008
1273 0x00000008 0x00000008
1274 0x100002a0 0x00000000
1275 0x00111111 0x00000000
1276 0x00000000 0x77ffc085
1277 0x00000000 0x81f1f108
1278 0x07070004 0x00000000
1279 0x016eeeee 0x5d75d720
1280 0x00514514 0x00514514
1281 0x5d75d700 0x0606003f
1282 0x00000000 0x00000000
1283 0x00000128 0x00cd000e
1284 0x00000000 0x00000004
1285 0x00004080 0x800037ea
1286 0x00000011
1287 >;
1288 };
1289
1290 };
1291 };
1292
1293 memory-controller@70019000 {
1294 emc-timings-1 {
1295 nvidia,ram-code = <1>;
1296
1297 timing-12750000 {
1298 clock-frequency = <12750000>;
1299
1300 nvidia,emem-configuration = <
1301 0x40040001 0x8000000a
1302 0x00000001 0x00000001
1303 0x00000002 0x00000000
1304 0x00000002 0x00000001
1305 0x00000003 0x00000008
1306 0x00000003 0x00000002
1307 0x00000003 0x00000006
1308 0x06030203 0x000a0502
1309 0x77e30303 0x70000f03
1310 0x001f0000
1311 >;
1312 };
1313
1314 timing-20400000 {
1315 clock-frequency = <20400000>;
1316
1317 nvidia,emem-configuration = <
1318 0x40020001 0x80000012
1319 0x00000001 0x00000001
1320 0x00000002 0x00000000
1321 0x00000002 0x00000001
1322 0x00000003 0x00000008
1323 0x00000003 0x00000002
1324 0x00000003 0x00000006
1325 0x06030203 0x000a0502
1326 0x76230303 0x70000f03
1327 0x001f0000
1328 >;
1329 };
1330
1331 timing-40800000 {
1332 clock-frequency = <40800000>;
1333
1334 nvidia,emem-configuration = <
1335 0xa0000001 0x80000017
1336 0x00000001 0x00000001
1337 0x00000002 0x00000000
1338 0x00000002 0x00000001
1339 0x00000003 0x00000008
1340 0x00000003 0x00000002
1341 0x00000003 0x00000006
1342 0x06030203 0x000a0502
1343 0x74a30303 0x70000f03
1344 0x001f0000
1345 >;
1346 };
1347
1348 timing-68000000 {
1349 clock-frequency = <68000000>;
1350
1351 nvidia,emem-configuration = <
1352 0x00000001 0x8000001e
1353 0x00000001 0x00000001
1354 0x00000002 0x00000000
1355 0x00000002 0x00000001
1356 0x00000003 0x00000008
1357 0x00000003 0x00000002
1358 0x00000003 0x00000006
1359 0x06030203 0x000a0502
1360 0x74230403 0x70000f03
1361 0x001f0000
1362 >;
1363 };
1364
1365 timing-102000000 {
1366 clock-frequency = <102000000>;
1367
1368 nvidia,emem-configuration = <
1369 0x08000001 0x80000026
1370 0x00000001 0x00000001
1371 0x00000003 0x00000000
1372 0x00000002 0x00000001
1373 0x00000003 0x00000008
1374 0x00000003 0x00000002
1375 0x00000003 0x00000006
1376 0x06030203 0x000a0503
1377 0x73c30504 0x70000f03
1378 0x001f0000
1379 >;
1380 };
1381
1382 timing-204000000 {
1383 clock-frequency = <204000000>;
1384
1385 nvidia,emem-configuration = <
1386 0x01000003 0x80000040
1387 0x00000001 0x00000001
1388 0x00000004 0x00000002
1389 0x00000003 0x00000001
1390 0x00000003 0x00000008
1391 0x00000003 0x00000002
1392 0x00000004 0x00000006
1393 0x06040203 0x000a0504
1394 0x73840a05 0x70000f03
1395 0x001f0000
1396 >;
1397 };
1398
1399 timing-300000000 {
1400 clock-frequency = <300000000>;
1401
1402 nvidia,emem-configuration = <
1403 0x08000004 0x80000040
1404 0x00000001 0x00000002
1405 0x00000007 0x00000004
1406 0x00000004 0x00000001
1407 0x00000002 0x00000007
1408 0x00000002 0x00000002
1409 0x00000004 0x00000006
1410 0x06040202 0x000b0607
1411 0x77450e08 0x70000f03
1412 0x001f0000
1413 >;
1414 };
1415
1416 timing-396000000 {
1417 clock-frequency = <396000000>;
1418
1419 nvidia,emem-configuration = <
1420 0x0f000005 0x80000040
1421 0x00000001 0x00000002
1422 0x00000009 0x00000005
1423 0x00000006 0x00000001
1424 0x00000002 0x00000008
1425 0x00000002 0x00000002
1426 0x00000004 0x00000006
1427 0x06040202 0x000d0709
1428 0x7586120a 0x70000f03
1429 0x001f0000
1430 >;
1431 };
1432
1433 timing-528000000 {
1434 clock-frequency = <528000000>;
1435
1436 nvidia,emem-configuration = <
1437 0x0f000007 0x80000040
1438 0x00000002 0x00000003
1439 0x0000000c 0x00000007
1440 0x00000008 0x00000001
1441 0x00000002 0x00000009
1442 0x00000002 0x00000002
1443 0x00000005 0x00000006
1444 0x06050202 0x0010090c
1445 0x7428180d 0x70000f03
1446 0x001f0000
1447 >;
1448 };
1449
1450 timing-600000000 {
1451 clock-frequency = <600000000>;
1452
1453 nvidia,emem-configuration = <
1454 0x00000009 0x80000040
1455 0x00000003 0x00000004
1456 0x0000000e 0x00000009
1457 0x0000000a 0x00000001
1458 0x00000003 0x0000000b
1459 0x00000002 0x00000002
1460 0x00000005 0x00000007
1461 0x07050202 0x00130b0e
1462 0x73a91b0f 0x70000f03
1463 0x001f0000
1464 >;
1465 };
1466
1467 timing-792000000 {
1468 clock-frequency = <792000000>;
1469
1470 nvidia,emem-configuration = <
1471 0x0e00000b 0x80000040
1472 0x00000004 0x00000005
1473 0x00000013 0x0000000c
1474 0x0000000d 0x00000002
1475 0x00000003 0x0000000c
1476 0x00000002 0x00000002
1477 0x00000006 0x00000008
1478 0x08060202 0x00170e13
1479 0x736c2414 0x70000f02
1480 0x001f0000
1481 >;
1482 };
1483
1484 timing-924000000 {
1485 clock-frequency = <924000000>;
1486
1487 nvidia,emem-configuration = <
1488 0x0e00000d 0x80000040
1489 0x00000005 0x00000006
1490 0x00000016 0x0000000e
1491 0x0000000f 0x00000002
1492 0x00000004 0x0000000e
1493 0x00000002 0x00000002
1494 0x00000006 0x00000009
1495 0x09060202 0x001a1016
1496 0x734e2a17 0x70000f02
1497 0x001f0000
1498 >;
1499 };
1500 };
1501 };
1502};
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
new file mode 100644
index 000000000000..653044a44f0d
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -0,0 +1,284 @@
1/*
2 * Copyright 2016 Toradex AG
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43
44#include <dt-bindings/input/input.h>
45#include "tegra124-apalis.dtsi"
46
47/ {
48 model = "Toradex Apalis TK1 on Apalis Evaluation Board";
49 compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1",
50 "nvidia,tegra124";
51
52 aliases {
53 rtc0 = "/i2c@7000c000/rtc@68";
54 rtc1 = "/i2c@7000d000/pmic@40";
55 rtc2 = "/rtc@7000e000";
56 serial0 = &uarta;
57 serial1 = &uartb;
58 serial2 = &uartc;
59 serial3 = &uartd;
60 };
61
62 chosen {
63 stdout-path = "serial0:115200n8";
64 };
65
66 pcie-controller@01003000 {
67 pci@1,0 {
68 status = "okay";
69 };
70 };
71
72 host1x@50000000 {
73 hdmi@54280000 {
74 status = "okay";
75 };
76 };
77
78 /* Apalis UART1 */
79 serial@70006000 {
80 status = "okay";
81 };
82
83 /* Apalis UART2 */
84 serial@70006040 {
85 status = "okay";
86 };
87
88 /* Apalis UART3 */
89 serial@70006200 {
90 status = "okay";
91 };
92
93 /* Apalis UART4 */
94 serial@70006300 {
95 status = "okay";
96 };
97
98 pwm@7000a000 {
99 status = "okay";
100 };
101
102 /*
103 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
104 * board)
105 */
106 i2c@7000c000 {
107 status = "okay";
108 clock-frequency = <100000>;
109
110 pcie-switch@58 {
111 compatible = "plx,pex8605";
112 reg = <0x58>;
113 };
114
115 /* M41T0M6 real time clock on carrier board */
116 rtc@68 {
117 compatible = "st,m41t00";
118 reg = <0x68>;
119 };
120 };
121
122 /*
123 * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID)
124 */
125 hdmi_ddc: i2c@7000c400 {
126 status = "okay";
127 clock-frequency = <100000>;
128 };
129
130 /*
131 * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
132 * on carrier board)
133 */
134 i2c@7000c500 {
135 status = "okay";
136 clock-frequency = <100000>;
137 };
138
139 /* I2C4 (DDC): unused */
140
141 /* SPI1: Apalis SPI1 */
142 spi@7000d400 {
143 status = "okay";
144 spi-max-frequency = <50000000>;
145
146 spidev0: spidev@0 {
147 compatible = "spidev";
148 reg = <0>;
149 spi-max-frequency = <50000000>;
150 };
151 };
152
153 /* SPI4: Apalis SPI2 */
154 spi@7000da00 {
155 status = "okay";
156 spi-max-frequency = <50000000>;
157
158 spidev1: spidev@0 {
159 compatible = "spidev";
160 reg = <0>;
161 spi-max-frequency = <50000000>;
162 };
163 };
164
165 /* Apalis Serial ATA */
166 sata@70020000 {
167 status = "okay";
168 };
169
170 hda@70030000 {
171 status = "okay";
172 };
173
174 usb@70090000 {
175 status = "okay";
176 };
177
178 /* Apalis MMC1 */
179 sdhci@700b0000 {
180 status = "okay";
181 /* MMC1_CD# */
182 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
183 bus-width = <4>;
184 vqmmc-supply = <&vddio_sdmmc1>;
185 };
186
187 /* Apalis SD1 */
188 sdhci@700b0400 {
189 status = "okay";
190 /*
191 * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
192 * features some magic properties even though the external
193 * loopback is disabled and the internal loopback used as per
194 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being
195 * set to 0xfffd according to the TRM!
196 * cd-gpios = <&gpio TEGRA_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
197 */
198 bus-width = <4>;
199 vqmmc-supply = <&vddio_sdmmc3>;
200 };
201
202 /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
203 usb@7d000000 {
204 status = "okay";
205 dr_mode = "otg";
206 };
207
208 usb-phy@7d000000 {
209 status = "okay";
210 vbus-supply = <&reg_usbo1_vbus>;
211 };
212
213 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
214 usb@7d004000 {
215 status = "okay";
216 };
217
218 usb-phy@7d004000 {
219 status = "okay";
220 vbus-supply = <&reg_usbh_vbus>;
221 };
222
223 /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */
224 usb@7d008000 {
225 status = "okay";
226 };
227
228 usb-phy@7d008000 {
229 status = "okay";
230 vbus-supply = <&reg_usbh_vbus>;
231 };
232
233 backlight: backlight {
234 compatible = "pwm-backlight";
235
236 /* BKL1_PWM */
237 pwms = <&pwm 3 5000000>;
238 brightness-levels = <255 231 223 207 191 159 127 0>;
239 default-brightness-level = <6>;
240 /* BKL1_ON */
241 enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
242 };
243
244 gpio-keys {
245 compatible = "gpio-keys";
246
247 wakeup {
248 label = "WAKE1_MICO";
249 gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>;
250 linux,code = <KEY_WAKEUP>;
251 debounce-interval = <10>;
252 wakeup-source;
253 };
254 };
255
256 reg_5v0: regulator-5v0 {
257 compatible = "regulator-fixed";
258 regulator-name = "5V_SW";
259 regulator-min-microvolt = <5000000>;
260 regulator-max-microvolt = <5000000>;
261 };
262
263 /* USBO1_EN */
264 reg_usbo1_vbus: regulator-usbo1-vbus {
265 compatible = "regulator-fixed";
266 regulator-name = "VCC_USBO1";
267 regulator-min-microvolt = <5000000>;
268 regulator-max-microvolt = <5000000>;
269 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
270 enable-active-high;
271 vin-supply = <&reg_5v0>;
272 };
273
274 /* USBH_EN */
275 reg_usbh_vbus: regulator-usbh-vbus {
276 compatible = "regulator-fixed";
277 regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
278 regulator-min-microvolt = <5000000>;
279 regulator-max-microvolt = <5000000>;
280 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
281 enable-active-high;
282 vin-supply = <&reg_5v0>;
283 };
284};
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
new file mode 100644
index 000000000000..e7a73db17613
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -0,0 +1,2100 @@
1/*
2 * Copyright 2016 Toradex AG
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include "tegra124.dtsi"
43#include "tegra124-apalis-emc.dtsi"
44
45/*
46 * Toradex Apalis TK1 Module Device Tree
47 * Compatible for Revisions 2GB: V1.0A
48 */
49/ {
50 model = "Toradex Apalis TK1";
51 compatible = "toradex,apalis-tk1", "nvidia,tegra124";
52
53 memory {
54 reg = <0x0 0x80000000 0x0 0x80000000>;
55 };
56
57 pcie-controller@01003000 {
58 status = "okay";
59
60 avddio-pex-supply = <&vdd_1v05>;
61 avdd-pex-pll-supply = <&vdd_1v05>;
62 avdd-pll-erefe-supply = <&avdd_1v05>;
63 dvddio-pex-supply = <&vdd_1v05>;
64 hvdd-pex-pll-e-supply = <&reg_3v3>;
65 hvdd-pex-supply = <&reg_3v3>;
66 vddio-pex-ctl-supply = <&reg_3v3>;
67
68 /* Apalis PCIe (additional lane Apalis type specific) */
69 pci@1,0 {
70 /* PCIE1_RX/TX and TS_DIFF1/2 */
71 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
72 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
73 phy-names = "pcie-0", "pcie-1";
74 };
75
76 /* I210 Gigabit Ethernet Controller (On-module) */
77 pci@2,0 {
78 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
79 phy-names = "pcie-0";
80 status = "okay";
81 };
82 };
83
84 host1x@50000000 {
85 hdmi@54280000 {
86 pll-supply = <&reg_1v05_avdd_hdmi_pll>;
87 vdd-supply = <&reg_3v3_avdd_hdmi>;
88
89 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
90 nvidia,hpd-gpio =
91 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
92 };
93 };
94
95 gpu@0,57000000 {
96 /*
97 * Node left disabled on purpose - the bootloader will enable
98 * it after having set the VPR up
99 */
100 vdd-supply = <&vdd_gpu>;
101 };
102
103 pinmux: pinmux@70000868 {
104 pinctrl-names = "default";
105 pinctrl-0 = <&state_default>;
106
107 state_default: pinmux {
108 /* Analogue Audio (On-module) */
109 dap3_fs_pp0 {
110 nvidia,pins = "dap3_fs_pp0";
111 nvidia,function = "i2s2";
112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
115 };
116 dap3_din_pp1 {
117 nvidia,pins = "dap3_din_pp1";
118 nvidia,function = "i2s2";
119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120 nvidia,tristate = <TEGRA_PIN_ENABLE>;
121 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
122 };
123 dap3_dout_pp2 {
124 nvidia,pins = "dap3_dout_pp2";
125 nvidia,function = "i2s2";
126 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
127 nvidia,tristate = <TEGRA_PIN_DISABLE>;
128 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
129 };
130 dap3_sclk_pp3 {
131 nvidia,pins = "dap3_sclk_pp3";
132 nvidia,function = "i2s2";
133 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
134 nvidia,tristate = <TEGRA_PIN_DISABLE>;
135 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
136 };
137 dap_mclk1_pw4 {
138 nvidia,pins = "dap_mclk1_pw4";
139 nvidia,function = "extperiph1";
140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
142 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
143 };
144
145 /* Apalis BKL1_ON */
146 pbb5 {
147 nvidia,pins = "pbb5";
148 nvidia,function = "vgp5";
149 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
150 nvidia,tristate = <TEGRA_PIN_DISABLE>;
151 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
152 };
153
154 /* Apalis BKL1_PWM */
155 pu6 {
156 nvidia,pins = "pu6";
157 nvidia,function = "pwm3";
158 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
160 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
161 };
162
163 /* Apalis CAM1_MCLK */
164 cam_mclk_pcc0 {
165 nvidia,pins = "cam_mclk_pcc0";
166 nvidia,function = "vi_alt3";
167 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
170 };
171
172 /* Apalis Digital Audio */
173 dap2_fs_pa2 {
174 nvidia,pins = "dap2_fs_pa2";
175 nvidia,function = "hda";
176 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
177 nvidia,tristate = <TEGRA_PIN_DISABLE>;
178 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
179 };
180 dap2_sclk_pa3 {
181 nvidia,pins = "dap2_sclk_pa3";
182 nvidia,function = "hda";
183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
184 nvidia,tristate = <TEGRA_PIN_DISABLE>;
185 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
186 };
187 dap2_din_pa4 {
188 nvidia,pins = "dap2_din_pa4";
189 nvidia,function = "hda";
190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <TEGRA_PIN_ENABLE>;
192 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
193 };
194 dap2_dout_pa5 {
195 nvidia,pins = "dap2_dout_pa5";
196 nvidia,function = "hda";
197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <TEGRA_PIN_DISABLE>;
199 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
200 };
201 pbb3 { /* DAP1_RESET */
202 nvidia,pins = "pbb3";
203 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
204 nvidia,tristate = <TEGRA_PIN_DISABLE>;
205 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
206 };
207 clk3_out_pee0 {
208 nvidia,pins = "clk3_out_pee0";
209 nvidia,function = "extperiph3";
210 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
211 nvidia,tristate = <TEGRA_PIN_DISABLE>;
212 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
213 };
214
215 /* Apalis GPIO */
216 ddc_scl_pv4 {
217 nvidia,pins = "ddc_scl_pv4";
218 nvidia,function = "rsvd2";
219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
220 nvidia,tristate = <TEGRA_PIN_DISABLE>;
221 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
222 };
223 ddc_sda_pv5 {
224 nvidia,pins = "ddc_sda_pv5";
225 nvidia,function = "rsvd2";
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
229 };
230 pex_l0_rst_n_pdd1 {
231 nvidia,pins = "pex_l0_rst_n_pdd1";
232 nvidia,function = "rsvd2";
233 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
236 };
237 pex_l0_clkreq_n_pdd2 {
238 nvidia,pins = "pex_l0_clkreq_n_pdd2";
239 nvidia,function = "rsvd2";
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
242 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
243 };
244 pex_l1_rst_n_pdd5 {
245 nvidia,pins = "pex_l1_rst_n_pdd5";
246 nvidia,function = "rsvd2";
247 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
250 };
251 pex_l1_clkreq_n_pdd6 {
252 nvidia,pins = "pex_l1_clkreq_n_pdd6";
253 nvidia,function = "rsvd2";
254 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
256 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
257 };
258 dp_hpd_pff0 {
259 nvidia,pins = "dp_hpd_pff0";
260 nvidia,function = "rsvd2";
261 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
263 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
264 };
265 pff2 {
266 nvidia,pins = "pff2";
267 nvidia,function = "rsvd2";
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
270 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
271 };
272 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
273 nvidia,pins = "owr";
274 nvidia,function = "rsvd2";
275 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
276 nvidia,tristate = <TEGRA_PIN_ENABLE>;
277 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
278 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
279 };
280
281 /* Apalis HDMI1_CEC */
282 hdmi_cec_pee3 {
283 nvidia,pins = "hdmi_cec_pee3";
284 nvidia,function = "cec";
285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
287 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
288 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
289 };
290
291 /* Apalis HDMI1_HPD */
292 hdmi_int_pn7 {
293 nvidia,pins = "hdmi_int_pn7";
294 nvidia,function = "rsvd1";
295 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
296 nvidia,tristate = <TEGRA_PIN_ENABLE>;
297 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
298 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
299 };
300
301 /* Apalis I2C1 */
302 gen1_i2c_scl_pc4 {
303 nvidia,pins = "gen1_i2c_scl_pc4";
304 nvidia,function = "i2c1";
305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
306 nvidia,tristate = <TEGRA_PIN_DISABLE>;
307 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
309 };
310 gen1_i2c_sda_pc5 {
311 nvidia,pins = "gen1_i2c_sda_pc5";
312 nvidia,function = "i2c1";
313 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
314 nvidia,tristate = <TEGRA_PIN_DISABLE>;
315 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
316 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
317 };
318
319 /* Apalis I2C2 (DDC) */
320 gen2_i2c_scl_pt5 {
321 nvidia,pins = "gen2_i2c_scl_pt5";
322 nvidia,function = "i2c2";
323 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
324 nvidia,tristate = <TEGRA_PIN_DISABLE>;
325 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
326 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
327 };
328 gen2_i2c_sda_pt6 {
329 nvidia,pins = "gen2_i2c_sda_pt6";
330 nvidia,function = "i2c2";
331 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
332 nvidia,tristate = <TEGRA_PIN_DISABLE>;
333 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
334 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
335 };
336
337 /* Apalis I2C3 (CAM) */
338 cam_i2c_scl_pbb1 {
339 nvidia,pins = "cam_i2c_scl_pbb1";
340 nvidia,function = "i2c3";
341 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
342 nvidia,tristate = <TEGRA_PIN_DISABLE>;
343 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
344 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
345 };
346 cam_i2c_sda_pbb2 {
347 nvidia,pins = "cam_i2c_sda_pbb2";
348 nvidia,function = "i2c3";
349 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
350 nvidia,tristate = <TEGRA_PIN_DISABLE>;
351 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
352 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
353 };
354
355 /* Apalis MMC1 */
356 sdmmc1_cd_n_pv3 { /* CD# GPIO */
357 nvidia,pins = "sdmmc1_wp_n_pv3";
358 nvidia,function = "sdmmc1";
359 nvidia,pull = <TEGRA_PIN_PULL_UP>;
360 nvidia,tristate = <TEGRA_PIN_ENABLE>;
361 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
362 };
363 clk2_out_pw5 { /* D5 GPIO */
364 nvidia,pins = "clk2_out_pw5";
365 nvidia,function = "rsvd2";
366 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
367 nvidia,tristate = <TEGRA_PIN_DISABLE>;
368 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369 };
370 sdmmc1_dat3_py4 {
371 nvidia,pins = "sdmmc1_dat3_py4";
372 nvidia,function = "sdmmc1";
373 nvidia,pull = <TEGRA_PIN_PULL_UP>;
374 nvidia,tristate = <TEGRA_PIN_DISABLE>;
375 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
376 };
377 sdmmc1_dat2_py5 {
378 nvidia,pins = "sdmmc1_dat2_py5";
379 nvidia,function = "sdmmc1";
380 nvidia,pull = <TEGRA_PIN_PULL_UP>;
381 nvidia,tristate = <TEGRA_PIN_DISABLE>;
382 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
383 };
384 sdmmc1_dat1_py6 {
385 nvidia,pins = "sdmmc1_dat1_py6";
386 nvidia,function = "sdmmc1";
387 nvidia,pull = <TEGRA_PIN_PULL_UP>;
388 nvidia,tristate = <TEGRA_PIN_DISABLE>;
389 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
390 };
391 sdmmc1_dat0_py7 {
392 nvidia,pins = "sdmmc1_dat0_py7";
393 nvidia,function = "sdmmc1";
394 nvidia,pull = <TEGRA_PIN_PULL_UP>;
395 nvidia,tristate = <TEGRA_PIN_DISABLE>;
396 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
397 };
398 sdmmc1_clk_pz0 {
399 nvidia,pins = "sdmmc1_clk_pz0";
400 nvidia,function = "sdmmc1";
401 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
402 nvidia,tristate = <TEGRA_PIN_DISABLE>;
403 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
404 };
405 sdmmc1_cmd_pz1 {
406 nvidia,pins = "sdmmc1_cmd_pz1";
407 nvidia,function = "sdmmc1";
408 nvidia,pull = <TEGRA_PIN_PULL_UP>;
409 nvidia,tristate = <TEGRA_PIN_DISABLE>;
410 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
411 };
412 clk2_req_pcc5 { /* D4 GPIO */
413 nvidia,pins = "clk2_req_pcc5";
414 nvidia,function = "rsvd2";
415 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
416 nvidia,tristate = <TEGRA_PIN_DISABLE>;
417 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
418 };
419 /*
420 * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it
421 * features some magic properties even though the
422 * external loopback is disabled and the internal
423 * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
424 * register's SDMMC_SPARE1 bits being set to 0xfffd
425 * according to the TRM!
426 */
427 sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
428 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
429 nvidia,function = "sdmmc3";
430 nvidia,pull = <TEGRA_PIN_PULL_UP>;
431 nvidia,tristate = <TEGRA_PIN_DISABLE>;
432 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
433 };
434 usb_vbus_en2_pff1 { /* D7 GPIO */
435 nvidia,pins = "usb_vbus_en2_pff1";
436 nvidia,function = "rsvd2";
437 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
438 nvidia,tristate = <TEGRA_PIN_DISABLE>;
439 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
440 };
441
442 /* Apalis PWM */
443 ph0 {
444 nvidia,pins = "ph0";
445 nvidia,function = "pwm0";
446 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
447 nvidia,tristate = <TEGRA_PIN_DISABLE>;
448 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
449 };
450 ph1 {
451 nvidia,pins = "ph1";
452 nvidia,function = "pwm1";
453 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454 nvidia,tristate = <TEGRA_PIN_DISABLE>;
455 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
456 };
457 ph2 {
458 nvidia,pins = "ph2";
459 nvidia,function = "pwm2";
460 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
461 nvidia,tristate = <TEGRA_PIN_DISABLE>;
462 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
463 };
464 /* PWM3 active on pu6 being Apalis BKL1_PWM */
465 ph3 {
466 nvidia,pins = "ph3";
467 nvidia,function = "gmi";
468 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
469 nvidia,tristate = <TEGRA_PIN_ENABLE>;
470 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
471 };
472
473 /* Apalis SATA1_ACT# */
474 dap1_dout_pn2 {
475 nvidia,pins = "dap1_dout_pn2";
476 nvidia,function = "gmi";
477 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
478 nvidia,tristate = <TEGRA_PIN_DISABLE>;
479 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
480 };
481
482 /* Apalis SD1 */
483 sdmmc3_clk_pa6 {
484 nvidia,pins = "sdmmc3_clk_pa6";
485 nvidia,function = "sdmmc3";
486 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
487 nvidia,tristate = <TEGRA_PIN_DISABLE>;
488 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
489 };
490 sdmmc3_cmd_pa7 {
491 nvidia,pins = "sdmmc3_cmd_pa7";
492 nvidia,function = "sdmmc3";
493 nvidia,pull = <TEGRA_PIN_PULL_UP>;
494 nvidia,tristate = <TEGRA_PIN_DISABLE>;
495 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
496 };
497 sdmmc3_dat3_pb4 {
498 nvidia,pins = "sdmmc3_dat3_pb4";
499 nvidia,function = "sdmmc3";
500 nvidia,pull = <TEGRA_PIN_PULL_UP>;
501 nvidia,tristate = <TEGRA_PIN_DISABLE>;
502 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
503 };
504 sdmmc3_dat2_pb5 {
505 nvidia,pins = "sdmmc3_dat2_pb5";
506 nvidia,function = "sdmmc3";
507 nvidia,pull = <TEGRA_PIN_PULL_UP>;
508 nvidia,tristate = <TEGRA_PIN_DISABLE>;
509 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
510 };
511 sdmmc3_dat1_pb6 {
512 nvidia,pins = "sdmmc3_dat1_pb6";
513 nvidia,function = "sdmmc3";
514 nvidia,pull = <TEGRA_PIN_PULL_UP>;
515 nvidia,tristate = <TEGRA_PIN_DISABLE>;
516 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
517 };
518 sdmmc3_dat0_pb7 {
519 nvidia,pins = "sdmmc3_dat0_pb7";
520 nvidia,function = "sdmmc3";
521 nvidia,pull = <TEGRA_PIN_PULL_UP>;
522 nvidia,tristate = <TEGRA_PIN_DISABLE>;
523 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
524 };
525 /*
526 * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
527 * features some magic properties even though the
528 * external loopback is disabled and the internal
529 * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
530 * register's SDMMC_SPARE1 bits being set to 0xfffd
531 * according to the TRM!
532 */
533 sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */
534 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
535 nvidia,function = "rsvd2";
536 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
537 nvidia,tristate = <TEGRA_PIN_ENABLE>;
538 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
539 };
540
541 /* Apalis SPDIF */
542 spdif_out_pk5 {
543 nvidia,pins = "spdif_out_pk5";
544 nvidia,function = "spdif";
545 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
546 nvidia,tristate = <TEGRA_PIN_DISABLE>;
547 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
548 };
549 spdif_in_pk6 {
550 nvidia,pins = "spdif_in_pk6";
551 nvidia,function = "spdif";
552 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
553 nvidia,tristate = <TEGRA_PIN_ENABLE>;
554 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
555 };
556
557 /* Apalis SPI1 */
558 ulpi_clk_py0 {
559 nvidia,pins = "ulpi_clk_py0";
560 nvidia,function = "spi1";
561 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
562 nvidia,tristate = <TEGRA_PIN_DISABLE>;
563 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
564 };
565 ulpi_dir_py1 {
566 nvidia,pins = "ulpi_dir_py1";
567 nvidia,function = "spi1";
568 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
569 nvidia,tristate = <TEGRA_PIN_ENABLE>;
570 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
571 };
572 ulpi_nxt_py2 {
573 nvidia,pins = "ulpi_nxt_py2";
574 nvidia,function = "spi1";
575 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
576 nvidia,tristate = <TEGRA_PIN_DISABLE>;
577 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
578 };
579 ulpi_stp_py3 {
580 nvidia,pins = "ulpi_stp_py3";
581 nvidia,function = "spi1";
582 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
583 nvidia,tristate = <TEGRA_PIN_DISABLE>;
584 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
585 };
586
587 /* Apalis SPI2 */
588 pg5 {
589 nvidia,pins = "pg5";
590 nvidia,function = "spi4";
591 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
592 nvidia,tristate = <TEGRA_PIN_DISABLE>;
593 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
594 };
595 pg6 {
596 nvidia,pins = "pg6";
597 nvidia,function = "spi4";
598 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
599 nvidia,tristate = <TEGRA_PIN_DISABLE>;
600 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
601 };
602 pg7 {
603 nvidia,pins = "pg7";
604 nvidia,function = "spi4";
605 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
606 nvidia,tristate = <TEGRA_PIN_ENABLE>;
607 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
608 };
609 pi3 {
610 nvidia,pins = "pi3";
611 nvidia,function = "spi4";
612 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613 nvidia,tristate = <TEGRA_PIN_DISABLE>;
614 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
615 };
616
617 /* Apalis UART1 */
618 pb1 { /* DCD GPIO */
619 nvidia,pins = "pb1";
620 nvidia,function = "rsvd2";
621 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
622 nvidia,tristate = <TEGRA_PIN_ENABLE>;
623 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
624 };
625 pk7 { /* RI GPIO */
626 nvidia,pins = "pk7";
627 nvidia,function = "rsvd2";
628 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
629 nvidia,tristate = <TEGRA_PIN_ENABLE>;
630 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
631 };
632 uart1_txd_pu0 {
633 nvidia,pins = "pu0";
634 nvidia,function = "uarta";
635 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
636 nvidia,tristate = <TEGRA_PIN_DISABLE>;
637 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
638 };
639 uart1_rxd_pu1 {
640 nvidia,pins = "pu1";
641 nvidia,function = "uarta";
642 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
643 nvidia,tristate = <TEGRA_PIN_ENABLE>;
644 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
645 };
646 uart1_cts_n_pu2 {
647 nvidia,pins = "pu2";
648 nvidia,function = "uarta";
649 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
650 nvidia,tristate = <TEGRA_PIN_ENABLE>;
651 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
652 };
653 uart1_rts_n_pu3 {
654 nvidia,pins = "pu3";
655 nvidia,function = "uarta";
656 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
657 nvidia,tristate = <TEGRA_PIN_DISABLE>;
658 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
659 };
660 uart3_cts_n_pa1 { /* DSR GPIO */
661 nvidia,pins = "uart3_cts_n_pa1";
662 nvidia,function = "gmi";
663 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
664 nvidia,tristate = <TEGRA_PIN_ENABLE>;
665 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
666 };
667 uart3_rts_n_pc0 { /* DTR GPIO */
668 nvidia,pins = "uart3_rts_n_pc0";
669 nvidia,function = "gmi";
670 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
671 nvidia,tristate = <TEGRA_PIN_DISABLE>;
672 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
673 };
674
675 /* Apalis UART2 */
676 uart2_txd_pc2 {
677 nvidia,pins = "uart2_txd_pc2";
678 nvidia,function = "irda";
679 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
680 nvidia,tristate = <TEGRA_PIN_DISABLE>;
681 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
682 };
683 uart2_rxd_pc3 {
684 nvidia,pins = "uart2_rxd_pc3";
685 nvidia,function = "irda";
686 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
687 nvidia,tristate = <TEGRA_PIN_ENABLE>;
688 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
689 };
690 uart2_cts_n_pj5 {
691 nvidia,pins = "uart2_cts_n_pj5";
692 nvidia,function = "uartb";
693 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
694 nvidia,tristate = <TEGRA_PIN_ENABLE>;
695 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
696 };
697 uart2_rts_n_pj6 {
698 nvidia,pins = "uart2_rts_n_pj6";
699 nvidia,function = "uartb";
700 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701 nvidia,tristate = <TEGRA_PIN_DISABLE>;
702 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
703 };
704
705 /* Apalis UART3 */
706 uart3_txd_pw6 {
707 nvidia,pins = "uart3_txd_pw6";
708 nvidia,function = "uartc";
709 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
710 nvidia,tristate = <TEGRA_PIN_DISABLE>;
711 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
712 };
713 uart3_rxd_pw7 {
714 nvidia,pins = "uart3_rxd_pw7";
715 nvidia,function = "uartc";
716 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
717 nvidia,tristate = <TEGRA_PIN_ENABLE>;
718 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
719 };
720
721 /* Apalis UART4 */
722 uart4_rxd_pb0 {
723 nvidia,pins = "pb0";
724 nvidia,function = "uartd";
725 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
726 nvidia,tristate = <TEGRA_PIN_ENABLE>;
727 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
728 };
729 uart4_txd_pj7 {
730 nvidia,pins = "pj7";
731 nvidia,function = "uartd";
732 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
733 nvidia,tristate = <TEGRA_PIN_DISABLE>;
734 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
735 };
736
737 /* Apalis USBH_EN */
738 usb_vbus_en1_pn5 {
739 nvidia,pins = "usb_vbus_en1_pn5";
740 nvidia,function = "rsvd2";
741 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
742 nvidia,tristate = <TEGRA_PIN_DISABLE>;
743 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
744 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
745 };
746
747 /* Apalis USBH_OC# */
748 pbb0 {
749 nvidia,pins = "pbb0";
750 nvidia,function = "vgp6";
751 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
752 nvidia,tristate = <TEGRA_PIN_ENABLE>;
753 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
754 };
755
756 /* Apalis USBO1_EN */
757 usb_vbus_en0_pn4 {
758 nvidia,pins = "usb_vbus_en0_pn4";
759 nvidia,function = "rsvd2";
760 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
761 nvidia,tristate = <TEGRA_PIN_DISABLE>;
762 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
763 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
764 };
765
766 /* Apalis USBO1_OC# */
767 pbb4 {
768 nvidia,pins = "pbb4";
769 nvidia,function = "vgp4";
770 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
771 nvidia,tristate = <TEGRA_PIN_ENABLE>;
772 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
773 };
774
775 /* Apalis WAKE1_MICO */
776 pex_wake_n_pdd3 {
777 nvidia,pins = "pex_wake_n_pdd3";
778 nvidia,function = "rsvd2";
779 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
780 nvidia,tristate = <TEGRA_PIN_ENABLE>;
781 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
782 };
783
784 /* CORE_PWR_REQ */
785 core_pwr_req {
786 nvidia,pins = "core_pwr_req";
787 nvidia,function = "pwron";
788 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
789 nvidia,tristate = <TEGRA_PIN_DISABLE>;
790 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
791 };
792
793 /* CPU_PWR_REQ */
794 cpu_pwr_req {
795 nvidia,pins = "cpu_pwr_req";
796 nvidia,function = "cpu";
797 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
798 nvidia,tristate = <TEGRA_PIN_DISABLE>;
799 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
800 };
801
802 /* DVFS */
803 dvfs_pwm_px0 {
804 nvidia,pins = "dvfs_pwm_px0";
805 nvidia,function = "cldvfs";
806 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
807 nvidia,tristate = <TEGRA_PIN_DISABLE>;
808 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
809 };
810 dvfs_clk_px2 {
811 nvidia,pins = "dvfs_clk_px2";
812 nvidia,function = "cldvfs";
813 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
814 nvidia,tristate = <TEGRA_PIN_DISABLE>;
815 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
816 };
817
818 /* eMMC */
819 sdmmc4_dat0_paa0 {
820 nvidia,pins = "sdmmc4_dat0_paa0";
821 nvidia,function = "sdmmc4";
822 nvidia,pull = <TEGRA_PIN_PULL_UP>;
823 nvidia,tristate = <TEGRA_PIN_DISABLE>;
824 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
825 };
826 sdmmc4_dat1_paa1 {
827 nvidia,pins = "sdmmc4_dat1_paa1";
828 nvidia,function = "sdmmc4";
829 nvidia,pull = <TEGRA_PIN_PULL_UP>;
830 nvidia,tristate = <TEGRA_PIN_DISABLE>;
831 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
832 };
833 sdmmc4_dat2_paa2 {
834 nvidia,pins = "sdmmc4_dat2_paa2";
835 nvidia,function = "sdmmc4";
836 nvidia,pull = <TEGRA_PIN_PULL_UP>;
837 nvidia,tristate = <TEGRA_PIN_DISABLE>;
838 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
839 };
840 sdmmc4_dat3_paa3 {
841 nvidia,pins = "sdmmc4_dat3_paa3";
842 nvidia,function = "sdmmc4";
843 nvidia,pull = <TEGRA_PIN_PULL_UP>;
844 nvidia,tristate = <TEGRA_PIN_DISABLE>;
845 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
846 };
847 sdmmc4_dat4_paa4 {
848 nvidia,pins = "sdmmc4_dat4_paa4";
849 nvidia,function = "sdmmc4";
850 nvidia,pull = <TEGRA_PIN_PULL_UP>;
851 nvidia,tristate = <TEGRA_PIN_DISABLE>;
852 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
853 };
854 sdmmc4_dat5_paa5 {
855 nvidia,pins = "sdmmc4_dat5_paa5";
856 nvidia,function = "sdmmc4";
857 nvidia,pull = <TEGRA_PIN_PULL_UP>;
858 nvidia,tristate = <TEGRA_PIN_DISABLE>;
859 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
860 };
861 sdmmc4_dat6_paa6 {
862 nvidia,pins = "sdmmc4_dat6_paa6";
863 nvidia,function = "sdmmc4";
864 nvidia,pull = <TEGRA_PIN_PULL_UP>;
865 nvidia,tristate = <TEGRA_PIN_DISABLE>;
866 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
867 };
868 sdmmc4_dat7_paa7 {
869 nvidia,pins = "sdmmc4_dat7_paa7";
870 nvidia,function = "sdmmc4";
871 nvidia,pull = <TEGRA_PIN_PULL_UP>;
872 nvidia,tristate = <TEGRA_PIN_DISABLE>;
873 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
874 };
875 sdmmc4_clk_pcc4 {
876 nvidia,pins = "sdmmc4_clk_pcc4";
877 nvidia,function = "sdmmc4";
878 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
879 nvidia,tristate = <TEGRA_PIN_DISABLE>;
880 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
881 };
882 sdmmc4_cmd_pt7 {
883 nvidia,pins = "sdmmc4_cmd_pt7";
884 nvidia,function = "sdmmc4";
885 nvidia,pull = <TEGRA_PIN_PULL_UP>;
886 nvidia,tristate = <TEGRA_PIN_DISABLE>;
887 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
888 };
889
890 /* JTAG_RTCK */
891 jtag_rtck {
892 nvidia,pins = "jtag_rtck";
893 nvidia,function = "rtck";
894 nvidia,pull = <TEGRA_PIN_PULL_UP>;
895 nvidia,tristate = <TEGRA_PIN_DISABLE>;
896 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
897 };
898
899 /* LAN_DEV_OFF# */
900 ulpi_data5_po6 {
901 nvidia,pins = "ulpi_data5_po6";
902 nvidia,function = "ulpi";
903 nvidia,pull = <TEGRA_PIN_PULL_UP>;
904 nvidia,tristate = <TEGRA_PIN_DISABLE>;
905 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
906 };
907
908 /* LAN_RESET# */
909 kb_row10_ps2 {
910 nvidia,pins = "kb_row10_ps2";
911 nvidia,function = "rsvd2";
912 nvidia,pull = <TEGRA_PIN_PULL_UP>;
913 nvidia,tristate = <TEGRA_PIN_DISABLE>;
914 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
915 };
916
917 /* LAN_WAKE# */
918 ulpi_data4_po5 {
919 nvidia,pins = "ulpi_data4_po5";
920 nvidia,function = "ulpi";
921 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
922 nvidia,tristate = <TEGRA_PIN_ENABLE>;
923 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
924 };
925
926 /* MCU_INT1# */
927 pk2 {
928 nvidia,pins = "pk2";
929 nvidia,function = "rsvd1";
930 nvidia,pull = <TEGRA_PIN_PULL_UP>;
931 nvidia,tristate = <TEGRA_PIN_ENABLE>;
932 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
933 };
934
935 /* MCU_INT2# */
936 pj2 {
937 nvidia,pins = "pj2";
938 nvidia,function = "rsvd1";
939 nvidia,pull = <TEGRA_PIN_PULL_UP>;
940 nvidia,tristate = <TEGRA_PIN_ENABLE>;
941 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
942 };
943
944 /* MCU_INT3# */
945 pi5 {
946 nvidia,pins = "pi5";
947 nvidia,function = "rsvd2";
948 nvidia,pull = <TEGRA_PIN_PULL_UP>;
949 nvidia,tristate = <TEGRA_PIN_ENABLE>;
950 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
951 };
952
953 /* MCU_INT4# */
954 pj0 {
955 nvidia,pins = "pj0";
956 nvidia,function = "rsvd1";
957 nvidia,pull = <TEGRA_PIN_PULL_UP>;
958 nvidia,tristate = <TEGRA_PIN_ENABLE>;
959 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
960 };
961
962 /* MCU_RESET */
963 pbb6 {
964 nvidia,pins = "pbb6";
965 nvidia,function = "rsvd2";
966 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
967 nvidia,tristate = <TEGRA_PIN_DISABLE>;
968 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
969 };
970
971 /* MCU SPI */
972 gpio_x4_aud_px4 {
973 nvidia,pins = "gpio_x4_aud_px4";
974 nvidia,function = "spi2";
975 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
976 nvidia,tristate = <TEGRA_PIN_DISABLE>;
977 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
978 };
979 gpio_x5_aud_px5 {
980 nvidia,pins = "gpio_x5_aud_px5";
981 nvidia,function = "spi2";
982 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
983 nvidia,tristate = <TEGRA_PIN_DISABLE>;
984 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
985 };
986 gpio_x6_aud_px6 { /* MCU_CS */
987 nvidia,pins = "gpio_x6_aud_px6";
988 nvidia,function = "spi2";
989 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
990 nvidia,tristate = <TEGRA_PIN_DISABLE>;
991 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
992 };
993 gpio_x7_aud_px7 {
994 nvidia,pins = "gpio_x7_aud_px7";
995 nvidia,function = "spi2";
996 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
997 nvidia,tristate = <TEGRA_PIN_ENABLE>;
998 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
999 };
1000 gpio_w2_aud_pw2 { /* MCU_CSEZP */
1001 nvidia,pins = "gpio_w2_aud_pw2";
1002 nvidia,function = "spi2";
1003 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1004 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1005 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1006 };
1007
1008 /* PMIC_CLK_32K */
1009 clk_32k_in {
1010 nvidia,pins = "clk_32k_in";
1011 nvidia,function = "clk";
1012 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1013 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1014 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1015 };
1016
1017 /* PMIC_CPU_OC_INT */
1018 clk_32k_out_pa0 {
1019 nvidia,pins = "clk_32k_out_pa0";
1020 nvidia,function = "soc";
1021 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1022 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1023 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1024 };
1025
1026 /* PWR_I2C */
1027 pwr_i2c_scl_pz6 {
1028 nvidia,pins = "pwr_i2c_scl_pz6";
1029 nvidia,function = "i2cpwr";
1030 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1031 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1032 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1033 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1034 };
1035 pwr_i2c_sda_pz7 {
1036 nvidia,pins = "pwr_i2c_sda_pz7";
1037 nvidia,function = "i2cpwr";
1038 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1039 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1040 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1041 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1042 };
1043
1044 /* PWR_INT_N */
1045 pwr_int_n {
1046 nvidia,pins = "pwr_int_n";
1047 nvidia,function = "pmi";
1048 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1049 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1050 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1051 };
1052
1053 /* RESET_MOCI_CTRL */
1054 pu4 {
1055 nvidia,pins = "pu4";
1056 nvidia,function = "gmi";
1057 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1058 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1059 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1060 };
1061
1062 /* RESET_OUT_N */
1063 reset_out_n {
1064 nvidia,pins = "reset_out_n";
1065 nvidia,function = "reset_out_n";
1066 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1067 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1068 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1069 };
1070
1071 /* SHIFT_CTRL_DIR_IN */
1072 kb_row0_pr0 {
1073 nvidia,pins = "kb_row0_pr0";
1074 nvidia,function = "rsvd2";
1075 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1076 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1077 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1078 };
1079 kb_row1_pr1 {
1080 nvidia,pins = "kb_row1_pr1";
1081 nvidia,function = "rsvd2";
1082 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1083 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1084 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1085 };
1086
1087 /* Configure level-shifter as output for HDA */
1088 kb_row11_ps3 {
1089 nvidia,pins = "kb_row11_ps3";
1090 nvidia,function = "rsvd2";
1091 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1092 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1093 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1094 };
1095
1096 /* SHIFT_CTRL_DIR_OUT */
1097 kb_col5_pq5 {
1098 nvidia,pins = "kb_col5_pq5";
1099 nvidia,function = "rsvd2";
1100 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1101 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1102 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1103 };
1104 kb_col6_pq6 {
1105 nvidia,pins = "kb_col6_pq6";
1106 nvidia,function = "rsvd2";
1107 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1108 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1109 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1110 };
1111 kb_col7_pq7 {
1112 nvidia,pins = "kb_col7_pq7";
1113 nvidia,function = "rsvd2";
1114 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1115 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1116 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1117 };
1118
1119 /* SHIFT_CTRL_OE */
1120 kb_col0_pq0 {
1121 nvidia,pins = "kb_col0_pq0";
1122 nvidia,function = "rsvd2";
1123 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1124 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1125 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1126 };
1127 kb_col1_pq1 {
1128 nvidia,pins = "kb_col1_pq1";
1129 nvidia,function = "rsvd2";
1130 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1131 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1132 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1133 };
1134 kb_col2_pq2 {
1135 nvidia,pins = "kb_col2_pq2";
1136 nvidia,function = "rsvd2";
1137 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1138 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1139 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1140 };
1141 kb_col4_pq4 {
1142 nvidia,pins = "kb_col4_pq4";
1143 nvidia,function = "kbc";
1144 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1145 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1146 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1147 };
1148 kb_row2_pr2 {
1149 nvidia,pins = "kb_row2_pr2";
1150 nvidia,function = "rsvd2";
1151 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1152 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1153 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1154 };
1155
1156 /* GPIO_PI6 aka TEMP_ALERT_L */
1157 pi6 {
1158 nvidia,pins = "pi6";
1159 nvidia,function = "rsvd1";
1160 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1161 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1162 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1163 };
1164
1165 /* TOUCH_INT */
1166 gpio_w3_aud_pw3 {
1167 nvidia,pins = "gpio_w3_aud_pw3";
1168 nvidia,function = "spi6";
1169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1170 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1171 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1172 };
1173
1174 pc7 { /* NC */
1175 nvidia,pins = "pc7";
1176 nvidia,function = "rsvd1";
1177 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1178 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1179 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1180 };
1181 pg0 { /* NC */
1182 nvidia,pins = "pg0";
1183 nvidia,function = "rsvd1";
1184 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1185 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1186 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1187 };
1188 pg1 { /* NC */
1189 nvidia,pins = "pg1";
1190 nvidia,function = "rsvd1";
1191 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1192 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1193 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1194 };
1195 pg2 { /* NC */
1196 nvidia,pins = "pg2";
1197 nvidia,function = "rsvd1";
1198 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1200 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1201 };
1202 pg3 { /* NC */
1203 nvidia,pins = "pg3";
1204 nvidia,function = "rsvd1";
1205 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1207 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1208 };
1209 pg4 { /* NC */
1210 nvidia,pins = "pg4";
1211 nvidia,function = "rsvd1";
1212 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1213 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1214 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1215 };
1216 ph4 { /* NC */
1217 nvidia,pins = "ph4";
1218 nvidia,function = "rsvd2";
1219 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1221 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1222 };
1223 ph5 { /* NC */
1224 nvidia,pins = "ph5";
1225 nvidia,function = "rsvd2";
1226 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1227 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1228 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1229 };
1230 ph6 { /* NC */
1231 nvidia,pins = "ph6";
1232 nvidia,function = "gmi";
1233 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1234 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1235 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1236 };
1237 ph7 { /* NC */
1238 nvidia,pins = "ph7";
1239 nvidia,function = "gmi";
1240 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1242 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1243 };
1244 pi0 { /* NC */
1245 nvidia,pins = "pi0";
1246 nvidia,function = "rsvd1";
1247 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1248 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1249 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1250 };
1251 pi1 { /* NC */
1252 nvidia,pins = "pi1";
1253 nvidia,function = "rsvd1";
1254 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1255 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1256 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1257 };
1258 pi2 { /* NC */
1259 nvidia,pins = "pi2";
1260 nvidia,function = "rsvd4";
1261 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1262 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1263 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1264 };
1265 pi4 { /* NC */
1266 nvidia,pins = "pi4";
1267 nvidia,function = "gmi";
1268 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1269 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1270 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1271 };
1272 pi7 { /* NC */
1273 nvidia,pins = "pi7";
1274 nvidia,function = "rsvd1";
1275 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1276 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1277 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1278 };
1279 pk0 { /* NC */
1280 nvidia,pins = "pk0";
1281 nvidia,function = "rsvd1";
1282 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1283 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1284 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1285 };
1286 pk1 { /* NC */
1287 nvidia,pins = "pk1";
1288 nvidia,function = "rsvd4";
1289 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1290 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1291 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1292 };
1293 pk3 { /* NC */
1294 nvidia,pins = "pk3";
1295 nvidia,function = "gmi";
1296 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1297 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1298 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1299 };
1300 pk4 { /* NC */
1301 nvidia,pins = "pk4";
1302 nvidia,function = "rsvd2";
1303 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1304 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1305 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1306 };
1307 dap1_fs_pn0 { /* NC */
1308 nvidia,pins = "dap1_fs_pn0";
1309 nvidia,function = "rsvd4";
1310 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1311 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1312 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1313 };
1314 dap1_din_pn1 { /* NC */
1315 nvidia,pins = "dap1_din_pn1";
1316 nvidia,function = "rsvd4";
1317 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1318 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1319 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1320 };
1321 dap1_sclk_pn3 { /* NC */
1322 nvidia,pins = "dap1_sclk_pn3";
1323 nvidia,function = "rsvd4";
1324 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1325 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1326 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1327 };
1328 ulpi_data7_po0 { /* NC */
1329 nvidia,pins = "ulpi_data7_po0";
1330 nvidia,function = "ulpi";
1331 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1332 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1333 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1334 };
1335 ulpi_data0_po1 { /* NC */
1336 nvidia,pins = "ulpi_data0_po1";
1337 nvidia,function = "ulpi";
1338 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1339 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1340 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1341 };
1342 ulpi_data1_po2 { /* NC */
1343 nvidia,pins = "ulpi_data1_po2";
1344 nvidia,function = "ulpi";
1345 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1346 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1347 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1348 };
1349 ulpi_data2_po3 { /* NC */
1350 nvidia,pins = "ulpi_data2_po3";
1351 nvidia,function = "ulpi";
1352 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1353 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1354 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1355 };
1356 ulpi_data3_po4 { /* NC */
1357 nvidia,pins = "ulpi_data3_po4";
1358 nvidia,function = "ulpi";
1359 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1360 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1361 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1362 };
1363 ulpi_data6_po7 { /* NC */
1364 nvidia,pins = "ulpi_data6_po7";
1365 nvidia,function = "ulpi";
1366 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1367 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1368 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1369 };
1370 dap4_fs_pp4 { /* NC */
1371 nvidia,pins = "dap4_fs_pp4";
1372 nvidia,function = "rsvd4";
1373 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1374 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1375 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1376 };
1377 dap4_din_pp5 { /* NC */
1378 nvidia,pins = "dap4_din_pp5";
1379 nvidia,function = "rsvd3";
1380 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1381 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1382 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1383 };
1384 dap4_dout_pp6 { /* NC */
1385 nvidia,pins = "dap4_dout_pp6";
1386 nvidia,function = "rsvd4";
1387 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1388 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1389 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1390 };
1391 dap4_sclk_pp7 { /* NC */
1392 nvidia,pins = "dap4_sclk_pp7";
1393 nvidia,function = "rsvd3";
1394 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1395 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1396 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1397 };
1398 kb_col3_pq3 { /* NC */
1399 nvidia,pins = "kb_col3_pq3";
1400 nvidia,function = "kbc";
1401 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1402 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1403 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1404 };
1405 kb_row3_pr3 { /* NC */
1406 nvidia,pins = "kb_row3_pr3";
1407 nvidia,function = "kbc";
1408 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1409 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1410 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1411 };
1412 kb_row4_pr4 { /* NC */
1413 nvidia,pins = "kb_row4_pr4";
1414 nvidia,function = "rsvd3";
1415 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1416 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1417 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1418 };
1419 kb_row5_pr5 { /* NC */
1420 nvidia,pins = "kb_row5_pr5";
1421 nvidia,function = "rsvd3";
1422 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1423 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1424 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1425 };
1426 kb_row6_pr6 { /* NC */
1427 nvidia,pins = "kb_row6_pr6";
1428 nvidia,function = "kbc";
1429 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1430 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1431 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1432 };
1433 kb_row7_pr7 { /* NC */
1434 nvidia,pins = "kb_row7_pr7";
1435 nvidia,function = "rsvd2";
1436 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1437 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1438 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1439 };
1440 kb_row8_ps0 { /* NC */
1441 nvidia,pins = "kb_row8_ps0";
1442 nvidia,function = "rsvd2";
1443 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1444 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1445 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1446 };
1447 kb_row9_ps1 { /* NC */
1448 nvidia,pins = "kb_row9_ps1";
1449 nvidia,function = "rsvd2";
1450 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1451 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1452 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1453 };
1454 kb_row12_ps4 { /* NC */
1455 nvidia,pins = "kb_row12_ps4";
1456 nvidia,function = "rsvd2";
1457 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1458 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1459 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1460 };
1461 kb_row13_ps5 { /* NC */
1462 nvidia,pins = "kb_row13_ps5";
1463 nvidia,function = "rsvd2";
1464 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1465 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1466 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1467 };
1468 kb_row14_ps6 { /* NC */
1469 nvidia,pins = "kb_row14_ps6";
1470 nvidia,function = "rsvd2";
1471 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1472 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1473 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1474 };
1475 kb_row15_ps7 { /* NC */
1476 nvidia,pins = "kb_row15_ps7";
1477 nvidia,function = "rsvd3";
1478 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1479 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1480 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1481 };
1482 kb_row16_pt0 { /* NC */
1483 nvidia,pins = "kb_row16_pt0";
1484 nvidia,function = "rsvd2";
1485 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1486 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1487 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1488 };
1489 kb_row17_pt1 { /* NC */
1490 nvidia,pins = "kb_row17_pt1";
1491 nvidia,function = "rsvd2";
1492 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1493 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1494 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1495 };
1496 pu5 { /* NC */
1497 nvidia,pins = "pu5";
1498 nvidia,function = "gmi";
1499 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1500 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1501 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1502 };
1503 pv0 { /* NC */
1504 nvidia,pins = "pv0";
1505 nvidia,function = "rsvd1";
1506 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1507 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1508 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1509 };
1510 pv1 { /* NC */
1511 nvidia,pins = "pv1";
1512 nvidia,function = "rsvd1";
1513 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1514 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1515 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1516 };
1517 sdmmc3_cd_n_pv2 { /* NC */
1518 nvidia,pins = "sdmmc3_cd_n_pv2";
1519 nvidia,function = "rsvd3";
1520 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1521 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1522 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1523 };
1524 gpio_x1_aud_px1 { /* NC */
1525 nvidia,pins = "gpio_x1_aud_px1";
1526 nvidia,function = "rsvd2";
1527 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1528 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1529 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1530 };
1531 gpio_x3_aud_px3 { /* NC */
1532 nvidia,pins = "gpio_x3_aud_px3";
1533 nvidia,function = "rsvd4";
1534 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1535 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1536 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1537 };
1538 pbb7 { /* NC */
1539 nvidia,pins = "pbb7";
1540 nvidia,function = "rsvd2";
1541 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1542 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1543 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1544 };
1545 pcc1 { /* NC */
1546 nvidia,pins = "pcc1";
1547 nvidia,function = "rsvd2";
1548 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1549 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1550 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1551 };
1552 pcc2 { /* NC */
1553 nvidia,pins = "pcc2";
1554 nvidia,function = "rsvd2";
1555 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1556 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1557 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1558 };
1559 clk3_req_pee1 { /* NC */
1560 nvidia,pins = "clk3_req_pee1";
1561 nvidia,function = "rsvd2";
1562 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1563 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1564 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1565 };
1566 dap_mclk1_req_pee2 { /* NC */
1567 nvidia,pins = "dap_mclk1_req_pee2";
1568 nvidia,function = "rsvd4";
1569 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1570 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1571 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1572 };
1573 };
1574 };
1575
1576 serial@70006040 {
1577 compatible = "nvidia,tegra124-hsuart";
1578 };
1579
1580 serial@70006200 {
1581 compatible = "nvidia,tegra124-hsuart";
1582 };
1583
1584 serial@70006300 {
1585 compatible = "nvidia,tegra124-hsuart";
1586 };
1587
1588 hdmi_ddc: i2c@7000c400 {
1589 clock-frequency = <100000>;
1590 };
1591
1592 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1593 i2c@7000d000 {
1594 status = "okay";
1595 clock-frequency = <400000>;
1596
1597 /* SGTL5000 audio codec */
1598 sgtl5000: codec@0a {
1599 compatible = "fsl,sgtl5000";
1600 reg = <0x0a>;
1601 VDDA-supply = <&reg_3v3>;
1602 VDDIO-supply = <&vddio_1v8>;
1603 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1604 };
1605
1606 pmic: pmic@40 {
1607 compatible = "ams,as3722";
1608 reg = <0x40>;
1609 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1610
1611 ams,system-power-controller;
1612
1613 #interrupt-cells = <2>;
1614 interrupt-controller;
1615
1616 gpio-controller;
1617 #gpio-cells = <2>;
1618
1619 pinctrl-names = "default";
1620 pinctrl-0 = <&as3722_default>;
1621
1622 as3722_default: pinmux {
1623 gpio2_7 {
1624 pins = "gpio2", /* PWR_EN_+V3.3 */
1625 "gpio7"; /* +V1.6_LPO */
1626 function = "gpio";
1627 bias-pull-up;
1628 };
1629
1630 gpio1_3_4_5_6 {
1631 pins = "gpio1", "gpio3", "gpio4",
1632 "gpio5", "gpio6";
1633 bias-high-impedance;
1634 };
1635 };
1636
1637 regulators {
1638 vsup-sd2-supply = <&reg_3v3>;
1639 vsup-sd3-supply = <&reg_3v3>;
1640 vsup-sd4-supply = <&reg_3v3>;
1641 vsup-sd5-supply = <&reg_3v3>;
1642 vin-ldo0-supply = <&vddio_ddr_1v35>;
1643 vin-ldo1-6-supply = <&reg_3v3>;
1644 vin-ldo2-5-7-supply = <&vddio_1v8>;
1645 vin-ldo3-4-supply = <&reg_3v3>;
1646 vin-ldo9-10-supply = <&reg_3v3>;
1647 vin-ldo11-supply = <&reg_3v3>;
1648
1649 vdd_cpu: sd0 {
1650 regulator-name = "+VDD_CPU_AP";
1651 regulator-min-microvolt = <700000>;
1652 regulator-max-microvolt = <1400000>;
1653 regulator-min-microamp = <3500000>;
1654 regulator-max-microamp = <3500000>;
1655 regulator-always-on;
1656 regulator-boot-on;
1657 ams,ext-control = <2>;
1658 };
1659
1660 sd1 {
1661 regulator-name = "+VDD_CORE";
1662 regulator-min-microvolt = <700000>;
1663 regulator-max-microvolt = <1350000>;
1664 regulator-min-microamp = <2500000>;
1665 regulator-max-microamp = <4000000>;
1666 regulator-always-on;
1667 regulator-boot-on;
1668 ams,ext-control = <1>;
1669 };
1670
1671 vddio_ddr_1v35: sd2 {
1672 regulator-name =
1673 "+V1.35_VDDIO_DDR(sd2)";
1674 regulator-min-microvolt = <1350000>;
1675 regulator-max-microvolt = <1350000>;
1676 regulator-always-on;
1677 regulator-boot-on;
1678 };
1679
1680 sd3 {
1681 regulator-name =
1682 "+V1.35_VDDIO_DDR(sd3)";
1683 regulator-min-microvolt = <1350000>;
1684 regulator-max-microvolt = <1350000>;
1685 regulator-always-on;
1686 regulator-boot-on;
1687 };
1688
1689 vdd_1v05: sd4 {
1690 regulator-name = "+V1.05";
1691 regulator-min-microvolt = <1050000>;
1692 regulator-max-microvolt = <1050000>;
1693 };
1694
1695 vddio_1v8: sd5 {
1696 regulator-name = "+V1.8";
1697 regulator-min-microvolt = <1800000>;
1698 regulator-max-microvolt = <1800000>;
1699 regulator-boot-on;
1700 regulator-always-on;
1701 };
1702
1703 vdd_gpu: sd6 {
1704 regulator-name = "+VDD_GPU_AP";
1705 regulator-min-microvolt = <650000>;
1706 regulator-max-microvolt = <1200000>;
1707 regulator-min-microamp = <3500000>;
1708 regulator-max-microamp = <3500000>;
1709 regulator-boot-on;
1710 regulator-always-on;
1711 };
1712
1713 avdd_1v05: ldo0 {
1714 regulator-name = "+V1.05_AVDD";
1715 regulator-min-microvolt = <1050000>;
1716 regulator-max-microvolt = <1050000>;
1717 regulator-boot-on;
1718 regulator-always-on;
1719 ams,ext-control = <1>;
1720 };
1721
1722 vddio_sdmmc1: ldo1 {
1723 regulator-name = "VDDIO_SDMMC1";
1724 regulator-min-microvolt = <1800000>;
1725 regulator-max-microvolt = <3300000>;
1726 };
1727
1728 ldo2 {
1729 regulator-name = "+V1.2";
1730 regulator-min-microvolt = <1200000>;
1731 regulator-max-microvolt = <1200000>;
1732 regulator-boot-on;
1733 regulator-always-on;
1734 };
1735
1736 ldo3 {
1737 regulator-name = "+V1.05_RTC";
1738 regulator-min-microvolt = <1000000>;
1739 regulator-max-microvolt = <1000000>;
1740 regulator-boot-on;
1741 regulator-always-on;
1742 ams,enable-tracking;
1743 };
1744
1745 /* 1.8V for LVDS, 3.3V for eDP */
1746 ldo4 {
1747 regulator-name = "AVDD_LVDS0_PLL";
1748 regulator-min-microvolt = <1800000>;
1749 regulator-max-microvolt = <1800000>;
1750 };
1751
1752 /* LDO5 not used */
1753
1754 vddio_sdmmc3: ldo6 {
1755 regulator-name = "VDDIO_SDMMC3";
1756 regulator-min-microvolt = <1800000>;
1757 regulator-max-microvolt = <3300000>;
1758 };
1759
1760 /* LDO7 not used */
1761
1762 ldo9 {
1763 regulator-name = "+V3.3_ETH(ldo9)";
1764 regulator-min-microvolt = <3300000>;
1765 regulator-max-microvolt = <3300000>;
1766 regulator-always-on;
1767 };
1768
1769 ldo10 {
1770 regulator-name = "+V3.3_ETH(ldo10)";
1771 regulator-min-microvolt = <3300000>;
1772 regulator-max-microvolt = <3300000>;
1773 regulator-always-on;
1774 };
1775
1776 ldo11 {
1777 regulator-name = "+V1.8_VPP_FUSE";
1778 regulator-min-microvolt = <1800000>;
1779 regulator-max-microvolt = <1800000>;
1780 };
1781 };
1782 };
1783
1784 /*
1785 * TMP451 temperature sensor
1786 * Note: THERM_N directly connected to AS3722 PMIC THERM
1787 */
1788 temperature-sensor@4c {
1789 compatible = "ti,tmp451";
1790 reg = <0x4c>;
1791 interrupt-parent = <&gpio>;
1792 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1793
1794 #thermal-sensor-cells = <1>;
1795 };
1796 };
1797
1798 /* SPI2: MCU SPI */
1799 spi@7000d600 {
1800 status = "okay";
1801 spi-max-frequency = <25000000>;
1802 };
1803
1804 pmc@7000e400 {
1805 nvidia,invert-interrupt;
1806 nvidia,suspend-mode = <1>;
1807 nvidia,cpu-pwr-good-time = <500>;
1808 nvidia,cpu-pwr-off-time = <300>;
1809 nvidia,core-pwr-good-time = <641 3845>;
1810 nvidia,core-pwr-off-time = <61036>;
1811 nvidia,core-power-req-active-high;
1812 nvidia,sys-clock-req-active-high;
1813
1814 /* Set power_off bit in ResetControl register of AS3722 PMIC */
1815 i2c-thermtrip {
1816 nvidia,i2c-controller-id = <4>;
1817 nvidia,bus-addr = <0x40>;
1818 nvidia,reg-addr = <0x36>;
1819 nvidia,reg-data = <0x2>;
1820 };
1821 };
1822
1823 sata@70020000 {
1824 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1825 phy-names = "sata-0";
1826
1827 avdd-supply = <&vdd_1v05>;
1828 hvdd-supply = <&reg_3v3>;
1829 vddio-supply = <&vdd_1v05>;
1830 };
1831
1832 usb@70090000 {
1833 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1834 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1835 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
1836 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1837 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1838 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1839 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1840
1841 avddio-pex-supply = <&vdd_1v05>;
1842 avdd-pll-erefe-supply = <&avdd_1v05>;
1843 avdd-pll-utmip-supply = <&vddio_1v8>;
1844 avdd-usb-ss-pll-supply = <&vdd_1v05>;
1845 avdd-usb-supply = <&reg_3v3>;
1846 dvddio-pex-supply = <&vdd_1v05>;
1847 hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
1848 hvdd-usb-ss-supply = <&reg_3v3>;
1849 };
1850
1851 padctl@7009f000 {
1852 pads {
1853 usb2 {
1854 status = "okay";
1855
1856 lanes {
1857 usb2-0 {
1858 nvidia,function = "xusb";
1859 status = "okay";
1860 };
1861
1862 usb2-1 {
1863 nvidia,function = "xusb";
1864 status = "okay";
1865 };
1866
1867 usb2-2 {
1868 nvidia,function = "xusb";
1869 status = "okay";
1870 };
1871 };
1872 };
1873
1874 pcie {
1875 status = "okay";
1876
1877 lanes {
1878 pcie-0 {
1879 nvidia,function = "usb3-ss";
1880 status = "okay";
1881 };
1882
1883 pcie-1 {
1884 nvidia,function = "usb3-ss";
1885 status = "okay";
1886 };
1887
1888 pcie-2 {
1889 nvidia,function = "pcie";
1890 status = "okay";
1891 };
1892
1893 pcie-3 {
1894 nvidia,function = "pcie";
1895 status = "okay";
1896 };
1897
1898 pcie-4 {
1899 nvidia,function = "pcie";
1900 status = "okay";
1901 };
1902 };
1903 };
1904
1905 sata {
1906 status = "okay";
1907
1908 lanes {
1909 sata-0 {
1910 nvidia,function = "sata";
1911 status = "okay";
1912 };
1913 };
1914 };
1915 };
1916
1917 ports {
1918 /* USBO1 */
1919 usb2-0 {
1920 status = "okay";
1921 mode = "otg";
1922
1923 vbus-supply = <&reg_usbo1_vbus>;
1924 };
1925
1926 /* USBH2 */
1927 usb2-1 {
1928 status = "okay";
1929 mode = "host";
1930
1931 vbus-supply = <&reg_usbh_vbus>;
1932 };
1933
1934 /* USBH4 */
1935 usb2-2 {
1936 status = "okay";
1937 mode = "host";
1938
1939 vbus-supply = <&reg_usbh_vbus>;
1940 };
1941
1942 usb3-0 {
1943 nvidia,usb2-companion = <2>;
1944 status = "okay";
1945 };
1946
1947 usb3-1 {
1948 nvidia,usb2-companion = <0>;
1949 status = "okay";
1950 };
1951 };
1952 };
1953
1954 /* eMMC */
1955 sdhci@700b0600 {
1956 status = "okay";
1957 bus-width = <8>;
1958 non-removable;
1959 };
1960
1961 /* CPU DFLL clock */
1962 clock@70110000 {
1963 status = "okay";
1964 vdd-cpu-supply = <&vdd_cpu>;
1965 nvidia,i2c-fs-rate = <400000>;
1966 };
1967
1968 ahub@70300000 {
1969 i2s@70301200 {
1970 status = "okay";
1971 };
1972 };
1973
1974 clocks {
1975 compatible = "simple-bus";
1976 #address-cells = <1>;
1977 #size-cells = <0>;
1978
1979 clk32k_in: clock@0 {
1980 compatible = "fixed-clock";
1981 reg = <0>;
1982 #clock-cells = <0>;
1983 clock-frequency = <32768>;
1984 };
1985 };
1986
1987 cpus {
1988 cpu@0 {
1989 vdd-cpu-supply = <&vdd_cpu>;
1990 };
1991 };
1992
1993 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
1994 compatible = "regulator-fixed";
1995 regulator-name = "+V1.05_AVDD_HDMI_PLL";
1996 regulator-min-microvolt = <1050000>;
1997 regulator-max-microvolt = <1050000>;
1998 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1999 vin-supply = <&vdd_1v05>;
2000 };
2001
2002 reg_3v3_mxm: regulator-3v3-mxm {
2003 compatible = "regulator-fixed";
2004 regulator-name = "+V3.3_MXM";
2005 regulator-min-microvolt = <3300000>;
2006 regulator-max-microvolt = <3300000>;
2007 regulator-always-on;
2008 regulator-boot-on;
2009 };
2010
2011 reg_3v3: regulator-3v3 {
2012 compatible = "regulator-fixed";
2013 regulator-name = "+V3.3";
2014 regulator-min-microvolt = <3300000>;
2015 regulator-max-microvolt = <3300000>;
2016 regulator-always-on;
2017 regulator-boot-on;
2018 /* PWR_EN_+V3.3 */
2019 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
2020 enable-active-high;
2021 vin-supply = <&reg_3v3_mxm>;
2022 };
2023
2024 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
2025 compatible = "regulator-fixed";
2026 regulator-name = "+V3.3_AVDD_HDMI";
2027 regulator-min-microvolt = <3300000>;
2028 regulator-max-microvolt = <3300000>;
2029 vin-supply = <&vdd_1v05>;
2030 };
2031
2032 sound {
2033 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
2034 "nvidia,tegra-audio-sgtl5000";
2035 nvidia,model = "Toradex Apalis TK1";
2036 nvidia,audio-routing =
2037 "Headphone Jack", "HP_OUT",
2038 "LINE_IN", "Line In Jack",
2039 "MIC_IN", "Mic Jack";
2040 nvidia,i2s-controller = <&tegra_i2s2>;
2041 nvidia,audio-codec = <&sgtl5000>;
2042 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2043 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2044 <&tegra_car TEGRA124_CLK_EXTERN1>;
2045 clock-names = "pll_a", "pll_a_out0", "mclk";
2046 };
2047
2048 thermal-zones {
2049 cpu {
2050 trips {
2051 trip@0 {
2052 temperature = <101000>;
2053 hysteresis = <0>;
2054 type = "critical";
2055 };
2056 };
2057
2058 cooling-maps {
2059 /*
2060 * There are currently no cooling maps because
2061 * there are no cooling devices
2062 */
2063 };
2064 };
2065
2066 mem {
2067 trips {
2068 trip@0 {
2069 temperature = <101000>;
2070 hysteresis = <0>;
2071 type = "critical";
2072 };
2073 };
2074
2075 cooling-maps {
2076 /*
2077 * There are currently no cooling maps because
2078 * there are no cooling devices
2079 */
2080 };
2081 };
2082
2083 gpu {
2084 trips {
2085 trip@0 {
2086 temperature = <101000>;
2087 hysteresis = <0>;
2088 type = "critical";
2089 };
2090 };
2091
2092 cooling-maps {
2093 /*
2094 * There are currently no cooling maps because
2095 * there are no cooling devices
2096 */
2097 };
2098 };
2099 };
2100};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
index 2c5cede686dc..accb7055165a 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
@@ -1,5 +1,5 @@
1/ { 1/ {
2 clock@0,60006000 { 2 clock@60006000 {
3 emc-timings-3 { 3 emc-timings-3 {
4 nvidia,ram-code = <3>; 4 nvidia,ram-code = <3>;
5 5
@@ -78,7 +78,7 @@
78 }; 78 };
79 }; 79 };
80 80
81 emc@0,7001b000 { 81 emc@7001b000 {
82 emc-timings-3 { 82 emc-timings-3 {
83 nvidia,ram-code = <3>; 83 nvidia,ram-code = <3>;
84 84
@@ -2101,7 +2101,7 @@
2101 }; 2101 };
2102 }; 2102 };
2103 2103
2104 memory-controller@0,70019000 { 2104 memory-controller@70019000 {
2105 emc-timings-3 { 2105 emc-timings-3 {
2106 nvidia,ram-code = <3>; 2106 nvidia,ram-code = <3>;
2107 2107
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 941f36263c8f..e52b82449a79 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -10,8 +10,8 @@
10 compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; 10 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
11 11
12 aliases { 12 aliases {
13 rtc0 = "/i2c@0,7000d000/pmic@40"; 13 rtc0 = "/i2c@7000d000/pmic@40";
14 rtc1 = "/rtc@0,7000e000"; 14 rtc1 = "/rtc@7000e000";
15 15
16 /* This order keeps the mapping DB9 connector <-> ttyS0 */ 16 /* This order keeps the mapping DB9 connector <-> ttyS0 */
17 serial0 = &uartd; 17 serial0 = &uartd;
@@ -27,7 +27,7 @@
27 reg = <0x0 0x80000000 0x0 0x80000000>; 27 reg = <0x0 0x80000000 0x0 0x80000000>;
28 }; 28 };
29 29
30 pcie-controller@0,01003000 { 30 pcie-controller@01003000 {
31 status = "okay"; 31 status = "okay";
32 32
33 avddio-pex-supply = <&vdd_1v05_run>; 33 avddio-pex-supply = <&vdd_1v05_run>;
@@ -40,21 +40,21 @@
40 40
41 /* Mini PCIe */ 41 /* Mini PCIe */
42 pci@1,0 { 42 pci@1,0 {
43 phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-4}>; 43 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
44 phy-names = "pcie-0"; 44 phy-names = "pcie-0";
45 status = "okay"; 45 status = "okay";
46 }; 46 };
47 47
48 /* Gigabit Ethernet */ 48 /* Gigabit Ethernet */
49 pci@2,0 { 49 pci@2,0 {
50 phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-2}>; 50 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
51 phy-names = "pcie-0"; 51 phy-names = "pcie-0";
52 status = "okay"; 52 status = "okay";
53 }; 53 };
54 }; 54 };
55 55
56 host1x@0,50000000 { 56 host1x@50000000 {
57 hdmi@0,54280000 { 57 hdmi@54280000 {
58 status = "okay"; 58 status = "okay";
59 59
60 hdmi-supply = <&vdd_5v0_hdmi>; 60 hdmi-supply = <&vdd_5v0_hdmi>;
@@ -75,7 +75,7 @@
75 vdd-supply = <&vdd_gpu>; 75 vdd-supply = <&vdd_gpu>;
76 }; 76 };
77 77
78 pinmux: pinmux@0,70000868 { 78 pinmux: pinmux@70000868 {
79 pinctrl-names = "boot"; 79 pinctrl-names = "boot";
80 pinctrl-0 = <&state_boot>; 80 pinctrl-0 = <&state_boot>;
81 81
@@ -1356,14 +1356,6 @@
1356 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1356 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1357 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1357 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1358 }; 1358 };
1359 owr {
1360 nvidia,pins = "owr";
1361 nvidia,function = "rsvd2";
1362 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1363 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1364 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1365 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
1366 };
1367 clk_32k_in { 1359 clk_32k_in {
1368 nvidia,pins = "clk_32k_in"; 1360 nvidia,pins = "clk_32k_in";
1369 nvidia,function = "clk"; 1361 nvidia,function = "clk";
@@ -1378,6 +1370,10 @@
1378 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1370 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1379 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1371 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1380 }; 1372 };
1373 dsi_b {
1374 nvidia,pins = "mipi_pad_ctrl_dsi_b";
1375 nvidia,function = "dsi_b";
1376 };
1381 }; 1377 };
1382 }; 1378 };
1383 1379
@@ -1404,12 +1400,12 @@
1404 }; 1400 };
1405 1401
1406 /* DB9 serial port */ 1402 /* DB9 serial port */
1407 serial@0,70006300 { 1403 serial@70006300 {
1408 status = "okay"; 1404 status = "okay";
1409 }; 1405 };
1410 1406
1411 /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ 1407 /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
1412 i2c@0,7000c000 { 1408 i2c@7000c000 {
1413 status = "okay"; 1409 status = "okay";
1414 clock-frequency = <100000>; 1410 clock-frequency = <100000>;
1415 1411
@@ -1437,25 +1433,25 @@
1437 }; 1433 };
1438 1434
1439 /* Expansion GEN2_I2C_* */ 1435 /* Expansion GEN2_I2C_* */
1440 i2c@0,7000c400 { 1436 i2c@7000c400 {
1441 status = "okay"; 1437 status = "okay";
1442 clock-frequency = <100000>; 1438 clock-frequency = <100000>;
1443 }; 1439 };
1444 1440
1445 /* Expansion CAM_I2C_* */ 1441 /* Expansion CAM_I2C_* */
1446 i2c@0,7000c500 { 1442 i2c@7000c500 {
1447 status = "okay"; 1443 status = "okay";
1448 clock-frequency = <100000>; 1444 clock-frequency = <100000>;
1449 }; 1445 };
1450 1446
1451 /* HDMI DDC */ 1447 /* HDMI DDC */
1452 hdmi_ddc: i2c@0,7000c700 { 1448 hdmi_ddc: i2c@7000c700 {
1453 status = "okay"; 1449 status = "okay";
1454 clock-frequency = <100000>; 1450 clock-frequency = <100000>;
1455 }; 1451 };
1456 1452
1457 /* Expansion PWR_I2C_*, on-board components */ 1453 /* Expansion PWR_I2C_*, on-board components */
1458 i2c@0,7000d000 { 1454 i2c@7000d000 {
1459 status = "okay"; 1455 status = "okay";
1460 clock-frequency = <400000>; 1456 clock-frequency = <400000>;
1461 1457
@@ -1646,12 +1642,12 @@
1646 }; 1642 };
1647 1643
1648 /* Expansion TS_SPI_* */ 1644 /* Expansion TS_SPI_* */
1649 spi@0,7000d400 { 1645 spi@7000d400 {
1650 status = "okay"; 1646 status = "okay";
1651 }; 1647 };
1652 1648
1653 /* Internal SPI */ 1649 /* Internal SPI */
1654 spi@0,7000da00 { 1650 spi@7000da00 {
1655 status = "okay"; 1651 status = "okay";
1656 spi-max-frequency = <25000000>; 1652 spi-max-frequency = <25000000>;
1657 spi-flash@0 { 1653 spi-flash@0 {
@@ -1661,7 +1657,7 @@
1661 }; 1657 };
1662 }; 1658 };
1663 1659
1664 pmc@0,7000e400 { 1660 pmc@7000e400 {
1665 nvidia,invert-interrupt; 1661 nvidia,invert-interrupt;
1666 nvidia,suspend-mode = <1>; 1662 nvidia,suspend-mode = <1>;
1667 nvidia,cpu-pwr-good-time = <500>; 1663 nvidia,cpu-pwr-good-time = <500>;
@@ -1680,10 +1676,10 @@
1680 }; 1676 };
1681 1677
1682 /* Serial ATA */ 1678 /* Serial ATA */
1683 sata@0,70020000 { 1679 sata@70020000 {
1684 status = "okay"; 1680 status = "okay";
1685 1681
1686 phys = <&{/padctl@0,7009f000/pads/sata/lanes/sata-0}>; 1682 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1687 phy-names = "sata-0"; 1683 phy-names = "sata-0";
1688 1684
1689 hvdd-supply = <&vdd_3v3_lp0>; 1685 hvdd-supply = <&vdd_3v3_lp0>;
@@ -1694,15 +1690,15 @@
1694 target-12v-supply = <&vdd_12v0_sata>; 1690 target-12v-supply = <&vdd_12v0_sata>;
1695 }; 1691 };
1696 1692
1697 hda@0,70030000 { 1693 hda@70030000 {
1698 status = "okay"; 1694 status = "okay";
1699 }; 1695 };
1700 1696
1701 usb@0,70090000 { 1697 usb@70090000 {
1702 phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ 1698 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
1703 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ 1699 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
1704 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ 1700 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
1705 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ 1701 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
1706 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; 1702 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
1707 1703
1708 avddio-pex-supply = <&vdd_1v05_run>; 1704 avddio-pex-supply = <&vdd_1v05_run>;
@@ -1717,7 +1713,7 @@
1717 status = "okay"; 1713 status = "okay";
1718 }; 1714 };
1719 1715
1720 padctl@0,7009f000 { 1716 padctl@7009f000 {
1721 status = "okay"; 1717 status = "okay";
1722 1718
1723 pads { 1719 pads {
@@ -1804,7 +1800,7 @@
1804 }; 1800 };
1805 1801
1806 /* SD card */ 1802 /* SD card */
1807 sdhci@0,700b0400 { 1803 sdhci@700b0400 {
1808 status = "okay"; 1804 status = "okay";
1809 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 1805 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
1810 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 1806 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
@@ -1814,40 +1810,40 @@
1814 }; 1810 };
1815 1811
1816 /* eMMC */ 1812 /* eMMC */
1817 sdhci@0,700b0600 { 1813 sdhci@700b0600 {
1818 status = "okay"; 1814 status = "okay";
1819 bus-width = <8>; 1815 bus-width = <8>;
1820 non-removable; 1816 non-removable;
1821 }; 1817 };
1822 1818
1823 /* CPU DFLL clock */ 1819 /* CPU DFLL clock */
1824 clock@0,70110000 { 1820 clock@70110000 {
1825 status = "okay"; 1821 status = "okay";
1826 vdd-cpu-supply = <&vdd_cpu>; 1822 vdd-cpu-supply = <&vdd_cpu>;
1827 nvidia,i2c-fs-rate = <400000>; 1823 nvidia,i2c-fs-rate = <400000>;
1828 }; 1824 };
1829 1825
1830 ahub@0,70300000 { 1826 ahub@70300000 {
1831 i2s@0,70301100 { 1827 i2s@70301100 {
1832 status = "okay"; 1828 status = "okay";
1833 }; 1829 };
1834 }; 1830 };
1835 1831
1836 /* mini-PCIe USB */ 1832 /* mini-PCIe USB */
1837 usb@0,7d004000 { 1833 usb@7d004000 {
1838 status = "okay"; 1834 status = "okay";
1839 }; 1835 };
1840 1836
1841 usb-phy@0,7d004000 { 1837 usb-phy@7d004000 {
1842 status = "okay"; 1838 status = "okay";
1843 }; 1839 };
1844 1840
1845 /* USB A connector */ 1841 /* USB A connector */
1846 usb@0,7d008000 { 1842 usb@7d008000 {
1847 status = "okay"; 1843 status = "okay";
1848 }; 1844 };
1849 1845
1850 usb-phy@0,7d008000 { 1846 usb-phy@7d008000 {
1851 status = "okay"; 1847 status = "okay";
1852 vbus-supply = <&vdd_usb3_vbus>; 1848 vbus-supply = <&vdd_usb3_vbus>;
1853 }; 1849 };
@@ -2049,7 +2045,7 @@
2049 thermal-zones { 2045 thermal-zones {
2050 cpu { 2046 cpu {
2051 trips { 2047 trips {
2052 trip@0 { 2048 trip {
2053 temperature = <101000>; 2049 temperature = <101000>;
2054 hysteresis = <0>; 2050 hysteresis = <0>;
2055 type = "critical"; 2051 type = "critical";
@@ -2063,7 +2059,7 @@
2063 2059
2064 mem { 2060 mem {
2065 trips { 2061 trips {
2066 trip@0 { 2062 trip {
2067 temperature = <101000>; 2063 temperature = <101000>;
2068 hysteresis = <0>; 2064 hysteresis = <0>;
2069 type = "critical"; 2065 type = "critical";
@@ -2077,7 +2073,7 @@
2077 2073
2078 gpu { 2074 gpu {
2079 trips { 2075 trips {
2080 trip@0 { 2076 trip {
2081 temperature = <101000>; 2077 temperature = <101000>;
2082 hysteresis = <0>; 2078 hysteresis = <0>;
2083 type = "critical"; 2079 type = "critical";
diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
index 1a5748d05dda..4458e86b2769 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
@@ -1,5 +1,5 @@
1/ { 1/ {
2 clock@0,60006000 { 2 clock@60006000 {
3 emc-timings-1 { 3 emc-timings-1 {
4 nvidia,ram-code = <1>; 4 nvidia,ram-code = <1>;
5 5
@@ -67,7 +67,7 @@
67 }; 67 };
68 }; 68 };
69 69
70 emc@0,7001b000 { 70 emc@7001b000 {
71 emc-timings-1 { 71 emc-timings-1 {
72 nvidia,ram-code = <1>; 72 nvidia,ram-code = <1>;
73 73
@@ -1754,7 +1754,7 @@
1754 }; 1754 };
1755 }; 1755 };
1756 1756
1757 memory-controller@0,70019000 { 1757 memory-controller@70019000 {
1758 emc-timings-1 { 1758 emc-timings-1 {
1759 nvidia,ram-code = <1>; 1759 nvidia,ram-code = <1>;
1760 1760
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
index 2d21253ea4e3..67d7cfb32541 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -15,7 +15,7 @@
15 ddc-i2c-bus = <&dpaux>; 15 ddc-i2c-bus = <&dpaux>;
16 }; 16 };
17 17
18 sdhci@0,700b0400 { /* SD Card on this bus */ 18 sdhci@700b0400 { /* SD Card on this bus */
19 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; 19 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
20 }; 20 };
21 21
@@ -26,7 +26,7 @@
26 nvidia,model = "GoogleNyanBig"; 26 nvidia,model = "GoogleNyanBig";
27 }; 27 };
28 28
29 pinmux@0,70000868 { 29 pinmux@70000868 {
30 pinctrl-names = "default"; 30 pinctrl-names = "default";
31 pinctrl-0 = <&pinmux_default>; 31 pinctrl-0 = <&pinmux_default>;
32 32
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
index 9ecd108f56cf..4e7b59e25728 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
@@ -1,5 +1,5 @@
1/ { 1/ {
2 clock@0,60006000 { 2 clock@60006000 {
3 emc-timings-1 { 3 emc-timings-1 {
4 nvidia,ram-code = <1>; 4 nvidia,ram-code = <1>;
5 5
@@ -67,7 +67,7 @@
67 }; 67 };
68 }; 68 };
69 69
70 emc@0,7001b000 { 70 emc@7001b000 {
71 emc-timings-1 { 71 emc-timings-1 {
72 nvidia,ram-code = <1>; 72 nvidia,ram-code = <1>;
73 73
@@ -1754,7 +1754,7 @@
1754 }; 1754 };
1755 }; 1755 };
1756 1756
1757 memory-controller@0,70019000 { 1757 memory-controller@70019000 {
1758 emc-timings-1 { 1758 emc-timings-1 {
1759 nvidia,ram-code = <1>; 1759 nvidia,ram-code = <1>;
1760 1760
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
index 0d30c514ffad..c9582361c26e 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
@@ -22,7 +22,7 @@
22 nvidia,model = "GoogleNyanBlaze"; 22 nvidia,model = "GoogleNyanBlaze";
23 }; 23 };
24 24
25 pinmux@0,70000868 { 25 pinmux@70000868 {
26 pinctrl-names = "default"; 26 pinctrl-names = "default";
27 pinctrl-0 = <&pinmux_default>; 27 pinctrl-0 = <&pinmux_default>;
28 28
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index 0710a600cc69..271505e0715f 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -3,8 +3,8 @@
3 3
4/ { 4/ {
5 aliases { 5 aliases {
6 rtc0 = "/i2c@0,7000d000/pmic@40"; 6 rtc0 = "/i2c@7000d000/pmic@40";
7 rtc1 = "/rtc@0,7000e000"; 7 rtc1 = "/rtc@7000e000";
8 serial0 = &uarta; 8 serial0 = &uarta;
9 }; 9 };
10 10
@@ -16,8 +16,8 @@
16 reg = <0x0 0x80000000 0x0 0x80000000>; 16 reg = <0x0 0x80000000 0x0 0x80000000>;
17 }; 17 };
18 18
19 host1x@0,50000000 { 19 host1x@50000000 {
20 hdmi@0,54280000 { 20 hdmi@54280000 {
21 status = "okay"; 21 status = "okay";
22 22
23 vdd-supply = <&vdd_3v3_hdmi>; 23 vdd-supply = <&vdd_3v3_hdmi>;
@@ -29,29 +29,29 @@
29 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 29 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
30 }; 30 };
31 31
32 sor@0,54540000 { 32 sor@54540000 {
33 status = "okay"; 33 status = "okay";
34 34
35 nvidia,dpaux = <&dpaux>; 35 nvidia,dpaux = <&dpaux>;
36 nvidia,panel = <&panel>; 36 nvidia,panel = <&panel>;
37 }; 37 };
38 38
39 dpaux@0,545c0000 { 39 dpaux@545c0000 {
40 vdd-supply = <&vdd_3v3_panel>; 40 vdd-supply = <&vdd_3v3_panel>;
41 status = "okay"; 41 status = "okay";
42 }; 42 };
43 }; 43 };
44 44
45 serial@0,70006000 { 45 serial@70006000 {
46 /* Debug connector on the bottom of the board near SD card. */ 46 /* Debug connector on the bottom of the board near SD card. */
47 status = "okay"; 47 status = "okay";
48 }; 48 };
49 49
50 pwm@0,7000a000 { 50 pwm@7000a000 {
51 status = "okay"; 51 status = "okay";
52 }; 52 };
53 53
54 i2c@0,7000c000 { 54 i2c@7000c000 {
55 status = "okay"; 55 status = "okay";
56 clock-frequency = <100000>; 56 clock-frequency = <100000>;
57 57
@@ -72,7 +72,7 @@
72 }; 72 };
73 }; 73 };
74 74
75 i2c@0,7000c400 { 75 i2c@7000c400 {
76 status = "okay"; 76 status = "okay";
77 clock-frequency = <100000>; 77 clock-frequency = <100000>;
78 78
@@ -85,7 +85,7 @@
85 }; 85 };
86 }; 86 };
87 87
88 i2c@0,7000c500 { 88 i2c@7000c500 {
89 status = "okay"; 89 status = "okay";
90 clock-frequency = <400000>; 90 clock-frequency = <400000>;
91 91
@@ -95,12 +95,12 @@
95 }; 95 };
96 }; 96 };
97 97
98 hdmi_ddc: i2c@0,7000c700 { 98 hdmi_ddc: i2c@7000c700 {
99 status = "okay"; 99 status = "okay";
100 clock-frequency = <100000>; 100 clock-frequency = <100000>;
101 }; 101 };
102 102
103 i2c@0,7000d000 { 103 i2c@7000d000 {
104 status = "okay"; 104 status = "okay";
105 clock-frequency = <400000>; 105 clock-frequency = <400000>;
106 106
@@ -301,7 +301,7 @@
301 }; 301 };
302 }; 302 };
303 303
304 spi@0,7000d400 { 304 spi@7000d400 {
305 status = "okay"; 305 status = "okay";
306 306
307 cros_ec: cros-ec@0 { 307 cros_ec: cros-ec@0 {
@@ -342,7 +342,7 @@
342 }; 342 };
343 }; 343 };
344 344
345 spi@0,7000da00 { 345 spi@7000da00 {
346 status = "okay"; 346 status = "okay";
347 spi-max-frequency = <25000000>; 347 spi-max-frequency = <25000000>;
348 348
@@ -353,7 +353,7 @@
353 }; 353 };
354 }; 354 };
355 355
356 pmc@0,7000e400 { 356 pmc@7000e400 {
357 nvidia,invert-interrupt; 357 nvidia,invert-interrupt;
358 nvidia,suspend-mode = <0>; 358 nvidia,suspend-mode = <0>;
359 nvidia,cpu-pwr-good-time = <500>; 359 nvidia,cpu-pwr-good-time = <500>;
@@ -364,16 +364,16 @@
364 nvidia,sys-clock-req-active-high; 364 nvidia,sys-clock-req-active-high;
365 }; 365 };
366 366
367 hda@0,70030000 { 367 hda@70030000 {
368 status = "okay"; 368 status = "okay";
369 }; 369 };
370 370
371 usb@0,70090000 { 371 usb@70090000 {
372 phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ 372 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
373 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ 373 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
374 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ 374 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
375 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ 375 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
376 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ 376 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
377 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; 377 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
378 378
379 avddio-pex-supply = <&vdd_1v05_run>; 379 avddio-pex-supply = <&vdd_1v05_run>;
@@ -388,7 +388,7 @@
388 status = "okay"; 388 status = "okay";
389 }; 389 };
390 390
391 padctl@0,7009f000 { 391 padctl@7009f000 {
392 status = "okay"; 392 status = "okay";
393 393
394 pads { 394 pads {
@@ -467,7 +467,7 @@
467 reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; 467 reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
468 }; 468 };
469 469
470 sdhci@0,700b0000 { /* WiFi/BT on this bus */ 470 sdhci@700b0000 { /* WiFi/BT on this bus */
471 status = "okay"; 471 status = "okay";
472 bus-width = <4>; 472 bus-width = <4>;
473 no-1-8-v; 473 no-1-8-v;
@@ -478,7 +478,7 @@
478 keep-power-in-suspend; 478 keep-power-in-suspend;
479 }; 479 };
480 480
481 sdhci@0,700b0400 { /* SD Card on this bus */ 481 sdhci@700b0400 { /* SD Card on this bus */
482 status = "okay"; 482 status = "okay";
483 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 483 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
484 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 484 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
@@ -487,7 +487,7 @@
487 vqmmc-supply = <&vddio_sdmmc3>; 487 vqmmc-supply = <&vddio_sdmmc3>;
488 }; 488 };
489 489
490 sdhci@0,700b0600 { /* eMMC on this bus */ 490 sdhci@700b0600 { /* eMMC on this bus */
491 status = "okay"; 491 status = "okay";
492 bus-width = <8>; 492 bus-width = <8>;
493 no-1-8-v; 493 no-1-8-v;
@@ -495,14 +495,14 @@
495 }; 495 };
496 496
497 /* CPU DFLL clock */ 497 /* CPU DFLL clock */
498 clock@0,70110000 { 498 clock@70110000 {
499 status = "disabled"; 499 status = "disabled";
500 vdd-cpu-supply = <&vdd_cpu>; 500 vdd-cpu-supply = <&vdd_cpu>;
501 nvidia,i2c-fs-rate = <400000>; 501 nvidia,i2c-fs-rate = <400000>;
502 }; 502 };
503 503
504 ahub@0,70300000 { 504 ahub@70300000 {
505 i2s@0,70301100 { 505 i2s@70301100 {
506 status = "okay"; 506 status = "okay";
507 }; 507 };
508 }; 508 };
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 973446d07182..6e59cec0962b 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -8,8 +8,8 @@
8 compatible = "nvidia,venice2", "nvidia,tegra124"; 8 compatible = "nvidia,venice2", "nvidia,tegra124";
9 9
10 aliases { 10 aliases {
11 rtc0 = "/i2c@0,7000d000/pmic@40"; 11 rtc0 = "/i2c@7000d000/pmic@40";
12 rtc1 = "/rtc@0,7000e000"; 12 rtc1 = "/rtc@7000e000";
13 serial0 = &uarta; 13 serial0 = &uarta;
14 }; 14 };
15 15
@@ -21,8 +21,8 @@
21 reg = <0x0 0x80000000 0x0 0x80000000>; 21 reg = <0x0 0x80000000 0x0 0x80000000>;
22 }; 22 };
23 23
24 host1x@0,50000000 { 24 host1x@50000000 {
25 hdmi@0,54280000 { 25 hdmi@54280000 {
26 status = "okay"; 26 status = "okay";
27 27
28 vdd-supply = <&vdd_3v3_hdmi>; 28 vdd-supply = <&vdd_3v3_hdmi>;
@@ -34,14 +34,14 @@
34 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 34 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
35 }; 35 };
36 36
37 sor@0,54540000 { 37 sor@54540000 {
38 status = "okay"; 38 status = "okay";
39 39
40 nvidia,dpaux = <&dpaux>; 40 nvidia,dpaux = <&dpaux>;
41 nvidia,panel = <&panel>; 41 nvidia,panel = <&panel>;
42 }; 42 };
43 43
44 dpaux@0,545c0000 { 44 dpaux@545c0000 {
45 vdd-supply = <&vdd_3v3_panel>; 45 vdd-supply = <&vdd_3v3_panel>;
46 status = "okay"; 46 status = "okay";
47 }; 47 };
@@ -55,7 +55,7 @@
55 vdd-supply = <&vdd_gpu>; 55 vdd-supply = <&vdd_gpu>;
56 }; 56 };
57 57
58 pinmux: pinmux@0,70000868 { 58 pinmux: pinmux@70000868 {
59 pinctrl-names = "boot"; 59 pinctrl-names = "boot";
60 pinctrl-0 = <&pinmux_boot>; 60 pinctrl-0 = <&pinmux_boot>;
61 61
@@ -596,15 +596,15 @@
596 }; 596 };
597 }; 597 };
598 598
599 serial@0,70006000 { 599 serial@70006000 {
600 status = "okay"; 600 status = "okay";
601 }; 601 };
602 602
603 pwm@0,7000a000 { 603 pwm@7000a000 {
604 status = "okay"; 604 status = "okay";
605 }; 605 };
606 606
607 i2c@0,7000c000 { 607 i2c@7000c000 {
608 status = "okay"; 608 status = "okay";
609 clock-frequency = <100000>; 609 clock-frequency = <100000>;
610 610
@@ -616,7 +616,7 @@
616 }; 616 };
617 }; 617 };
618 618
619 i2c@0,7000c400 { 619 i2c@7000c400 {
620 status = "okay"; 620 status = "okay";
621 clock-frequency = <100000>; 621 clock-frequency = <100000>;
622 622
@@ -629,17 +629,17 @@
629 }; 629 };
630 }; 630 };
631 631
632 i2c@0,7000c500 { 632 i2c@7000c500 {
633 status = "okay"; 633 status = "okay";
634 clock-frequency = <100000>; 634 clock-frequency = <100000>;
635 }; 635 };
636 636
637 hdmi_ddc: i2c@0,7000c700 { 637 hdmi_ddc: i2c@7000c700 {
638 status = "okay"; 638 status = "okay";
639 clock-frequency = <100000>; 639 clock-frequency = <100000>;
640 }; 640 };
641 641
642 i2c@0,7000d000 { 642 i2c@7000d000 {
643 status = "okay"; 643 status = "okay";
644 clock-frequency = <400000>; 644 clock-frequency = <400000>;
645 645
@@ -834,7 +834,7 @@
834 }; 834 };
835 }; 835 };
836 836
837 spi@0,7000d400 { 837 spi@7000d400 {
838 status = "okay"; 838 status = "okay";
839 839
840 cros_ec: cros-ec@0 { 840 cros_ec: cros-ec@0 {
@@ -874,7 +874,7 @@
874 }; 874 };
875 }; 875 };
876 876
877 spi@0,7000da00 { 877 spi@7000da00 {
878 status = "okay"; 878 status = "okay";
879 spi-max-frequency = <25000000>; 879 spi-max-frequency = <25000000>;
880 spi-flash@0 { 880 spi-flash@0 {
@@ -884,7 +884,7 @@
884 }; 884 };
885 }; 885 };
886 886
887 pmc@0,7000e400 { 887 pmc@7000e400 {
888 nvidia,invert-interrupt; 888 nvidia,invert-interrupt;
889 nvidia,suspend-mode = <1>; 889 nvidia,suspend-mode = <1>;
890 nvidia,cpu-pwr-good-time = <500>; 890 nvidia,cpu-pwr-good-time = <500>;
@@ -895,16 +895,16 @@
895 nvidia,sys-clock-req-active-high; 895 nvidia,sys-clock-req-active-high;
896 }; 896 };
897 897
898 hda@0,70030000 { 898 hda@70030000 {
899 status = "okay"; 899 status = "okay";
900 }; 900 };
901 901
902 usb@0,70090000 { 902 usb@70090000 {
903 phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ 903 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
904 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ 904 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
905 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ 905 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
906 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ 906 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
907 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ 907 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
908 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; 908 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
909 909
910 avddio-pex-supply = <&vdd_1v05_run>; 910 avddio-pex-supply = <&vdd_1v05_run>;
@@ -919,7 +919,7 @@
919 status = "okay"; 919 status = "okay";
920 }; 920 };
921 921
922 padctl@0,7009f000 { 922 padctl@7009f000 {
923 pads { 923 pads {
924 usb2 { 924 usb2 {
925 status = "okay"; 925 status = "okay";
@@ -998,7 +998,7 @@
998 }; 998 };
999 }; 999 };
1000 1000
1001 sdhci@0,700b0400 { 1001 sdhci@700b0400 {
1002 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 1002 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
1003 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 1003 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
1004 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; 1004 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
@@ -1007,41 +1007,41 @@
1007 vqmmc-supply = <&vddio_sdmmc3>; 1007 vqmmc-supply = <&vddio_sdmmc3>;
1008 }; 1008 };
1009 1009
1010 sdhci@0,700b0600 { 1010 sdhci@700b0600 {
1011 status = "okay"; 1011 status = "okay";
1012 bus-width = <8>; 1012 bus-width = <8>;
1013 non-removable; 1013 non-removable;
1014 }; 1014 };
1015 1015
1016 ahub@0,70300000 { 1016 ahub@70300000 {
1017 i2s@0,70301100 { 1017 i2s@70301100 {
1018 status = "okay"; 1018 status = "okay";
1019 }; 1019 };
1020 }; 1020 };
1021 1021
1022 usb@0,7d000000 { 1022 usb@7d000000 {
1023 status = "okay"; 1023 status = "okay";
1024 }; 1024 };
1025 1025
1026 usb-phy@0,7d000000 { 1026 usb-phy@7d000000 {
1027 status = "okay"; 1027 status = "okay";
1028 vbus-supply = <&vdd_usb1_vbus>; 1028 vbus-supply = <&vdd_usb1_vbus>;
1029 }; 1029 };
1030 1030
1031 usb@0,7d004000 { 1031 usb@7d004000 {
1032 status = "okay"; 1032 status = "okay";
1033 }; 1033 };
1034 1034
1035 usb-phy@0,7d004000 { 1035 usb-phy@7d004000 {
1036 status = "okay"; 1036 status = "okay";
1037 vbus-supply = <&vdd_run_cam>; 1037 vbus-supply = <&vdd_run_cam>;
1038 }; 1038 };
1039 1039
1040 usb@0,7d008000 { 1040 usb@7d008000 {
1041 status = "okay"; 1041 status = "okay";
1042 }; 1042 };
1043 1043
1044 usb-phy@0,7d008000 { 1044 usb-phy@7d008000 {
1045 status = "okay"; 1045 status = "okay";
1046 vbus-supply = <&vdd_usb3_vbus>; 1046 vbus-supply = <&vdd_usb3_vbus>;
1047 }; 1047 };
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index ea4811870de2..ea340f9de448 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -14,7 +14,7 @@
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 pcie-controller@0,01003000 { 17 pcie-controller@01003000 {
18 compatible = "nvidia,tegra124-pcie"; 18 compatible = "nvidia,tegra124-pcie";
19 device_type = "pci"; 19 device_type = "pci";
20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -77,7 +77,7 @@
77 }; 77 };
78 }; 78 };
79 79
80 host1x@0,50000000 { 80 host1x@50000000 {
81 compatible = "nvidia,tegra124-host1x", "simple-bus"; 81 compatible = "nvidia,tegra124-host1x", "simple-bus";
82 reg = <0x0 0x50000000 0x0 0x00034000>; 82 reg = <0x0 0x50000000 0x0 0x00034000>;
83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -91,7 +91,7 @@
91 91
92 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 92 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
93 93
94 dc@0,54200000 { 94 dc@54200000 {
95 compatible = "nvidia,tegra124-dc"; 95 compatible = "nvidia,tegra124-dc";
96 reg = <0x0 0x54200000 0x0 0x00040000>; 96 reg = <0x0 0x54200000 0x0 0x00040000>;
97 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 97 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
@@ -106,7 +106,7 @@
106 nvidia,head = <0>; 106 nvidia,head = <0>;
107 }; 107 };
108 108
109 dc@0,54240000 { 109 dc@54240000 {
110 compatible = "nvidia,tegra124-dc"; 110 compatible = "nvidia,tegra124-dc";
111 reg = <0x0 0x54240000 0x0 0x00040000>; 111 reg = <0x0 0x54240000 0x0 0x00040000>;
112 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 112 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
@@ -121,7 +121,7 @@
121 nvidia,head = <1>; 121 nvidia,head = <1>;
122 }; 122 };
123 123
124 hdmi@0,54280000 { 124 hdmi@54280000 {
125 compatible = "nvidia,tegra124-hdmi"; 125 compatible = "nvidia,tegra124-hdmi";
126 reg = <0x0 0x54280000 0x0 0x00040000>; 126 reg = <0x0 0x54280000 0x0 0x00040000>;
127 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 127 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -133,7 +133,7 @@
133 status = "disabled"; 133 status = "disabled";
134 }; 134 };
135 135
136 sor@0,54540000 { 136 sor@54540000 {
137 compatible = "nvidia,tegra124-sor"; 137 compatible = "nvidia,tegra124-sor";
138 reg = <0x0 0x54540000 0x0 0x00040000>; 138 reg = <0x0 0x54540000 0x0 0x00040000>;
139 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 139 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -147,7 +147,7 @@
147 status = "disabled"; 147 status = "disabled";
148 }; 148 };
149 149
150 dpaux: dpaux@0,545c0000 { 150 dpaux: dpaux@545c0000 {
151 compatible = "nvidia,tegra124-dpaux"; 151 compatible = "nvidia,tegra124-dpaux";
152 reg = <0x0 0x545c0000 0x0 0x00040000>; 152 reg = <0x0 0x545c0000 0x0 0x00040000>;
153 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 153 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
@@ -160,7 +160,7 @@
160 }; 160 };
161 }; 161 };
162 162
163 gic: interrupt-controller@0,50041000 { 163 gic: interrupt-controller@50041000 {
164 compatible = "arm,cortex-a15-gic"; 164 compatible = "arm,cortex-a15-gic";
165 #interrupt-cells = <3>; 165 #interrupt-cells = <3>;
166 interrupt-controller; 166 interrupt-controller;
@@ -173,6 +173,11 @@
173 interrupt-parent = <&gic>; 173 interrupt-parent = <&gic>;
174 }; 174 };
175 175
176 /*
177 * Please keep the following 0, notation in place as a former mainline
178 * U-Boot version was looking for that particular notation in order to
179 * perform required fix-ups on that GPU node.
180 */
176 gpu@0,57000000 { 181 gpu@0,57000000 {
177 compatible = "nvidia,gk20a"; 182 compatible = "nvidia,gk20a";
178 reg = <0x0 0x57000000 0x0 0x01000000>, 183 reg = <0x0 0x57000000 0x0 0x01000000>,
@@ -203,7 +208,7 @@
203 interrupt-parent = <&gic>; 208 interrupt-parent = <&gic>;
204 }; 209 };
205 210
206 timer@0,60005000 { 211 timer@60005000 {
207 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 212 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
208 reg = <0x0 0x60005000 0x0 0x400>; 213 reg = <0x0 0x60005000 0x0 0x400>;
209 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 214 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -215,7 +220,7 @@
215 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 220 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
216 }; 221 };
217 222
218 tegra_car: clock@0,60006000 { 223 tegra_car: clock@60006000 {
219 compatible = "nvidia,tegra124-car"; 224 compatible = "nvidia,tegra124-car";
220 reg = <0x0 0x60006000 0x0 0x1000>; 225 reg = <0x0 0x60006000 0x0 0x1000>;
221 #clock-cells = <1>; 226 #clock-cells = <1>;
@@ -223,12 +228,12 @@
223 nvidia,external-memory-controller = <&emc>; 228 nvidia,external-memory-controller = <&emc>;
224 }; 229 };
225 230
226 flow-controller@0,60007000 { 231 flow-controller@60007000 {
227 compatible = "nvidia,tegra124-flowctrl"; 232 compatible = "nvidia,tegra124-flowctrl";
228 reg = <0x0 0x60007000 0x0 0x1000>; 233 reg = <0x0 0x60007000 0x0 0x1000>;
229 }; 234 };
230 235
231 actmon@0,6000c800 { 236 actmon@6000c800 {
232 compatible = "nvidia,tegra124-actmon"; 237 compatible = "nvidia,tegra124-actmon";
233 reg = <0x0 0x6000c800 0x0 0x400>; 238 reg = <0x0 0x6000c800 0x0 0x400>;
234 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 239 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -239,7 +244,7 @@
239 reset-names = "actmon"; 244 reset-names = "actmon";
240 }; 245 };
241 246
242 gpio: gpio@0,6000d000 { 247 gpio: gpio@6000d000 {
243 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 248 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
244 reg = <0x0 0x6000d000 0x0 0x1000>; 249 reg = <0x0 0x6000d000 0x0 0x1000>;
245 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -259,7 +264,7 @@
259 */ 264 */
260 }; 265 };
261 266
262 apbdma: dma@0,60020000 { 267 apbdma: dma@60020000 {
263 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 268 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
264 reg = <0x0 0x60020000 0x0 0x1400>; 269 reg = <0x0 0x60020000 0x0 0x1400>;
265 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -300,13 +305,13 @@
300 #dma-cells = <1>; 305 #dma-cells = <1>;
301 }; 306 };
302 307
303 apbmisc@0,70000800 { 308 apbmisc@70000800 {
304 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 309 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
305 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 310 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
306 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 311 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
307 }; 312 };
308 313
309 pinmux: pinmux@0,70000868 { 314 pinmux: pinmux@70000868 {
310 compatible = "nvidia,tegra124-pinmux"; 315 compatible = "nvidia,tegra124-pinmux";
311 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 316 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
312 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 317 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
@@ -321,7 +326,7 @@
321 * the APB DMA based serial driver, the compatible is 326 * the APB DMA based serial driver, the compatible is
322 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 327 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
323 */ 328 */
324 uarta: serial@0,70006000 { 329 uarta: serial@70006000 {
325 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
326 reg = <0x0 0x70006000 0x0 0x40>; 331 reg = <0x0 0x70006000 0x0 0x40>;
327 reg-shift = <2>; 332 reg-shift = <2>;
@@ -334,7 +339,7 @@
334 status = "disabled"; 339 status = "disabled";
335 }; 340 };
336 341
337 uartb: serial@0,70006040 { 342 uartb: serial@70006040 {
338 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 343 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
339 reg = <0x0 0x70006040 0x0 0x40>; 344 reg = <0x0 0x70006040 0x0 0x40>;
340 reg-shift = <2>; 345 reg-shift = <2>;
@@ -347,7 +352,7 @@
347 status = "disabled"; 352 status = "disabled";
348 }; 353 };
349 354
350 uartc: serial@0,70006200 { 355 uartc: serial@70006200 {
351 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 356 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
352 reg = <0x0 0x70006200 0x0 0x40>; 357 reg = <0x0 0x70006200 0x0 0x40>;
353 reg-shift = <2>; 358 reg-shift = <2>;
@@ -360,7 +365,7 @@
360 status = "disabled"; 365 status = "disabled";
361 }; 366 };
362 367
363 uartd: serial@0,70006300 { 368 uartd: serial@70006300 {
364 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 369 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
365 reg = <0x0 0x70006300 0x0 0x40>; 370 reg = <0x0 0x70006300 0x0 0x40>;
366 reg-shift = <2>; 371 reg-shift = <2>;
@@ -373,7 +378,7 @@
373 status = "disabled"; 378 status = "disabled";
374 }; 379 };
375 380
376 pwm: pwm@0,7000a000 { 381 pwm: pwm@7000a000 {
377 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 382 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
378 reg = <0x0 0x7000a000 0x0 0x100>; 383 reg = <0x0 0x7000a000 0x0 0x100>;
379 #pwm-cells = <2>; 384 #pwm-cells = <2>;
@@ -383,7 +388,7 @@
383 status = "disabled"; 388 status = "disabled";
384 }; 389 };
385 390
386 i2c@0,7000c000 { 391 i2c@7000c000 {
387 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 392 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
388 reg = <0x0 0x7000c000 0x0 0x100>; 393 reg = <0x0 0x7000c000 0x0 0x100>;
389 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 394 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -398,7 +403,7 @@
398 status = "disabled"; 403 status = "disabled";
399 }; 404 };
400 405
401 i2c@0,7000c400 { 406 i2c@7000c400 {
402 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 407 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
403 reg = <0x0 0x7000c400 0x0 0x100>; 408 reg = <0x0 0x7000c400 0x0 0x100>;
404 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 409 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -413,7 +418,7 @@
413 status = "disabled"; 418 status = "disabled";
414 }; 419 };
415 420
416 i2c@0,7000c500 { 421 i2c@7000c500 {
417 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 422 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
418 reg = <0x0 0x7000c500 0x0 0x100>; 423 reg = <0x0 0x7000c500 0x0 0x100>;
419 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 424 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -428,7 +433,7 @@
428 status = "disabled"; 433 status = "disabled";
429 }; 434 };
430 435
431 i2c@0,7000c700 { 436 i2c@7000c700 {
432 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 437 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
433 reg = <0x0 0x7000c700 0x0 0x100>; 438 reg = <0x0 0x7000c700 0x0 0x100>;
434 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 439 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
@@ -443,7 +448,7 @@
443 status = "disabled"; 448 status = "disabled";
444 }; 449 };
445 450
446 i2c@0,7000d000 { 451 i2c@7000d000 {
447 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 452 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
448 reg = <0x0 0x7000d000 0x0 0x100>; 453 reg = <0x0 0x7000d000 0x0 0x100>;
449 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 454 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -458,7 +463,7 @@
458 status = "disabled"; 463 status = "disabled";
459 }; 464 };
460 465
461 i2c@0,7000d100 { 466 i2c@7000d100 {
462 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 467 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
463 reg = <0x0 0x7000d100 0x0 0x100>; 468 reg = <0x0 0x7000d100 0x0 0x100>;
464 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 469 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
@@ -473,7 +478,7 @@
473 status = "disabled"; 478 status = "disabled";
474 }; 479 };
475 480
476 spi@0,7000d400 { 481 spi@7000d400 {
477 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 482 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
478 reg = <0x0 0x7000d400 0x0 0x200>; 483 reg = <0x0 0x7000d400 0x0 0x200>;
479 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 484 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
@@ -488,7 +493,7 @@
488 status = "disabled"; 493 status = "disabled";
489 }; 494 };
490 495
491 spi@0,7000d600 { 496 spi@7000d600 {
492 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 497 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
493 reg = <0x0 0x7000d600 0x0 0x200>; 498 reg = <0x0 0x7000d600 0x0 0x200>;
494 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 499 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -503,7 +508,7 @@
503 status = "disabled"; 508 status = "disabled";
504 }; 509 };
505 510
506 spi@0,7000d800 { 511 spi@7000d800 {
507 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 512 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
508 reg = <0x0 0x7000d800 0x0 0x200>; 513 reg = <0x0 0x7000d800 0x0 0x200>;
509 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 514 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -518,7 +523,7 @@
518 status = "disabled"; 523 status = "disabled";
519 }; 524 };
520 525
521 spi@0,7000da00 { 526 spi@7000da00 {
522 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 527 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
523 reg = <0x0 0x7000da00 0x0 0x200>; 528 reg = <0x0 0x7000da00 0x0 0x200>;
524 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 529 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
@@ -533,7 +538,7 @@
533 status = "disabled"; 538 status = "disabled";
534 }; 539 };
535 540
536 spi@0,7000dc00 { 541 spi@7000dc00 {
537 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 542 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
538 reg = <0x0 0x7000dc00 0x0 0x200>; 543 reg = <0x0 0x7000dc00 0x0 0x200>;
539 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 544 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
@@ -548,7 +553,7 @@
548 status = "disabled"; 553 status = "disabled";
549 }; 554 };
550 555
551 spi@0,7000de00 { 556 spi@7000de00 {
552 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 557 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
553 reg = <0x0 0x7000de00 0x0 0x200>; 558 reg = <0x0 0x7000de00 0x0 0x200>;
554 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 559 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
@@ -563,21 +568,21 @@
563 status = "disabled"; 568 status = "disabled";
564 }; 569 };
565 570
566 rtc@0,7000e000 { 571 rtc@7000e000 {
567 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 572 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
568 reg = <0x0 0x7000e000 0x0 0x100>; 573 reg = <0x0 0x7000e000 0x0 0x100>;
569 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 574 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&tegra_car TEGRA124_CLK_RTC>; 575 clocks = <&tegra_car TEGRA124_CLK_RTC>;
571 }; 576 };
572 577
573 pmc@0,7000e400 { 578 pmc@7000e400 {
574 compatible = "nvidia,tegra124-pmc"; 579 compatible = "nvidia,tegra124-pmc";
575 reg = <0x0 0x7000e400 0x0 0x400>; 580 reg = <0x0 0x7000e400 0x0 0x400>;
576 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 581 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
577 clock-names = "pclk", "clk32k_in"; 582 clock-names = "pclk", "clk32k_in";
578 }; 583 };
579 584
580 fuse@0,7000f800 { 585 fuse@7000f800 {
581 compatible = "nvidia,tegra124-efuse"; 586 compatible = "nvidia,tegra124-efuse";
582 reg = <0x0 0x7000f800 0x0 0x400>; 587 reg = <0x0 0x7000f800 0x0 0x400>;
583 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 588 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
@@ -586,7 +591,7 @@
586 reset-names = "fuse"; 591 reset-names = "fuse";
587 }; 592 };
588 593
589 mc: memory-controller@0,70019000 { 594 mc: memory-controller@70019000 {
590 compatible = "nvidia,tegra124-mc"; 595 compatible = "nvidia,tegra124-mc";
591 reg = <0x0 0x70019000 0x0 0x1000>; 596 reg = <0x0 0x70019000 0x0 0x1000>;
592 clocks = <&tegra_car TEGRA124_CLK_MC>; 597 clocks = <&tegra_car TEGRA124_CLK_MC>;
@@ -597,14 +602,14 @@
597 #iommu-cells = <1>; 602 #iommu-cells = <1>;
598 }; 603 };
599 604
600 emc: emc@0,7001b000 { 605 emc: emc@7001b000 {
601 compatible = "nvidia,tegra124-emc"; 606 compatible = "nvidia,tegra124-emc";
602 reg = <0x0 0x7001b000 0x0 0x1000>; 607 reg = <0x0 0x7001b000 0x0 0x1000>;
603 608
604 nvidia,memory-controller = <&mc>; 609 nvidia,memory-controller = <&mc>;
605 }; 610 };
606 611
607 sata@0,70020000 { 612 sata@70020000 {
608 compatible = "nvidia,tegra124-ahci"; 613 compatible = "nvidia,tegra124-ahci";
609 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 614 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
610 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 615 <0x0 0x70020000 0x0 0x7000>; /* SATA */
@@ -621,7 +626,7 @@
621 status = "disabled"; 626 status = "disabled";
622 }; 627 };
623 628
624 hda@0,70030000 { 629 hda@70030000 {
625 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 630 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
626 reg = <0x0 0x70030000 0x0 0x10000>; 631 reg = <0x0 0x70030000 0x0 0x10000>;
627 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 632 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -636,7 +641,7 @@
636 status = "disabled"; 641 status = "disabled";
637 }; 642 };
638 643
639 usb@0,70090000 { 644 usb@70090000 {
640 compatible = "nvidia,tegra124-xusb"; 645 compatible = "nvidia,tegra124-xusb";
641 reg = <0x0 0x70090000 0x0 0x8000>, 646 reg = <0x0 0x70090000 0x0 0x8000>,
642 <0x0 0x70098000 0x0 0x1000>, 647 <0x0 0x70098000 0x0 0x1000>,
@@ -671,7 +676,7 @@
671 status = "disabled"; 676 status = "disabled";
672 }; 677 };
673 678
674 padctl: padctl@0,7009f000 { 679 padctl: padctl@7009f000 {
675 compatible = "nvidia,tegra124-xusb-padctl"; 680 compatible = "nvidia,tegra124-xusb-padctl";
676 reg = <0x0 0x7009f000 0x0 0x1000>; 681 reg = <0x0 0x7009f000 0x0 0x1000>;
677 resets = <&tegra_car 142>; 682 resets = <&tegra_car 142>;
@@ -804,7 +809,7 @@
804 }; 809 };
805 }; 810 };
806 811
807 sdhci@0,700b0000 { 812 sdhci@700b0000 {
808 compatible = "nvidia,tegra124-sdhci"; 813 compatible = "nvidia,tegra124-sdhci";
809 reg = <0x0 0x700b0000 0x0 0x200>; 814 reg = <0x0 0x700b0000 0x0 0x200>;
810 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 815 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -814,7 +819,7 @@
814 status = "disabled"; 819 status = "disabled";
815 }; 820 };
816 821
817 sdhci@0,700b0200 { 822 sdhci@700b0200 {
818 compatible = "nvidia,tegra124-sdhci"; 823 compatible = "nvidia,tegra124-sdhci";
819 reg = <0x0 0x700b0200 0x0 0x200>; 824 reg = <0x0 0x700b0200 0x0 0x200>;
820 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 825 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
@@ -824,7 +829,7 @@
824 status = "disabled"; 829 status = "disabled";
825 }; 830 };
826 831
827 sdhci@0,700b0400 { 832 sdhci@700b0400 {
828 compatible = "nvidia,tegra124-sdhci"; 833 compatible = "nvidia,tegra124-sdhci";
829 reg = <0x0 0x700b0400 0x0 0x200>; 834 reg = <0x0 0x700b0400 0x0 0x200>;
830 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 835 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -834,7 +839,7 @@
834 status = "disabled"; 839 status = "disabled";
835 }; 840 };
836 841
837 sdhci@0,700b0600 { 842 sdhci@700b0600 {
838 compatible = "nvidia,tegra124-sdhci"; 843 compatible = "nvidia,tegra124-sdhci";
839 reg = <0x0 0x700b0600 0x0 0x200>; 844 reg = <0x0 0x700b0600 0x0 0x200>;
840 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 845 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
@@ -844,7 +849,7 @@
844 status = "disabled"; 849 status = "disabled";
845 }; 850 };
846 851
847 soctherm: thermal-sensor@0,700e2000 { 852 soctherm: thermal-sensor@700e2000 {
848 compatible = "nvidia,tegra124-soctherm"; 853 compatible = "nvidia,tegra124-soctherm";
849 reg = <0x0 0x700e2000 0x0 0x1000>; 854 reg = <0x0 0x700e2000 0x0 0x1000>;
850 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 855 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
@@ -856,7 +861,7 @@
856 #thermal-sensor-cells = <1>; 861 #thermal-sensor-cells = <1>;
857 }; 862 };
858 863
859 dfll: clock@0,70110000 { 864 dfll: clock@70110000 {
860 compatible = "nvidia,tegra124-dfll"; 865 compatible = "nvidia,tegra124-dfll";
861 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 866 reg = <0 0x70110000 0 0x100>, /* DFLL control */
862 <0 0x70110000 0 0x100>, /* I2C output control */ 867 <0 0x70110000 0 0x100>, /* I2C output control */
@@ -880,7 +885,7 @@
880 status = "disabled"; 885 status = "disabled";
881 }; 886 };
882 887
883 ahub@0,70300000 { 888 ahub@70300000 {
884 compatible = "nvidia,tegra124-ahub"; 889 compatible = "nvidia,tegra124-ahub";
885 reg = <0x0 0x70300000 0x0 0x200>, 890 reg = <0x0 0x70300000 0x0 0x200>,
886 <0x0 0x70300800 0x0 0x800>, 891 <0x0 0x70300800 0x0 0x800>,
@@ -932,7 +937,7 @@
932 #address-cells = <2>; 937 #address-cells = <2>;
933 #size-cells = <2>; 938 #size-cells = <2>;
934 939
935 tegra_i2s0: i2s@0,70301000 { 940 tegra_i2s0: i2s@70301000 {
936 compatible = "nvidia,tegra124-i2s"; 941 compatible = "nvidia,tegra124-i2s";
937 reg = <0x0 0x70301000 0x0 0x100>; 942 reg = <0x0 0x70301000 0x0 0x100>;
938 nvidia,ahub-cif-ids = <4 4>; 943 nvidia,ahub-cif-ids = <4 4>;
@@ -942,7 +947,7 @@
942 status = "disabled"; 947 status = "disabled";
943 }; 948 };
944 949
945 tegra_i2s1: i2s@0,70301100 { 950 tegra_i2s1: i2s@70301100 {
946 compatible = "nvidia,tegra124-i2s"; 951 compatible = "nvidia,tegra124-i2s";
947 reg = <0x0 0x70301100 0x0 0x100>; 952 reg = <0x0 0x70301100 0x0 0x100>;
948 nvidia,ahub-cif-ids = <5 5>; 953 nvidia,ahub-cif-ids = <5 5>;
@@ -952,7 +957,7 @@
952 status = "disabled"; 957 status = "disabled";
953 }; 958 };
954 959
955 tegra_i2s2: i2s@0,70301200 { 960 tegra_i2s2: i2s@70301200 {
956 compatible = "nvidia,tegra124-i2s"; 961 compatible = "nvidia,tegra124-i2s";
957 reg = <0x0 0x70301200 0x0 0x100>; 962 reg = <0x0 0x70301200 0x0 0x100>;
958 nvidia,ahub-cif-ids = <6 6>; 963 nvidia,ahub-cif-ids = <6 6>;
@@ -962,7 +967,7 @@
962 status = "disabled"; 967 status = "disabled";
963 }; 968 };
964 969
965 tegra_i2s3: i2s@0,70301300 { 970 tegra_i2s3: i2s@70301300 {
966 compatible = "nvidia,tegra124-i2s"; 971 compatible = "nvidia,tegra124-i2s";
967 reg = <0x0 0x70301300 0x0 0x100>; 972 reg = <0x0 0x70301300 0x0 0x100>;
968 nvidia,ahub-cif-ids = <7 7>; 973 nvidia,ahub-cif-ids = <7 7>;
@@ -972,7 +977,7 @@
972 status = "disabled"; 977 status = "disabled";
973 }; 978 };
974 979
975 tegra_i2s4: i2s@0,70301400 { 980 tegra_i2s4: i2s@70301400 {
976 compatible = "nvidia,tegra124-i2s"; 981 compatible = "nvidia,tegra124-i2s";
977 reg = <0x0 0x70301400 0x0 0x100>; 982 reg = <0x0 0x70301400 0x0 0x100>;
978 nvidia,ahub-cif-ids = <8 8>; 983 nvidia,ahub-cif-ids = <8 8>;
@@ -983,7 +988,7 @@
983 }; 988 };
984 }; 989 };
985 990
986 usb@0,7d000000 { 991 usb@7d000000 {
987 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 992 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
988 reg = <0x0 0x7d000000 0x0 0x4000>; 993 reg = <0x0 0x7d000000 0x0 0x4000>;
989 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 994 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -995,7 +1000,7 @@
995 status = "disabled"; 1000 status = "disabled";
996 }; 1001 };
997 1002
998 phy1: usb-phy@0,7d000000 { 1003 phy1: usb-phy@7d000000 {
999 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1004 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1000 reg = <0x0 0x7d000000 0x0 0x4000>, 1005 reg = <0x0 0x7d000000 0x0 0x4000>,
1001 <0x0 0x7d000000 0x0 0x4000>; 1006 <0x0 0x7d000000 0x0 0x4000>;
@@ -1020,7 +1025,7 @@
1020 status = "disabled"; 1025 status = "disabled";
1021 }; 1026 };
1022 1027
1023 usb@0,7d004000 { 1028 usb@7d004000 {
1024 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1029 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1025 reg = <0x0 0x7d004000 0x0 0x4000>; 1030 reg = <0x0 0x7d004000 0x0 0x4000>;
1026 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1031 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@@ -1032,7 +1037,7 @@
1032 status = "disabled"; 1037 status = "disabled";
1033 }; 1038 };
1034 1039
1035 phy2: usb-phy@0,7d004000 { 1040 phy2: usb-phy@7d004000 {
1036 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1041 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1037 reg = <0x0 0x7d004000 0x0 0x4000>, 1042 reg = <0x0 0x7d004000 0x0 0x4000>,
1038 <0x0 0x7d000000 0x0 0x4000>; 1043 <0x0 0x7d000000 0x0 0x4000>;
@@ -1056,7 +1061,7 @@
1056 status = "disabled"; 1061 status = "disabled";
1057 }; 1062 };
1058 1063
1059 usb@0,7d008000 { 1064 usb@7d008000 {
1060 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1065 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1061 reg = <0x0 0x7d008000 0x0 0x4000>; 1066 reg = <0x0 0x7d008000 0x0 0x4000>;
1062 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1067 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -1068,7 +1073,7 @@
1068 status = "disabled"; 1073 status = "disabled";
1069 }; 1074 };
1070 1075
1071 phy3: usb-phy@0,7d008000 { 1076 phy3: usb-phy@7d008000 {
1072 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1077 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1073 reg = <0x0 0x7d008000 0x0 0x4000>, 1078 reg = <0x0 0x7d008000 0x0 0x4000>,
1074 <0x0 0x7d000000 0x0 0x4000>; 1079 <0x0 0x7d000000 0x0 0x4000>;
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 8e0066ad9628..1242b841f147 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -478,7 +478,7 @@
478 478
479 clk32k_in: clock@0 { 479 clk32k_in: clock@0 {
480 compatible = "fixed-clock"; 480 compatible = "fixed-clock";
481 reg=<0>; 481 reg = <0>;
482 #clock-cells = <0>; 482 #clock-cells = <0>;
483 clock-frequency = <32768>; 483 clock-frequency = <32768>;
484 }; 484 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index d2e960cbc001..d4fb4d39ede7 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -646,7 +646,7 @@
646 646
647 clk32k_in: clock@0 { 647 clk32k_in: clock@0 {
648 compatible = "fixed-clock"; 648 compatible = "fixed-clock";
649 reg=<0>; 649 reg = <0>;
650 #clock-cells = <0>; 650 #clock-cells = <0>;
651 clock-frequency = <32768>; 651 clock-frequency = <32768>;
652 }; 652 };
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 33ed2b23026b..4e361a8c167e 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -512,7 +512,7 @@
512 512
513 clk32k_in: clock@0 { 513 clk32k_in: clock@0 {
514 compatible = "fixed-clock"; 514 compatible = "fixed-clock";
515 reg=<0>; 515 reg = <0>;
516 #clock-cells = <0>; 516 #clock-cells = <0>;
517 clock-frequency = <32768>; 517 clock-frequency = <32768>;
518 }; 518 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 94b60a710dd8..2017acacc00c 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -798,7 +798,7 @@
798 798
799 clk32k_in: clock@0 { 799 clk32k_in: clock@0 {
800 compatible = "fixed-clock"; 800 compatible = "fixed-clock";
801 reg=<0>; 801 reg = <0>;
802 #clock-cells = <0>; 802 #clock-cells = <0>;
803 clock-frequency = <32768>; 803 clock-frequency = <32768>;
804 }; 804 };
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 025e9e8037da..27d2bbbf1eae 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -508,7 +508,7 @@
508 508
509 clk32k_in: clock@0 { 509 clk32k_in: clock@0 {
510 compatible = "fixed-clock"; 510 compatible = "fixed-clock";
511 reg=<0>; 511 reg = <0>;
512 #clock-cells = <0>; 512 #clock-cells = <0>;
513 clock-frequency = <32768>; 513 clock-frequency = <32768>;
514 }; 514 };
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 4a035f74043a..381747f114a9 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -383,7 +383,7 @@
383 383
384 clk32k_in: clock@0 { 384 clk32k_in: clock@0 {
385 compatible = "fixed-clock"; 385 compatible = "fixed-clock";
386 reg=<0>; 386 reg = <0>;
387 #clock-cells = <0>; 387 #clock-cells = <0>;
388 clock-frequency = <32768>; 388 clock-frequency = <32768>;
389 }; 389 };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index a28c060a839b..8f0aaabf7e28 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -592,7 +592,7 @@
592 592
593 clk32k_in: clock@0 { 593 clk32k_in: clock@0 {
594 compatible = "fixed-clock"; 594 compatible = "fixed-clock";
595 reg=<0>; 595 reg = <0>;
596 #clock-cells = <0>; 596 #clock-cells = <0>;
597 clock-frequency = <32768>; 597 clock-frequency = <32768>;
598 }; 598 };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 073806d07b2b..1e06f854c8b4 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -569,7 +569,7 @@
569 569
570 clk32k_in: clock@0 { 570 clk32k_in: clock@0 {
571 compatible = "fixed-clock"; 571 compatible = "fixed-clock";
572 reg=<0>; 572 reg = <0>;
573 #clock-cells = <0>; 573 #clock-cells = <0>;
574 clock-frequency = <32768>; 574 clock-frequency = <32768>;
575 }; 575 };
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index bf361277fe10..192b95177aac 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -567,7 +567,7 @@
567 blocks = <0x5>; 567 blocks = <0x5>;
568 irq-trigger = <0x1>; 568 irq-trigger = <0x1>;
569 569
570 stmpe_touchscreen { 570 stmpe_touchscreen@0 {
571 compatible = "st,stmpe-ts"; 571 compatible = "st,stmpe-ts";
572 reg = <0>; 572 reg = <0>;
573 /* 3.25 MHz ADC clock speed */ 573 /* 3.25 MHz ADC clock speed */
@@ -674,13 +674,14 @@
674 674
675 clk32k_in: clk@0 { 675 clk32k_in: clk@0 {
676 compatible = "fixed-clock"; 676 compatible = "fixed-clock";
677 reg=<0>; 677 reg = <0>;
678 #clock-cells = <0>; 678 #clock-cells = <0>;
679 clock-frequency = <32768>; 679 clock-frequency = <32768>;
680 }; 680 };
681
681 clk16m: clk@1 { 682 clk16m: clk@1 {
682 compatible = "fixed-clock"; 683 compatible = "fixed-clock";
683 reg=<1>; 684 reg = <1>;
684 #clock-cells = <0>; 685 #clock-cells = <0>;
685 clock-frequency = <16000000>; 686 clock-frequency = <16000000>;
686 clock-output-names = "clk16m"; 687 clock-output-names = "clk16m";
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 1eca3b28ac64..c6a67a964fe3 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1951,7 +1951,7 @@
1951 1951
1952 clk32k_in: clock@0 { 1952 clk32k_in: clock@0 {
1953 compatible = "fixed-clock"; 1953 compatible = "fixed-clock";
1954 reg=<0>; 1954 reg = <0>;
1955 #clock-cells = <0>; 1955 #clock-cells = <0>;
1956 clock-frequency = <32768>; 1956 clock-frequency = <32768>;
1957 }; 1957 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 4721c1c9c780..f11012bb58cc 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -423,7 +423,7 @@
423 423
424 clk32k_in: clock@0 { 424 clk32k_in: clock@0 {
425 compatible = "fixed-clock"; 425 compatible = "fixed-clock";
426 reg=<0>; 426 reg = <0>;
427 #clock-cells = <0>; 427 #clock-cells = <0>;
428 clock-frequency = <32768>; 428 clock-frequency = <32768>;
429 }; 429 };
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
index 76875c3160fe..a8c0318743b6 100644
--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -131,7 +131,7 @@
131 clocks { 131 clocks {
132 clk16m: clk@1 { 132 clk16m: clk@1 {
133 compatible = "fixed-clock"; 133 compatible = "fixed-clock";
134 reg=<1>; 134 reg = <1>;
135 #clock-cells = <0>; 135 #clock-cells = <0>;
136 clock-frequency = <16000000>; 136 clock-frequency = <16000000>;
137 clock-output-names = "clk16m"; 137 clock-output-names = "clk16m";
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 2d8c58fd9357..a265534cd314 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -420,7 +420,7 @@
420 420
421 clk32k_in: clk@0 { 421 clk32k_in: clk@0 {
422 compatible = "fixed-clock"; 422 compatible = "fixed-clock";
423 reg=<0>; 423 reg = <0>;
424 #clock-cells = <0>; 424 #clock-cells = <0>;
425 clock-frequency = <32768>; 425 clock-frequency = <32768>;
426 }; 426 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 04:04:26 -0400