diff options
author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2015-11-05 11:39:52 -0500 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2017-04-03 05:36:40 -0400 |
commit | 9f759225e42b00ad0c5a55907f443b388e8960f4 (patch) | |
tree | ad3c4b7b29003cdc70002fb3b8c9dcd41b33f93e | |
parent | a1a37647d240ffb0b6480c2ecd1b02a4c21f6926 (diff) |
drm/omap: use dispc_ops
Change omapdrm to get dispc_ops and use that to call the dispc functions
instead or direct function calls.
The change is very straightforward.
The only problem was in omap_crtc_init() which calls pipe2vbl(crtc), and
at that point of time the crtc->dev link, which is used to get the
dispc_ops, has not been set up yet. This patch makes omap_crtc_init()
skip the call to pipe2vbl() and instead calls
dispc_ops->mgr_get_vsync_irq() directly.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
-rw-r--r-- | drivers/gpu/drm/omapdrm/omap_crtc.c | 36 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/omap_drv.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/omap_drv.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/omap_irq.c | 33 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/omap_plane.c | 15 |
5 files changed, 57 insertions, 39 deletions
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 49fc61963af4..1db96b077ae8 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c | |||
@@ -107,10 +107,12 @@ static struct omap_dss_device *omap_crtc_output[8]; | |||
107 | static int omap_crtc_dss_connect(enum omap_channel channel, | 107 | static int omap_crtc_dss_connect(enum omap_channel channel, |
108 | struct omap_dss_device *dst) | 108 | struct omap_dss_device *dst) |
109 | { | 109 | { |
110 | const struct dispc_ops *dispc_ops = dispc_get_ops(); | ||
111 | |||
110 | if (omap_crtc_output[channel]) | 112 | if (omap_crtc_output[channel]) |
111 | return -EINVAL; | 113 | return -EINVAL; |
112 | 114 | ||
113 | if ((dispc_mgr_get_supported_outputs(channel) & dst->id) == 0) | 115 | if ((dispc_ops->mgr_get_supported_outputs(channel) & dst->id) == 0) |
114 | return -EINVAL; | 116 | return -EINVAL; |
115 | 117 | ||
116 | omap_crtc_output[channel] = dst; | 118 | omap_crtc_output[channel] = dst; |
@@ -134,6 +136,7 @@ static void omap_crtc_dss_start_update(enum omap_channel channel) | |||
134 | static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) | 136 | static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) |
135 | { | 137 | { |
136 | struct drm_device *dev = crtc->dev; | 138 | struct drm_device *dev = crtc->dev; |
139 | struct omap_drm_private *priv = dev->dev_private; | ||
137 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | 140 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
138 | enum omap_channel channel = omap_crtc->channel; | 141 | enum omap_channel channel = omap_crtc->channel; |
139 | struct omap_irq_wait *wait; | 142 | struct omap_irq_wait *wait; |
@@ -144,7 +147,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) | |||
144 | return; | 147 | return; |
145 | 148 | ||
146 | if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) { | 149 | if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) { |
147 | dispc_mgr_enable(channel, enable); | 150 | priv->dispc_ops->mgr_enable(channel, enable); |
148 | omap_crtc->enabled = enable; | 151 | omap_crtc->enabled = enable; |
149 | return; | 152 | return; |
150 | } | 153 | } |
@@ -157,8 +160,8 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) | |||
157 | omap_crtc->ignore_digit_sync_lost = true; | 160 | omap_crtc->ignore_digit_sync_lost = true; |
158 | } | 161 | } |
159 | 162 | ||
160 | framedone_irq = dispc_mgr_get_framedone_irq(channel); | 163 | framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(channel); |
161 | vsync_irq = dispc_mgr_get_vsync_irq(channel); | 164 | vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(channel); |
162 | 165 | ||
163 | if (enable) { | 166 | if (enable) { |
164 | wait = omap_irq_wait_init(dev, vsync_irq, 1); | 167 | wait = omap_irq_wait_init(dev, vsync_irq, 1); |
@@ -178,7 +181,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) | |||
178 | wait = omap_irq_wait_init(dev, vsync_irq, 2); | 181 | wait = omap_irq_wait_init(dev, vsync_irq, 2); |
179 | } | 182 | } |
180 | 183 | ||
181 | dispc_mgr_enable(channel, enable); | 184 | priv->dispc_ops->mgr_enable(channel, enable); |
182 | omap_crtc->enabled = enable; | 185 | omap_crtc->enabled = enable; |
183 | 186 | ||
184 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); | 187 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); |
@@ -198,9 +201,9 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) | |||
198 | static int omap_crtc_dss_enable(enum omap_channel channel) | 201 | static int omap_crtc_dss_enable(enum omap_channel channel) |
199 | { | 202 | { |
200 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; | 203 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
204 | struct omap_drm_private *priv = omap_crtc->base.dev->dev_private; | ||
201 | 205 | ||
202 | dispc_mgr_set_timings(omap_crtc->channel, | 206 | priv->dispc_ops->mgr_set_timings(omap_crtc->channel, &omap_crtc->vm); |
203 | &omap_crtc->vm); | ||
204 | omap_crtc_set_enabled(&omap_crtc->base, true); | 207 | omap_crtc_set_enabled(&omap_crtc->base, true); |
205 | 208 | ||
206 | return 0; | 209 | return 0; |
@@ -225,8 +228,10 @@ static void omap_crtc_dss_set_lcd_config(enum omap_channel channel, | |||
225 | const struct dss_lcd_mgr_config *config) | 228 | const struct dss_lcd_mgr_config *config) |
226 | { | 229 | { |
227 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; | 230 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
231 | struct omap_drm_private *priv = omap_crtc->base.dev->dev_private; | ||
232 | |||
228 | DBG("%s", omap_crtc->name); | 233 | DBG("%s", omap_crtc->name); |
229 | dispc_mgr_set_lcd_config(omap_crtc->channel, config); | 234 | priv->dispc_ops->mgr_set_lcd_config(omap_crtc->channel, config); |
230 | } | 235 | } |
231 | 236 | ||
232 | static int omap_crtc_dss_register_framedone( | 237 | static int omap_crtc_dss_register_framedone( |
@@ -274,6 +279,8 @@ void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus) | |||
274 | void omap_crtc_vblank_irq(struct drm_crtc *crtc) | 279 | void omap_crtc_vblank_irq(struct drm_crtc *crtc) |
275 | { | 280 | { |
276 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | 281 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
282 | struct drm_device *dev = omap_crtc->base.dev; | ||
283 | struct omap_drm_private *priv = dev->dev_private; | ||
277 | bool pending; | 284 | bool pending; |
278 | 285 | ||
279 | spin_lock(&crtc->dev->event_lock); | 286 | spin_lock(&crtc->dev->event_lock); |
@@ -281,7 +288,7 @@ void omap_crtc_vblank_irq(struct drm_crtc *crtc) | |||
281 | * If the dispc is busy we're racing the flush operation. Try again on | 288 | * If the dispc is busy we're racing the flush operation. Try again on |
282 | * the next vblank interrupt. | 289 | * the next vblank interrupt. |
283 | */ | 290 | */ |
284 | if (dispc_mgr_go_busy(omap_crtc->channel)) { | 291 | if (priv->dispc_ops->mgr_go_busy(omap_crtc->channel)) { |
285 | spin_unlock(&crtc->dev->event_lock); | 292 | spin_unlock(&crtc->dev->event_lock); |
286 | return; | 293 | return; |
287 | } | 294 | } |
@@ -307,6 +314,7 @@ void omap_crtc_vblank_irq(struct drm_crtc *crtc) | |||
307 | 314 | ||
308 | static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc) | 315 | static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc) |
309 | { | 316 | { |
317 | struct omap_drm_private *priv = crtc->dev->dev_private; | ||
310 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | 318 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
311 | struct omap_overlay_manager_info info; | 319 | struct omap_overlay_manager_info info; |
312 | 320 | ||
@@ -317,7 +325,7 @@ static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc) | |||
317 | info.partial_alpha_enabled = false; | 325 | info.partial_alpha_enabled = false; |
318 | info.cpr_enable = false; | 326 | info.cpr_enable = false; |
319 | 327 | ||
320 | dispc_mgr_setup(omap_crtc->channel, &info); | 328 | priv->dispc_ops->mgr_setup(omap_crtc->channel, &info); |
321 | } | 329 | } |
322 | 330 | ||
323 | /* ----------------------------------------------------------------------------- | 331 | /* ----------------------------------------------------------------------------- |
@@ -401,6 +409,7 @@ static void omap_crtc_atomic_begin(struct drm_crtc *crtc, | |||
401 | static void omap_crtc_atomic_flush(struct drm_crtc *crtc, | 409 | static void omap_crtc_atomic_flush(struct drm_crtc *crtc, |
402 | struct drm_crtc_state *old_crtc_state) | 410 | struct drm_crtc_state *old_crtc_state) |
403 | { | 411 | { |
412 | struct omap_drm_private *priv = crtc->dev->dev_private; | ||
404 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | 413 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
405 | int ret; | 414 | int ret; |
406 | 415 | ||
@@ -414,7 +423,7 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc, | |||
414 | length = crtc->state->gamma_lut->length / | 423 | length = crtc->state->gamma_lut->length / |
415 | sizeof(*lut); | 424 | sizeof(*lut); |
416 | } | 425 | } |
417 | dispc_mgr_set_gamma(omap_crtc->channel, lut, length); | 426 | priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length); |
418 | } | 427 | } |
419 | 428 | ||
420 | omap_crtc_write_crtc_properties(crtc); | 429 | omap_crtc_write_crtc_properties(crtc); |
@@ -429,7 +438,7 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc, | |||
429 | WARN_ON(ret != 0); | 438 | WARN_ON(ret != 0); |
430 | 439 | ||
431 | spin_lock_irq(&crtc->dev->event_lock); | 440 | spin_lock_irq(&crtc->dev->event_lock); |
432 | dispc_mgr_go(omap_crtc->channel); | 441 | priv->dispc_ops->mgr_go(omap_crtc->channel); |
433 | 442 | ||
434 | WARN_ON(omap_crtc->pending); | 443 | WARN_ON(omap_crtc->pending); |
435 | omap_crtc->pending = true; | 444 | omap_crtc->pending = true; |
@@ -542,6 +551,7 @@ void omap_crtc_pre_uninit(void) | |||
542 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, | 551 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, |
543 | struct drm_plane *plane, enum omap_channel channel, int id) | 552 | struct drm_plane *plane, enum omap_channel channel, int id) |
544 | { | 553 | { |
554 | struct omap_drm_private *priv = dev->dev_private; | ||
545 | struct drm_crtc *crtc = NULL; | 555 | struct drm_crtc *crtc = NULL; |
546 | struct omap_crtc *omap_crtc; | 556 | struct omap_crtc *omap_crtc; |
547 | int ret; | 557 | int ret; |
@@ -575,7 +585,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, | |||
575 | * extracted with dispc_mgr_gamma_size(). If it returns 0 | 585 | * extracted with dispc_mgr_gamma_size(). If it returns 0 |
576 | * gamma table is not supprted. | 586 | * gamma table is not supprted. |
577 | */ | 587 | */ |
578 | if (dispc_mgr_gamma_size(channel)) { | 588 | if (priv->dispc_ops->mgr_gamma_size(channel)) { |
579 | uint gamma_lut_size = 256; | 589 | uint gamma_lut_size = 256; |
580 | 590 | ||
581 | drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size); | 591 | drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size); |
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index db0b485ef6c2..c7dbf30a61fa 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c | |||
@@ -93,7 +93,7 @@ static void omap_atomic_complete(struct omap_atomic_state_commit *commit) | |||
93 | struct drm_atomic_state *old_state = commit->state; | 93 | struct drm_atomic_state *old_state = commit->state; |
94 | 94 | ||
95 | /* Apply the atomic update. */ | 95 | /* Apply the atomic update. */ |
96 | dispc_runtime_get(); | 96 | priv->dispc_ops->runtime_get(); |
97 | 97 | ||
98 | drm_atomic_helper_commit_modeset_disables(dev, old_state); | 98 | drm_atomic_helper_commit_modeset_disables(dev, old_state); |
99 | 99 | ||
@@ -117,7 +117,7 @@ static void omap_atomic_complete(struct omap_atomic_state_commit *commit) | |||
117 | 117 | ||
118 | drm_atomic_helper_cleanup_planes(dev, old_state); | 118 | drm_atomic_helper_cleanup_planes(dev, old_state); |
119 | 119 | ||
120 | dispc_runtime_put(); | 120 | priv->dispc_ops->runtime_put(); |
121 | 121 | ||
122 | drm_atomic_state_put(old_state); | 122 | drm_atomic_state_put(old_state); |
123 | 123 | ||
@@ -320,8 +320,8 @@ static int omap_modeset_init(struct drm_device *dev) | |||
320 | { | 320 | { |
321 | struct omap_drm_private *priv = dev->dev_private; | 321 | struct omap_drm_private *priv = dev->dev_private; |
322 | struct omap_dss_device *dssdev = NULL; | 322 | struct omap_dss_device *dssdev = NULL; |
323 | int num_ovls = dispc_get_num_ovls(); | 323 | int num_ovls = priv->dispc_ops->get_num_ovls(); |
324 | int num_mgrs = dispc_get_num_mgrs(); | 324 | int num_mgrs = priv->dispc_ops->get_num_mgrs(); |
325 | int num_crtcs; | 325 | int num_crtcs; |
326 | int i, id = 0; | 326 | int i, id = 0; |
327 | int ret; | 327 | int ret; |
@@ -782,6 +782,8 @@ static int pdev_probe(struct platform_device *pdev) | |||
782 | goto err_disconnect_dssdevs; | 782 | goto err_disconnect_dssdevs; |
783 | } | 783 | } |
784 | 784 | ||
785 | priv->dispc_ops = dispc_get_ops(); | ||
786 | |||
785 | priv->omaprev = pdata->omaprev; | 787 | priv->omaprev = pdata->omaprev; |
786 | priv->wq = alloc_ordered_workqueue("omapdrm", 0); | 788 | priv->wq = alloc_ordered_workqueue("omapdrm", 0); |
787 | 789 | ||
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index 9098ea138269..3cb7bf259670 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h | |||
@@ -59,6 +59,8 @@ int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, | |||
59 | struct omap_drm_private { | 59 | struct omap_drm_private { |
60 | uint32_t omaprev; | 60 | uint32_t omaprev; |
61 | 61 | ||
62 | const struct dispc_ops *dispc_ops; | ||
63 | |||
62 | unsigned int num_crtcs; | 64 | unsigned int num_crtcs; |
63 | struct drm_crtc *crtcs[8]; | 65 | struct drm_crtc *crtcs[8]; |
64 | 66 | ||
diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index a3fd6e8266c8..26a3c06aa14d 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c | |||
@@ -40,8 +40,8 @@ static void omap_irq_update(struct drm_device *dev) | |||
40 | 40 | ||
41 | DBG("irqmask=%08x", irqmask); | 41 | DBG("irqmask=%08x", irqmask); |
42 | 42 | ||
43 | dispc_write_irqenable(irqmask); | 43 | priv->dispc_ops->write_irqenable(irqmask); |
44 | dispc_read_irqenable(); /* flush posted write */ | 44 | priv->dispc_ops->read_irqenable(); /* flush posted write */ |
45 | } | 45 | } |
46 | 46 | ||
47 | static void omap_irq_wait_handler(struct omap_irq_wait *wait) | 47 | static void omap_irq_wait_handler(struct omap_irq_wait *wait) |
@@ -111,7 +111,7 @@ int omap_irq_enable_vblank(struct drm_crtc *crtc) | |||
111 | DBG("dev=%p, crtc=%u", dev, channel); | 111 | DBG("dev=%p, crtc=%u", dev, channel); |
112 | 112 | ||
113 | spin_lock_irqsave(&priv->wait_lock, flags); | 113 | spin_lock_irqsave(&priv->wait_lock, flags); |
114 | priv->irq_mask |= dispc_mgr_get_vsync_irq(channel); | 114 | priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(channel); |
115 | omap_irq_update(dev); | 115 | omap_irq_update(dev); |
116 | spin_unlock_irqrestore(&priv->wait_lock, flags); | 116 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
117 | 117 | ||
@@ -137,7 +137,7 @@ void omap_irq_disable_vblank(struct drm_crtc *crtc) | |||
137 | DBG("dev=%p, crtc=%u", dev, channel); | 137 | DBG("dev=%p, crtc=%u", dev, channel); |
138 | 138 | ||
139 | spin_lock_irqsave(&priv->wait_lock, flags); | 139 | spin_lock_irqsave(&priv->wait_lock, flags); |
140 | priv->irq_mask &= ~dispc_mgr_get_vsync_irq(channel); | 140 | priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(channel); |
141 | omap_irq_update(dev); | 141 | omap_irq_update(dev); |
142 | spin_unlock_irqrestore(&priv->wait_lock, flags); | 142 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
143 | } | 143 | } |
@@ -200,9 +200,9 @@ static irqreturn_t omap_irq_handler(int irq, void *arg) | |||
200 | unsigned int id; | 200 | unsigned int id; |
201 | u32 irqstatus; | 201 | u32 irqstatus; |
202 | 202 | ||
203 | irqstatus = dispc_read_irqstatus(); | 203 | irqstatus = priv->dispc_ops->read_irqstatus(); |
204 | dispc_clear_irqstatus(irqstatus); | 204 | priv->dispc_ops->clear_irqstatus(irqstatus); |
205 | dispc_read_irqstatus(); /* flush posted write */ | 205 | priv->dispc_ops->read_irqstatus(); /* flush posted write */ |
206 | 206 | ||
207 | VERB("irqs: %08x", irqstatus); | 207 | VERB("irqs: %08x", irqstatus); |
208 | 208 | ||
@@ -210,12 +210,12 @@ static irqreturn_t omap_irq_handler(int irq, void *arg) | |||
210 | struct drm_crtc *crtc = priv->crtcs[id]; | 210 | struct drm_crtc *crtc = priv->crtcs[id]; |
211 | enum omap_channel channel = omap_crtc_channel(crtc); | 211 | enum omap_channel channel = omap_crtc_channel(crtc); |
212 | 212 | ||
213 | if (irqstatus & dispc_mgr_get_vsync_irq(channel)) { | 213 | if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(channel)) { |
214 | drm_handle_vblank(dev, id); | 214 | drm_handle_vblank(dev, id); |
215 | omap_crtc_vblank_irq(crtc); | 215 | omap_crtc_vblank_irq(crtc); |
216 | } | 216 | } |
217 | 217 | ||
218 | if (irqstatus & dispc_mgr_get_sync_lost_irq(channel)) | 218 | if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(channel)) |
219 | omap_crtc_error_irq(crtc, irqstatus); | 219 | omap_crtc_error_irq(crtc, irqstatus); |
220 | } | 220 | } |
221 | 221 | ||
@@ -249,7 +249,7 @@ static const u32 omap_underflow_irqs[] = { | |||
249 | int omap_drm_irq_install(struct drm_device *dev) | 249 | int omap_drm_irq_install(struct drm_device *dev) |
250 | { | 250 | { |
251 | struct omap_drm_private *priv = dev->dev_private; | 251 | struct omap_drm_private *priv = dev->dev_private; |
252 | unsigned int num_mgrs = dispc_get_num_mgrs(); | 252 | unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(); |
253 | unsigned int max_planes; | 253 | unsigned int max_planes; |
254 | unsigned int i; | 254 | unsigned int i; |
255 | int ret; | 255 | int ret; |
@@ -267,13 +267,13 @@ int omap_drm_irq_install(struct drm_device *dev) | |||
267 | } | 267 | } |
268 | 268 | ||
269 | for (i = 0; i < num_mgrs; ++i) | 269 | for (i = 0; i < num_mgrs; ++i) |
270 | priv->irq_mask |= dispc_mgr_get_sync_lost_irq(i); | 270 | priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(i); |
271 | 271 | ||
272 | dispc_runtime_get(); | 272 | priv->dispc_ops->runtime_get(); |
273 | dispc_clear_irqstatus(0xffffffff); | 273 | priv->dispc_ops->clear_irqstatus(0xffffffff); |
274 | dispc_runtime_put(); | 274 | priv->dispc_ops->runtime_put(); |
275 | 275 | ||
276 | ret = dispc_request_irq(omap_irq_handler, dev); | 276 | ret = priv->dispc_ops->request_irq(omap_irq_handler, dev); |
277 | if (ret < 0) | 277 | if (ret < 0) |
278 | return ret; | 278 | return ret; |
279 | 279 | ||
@@ -284,6 +284,7 @@ int omap_drm_irq_install(struct drm_device *dev) | |||
284 | 284 | ||
285 | void omap_drm_irq_uninstall(struct drm_device *dev) | 285 | void omap_drm_irq_uninstall(struct drm_device *dev) |
286 | { | 286 | { |
287 | struct omap_drm_private *priv = dev->dev_private; | ||
287 | unsigned long irqflags; | 288 | unsigned long irqflags; |
288 | int i; | 289 | int i; |
289 | 290 | ||
@@ -304,5 +305,5 @@ void omap_drm_irq_uninstall(struct drm_device *dev) | |||
304 | spin_unlock_irqrestore(&dev->vbl_lock, irqflags); | 305 | spin_unlock_irqrestore(&dev->vbl_lock, irqflags); |
305 | } | 306 | } |
306 | 307 | ||
307 | dispc_free_irq(dev); | 308 | priv->dispc_ops->free_irq(dev); |
308 | } | 309 | } |
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 1067695af401..bdd74692e0cd 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c | |||
@@ -76,6 +76,7 @@ static void omap_plane_cleanup_fb(struct drm_plane *plane, | |||
76 | static void omap_plane_atomic_update(struct drm_plane *plane, | 76 | static void omap_plane_atomic_update(struct drm_plane *plane, |
77 | struct drm_plane_state *old_state) | 77 | struct drm_plane_state *old_state) |
78 | { | 78 | { |
79 | struct omap_drm_private *priv = plane->dev->dev_private; | ||
79 | struct omap_plane *omap_plane = to_omap_plane(plane); | 80 | struct omap_plane *omap_plane = to_omap_plane(plane); |
80 | struct drm_plane_state *state = plane->state; | 81 | struct drm_plane_state *state = plane->state; |
81 | struct omap_plane_state *omap_state = to_omap_plane_state(state); | 82 | struct omap_plane_state *omap_state = to_omap_plane_state(state); |
@@ -123,25 +124,26 @@ static void omap_plane_atomic_update(struct drm_plane *plane, | |||
123 | DBG("%d,%d %pad %pad", info.pos_x, info.pos_y, | 124 | DBG("%d,%d %pad %pad", info.pos_x, info.pos_y, |
124 | &info.paddr, &info.p_uv_addr); | 125 | &info.paddr, &info.p_uv_addr); |
125 | 126 | ||
126 | dispc_ovl_set_channel_out(omap_plane->id, | 127 | priv->dispc_ops->ovl_set_channel_out(omap_plane->id, |
127 | omap_crtc_channel(state->crtc)); | 128 | omap_crtc_channel(state->crtc)); |
128 | 129 | ||
129 | /* and finally, update omapdss: */ | 130 | /* and finally, update omapdss: */ |
130 | ret = dispc_ovl_setup(omap_plane->id, &info, false, | 131 | ret = priv->dispc_ops->ovl_setup(omap_plane->id, &info, false, |
131 | omap_crtc_timings(state->crtc), false); | 132 | omap_crtc_timings(state->crtc), false); |
132 | if (ret) { | 133 | if (ret) { |
133 | dev_err(plane->dev->dev, "Failed to setup plane %s\n", | 134 | dev_err(plane->dev->dev, "Failed to setup plane %s\n", |
134 | omap_plane->name); | 135 | omap_plane->name); |
135 | dispc_ovl_enable(omap_plane->id, false); | 136 | priv->dispc_ops->ovl_enable(omap_plane->id, false); |
136 | return; | 137 | return; |
137 | } | 138 | } |
138 | 139 | ||
139 | dispc_ovl_enable(omap_plane->id, true); | 140 | priv->dispc_ops->ovl_enable(omap_plane->id, true); |
140 | } | 141 | } |
141 | 142 | ||
142 | static void omap_plane_atomic_disable(struct drm_plane *plane, | 143 | static void omap_plane_atomic_disable(struct drm_plane *plane, |
143 | struct drm_plane_state *old_state) | 144 | struct drm_plane_state *old_state) |
144 | { | 145 | { |
146 | struct omap_drm_private *priv = plane->dev->dev_private; | ||
145 | struct omap_plane_state *omap_state = to_omap_plane_state(plane->state); | 147 | struct omap_plane_state *omap_state = to_omap_plane_state(plane->state); |
146 | struct omap_plane *omap_plane = to_omap_plane(plane); | 148 | struct omap_plane *omap_plane = to_omap_plane(plane); |
147 | 149 | ||
@@ -149,7 +151,7 @@ static void omap_plane_atomic_disable(struct drm_plane *plane, | |||
149 | omap_state->zorder = plane->type == DRM_PLANE_TYPE_PRIMARY | 151 | omap_state->zorder = plane->type == DRM_PLANE_TYPE_PRIMARY |
150 | ? 0 : omap_plane->id; | 152 | ? 0 : omap_plane->id; |
151 | 153 | ||
152 | dispc_ovl_enable(omap_plane->id, false); | 154 | priv->dispc_ops->ovl_enable(omap_plane->id, false); |
153 | } | 155 | } |
154 | 156 | ||
155 | static int omap_plane_atomic_check(struct drm_plane *plane, | 157 | static int omap_plane_atomic_check(struct drm_plane *plane, |
@@ -340,6 +342,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, | |||
340 | int id, enum drm_plane_type type, | 342 | int id, enum drm_plane_type type, |
341 | u32 possible_crtcs) | 343 | u32 possible_crtcs) |
342 | { | 344 | { |
345 | struct omap_drm_private *priv = dev->dev_private; | ||
343 | struct drm_plane *plane; | 346 | struct drm_plane *plane; |
344 | struct omap_plane *omap_plane; | 347 | struct omap_plane *omap_plane; |
345 | int ret; | 348 | int ret; |
@@ -352,7 +355,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, | |||
352 | 355 | ||
353 | omap_plane->nformats = omap_framebuffer_get_formats( | 356 | omap_plane->nformats = omap_framebuffer_get_formats( |
354 | omap_plane->formats, ARRAY_SIZE(omap_plane->formats), | 357 | omap_plane->formats, ARRAY_SIZE(omap_plane->formats), |
355 | dispc_ovl_get_color_modes(id)); | 358 | priv->dispc_ops->ovl_get_color_modes(id)); |
356 | omap_plane->id = id; | 359 | omap_plane->id = id; |
357 | omap_plane->name = plane_names[id]; | 360 | omap_plane->name = plane_names[id]; |
358 | 361 | ||