Merge tag 'amlogic-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

Pull "Amlogic 32-bit DT updates for v4.15, round 2" from Kevin Hilman:
- enable new GPIO IRQ controller
- add efuse node

* tag 'amlogic-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM: dts: meson: add the efuse node
  ARM: dts: meson8b: enable gpio interrupt controller
  ARM: dts: meson8b: add support for booting the secondary CPU cores
  ARM: dts: meson8: add support for booting the secondary CPU cores

4 files changed, 88 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 290a183e87c5..4926133077b3 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -85,6 +85,15 @@
                                 reg = <0x7c00 0x200>;
                         };
 
+                        gpio_intc: interrupt-controller@9880 {
+                                compatible = "amlogic,meson-gpio-intc";
+                                reg = <0xc1109880 0x10>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
+                                status = "disabled";
+                        };
+
                         hwrng: rng@8100 {
                                 compatible = "amlogic,meson-rng";
                                 reg = <0x8100 0x8>;
@@ -271,5 +280,20 @@
                         compatible = "amlogic,meson-mx-bootrom", "syscon";
                         reg = <0xd9040000 0x10000>;
                 };
+
+                secbus: secbus@da000000 {
+                        compatible = "simple-bus";
+                        reg = <0xda000000 0x6000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0xda000000 0x6000>;
+
+                        efuse: nvmem@0 {
+                                compatible = "amlogic,meson6-efuse";
+                                reg = <0x0 0x2000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                        };
+                };
         };
 }; /* end of / */
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index ef281d290052..9b463211339f 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -84,6 +84,9 @@
         };
 }; /* end of / */
 
+&efuse {
+        status = "disabled";
+};
 
 &uart_AO {
         clocks = <&xtal>, <&clk81>, <&clk81>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index e6abcc7a1084..661287806ead 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -45,6 +45,7 @@
 
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include "meson.dtsi"
 
 / {
@@ -60,6 +61,8 @@
                         compatible = "arm,cortex-a9";
                         next-level-cache = <&L2>;
                         reg = <0x200>;
+                        enable-method = "amlogic,meson8-smp";
+                        resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
                 };
 
                 cpu@201 {
@@ -67,6 +70,8 @@
                         compatible = "arm,cortex-a9";
                         next-level-cache = <&L2>;
                         reg = <0x201>;
+                        enable-method = "amlogic,meson8-smp";
+                        resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
                 };
 
                 cpu@202 {
@@ -74,6 +79,8 @@
                         compatible = "arm,cortex-a9";
                         next-level-cache = <&L2>;
                         reg = <0x202>;
+                        enable-method = "amlogic,meson8-smp";
+                        resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
                 };
 
                 cpu@203 {
@@ -81,6 +88,8 @@
                         compatible = "arm,cortex-a9";
                         next-level-cache = <&L2>;
                         reg = <0x203>;
+                        enable-method = "amlogic,meson8-smp";
+                        resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
                 };
         };
 
@@ -118,6 +127,11 @@
 }; /* end of / */
 
 &aobus {
+        pmu: pmu@e0 {
+                compatible = "amlogic,meson8-pmu", "syscon";
+                reg = <0xe0 0x8>;
+        };
+
         pinctrl_aobus: pinctrl@84 {
                 compatible = "amlogic,meson8-aobus-pinctrl";
                 reg = <0x84 0xc>;
@@ -254,6 +268,19 @@
         };
 };
 
+&ahb_sram {
+        smp-sram@1ff80 {
+                compatible = "amlogic,meson8-smp-sram";
+                reg = <0x1ff80 0x8>;
+        };
+};
+
+&efuse {
+        compatible = "amlogic,meson8-efuse";
+        clocks = <&clkc CLKID_EFUSE>;
+        clock-names = "core";
+};
+
 &ethmac {
         clocks = <&clkc CLKID_ETH>;
         clock-names = "stmmaceth";
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 283c68c6b1f4..7ecce8890d21 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -47,6 +47,7 @@
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8b-gpio.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include "meson.dtsi"
 
 / {
@@ -59,6 +60,8 @@
                         compatible = "arm,cortex-a5";
                         next-level-cache = <&L2>;
                         reg = <0x200>;
+                        enable-method = "amlogic,meson8b-smp";
+                        resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
                 };
 
                 cpu@201 {
@@ -66,6 +69,8 @@
                         compatible = "arm,cortex-a5";
                         next-level-cache = <&L2>;
                         reg = <0x201>;
+                        enable-method = "amlogic,meson8b-smp";
+                        resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
                 };
 
                 cpu@202 {
@@ -73,6 +78,8 @@
                         compatible = "arm,cortex-a5";
                         next-level-cache = <&L2>;
                         reg = <0x202>;
+                        enable-method = "amlogic,meson8b-smp";
+                        resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
                 };
 
                 cpu@203 {
@@ -80,6 +87,8 @@
                         compatible = "arm,cortex-a5";
                         next-level-cache = <&L2>;
                         reg = <0x203>;
+                        enable-method = "amlogic,meson8b-smp";
+                        resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
                 };
         };
 
@@ -102,6 +111,11 @@
 }; /* end of / */
 
 &aobus {
+        pmu: pmu@e0 {
+                compatible = "amlogic,meson8b-pmu", "syscon";
+                reg = <0xe0 0x18>;
+        };
+
         pinctrl_aobus: pinctrl@84 {
                 compatible = "amlogic,meson8b-aobus-pinctrl";
                 reg = <0x84 0xc>;
@@ -174,11 +188,31 @@
         };
 };
 
+&ahb_sram {
+        smp-sram@1ff80 {
+                compatible = "amlogic,meson8b-smp-sram";
+                reg = <0x1ff80 0x8>;
+        };
+};
+
+
+&efuse {
+        compatible = "amlogic,meson8b-efuse";
+        clocks = <&clkc CLKID_EFUSE>;
+        clock-names = "core";
+};
+
 &ethmac {
         clocks = <&clkc CLKID_ETH>;
         clock-names = "stmmaceth";
 };
 
+&gpio_intc {
+        compatible = "amlogic,meson-gpio-intc",
+                     "amlogic,meson8b-gpio-intc";
+        status = "okay";
+};
+
 &hwrng {
         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
         clocks = <&clkc CLKID_RNG0>;