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authorRakesh Pillai <pillair@qti.qualcomm.com>2017-12-11 09:22:54 -0500
committerKalle Valo <kvalo@qca.qualcomm.com>2017-12-14 10:33:18 -0500
commit9f2992fea580a48135591873e5e3ac7e01444207 (patch)
tree283f2c00dbc127c05133d3984295ad1213800ea4
parent1807da49733e69bf6a6abd32c1e9b9c3b1f647e8 (diff)
ath10k: wmi: get wmi init parameter values from hw params
The parameter values for skid limit, number of peers and wds entries values which are sent in wmi init cmd are hardware specific. Add support to obtain skid limit, number of peers and wds entries values from hw params which will have the hw specific values for these parameters. Signed-off-by: Rakesh Pillai <pillair@qti.qualcomm.com> Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
-rw-r--r--drivers/net/wireless/ath/ath10k/core.c36
-rw-r--r--drivers/net/wireless/ath/ath10k/hw.h4
-rw-r--r--drivers/net/wireless/ath/ath10k/wmi-tlv.c7
3 files changed, 44 insertions, 3 deletions
diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c
index 9ff118114cb3..762012d6c78f 100644
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -75,6 +75,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
75 .vht160_mcs_rx_highest = 0, 75 .vht160_mcs_rx_highest = 0,
76 .vht160_mcs_tx_highest = 0, 76 .vht160_mcs_tx_highest = 0,
77 .n_cipher_suites = 8, 77 .n_cipher_suites = 8,
78 .num_peers = TARGET_TLV_NUM_PEERS,
79 .ast_skid_limit = 0x10,
80 .num_wds_entries = 0x20,
78 }, 81 },
79 { 82 {
80 .id = QCA9887_HW_1_0_VERSION, 83 .id = QCA9887_HW_1_0_VERSION,
@@ -99,6 +102,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
99 .vht160_mcs_rx_highest = 0, 102 .vht160_mcs_rx_highest = 0,
100 .vht160_mcs_tx_highest = 0, 103 .vht160_mcs_tx_highest = 0,
101 .n_cipher_suites = 8, 104 .n_cipher_suites = 8,
105 .num_peers = TARGET_TLV_NUM_PEERS,
106 .ast_skid_limit = 0x10,
107 .num_wds_entries = 0x20,
102 }, 108 },
103 { 109 {
104 .id = QCA6174_HW_2_1_VERSION, 110 .id = QCA6174_HW_2_1_VERSION,
@@ -122,6 +128,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
122 .vht160_mcs_rx_highest = 0, 128 .vht160_mcs_rx_highest = 0,
123 .vht160_mcs_tx_highest = 0, 129 .vht160_mcs_tx_highest = 0,
124 .n_cipher_suites = 8, 130 .n_cipher_suites = 8,
131 .num_peers = TARGET_TLV_NUM_PEERS,
132 .ast_skid_limit = 0x10,
133 .num_wds_entries = 0x20,
125 }, 134 },
126 { 135 {
127 .id = QCA6174_HW_2_1_VERSION, 136 .id = QCA6174_HW_2_1_VERSION,
@@ -145,6 +154,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
145 .vht160_mcs_rx_highest = 0, 154 .vht160_mcs_rx_highest = 0,
146 .vht160_mcs_tx_highest = 0, 155 .vht160_mcs_tx_highest = 0,
147 .n_cipher_suites = 8, 156 .n_cipher_suites = 8,
157 .num_peers = TARGET_TLV_NUM_PEERS,
158 .ast_skid_limit = 0x10,
159 .num_wds_entries = 0x20,
148 }, 160 },
149 { 161 {
150 .id = QCA6174_HW_3_0_VERSION, 162 .id = QCA6174_HW_3_0_VERSION,
@@ -168,6 +180,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
168 .vht160_mcs_rx_highest = 0, 180 .vht160_mcs_rx_highest = 0,
169 .vht160_mcs_tx_highest = 0, 181 .vht160_mcs_tx_highest = 0,
170 .n_cipher_suites = 8, 182 .n_cipher_suites = 8,
183 .num_peers = TARGET_TLV_NUM_PEERS,
184 .ast_skid_limit = 0x10,
185 .num_wds_entries = 0x20,
171 }, 186 },
172 { 187 {
173 .id = QCA6174_HW_3_2_VERSION, 188 .id = QCA6174_HW_3_2_VERSION,
@@ -194,6 +209,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
194 .vht160_mcs_rx_highest = 0, 209 .vht160_mcs_rx_highest = 0,
195 .vht160_mcs_tx_highest = 0, 210 .vht160_mcs_tx_highest = 0,
196 .n_cipher_suites = 8, 211 .n_cipher_suites = 8,
212 .num_peers = TARGET_TLV_NUM_PEERS,
213 .ast_skid_limit = 0x10,
214 .num_wds_entries = 0x20,
197 }, 215 },
198 { 216 {
199 .id = QCA99X0_HW_2_0_DEV_VERSION, 217 .id = QCA99X0_HW_2_0_DEV_VERSION,
@@ -223,6 +241,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
223 .vht160_mcs_rx_highest = 0, 241 .vht160_mcs_rx_highest = 0,
224 .vht160_mcs_tx_highest = 0, 242 .vht160_mcs_tx_highest = 0,
225 .n_cipher_suites = 11, 243 .n_cipher_suites = 11,
244 .num_peers = TARGET_TLV_NUM_PEERS,
245 .ast_skid_limit = 0x10,
246 .num_wds_entries = 0x20,
226 }, 247 },
227 { 248 {
228 .id = QCA9984_HW_1_0_DEV_VERSION, 249 .id = QCA9984_HW_1_0_DEV_VERSION,
@@ -257,6 +278,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
257 .vht160_mcs_rx_highest = 1560, 278 .vht160_mcs_rx_highest = 1560,
258 .vht160_mcs_tx_highest = 1560, 279 .vht160_mcs_tx_highest = 1560,
259 .n_cipher_suites = 11, 280 .n_cipher_suites = 11,
281 .num_peers = TARGET_TLV_NUM_PEERS,
282 .ast_skid_limit = 0x10,
283 .num_wds_entries = 0x20,
260 }, 284 },
261 { 285 {
262 .id = QCA9888_HW_2_0_DEV_VERSION, 286 .id = QCA9888_HW_2_0_DEV_VERSION,
@@ -290,6 +314,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
290 .vht160_mcs_rx_highest = 780, 314 .vht160_mcs_rx_highest = 780,
291 .vht160_mcs_tx_highest = 780, 315 .vht160_mcs_tx_highest = 780,
292 .n_cipher_suites = 11, 316 .n_cipher_suites = 11,
317 .num_peers = TARGET_TLV_NUM_PEERS,
318 .ast_skid_limit = 0x10,
319 .num_wds_entries = 0x20,
293 }, 320 },
294 { 321 {
295 .id = QCA9377_HW_1_0_DEV_VERSION, 322 .id = QCA9377_HW_1_0_DEV_VERSION,
@@ -313,6 +340,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
313 .vht160_mcs_rx_highest = 0, 340 .vht160_mcs_rx_highest = 0,
314 .vht160_mcs_tx_highest = 0, 341 .vht160_mcs_tx_highest = 0,
315 .n_cipher_suites = 8, 342 .n_cipher_suites = 8,
343 .num_peers = TARGET_TLV_NUM_PEERS,
344 .ast_skid_limit = 0x10,
345 .num_wds_entries = 0x20,
316 }, 346 },
317 { 347 {
318 .id = QCA9377_HW_1_1_DEV_VERSION, 348 .id = QCA9377_HW_1_1_DEV_VERSION,
@@ -338,6 +368,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
338 .vht160_mcs_rx_highest = 0, 368 .vht160_mcs_rx_highest = 0,
339 .vht160_mcs_tx_highest = 0, 369 .vht160_mcs_tx_highest = 0,
340 .n_cipher_suites = 8, 370 .n_cipher_suites = 8,
371 .num_peers = TARGET_TLV_NUM_PEERS,
372 .ast_skid_limit = 0x10,
373 .num_wds_entries = 0x20,
341 }, 374 },
342 { 375 {
343 .id = QCA4019_HW_1_0_DEV_VERSION, 376 .id = QCA4019_HW_1_0_DEV_VERSION,
@@ -368,6 +401,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
368 .vht160_mcs_rx_highest = 0, 401 .vht160_mcs_rx_highest = 0,
369 .vht160_mcs_tx_highest = 0, 402 .vht160_mcs_tx_highest = 0,
370 .n_cipher_suites = 11, 403 .n_cipher_suites = 11,
404 .num_peers = TARGET_TLV_NUM_PEERS,
405 .ast_skid_limit = 0x10,
406 .num_wds_entries = 0x20,
371 }, 407 },
372}; 408};
373 409
diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h
index 05f26e5858ad..fedb6c799374 100644
--- a/drivers/net/wireless/ath/ath10k/hw.h
+++ b/drivers/net/wireless/ath/ath10k/hw.h
@@ -553,6 +553,10 @@ struct ath10k_hw_params {
553 553
554 /* Number of ciphers supported (i.e First N) in cipher_suites array */ 554 /* Number of ciphers supported (i.e First N) in cipher_suites array */
555 int n_cipher_suites; 555 int n_cipher_suites;
556
557 u32 num_peers;
558 u32 ast_skid_limit;
559 u32 num_wds_entries;
556}; 560};
557 561
558struct htt_rx_desc; 562struct htt_rx_desc;
diff --git a/drivers/net/wireless/ath/ath10k/wmi-tlv.c b/drivers/net/wireless/ath/ath10k/wmi-tlv.c
index 9910cc65af90..8d53063bd503 100644
--- a/drivers/net/wireless/ath/ath10k/wmi-tlv.c
+++ b/drivers/net/wireless/ath/ath10k/wmi-tlv.c
@@ -1439,7 +1439,10 @@ static struct sk_buff *ath10k_wmi_tlv_op_gen_init(struct ath10k *ar)
1439 cmd->num_host_mem_chunks = __cpu_to_le32(ar->wmi.num_mem_chunks); 1439 cmd->num_host_mem_chunks = __cpu_to_le32(ar->wmi.num_mem_chunks);
1440 1440
1441 cfg->num_vdevs = __cpu_to_le32(TARGET_TLV_NUM_VDEVS); 1441 cfg->num_vdevs = __cpu_to_le32(TARGET_TLV_NUM_VDEVS);
1442 cfg->num_peers = __cpu_to_le32(TARGET_TLV_NUM_PEERS); 1442
1443 cfg->num_peers = __cpu_to_le32(ar->hw_params.num_peers);
1444 cfg->ast_skid_limit = __cpu_to_le32(ar->hw_params.ast_skid_limit);
1445 cfg->num_wds_entries = __cpu_to_le32(ar->hw_params.num_wds_entries);
1443 1446
1444 if (test_bit(WMI_SERVICE_RX_FULL_REORDER, ar->wmi.svc_map)) { 1447 if (test_bit(WMI_SERVICE_RX_FULL_REORDER, ar->wmi.svc_map)) {
1445 cfg->num_offload_peers = __cpu_to_le32(TARGET_TLV_NUM_VDEVS); 1448 cfg->num_offload_peers = __cpu_to_le32(TARGET_TLV_NUM_VDEVS);
@@ -1451,7 +1454,6 @@ static struct sk_buff *ath10k_wmi_tlv_op_gen_init(struct ath10k *ar)
1451 1454
1452 cfg->num_peer_keys = __cpu_to_le32(2); 1455 cfg->num_peer_keys = __cpu_to_le32(2);
1453 cfg->num_tids = __cpu_to_le32(TARGET_TLV_NUM_TIDS); 1456 cfg->num_tids = __cpu_to_le32(TARGET_TLV_NUM_TIDS);
1454 cfg->ast_skid_limit = __cpu_to_le32(0x10);
1455 cfg->tx_chain_mask = __cpu_to_le32(0x7); 1457 cfg->tx_chain_mask = __cpu_to_le32(0x7);
1456 cfg->rx_chain_mask = __cpu_to_le32(0x7); 1458 cfg->rx_chain_mask = __cpu_to_le32(0x7);
1457 cfg->rx_timeout_pri[0] = __cpu_to_le32(0x64); 1459 cfg->rx_timeout_pri[0] = __cpu_to_le32(0x64);
@@ -1467,7 +1469,6 @@ static struct sk_buff *ath10k_wmi_tlv_op_gen_init(struct ath10k *ar)
1467 cfg->num_mcast_table_elems = __cpu_to_le32(0); 1469 cfg->num_mcast_table_elems = __cpu_to_le32(0);
1468 cfg->mcast2ucast_mode = __cpu_to_le32(0); 1470 cfg->mcast2ucast_mode = __cpu_to_le32(0);
1469 cfg->tx_dbg_log_size = __cpu_to_le32(0x400); 1471 cfg->tx_dbg_log_size = __cpu_to_le32(0x400);
1470 cfg->num_wds_entries = __cpu_to_le32(0x20);
1471 cfg->dma_burst_size = __cpu_to_le32(0); 1472 cfg->dma_burst_size = __cpu_to_le32(0);
1472 cfg->mac_aggr_delim = __cpu_to_le32(0); 1473 cfg->mac_aggr_delim = __cpu_to_le32(0);
1473 cfg->rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(0); 1474 cfg->rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(0);