drm/radeon: don't use fractional dividers on RS[78]80 if SS is enabled

Seems to cause problems for some older hardware. Kudos to Thom Kouwenhoven
for working a lot with the PLLs and figuring this out.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 2e216e2ea78c..259cd6e6d71c 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -589,7 +589,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
                 /* use frac fb div on RS780/RS880 */
-                if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
+                if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
+                    && !radeon_crtc->ss_enabled)
                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
                 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
@@ -626,7 +627,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                         if (radeon_crtc->ss.refdiv) {
                                 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
                                 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
-                                if (ASIC_IS_AVIVO(rdev))
+                                if (rdev->family >= CHIP_RV770)
                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
                         }
                 }