diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-10 18:34:55 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-10 18:34:55 -0400 |
commit | 9ee4d7a6538308a7681b638d2f35f2a301420355 (patch) | |
tree | c037dee441f92e127f5c88e96e537abd5dd41a63 | |
parent | dbd1abb209715544bf37ffa0a3798108e140e3ec (diff) | |
parent | a0347f20aaacc96a203c9609877ecc77093cbe30 (diff) |
Merge branch 'akpm' (patches from Andrew Morton)
Merge leftovers from Andrew Morton:
"A few leftovers: ocfs2, gcov, RTC"
* emailed patches from Andrew Morton <akpm@linux-foundation.org>:
rtc: s5m: consolidate two device type switch statements
rtc: s5m: add support for S2MPS14 RTC
rtc: s5m: support different register layout
rtc: s5m: use shorter time of register update
rtc: s5m: remove undocumented time init on first boot
mfd/rtc: sec/s5m: rename SEC* symbols to S5M
gcov: add support for GCC 4.9
ocfs2/o2net: incorrect to terminate accepting connections loop upon rejecting an invalid one
-rw-r--r-- | drivers/rtc/Kconfig | 4 | ||||
-rw-r--r-- | drivers/rtc/rtc-s5m.c | 310 | ||||
-rw-r--r-- | fs/ocfs2/cluster/tcp.c | 31 | ||||
-rw-r--r-- | include/linux/mfd/samsung/rtc.h | 86 | ||||
-rw-r--r-- | kernel/gcov/base.c | 6 | ||||
-rw-r--r-- | kernel/gcov/gcc_4_7.c | 5 |
6 files changed, 292 insertions, 150 deletions
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 71988b69eca6..0754f5c7cb3b 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig | |||
@@ -530,11 +530,11 @@ config RTC_DRV_RV3029C2 | |||
530 | will be called rtc-rv3029c2. | 530 | will be called rtc-rv3029c2. |
531 | 531 | ||
532 | config RTC_DRV_S5M | 532 | config RTC_DRV_S5M |
533 | tristate "Samsung S5M series" | 533 | tristate "Samsung S2M/S5M series" |
534 | depends on MFD_SEC_CORE | 534 | depends on MFD_SEC_CORE |
535 | help | 535 | help |
536 | If you say yes here you will get support for the | 536 | If you say yes here you will get support for the |
537 | RTC of Samsung S5M PMIC series. | 537 | RTC of Samsung S2MPS14 and S5M PMIC series. |
538 | 538 | ||
539 | This driver can also be built as a module. If so, the module | 539 | This driver can also be built as a module. If so, the module |
540 | will be called rtc-s5m. | 540 | will be called rtc-s5m. |
diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c index 8ec2d6a1dbe1..8f06250a0389 100644 --- a/drivers/rtc/rtc-s5m.c +++ b/drivers/rtc/rtc-s5m.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd | 2 | * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd |
3 | * http://www.samsung.com | 3 | * http://www.samsung.com |
4 | * | 4 | * |
5 | * Copyright (C) 2013 Google, Inc | 5 | * Copyright (C) 2013 Google, Inc |
@@ -17,27 +17,76 @@ | |||
17 | 17 | ||
18 | #include <linux/module.h> | 18 | #include <linux/module.h> |
19 | #include <linux/i2c.h> | 19 | #include <linux/i2c.h> |
20 | #include <linux/slab.h> | ||
21 | #include <linux/bcd.h> | 20 | #include <linux/bcd.h> |
22 | #include <linux/bitops.h> | ||
23 | #include <linux/regmap.h> | 21 | #include <linux/regmap.h> |
24 | #include <linux/rtc.h> | 22 | #include <linux/rtc.h> |
25 | #include <linux/delay.h> | ||
26 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
27 | #include <linux/mfd/samsung/core.h> | 24 | #include <linux/mfd/samsung/core.h> |
28 | #include <linux/mfd/samsung/irq.h> | 25 | #include <linux/mfd/samsung/irq.h> |
29 | #include <linux/mfd/samsung/rtc.h> | 26 | #include <linux/mfd/samsung/rtc.h> |
27 | #include <linux/mfd/samsung/s2mps14.h> | ||
30 | 28 | ||
31 | /* | 29 | /* |
32 | * Maximum number of retries for checking changes in UDR field | 30 | * Maximum number of retries for checking changes in UDR field |
33 | * of SEC_RTC_UDR_CON register (to limit possible endless loop). | 31 | * of S5M_RTC_UDR_CON register (to limit possible endless loop). |
34 | * | 32 | * |
35 | * After writing to RTC registers (setting time or alarm) read the UDR field | 33 | * After writing to RTC registers (setting time or alarm) read the UDR field |
36 | * in SEC_RTC_UDR_CON register. UDR is auto-cleared when data have | 34 | * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have |
37 | * been transferred. | 35 | * been transferred. |
38 | */ | 36 | */ |
39 | #define UDR_READ_RETRY_CNT 5 | 37 | #define UDR_READ_RETRY_CNT 5 |
40 | 38 | ||
39 | /* Registers used by the driver which are different between chipsets. */ | ||
40 | struct s5m_rtc_reg_config { | ||
41 | /* Number of registers used for setting time/alarm0/alarm1 */ | ||
42 | unsigned int regs_count; | ||
43 | /* First register for time, seconds */ | ||
44 | unsigned int time; | ||
45 | /* RTC control register */ | ||
46 | unsigned int ctrl; | ||
47 | /* First register for alarm 0, seconds */ | ||
48 | unsigned int alarm0; | ||
49 | /* First register for alarm 1, seconds */ | ||
50 | unsigned int alarm1; | ||
51 | /* SMPL/WTSR register */ | ||
52 | unsigned int smpl_wtsr; | ||
53 | /* | ||
54 | * Register for update flag (UDR). Typically setting UDR field to 1 | ||
55 | * will enable update of time or alarm register. Then it will be | ||
56 | * auto-cleared after successful update. | ||
57 | */ | ||
58 | unsigned int rtc_udr_update; | ||
59 | /* Mask for UDR field in 'rtc_udr_update' register */ | ||
60 | unsigned int rtc_udr_mask; | ||
61 | }; | ||
62 | |||
63 | /* Register map for S5M8763 and S5M8767 */ | ||
64 | static const struct s5m_rtc_reg_config s5m_rtc_regs = { | ||
65 | .regs_count = 8, | ||
66 | .time = S5M_RTC_SEC, | ||
67 | .ctrl = S5M_ALARM1_CONF, | ||
68 | .alarm0 = S5M_ALARM0_SEC, | ||
69 | .alarm1 = S5M_ALARM1_SEC, | ||
70 | .smpl_wtsr = S5M_WTSR_SMPL_CNTL, | ||
71 | .rtc_udr_update = S5M_RTC_UDR_CON, | ||
72 | .rtc_udr_mask = S5M_RTC_UDR_MASK, | ||
73 | }; | ||
74 | |||
75 | /* | ||
76 | * Register map for S2MPS14. | ||
77 | * It may be also suitable for S2MPS11 but this was not tested. | ||
78 | */ | ||
79 | static const struct s5m_rtc_reg_config s2mps_rtc_regs = { | ||
80 | .regs_count = 7, | ||
81 | .time = S2MPS_RTC_SEC, | ||
82 | .ctrl = S2MPS_RTC_CTRL, | ||
83 | .alarm0 = S2MPS_ALARM0_SEC, | ||
84 | .alarm1 = S2MPS_ALARM1_SEC, | ||
85 | .smpl_wtsr = S2MPS_WTSR_SMPL_CNTL, | ||
86 | .rtc_udr_update = S2MPS_RTC_UDR_CON, | ||
87 | .rtc_udr_mask = S2MPS_RTC_WUDR_MASK, | ||
88 | }; | ||
89 | |||
41 | struct s5m_rtc_info { | 90 | struct s5m_rtc_info { |
42 | struct device *dev; | 91 | struct device *dev; |
43 | struct i2c_client *i2c; | 92 | struct i2c_client *i2c; |
@@ -48,13 +97,14 @@ struct s5m_rtc_info { | |||
48 | int device_type; | 97 | int device_type; |
49 | int rtc_24hr_mode; | 98 | int rtc_24hr_mode; |
50 | bool wtsr_smpl; | 99 | bool wtsr_smpl; |
100 | const struct s5m_rtc_reg_config *regs; | ||
51 | }; | 101 | }; |
52 | 102 | ||
53 | static const struct regmap_config s5m_rtc_regmap_config = { | 103 | static const struct regmap_config s5m_rtc_regmap_config = { |
54 | .reg_bits = 8, | 104 | .reg_bits = 8, |
55 | .val_bits = 8, | 105 | .val_bits = 8, |
56 | 106 | ||
57 | .max_register = SEC_RTC_REG_MAX, | 107 | .max_register = S5M_RTC_REG_MAX, |
58 | }; | 108 | }; |
59 | 109 | ||
60 | static const struct regmap_config s2mps14_rtc_regmap_config = { | 110 | static const struct regmap_config s2mps14_rtc_regmap_config = { |
@@ -119,8 +169,9 @@ static inline int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info) | |||
119 | unsigned int data; | 169 | unsigned int data; |
120 | 170 | ||
121 | do { | 171 | do { |
122 | ret = regmap_read(info->regmap, SEC_RTC_UDR_CON, &data); | 172 | ret = regmap_read(info->regmap, info->regs->rtc_udr_update, |
123 | } while (--retry && (data & RTC_UDR_MASK) && !ret); | 173 | &data); |
174 | } while (--retry && (data & info->regs->rtc_udr_mask) && !ret); | ||
124 | 175 | ||
125 | if (!retry) | 176 | if (!retry) |
126 | dev_err(info->dev, "waiting for UDR update, reached max number of retries\n"); | 177 | dev_err(info->dev, "waiting for UDR update, reached max number of retries\n"); |
@@ -128,21 +179,53 @@ static inline int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info) | |||
128 | return ret; | 179 | return ret; |
129 | } | 180 | } |
130 | 181 | ||
182 | static inline int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info, | ||
183 | struct rtc_wkalrm *alarm) | ||
184 | { | ||
185 | int ret; | ||
186 | unsigned int val; | ||
187 | |||
188 | switch (info->device_type) { | ||
189 | case S5M8767X: | ||
190 | case S5M8763X: | ||
191 | ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val); | ||
192 | val &= S5M_ALARM0_STATUS; | ||
193 | break; | ||
194 | case S2MPS14X: | ||
195 | ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2, | ||
196 | &val); | ||
197 | val &= S2MPS_ALARM0_STATUS; | ||
198 | break; | ||
199 | default: | ||
200 | return -EINVAL; | ||
201 | } | ||
202 | if (ret < 0) | ||
203 | return ret; | ||
204 | |||
205 | if (val) | ||
206 | alarm->pending = 1; | ||
207 | else | ||
208 | alarm->pending = 0; | ||
209 | |||
210 | return 0; | ||
211 | } | ||
212 | |||
131 | static inline int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info) | 213 | static inline int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info) |
132 | { | 214 | { |
133 | int ret; | 215 | int ret; |
134 | unsigned int data; | 216 | unsigned int data; |
135 | 217 | ||
136 | ret = regmap_read(info->regmap, SEC_RTC_UDR_CON, &data); | 218 | ret = regmap_read(info->regmap, info->regs->rtc_udr_update, &data); |
137 | if (ret < 0) { | 219 | if (ret < 0) { |
138 | dev_err(info->dev, "failed to read update reg(%d)\n", ret); | 220 | dev_err(info->dev, "failed to read update reg(%d)\n", ret); |
139 | return ret; | 221 | return ret; |
140 | } | 222 | } |
141 | 223 | ||
142 | data |= RTC_TIME_EN_MASK; | 224 | data |= info->regs->rtc_udr_mask; |
143 | data |= RTC_UDR_MASK; | 225 | if (info->device_type == S5M8763X || info->device_type == S5M8767X) |
226 | data |= S5M_RTC_TIME_EN_MASK; | ||
144 | 227 | ||
145 | ret = regmap_write(info->regmap, SEC_RTC_UDR_CON, data); | 228 | ret = regmap_write(info->regmap, info->regs->rtc_udr_update, data); |
146 | if (ret < 0) { | 229 | if (ret < 0) { |
147 | dev_err(info->dev, "failed to write update reg(%d)\n", ret); | 230 | dev_err(info->dev, "failed to write update reg(%d)\n", ret); |
148 | return ret; | 231 | return ret; |
@@ -158,17 +241,27 @@ static inline int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info) | |||
158 | int ret; | 241 | int ret; |
159 | unsigned int data; | 242 | unsigned int data; |
160 | 243 | ||
161 | ret = regmap_read(info->regmap, SEC_RTC_UDR_CON, &data); | 244 | ret = regmap_read(info->regmap, info->regs->rtc_udr_update, &data); |
162 | if (ret < 0) { | 245 | if (ret < 0) { |
163 | dev_err(info->dev, "%s: fail to read update reg(%d)\n", | 246 | dev_err(info->dev, "%s: fail to read update reg(%d)\n", |
164 | __func__, ret); | 247 | __func__, ret); |
165 | return ret; | 248 | return ret; |
166 | } | 249 | } |
167 | 250 | ||
168 | data &= ~RTC_TIME_EN_MASK; | 251 | data |= info->regs->rtc_udr_mask; |
169 | data |= RTC_UDR_MASK; | 252 | switch (info->device_type) { |
253 | case S5M8763X: | ||
254 | case S5M8767X: | ||
255 | data &= ~S5M_RTC_TIME_EN_MASK; | ||
256 | break; | ||
257 | case S2MPS14X: | ||
258 | data |= S2MPS_RTC_RUDR_MASK; | ||
259 | break; | ||
260 | default: | ||
261 | return -EINVAL; | ||
262 | } | ||
170 | 263 | ||
171 | ret = regmap_write(info->regmap, SEC_RTC_UDR_CON, data); | 264 | ret = regmap_write(info->regmap, info->regs->rtc_udr_update, data); |
172 | if (ret < 0) { | 265 | if (ret < 0) { |
173 | dev_err(info->dev, "%s: fail to write update reg(%d)\n", | 266 | dev_err(info->dev, "%s: fail to write update reg(%d)\n", |
174 | __func__, ret); | 267 | __func__, ret); |
@@ -215,10 +308,22 @@ static void s5m8763_tm_to_data(struct rtc_time *tm, u8 *data) | |||
215 | static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm) | 308 | static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm) |
216 | { | 309 | { |
217 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | 310 | struct s5m_rtc_info *info = dev_get_drvdata(dev); |
218 | u8 data[8]; | 311 | u8 data[info->regs->regs_count]; |
219 | int ret; | 312 | int ret; |
220 | 313 | ||
221 | ret = regmap_bulk_read(info->regmap, SEC_RTC_SEC, data, 8); | 314 | if (info->device_type == S2MPS14X) { |
315 | ret = regmap_update_bits(info->regmap, | ||
316 | info->regs->rtc_udr_update, | ||
317 | S2MPS_RTC_RUDR_MASK, S2MPS_RTC_RUDR_MASK); | ||
318 | if (ret) { | ||
319 | dev_err(dev, | ||
320 | "Failed to prepare registers for time reading: %d\n", | ||
321 | ret); | ||
322 | return ret; | ||
323 | } | ||
324 | } | ||
325 | ret = regmap_bulk_read(info->regmap, info->regs->time, data, | ||
326 | info->regs->regs_count); | ||
222 | if (ret < 0) | 327 | if (ret < 0) |
223 | return ret; | 328 | return ret; |
224 | 329 | ||
@@ -228,6 +333,7 @@ static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm) | |||
228 | break; | 333 | break; |
229 | 334 | ||
230 | case S5M8767X: | 335 | case S5M8767X: |
336 | case S2MPS14X: | ||
231 | s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode); | 337 | s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode); |
232 | break; | 338 | break; |
233 | 339 | ||
@@ -245,7 +351,7 @@ static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm) | |||
245 | static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) | 351 | static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) |
246 | { | 352 | { |
247 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | 353 | struct s5m_rtc_info *info = dev_get_drvdata(dev); |
248 | u8 data[8]; | 354 | u8 data[info->regs->regs_count]; |
249 | int ret = 0; | 355 | int ret = 0; |
250 | 356 | ||
251 | switch (info->device_type) { | 357 | switch (info->device_type) { |
@@ -253,6 +359,7 @@ static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) | |||
253 | s5m8763_tm_to_data(tm, data); | 359 | s5m8763_tm_to_data(tm, data); |
254 | break; | 360 | break; |
255 | case S5M8767X: | 361 | case S5M8767X: |
362 | case S2MPS14X: | ||
256 | ret = s5m8767_tm_to_data(tm, data); | 363 | ret = s5m8767_tm_to_data(tm, data); |
257 | break; | 364 | break; |
258 | default: | 365 | default: |
@@ -266,7 +373,8 @@ static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) | |||
266 | 1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday, | 373 | 1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday, |
267 | tm->tm_hour, tm->tm_min, tm->tm_sec, tm->tm_wday); | 374 | tm->tm_hour, tm->tm_min, tm->tm_sec, tm->tm_wday); |
268 | 375 | ||
269 | ret = regmap_raw_write(info->regmap, SEC_RTC_SEC, data, 8); | 376 | ret = regmap_raw_write(info->regmap, info->regs->time, data, |
377 | info->regs->regs_count); | ||
270 | if (ret < 0) | 378 | if (ret < 0) |
271 | return ret; | 379 | return ret; |
272 | 380 | ||
@@ -278,70 +386,60 @@ static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) | |||
278 | static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | 386 | static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
279 | { | 387 | { |
280 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | 388 | struct s5m_rtc_info *info = dev_get_drvdata(dev); |
281 | u8 data[8]; | 389 | u8 data[info->regs->regs_count]; |
282 | unsigned int val; | 390 | unsigned int val; |
283 | int ret, i; | 391 | int ret, i; |
284 | 392 | ||
285 | ret = regmap_bulk_read(info->regmap, SEC_ALARM0_SEC, data, 8); | 393 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
394 | info->regs->regs_count); | ||
286 | if (ret < 0) | 395 | if (ret < 0) |
287 | return ret; | 396 | return ret; |
288 | 397 | ||
289 | switch (info->device_type) { | 398 | switch (info->device_type) { |
290 | case S5M8763X: | 399 | case S5M8763X: |
291 | s5m8763_data_to_tm(data, &alrm->time); | 400 | s5m8763_data_to_tm(data, &alrm->time); |
292 | ret = regmap_read(info->regmap, SEC_ALARM0_CONF, &val); | 401 | ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val); |
293 | if (ret < 0) | 402 | if (ret < 0) |
294 | return ret; | 403 | return ret; |
295 | 404 | ||
296 | alrm->enabled = !!val; | 405 | alrm->enabled = !!val; |
297 | |||
298 | ret = regmap_read(info->regmap, SEC_RTC_STATUS, &val); | ||
299 | if (ret < 0) | ||
300 | return ret; | ||
301 | |||
302 | break; | 406 | break; |
303 | 407 | ||
304 | case S5M8767X: | 408 | case S5M8767X: |
409 | case S2MPS14X: | ||
305 | s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode); | 410 | s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode); |
306 | dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, | ||
307 | 1900 + alrm->time.tm_year, 1 + alrm->time.tm_mon, | ||
308 | alrm->time.tm_mday, alrm->time.tm_hour, | ||
309 | alrm->time.tm_min, alrm->time.tm_sec, | ||
310 | alrm->time.tm_wday); | ||
311 | |||
312 | alrm->enabled = 0; | 411 | alrm->enabled = 0; |
313 | for (i = 0; i < 7; i++) { | 412 | for (i = 0; i < info->regs->regs_count; i++) { |
314 | if (data[i] & ALARM_ENABLE_MASK) { | 413 | if (data[i] & ALARM_ENABLE_MASK) { |
315 | alrm->enabled = 1; | 414 | alrm->enabled = 1; |
316 | break; | 415 | break; |
317 | } | 416 | } |
318 | } | 417 | } |
319 | |||
320 | alrm->pending = 0; | ||
321 | ret = regmap_read(info->regmap, SEC_RTC_STATUS, &val); | ||
322 | if (ret < 0) | ||
323 | return ret; | ||
324 | break; | 418 | break; |
325 | 419 | ||
326 | default: | 420 | default: |
327 | return -EINVAL; | 421 | return -EINVAL; |
328 | } | 422 | } |
329 | 423 | ||
330 | if (val & ALARM0_STATUS) | 424 | dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, |
331 | alrm->pending = 1; | 425 | 1900 + alrm->time.tm_year, 1 + alrm->time.tm_mon, |
332 | else | 426 | alrm->time.tm_mday, alrm->time.tm_hour, |
333 | alrm->pending = 0; | 427 | alrm->time.tm_min, alrm->time.tm_sec, |
428 | alrm->time.tm_wday); | ||
429 | |||
430 | ret = s5m_check_peding_alarm_interrupt(info, alrm); | ||
334 | 431 | ||
335 | return 0; | 432 | return 0; |
336 | } | 433 | } |
337 | 434 | ||
338 | static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info) | 435 | static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info) |
339 | { | 436 | { |
340 | u8 data[8]; | 437 | u8 data[info->regs->regs_count]; |
341 | int ret, i; | 438 | int ret, i; |
342 | struct rtc_time tm; | 439 | struct rtc_time tm; |
343 | 440 | ||
344 | ret = regmap_bulk_read(info->regmap, SEC_ALARM0_SEC, data, 8); | 441 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
442 | info->regs->regs_count); | ||
345 | if (ret < 0) | 443 | if (ret < 0) |
346 | return ret; | 444 | return ret; |
347 | 445 | ||
@@ -352,14 +450,16 @@ static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info) | |||
352 | 450 | ||
353 | switch (info->device_type) { | 451 | switch (info->device_type) { |
354 | case S5M8763X: | 452 | case S5M8763X: |
355 | ret = regmap_write(info->regmap, SEC_ALARM0_CONF, 0); | 453 | ret = regmap_write(info->regmap, S5M_ALARM0_CONF, 0); |
356 | break; | 454 | break; |
357 | 455 | ||
358 | case S5M8767X: | 456 | case S5M8767X: |
359 | for (i = 0; i < 7; i++) | 457 | case S2MPS14X: |
458 | for (i = 0; i < info->regs->regs_count; i++) | ||
360 | data[i] &= ~ALARM_ENABLE_MASK; | 459 | data[i] &= ~ALARM_ENABLE_MASK; |
361 | 460 | ||
362 | ret = regmap_raw_write(info->regmap, SEC_ALARM0_SEC, data, 8); | 461 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
462 | info->regs->regs_count); | ||
363 | if (ret < 0) | 463 | if (ret < 0) |
364 | return ret; | 464 | return ret; |
365 | 465 | ||
@@ -377,11 +477,12 @@ static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info) | |||
377 | static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) | 477 | static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) |
378 | { | 478 | { |
379 | int ret; | 479 | int ret; |
380 | u8 data[8]; | 480 | u8 data[info->regs->regs_count]; |
381 | u8 alarm0_conf; | 481 | u8 alarm0_conf; |
382 | struct rtc_time tm; | 482 | struct rtc_time tm; |
383 | 483 | ||
384 | ret = regmap_bulk_read(info->regmap, SEC_ALARM0_SEC, data, 8); | 484 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
485 | info->regs->regs_count); | ||
385 | if (ret < 0) | 486 | if (ret < 0) |
386 | return ret; | 487 | return ret; |
387 | 488 | ||
@@ -393,10 +494,11 @@ static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) | |||
393 | switch (info->device_type) { | 494 | switch (info->device_type) { |
394 | case S5M8763X: | 495 | case S5M8763X: |
395 | alarm0_conf = 0x77; | 496 | alarm0_conf = 0x77; |
396 | ret = regmap_write(info->regmap, SEC_ALARM0_CONF, alarm0_conf); | 497 | ret = regmap_write(info->regmap, S5M_ALARM0_CONF, alarm0_conf); |
397 | break; | 498 | break; |
398 | 499 | ||
399 | case S5M8767X: | 500 | case S5M8767X: |
501 | case S2MPS14X: | ||
400 | data[RTC_SEC] |= ALARM_ENABLE_MASK; | 502 | data[RTC_SEC] |= ALARM_ENABLE_MASK; |
401 | data[RTC_MIN] |= ALARM_ENABLE_MASK; | 503 | data[RTC_MIN] |= ALARM_ENABLE_MASK; |
402 | data[RTC_HOUR] |= ALARM_ENABLE_MASK; | 504 | data[RTC_HOUR] |= ALARM_ENABLE_MASK; |
@@ -408,7 +510,8 @@ static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) | |||
408 | if (data[RTC_YEAR1] & 0x7f) | 510 | if (data[RTC_YEAR1] & 0x7f) |
409 | data[RTC_YEAR1] |= ALARM_ENABLE_MASK; | 511 | data[RTC_YEAR1] |= ALARM_ENABLE_MASK; |
410 | 512 | ||
411 | ret = regmap_raw_write(info->regmap, SEC_ALARM0_SEC, data, 8); | 513 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
514 | info->regs->regs_count); | ||
412 | if (ret < 0) | 515 | if (ret < 0) |
413 | return ret; | 516 | return ret; |
414 | ret = s5m8767_rtc_set_alarm_reg(info); | 517 | ret = s5m8767_rtc_set_alarm_reg(info); |
@@ -425,7 +528,7 @@ static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) | |||
425 | static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | 528 | static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
426 | { | 529 | { |
427 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | 530 | struct s5m_rtc_info *info = dev_get_drvdata(dev); |
428 | u8 data[8]; | 531 | u8 data[info->regs->regs_count]; |
429 | int ret; | 532 | int ret; |
430 | 533 | ||
431 | switch (info->device_type) { | 534 | switch (info->device_type) { |
@@ -434,6 +537,7 @@ static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |||
434 | break; | 537 | break; |
435 | 538 | ||
436 | case S5M8767X: | 539 | case S5M8767X: |
540 | case S2MPS14X: | ||
437 | s5m8767_tm_to_data(&alrm->time, data); | 541 | s5m8767_tm_to_data(&alrm->time, data); |
438 | break; | 542 | break; |
439 | 543 | ||
@@ -450,7 +554,8 @@ static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |||
450 | if (ret < 0) | 554 | if (ret < 0) |
451 | return ret; | 555 | return ret; |
452 | 556 | ||
453 | ret = regmap_raw_write(info->regmap, SEC_ALARM0_SEC, data, 8); | 557 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
558 | info->regs->regs_count); | ||
454 | if (ret < 0) | 559 | if (ret < 0) |
455 | return ret; | 560 | return ret; |
456 | 561 | ||
@@ -495,7 +600,7 @@ static const struct rtc_class_ops s5m_rtc_ops = { | |||
495 | static void s5m_rtc_enable_wtsr(struct s5m_rtc_info *info, bool enable) | 600 | static void s5m_rtc_enable_wtsr(struct s5m_rtc_info *info, bool enable) |
496 | { | 601 | { |
497 | int ret; | 602 | int ret; |
498 | ret = regmap_update_bits(info->regmap, SEC_WTSR_SMPL_CNTL, | 603 | ret = regmap_update_bits(info->regmap, info->regs->smpl_wtsr, |
499 | WTSR_ENABLE_MASK, | 604 | WTSR_ENABLE_MASK, |
500 | enable ? WTSR_ENABLE_MASK : 0); | 605 | enable ? WTSR_ENABLE_MASK : 0); |
501 | if (ret < 0) | 606 | if (ret < 0) |
@@ -506,7 +611,7 @@ static void s5m_rtc_enable_wtsr(struct s5m_rtc_info *info, bool enable) | |||
506 | static void s5m_rtc_enable_smpl(struct s5m_rtc_info *info, bool enable) | 611 | static void s5m_rtc_enable_smpl(struct s5m_rtc_info *info, bool enable) |
507 | { | 612 | { |
508 | int ret; | 613 | int ret; |
509 | ret = regmap_update_bits(info->regmap, SEC_WTSR_SMPL_CNTL, | 614 | ret = regmap_update_bits(info->regmap, info->regs->smpl_wtsr, |
510 | SMPL_ENABLE_MASK, | 615 | SMPL_ENABLE_MASK, |
511 | enable ? SMPL_ENABLE_MASK : 0); | 616 | enable ? SMPL_ENABLE_MASK : 0); |
512 | if (ret < 0) | 617 | if (ret < 0) |
@@ -517,50 +622,41 @@ static void s5m_rtc_enable_smpl(struct s5m_rtc_info *info, bool enable) | |||
517 | static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info) | 622 | static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info) |
518 | { | 623 | { |
519 | u8 data[2]; | 624 | u8 data[2]; |
520 | unsigned int tp_read; | ||
521 | int ret; | 625 | int ret; |
522 | struct rtc_time tm; | ||
523 | 626 | ||
524 | ret = regmap_read(info->regmap, SEC_RTC_UDR_CON, &tp_read); | 627 | switch (info->device_type) { |
525 | if (ret < 0) { | 628 | case S5M8763X: |
526 | dev_err(info->dev, "%s: fail to read control reg(%d)\n", | 629 | case S5M8767X: |
527 | __func__, ret); | 630 | /* UDR update time. Default of 7.32 ms is too long. */ |
528 | return ret; | 631 | ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON, |
529 | } | 632 | S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US); |
633 | if (ret < 0) | ||
634 | dev_err(info->dev, "%s: fail to change UDR time: %d\n", | ||
635 | __func__, ret); | ||
530 | 636 | ||
531 | /* Set RTC control register : Binary mode, 24hour mode */ | 637 | /* Set RTC control register : Binary mode, 24hour mode */ |
532 | data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | 638 | data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); |
533 | data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | 639 | data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); |
640 | |||
641 | ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2); | ||
642 | break; | ||
643 | |||
644 | case S2MPS14X: | ||
645 | data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | ||
646 | ret = regmap_write(info->regmap, info->regs->ctrl, data[0]); | ||
647 | break; | ||
648 | |||
649 | default: | ||
650 | return -EINVAL; | ||
651 | } | ||
534 | 652 | ||
535 | info->rtc_24hr_mode = 1; | 653 | info->rtc_24hr_mode = 1; |
536 | ret = regmap_raw_write(info->regmap, SEC_ALARM0_CONF, data, 2); | ||
537 | if (ret < 0) { | 654 | if (ret < 0) { |
538 | dev_err(info->dev, "%s: fail to write controlm reg(%d)\n", | 655 | dev_err(info->dev, "%s: fail to write controlm reg(%d)\n", |
539 | __func__, ret); | 656 | __func__, ret); |
540 | return ret; | 657 | return ret; |
541 | } | 658 | } |
542 | 659 | ||
543 | /* In first boot time, Set rtc time to 1/1/2012 00:00:00(SUN) */ | ||
544 | if ((tp_read & RTC_TCON_MASK) == 0) { | ||
545 | dev_dbg(info->dev, "rtc init\n"); | ||
546 | tm.tm_sec = 0; | ||
547 | tm.tm_min = 0; | ||
548 | tm.tm_hour = 0; | ||
549 | tm.tm_wday = 0; | ||
550 | tm.tm_mday = 1; | ||
551 | tm.tm_mon = 0; | ||
552 | tm.tm_year = 112; | ||
553 | tm.tm_yday = 0; | ||
554 | tm.tm_isdst = 0; | ||
555 | ret = s5m_rtc_set_time(info->dev, &tm); | ||
556 | } | ||
557 | |||
558 | ret = regmap_update_bits(info->regmap, SEC_RTC_UDR_CON, | ||
559 | RTC_TCON_MASK, tp_read | RTC_TCON_MASK); | ||
560 | if (ret < 0) | ||
561 | dev_err(info->dev, "%s: fail to update TCON reg(%d)\n", | ||
562 | __func__, ret); | ||
563 | |||
564 | return ret; | 660 | return ret; |
565 | } | 661 | } |
566 | 662 | ||
@@ -570,7 +666,7 @@ static int s5m_rtc_probe(struct platform_device *pdev) | |||
570 | struct sec_platform_data *pdata = s5m87xx->pdata; | 666 | struct sec_platform_data *pdata = s5m87xx->pdata; |
571 | struct s5m_rtc_info *info; | 667 | struct s5m_rtc_info *info; |
572 | const struct regmap_config *regmap_cfg; | 668 | const struct regmap_config *regmap_cfg; |
573 | int ret; | 669 | int ret, alarm_irq; |
574 | 670 | ||
575 | if (!pdata) { | 671 | if (!pdata) { |
576 | dev_err(pdev->dev.parent, "Platform data not supplied\n"); | 672 | dev_err(pdev->dev.parent, "Platform data not supplied\n"); |
@@ -584,12 +680,18 @@ static int s5m_rtc_probe(struct platform_device *pdev) | |||
584 | switch (pdata->device_type) { | 680 | switch (pdata->device_type) { |
585 | case S2MPS14X: | 681 | case S2MPS14X: |
586 | regmap_cfg = &s2mps14_rtc_regmap_config; | 682 | regmap_cfg = &s2mps14_rtc_regmap_config; |
683 | info->regs = &s2mps_rtc_regs; | ||
684 | alarm_irq = S2MPS14_IRQ_RTCA0; | ||
587 | break; | 685 | break; |
588 | case S5M8763X: | 686 | case S5M8763X: |
589 | regmap_cfg = &s5m_rtc_regmap_config; | 687 | regmap_cfg = &s5m_rtc_regmap_config; |
688 | info->regs = &s5m_rtc_regs; | ||
689 | alarm_irq = S5M8763_IRQ_ALARM0; | ||
590 | break; | 690 | break; |
591 | case S5M8767X: | 691 | case S5M8767X: |
592 | regmap_cfg = &s5m_rtc_regmap_config; | 692 | regmap_cfg = &s5m_rtc_regmap_config; |
693 | info->regs = &s5m_rtc_regs; | ||
694 | alarm_irq = S5M8767_IRQ_RTCA1; | ||
593 | break; | 695 | break; |
594 | default: | 696 | default: |
595 | dev_err(&pdev->dev, "Device type is not supported by RTC driver\n"); | 697 | dev_err(&pdev->dev, "Device type is not supported by RTC driver\n"); |
@@ -615,20 +717,11 @@ static int s5m_rtc_probe(struct platform_device *pdev) | |||
615 | info->device_type = s5m87xx->device_type; | 717 | info->device_type = s5m87xx->device_type; |
616 | info->wtsr_smpl = s5m87xx->wtsr_smpl; | 718 | info->wtsr_smpl = s5m87xx->wtsr_smpl; |
617 | 719 | ||
618 | switch (pdata->device_type) { | 720 | info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq); |
619 | case S5M8763X: | 721 | if (info->irq <= 0) { |
620 | info->irq = regmap_irq_get_virq(s5m87xx->irq_data, | ||
621 | S5M8763_IRQ_ALARM0); | ||
622 | break; | ||
623 | |||
624 | case S5M8767X: | ||
625 | info->irq = regmap_irq_get_virq(s5m87xx->irq_data, | ||
626 | S5M8767_IRQ_RTCA1); | ||
627 | break; | ||
628 | |||
629 | default: | ||
630 | ret = -EINVAL; | 722 | ret = -EINVAL; |
631 | dev_err(&pdev->dev, "Unsupported device type: %d\n", ret); | 723 | dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n", |
724 | alarm_irq); | ||
632 | goto err; | 725 | goto err; |
633 | } | 726 | } |
634 | 727 | ||
@@ -676,7 +769,7 @@ static void s5m_rtc_shutdown(struct platform_device *pdev) | |||
676 | if (info->wtsr_smpl) { | 769 | if (info->wtsr_smpl) { |
677 | for (i = 0; i < 3; i++) { | 770 | for (i = 0; i < 3; i++) { |
678 | s5m_rtc_enable_wtsr(info, false); | 771 | s5m_rtc_enable_wtsr(info, false); |
679 | regmap_read(info->regmap, SEC_WTSR_SMPL_CNTL, &val); | 772 | regmap_read(info->regmap, info->regs->smpl_wtsr, &val); |
680 | pr_debug("%s: WTSR_SMPL reg(0x%02x)\n", __func__, val); | 773 | pr_debug("%s: WTSR_SMPL reg(0x%02x)\n", __func__, val); |
681 | if (val & WTSR_ENABLE_MASK) | 774 | if (val & WTSR_ENABLE_MASK) |
682 | pr_emerg("%s: fail to disable WTSR\n", | 775 | pr_emerg("%s: fail to disable WTSR\n", |
@@ -730,7 +823,8 @@ static int s5m_rtc_suspend(struct device *dev) | |||
730 | static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume); | 823 | static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume); |
731 | 824 | ||
732 | static const struct platform_device_id s5m_rtc_id[] = { | 825 | static const struct platform_device_id s5m_rtc_id[] = { |
733 | { "s5m-rtc", 0 }, | 826 | { "s5m-rtc", S5M8767X }, |
827 | { "s2mps14-rtc", S2MPS14X }, | ||
734 | }; | 828 | }; |
735 | 829 | ||
736 | static struct platform_driver s5m_rtc_driver = { | 830 | static struct platform_driver s5m_rtc_driver = { |
@@ -749,6 +843,6 @@ module_platform_driver(s5m_rtc_driver); | |||
749 | 843 | ||
750 | /* Module information */ | 844 | /* Module information */ |
751 | MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); | 845 | MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); |
752 | MODULE_DESCRIPTION("Samsung S5M RTC driver"); | 846 | MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver"); |
753 | MODULE_LICENSE("GPL"); | 847 | MODULE_LICENSE("GPL"); |
754 | MODULE_ALIAS("platform:s5m-rtc"); | 848 | MODULE_ALIAS("platform:s5m-rtc"); |
diff --git a/fs/ocfs2/cluster/tcp.c b/fs/ocfs2/cluster/tcp.c index a68e07a9bd46..681691bc233a 100644 --- a/fs/ocfs2/cluster/tcp.c +++ b/fs/ocfs2/cluster/tcp.c | |||
@@ -1799,7 +1799,7 @@ int o2net_register_hb_callbacks(void) | |||
1799 | 1799 | ||
1800 | /* ------------------------------------------------------------ */ | 1800 | /* ------------------------------------------------------------ */ |
1801 | 1801 | ||
1802 | static int o2net_accept_one(struct socket *sock) | 1802 | static int o2net_accept_one(struct socket *sock, int *more) |
1803 | { | 1803 | { |
1804 | int ret, slen; | 1804 | int ret, slen; |
1805 | struct sockaddr_in sin; | 1805 | struct sockaddr_in sin; |
@@ -1810,6 +1810,7 @@ static int o2net_accept_one(struct socket *sock) | |||
1810 | struct o2net_node *nn; | 1810 | struct o2net_node *nn; |
1811 | 1811 | ||
1812 | BUG_ON(sock == NULL); | 1812 | BUG_ON(sock == NULL); |
1813 | *more = 0; | ||
1813 | ret = sock_create_lite(sock->sk->sk_family, sock->sk->sk_type, | 1814 | ret = sock_create_lite(sock->sk->sk_family, sock->sk->sk_type, |
1814 | sock->sk->sk_protocol, &new_sock); | 1815 | sock->sk->sk_protocol, &new_sock); |
1815 | if (ret) | 1816 | if (ret) |
@@ -1821,6 +1822,7 @@ static int o2net_accept_one(struct socket *sock) | |||
1821 | if (ret < 0) | 1822 | if (ret < 0) |
1822 | goto out; | 1823 | goto out; |
1823 | 1824 | ||
1825 | *more = 1; | ||
1824 | new_sock->sk->sk_allocation = GFP_ATOMIC; | 1826 | new_sock->sk->sk_allocation = GFP_ATOMIC; |
1825 | 1827 | ||
1826 | ret = o2net_set_nodelay(new_sock); | 1828 | ret = o2net_set_nodelay(new_sock); |
@@ -1919,11 +1921,36 @@ out: | |||
1919 | return ret; | 1921 | return ret; |
1920 | } | 1922 | } |
1921 | 1923 | ||
1924 | /* | ||
1925 | * This function is invoked in response to one or more | ||
1926 | * pending accepts at softIRQ level. We must drain the | ||
1927 | * entire que before returning. | ||
1928 | */ | ||
1929 | |||
1922 | static void o2net_accept_many(struct work_struct *work) | 1930 | static void o2net_accept_many(struct work_struct *work) |
1923 | { | 1931 | { |
1924 | struct socket *sock = o2net_listen_sock; | 1932 | struct socket *sock = o2net_listen_sock; |
1925 | while (o2net_accept_one(sock) == 0) | 1933 | int more; |
1934 | int err; | ||
1935 | |||
1936 | /* | ||
1937 | * It is critical to note that due to interrupt moderation | ||
1938 | * at the network driver level, we can't assume to get a | ||
1939 | * softIRQ for every single conn since tcp SYN packets | ||
1940 | * can arrive back-to-back, and therefore many pending | ||
1941 | * accepts may result in just 1 softIRQ. If we terminate | ||
1942 | * the o2net_accept_one() loop upon seeing an err, what happens | ||
1943 | * to the rest of the conns in the queue? If no new SYN | ||
1944 | * arrives for hours, no softIRQ will be delivered, | ||
1945 | * and the connections will just sit in the queue. | ||
1946 | */ | ||
1947 | |||
1948 | for (;;) { | ||
1949 | err = o2net_accept_one(sock, &more); | ||
1950 | if (!more) | ||
1951 | break; | ||
1926 | cond_resched(); | 1952 | cond_resched(); |
1953 | } | ||
1927 | } | 1954 | } |
1928 | 1955 | ||
1929 | static void o2net_listen_data_ready(struct sock *sk) | 1956 | static void o2net_listen_data_ready(struct sock *sk) |
diff --git a/include/linux/mfd/samsung/rtc.h b/include/linux/mfd/samsung/rtc.h index 3e02b768d537..b6401e7661c7 100644 --- a/include/linux/mfd/samsung/rtc.h +++ b/include/linux/mfd/samsung/rtc.h | |||
@@ -18,38 +18,38 @@ | |||
18 | #ifndef __LINUX_MFD_SEC_RTC_H | 18 | #ifndef __LINUX_MFD_SEC_RTC_H |
19 | #define __LINUX_MFD_SEC_RTC_H | 19 | #define __LINUX_MFD_SEC_RTC_H |
20 | 20 | ||
21 | enum sec_rtc_reg { | 21 | enum s5m_rtc_reg { |
22 | SEC_RTC_SEC, | 22 | S5M_RTC_SEC, |
23 | SEC_RTC_MIN, | 23 | S5M_RTC_MIN, |
24 | SEC_RTC_HOUR, | 24 | S5M_RTC_HOUR, |
25 | SEC_RTC_WEEKDAY, | 25 | S5M_RTC_WEEKDAY, |
26 | SEC_RTC_DATE, | 26 | S5M_RTC_DATE, |
27 | SEC_RTC_MONTH, | 27 | S5M_RTC_MONTH, |
28 | SEC_RTC_YEAR1, | 28 | S5M_RTC_YEAR1, |
29 | SEC_RTC_YEAR2, | 29 | S5M_RTC_YEAR2, |
30 | SEC_ALARM0_SEC, | 30 | S5M_ALARM0_SEC, |
31 | SEC_ALARM0_MIN, | 31 | S5M_ALARM0_MIN, |
32 | SEC_ALARM0_HOUR, | 32 | S5M_ALARM0_HOUR, |
33 | SEC_ALARM0_WEEKDAY, | 33 | S5M_ALARM0_WEEKDAY, |
34 | SEC_ALARM0_DATE, | 34 | S5M_ALARM0_DATE, |
35 | SEC_ALARM0_MONTH, | 35 | S5M_ALARM0_MONTH, |
36 | SEC_ALARM0_YEAR1, | 36 | S5M_ALARM0_YEAR1, |
37 | SEC_ALARM0_YEAR2, | 37 | S5M_ALARM0_YEAR2, |
38 | SEC_ALARM1_SEC, | 38 | S5M_ALARM1_SEC, |
39 | SEC_ALARM1_MIN, | 39 | S5M_ALARM1_MIN, |
40 | SEC_ALARM1_HOUR, | 40 | S5M_ALARM1_HOUR, |
41 | SEC_ALARM1_WEEKDAY, | 41 | S5M_ALARM1_WEEKDAY, |
42 | SEC_ALARM1_DATE, | 42 | S5M_ALARM1_DATE, |
43 | SEC_ALARM1_MONTH, | 43 | S5M_ALARM1_MONTH, |
44 | SEC_ALARM1_YEAR1, | 44 | S5M_ALARM1_YEAR1, |
45 | SEC_ALARM1_YEAR2, | 45 | S5M_ALARM1_YEAR2, |
46 | SEC_ALARM0_CONF, | 46 | S5M_ALARM0_CONF, |
47 | SEC_ALARM1_CONF, | 47 | S5M_ALARM1_CONF, |
48 | SEC_RTC_STATUS, | 48 | S5M_RTC_STATUS, |
49 | SEC_WTSR_SMPL_CNTL, | 49 | S5M_WTSR_SMPL_CNTL, |
50 | SEC_RTC_UDR_CON, | 50 | S5M_RTC_UDR_CON, |
51 | 51 | ||
52 | SEC_RTC_REG_MAX, | 52 | S5M_RTC_REG_MAX, |
53 | }; | 53 | }; |
54 | 54 | ||
55 | enum s2mps_rtc_reg { | 55 | enum s2mps_rtc_reg { |
@@ -88,9 +88,9 @@ enum s2mps_rtc_reg { | |||
88 | #define HOUR_12 (1 << 7) | 88 | #define HOUR_12 (1 << 7) |
89 | #define HOUR_AMPM (1 << 6) | 89 | #define HOUR_AMPM (1 << 6) |
90 | #define HOUR_PM (1 << 5) | 90 | #define HOUR_PM (1 << 5) |
91 | #define ALARM0_STATUS (1 << 1) | 91 | #define S5M_ALARM0_STATUS (1 << 1) |
92 | #define ALARM1_STATUS (1 << 2) | 92 | #define S5M_ALARM1_STATUS (1 << 2) |
93 | #define UPDATE_AD (1 << 0) | 93 | #define S5M_UPDATE_AD (1 << 0) |
94 | 94 | ||
95 | #define S2MPS_ALARM0_STATUS (1 << 2) | 95 | #define S2MPS_ALARM0_STATUS (1 << 2) |
96 | #define S2MPS_ALARM1_STATUS (1 << 1) | 96 | #define S2MPS_ALARM1_STATUS (1 << 1) |
@@ -101,16 +101,26 @@ enum s2mps_rtc_reg { | |||
101 | #define MODEL24_SHIFT 1 | 101 | #define MODEL24_SHIFT 1 |
102 | #define MODEL24_MASK (1 << MODEL24_SHIFT) | 102 | #define MODEL24_MASK (1 << MODEL24_SHIFT) |
103 | /* RTC Update Register1 */ | 103 | /* RTC Update Register1 */ |
104 | #define RTC_UDR_SHIFT 0 | 104 | #define S5M_RTC_UDR_SHIFT 0 |
105 | #define RTC_UDR_MASK (1 << RTC_UDR_SHIFT) | 105 | #define S5M_RTC_UDR_MASK (1 << S5M_RTC_UDR_SHIFT) |
106 | #define S2MPS_RTC_WUDR_SHIFT 4 | 106 | #define S2MPS_RTC_WUDR_SHIFT 4 |
107 | #define S2MPS_RTC_WUDR_MASK (1 << S2MPS_RTC_WUDR_SHIFT) | 107 | #define S2MPS_RTC_WUDR_MASK (1 << S2MPS_RTC_WUDR_SHIFT) |
108 | #define S2MPS_RTC_RUDR_SHIFT 0 | 108 | #define S2MPS_RTC_RUDR_SHIFT 0 |
109 | #define S2MPS_RTC_RUDR_MASK (1 << S2MPS_RTC_RUDR_SHIFT) | 109 | #define S2MPS_RTC_RUDR_MASK (1 << S2MPS_RTC_RUDR_SHIFT) |
110 | #define RTC_TCON_SHIFT 1 | 110 | #define RTC_TCON_SHIFT 1 |
111 | #define RTC_TCON_MASK (1 << RTC_TCON_SHIFT) | 111 | #define RTC_TCON_MASK (1 << RTC_TCON_SHIFT) |
112 | #define RTC_TIME_EN_SHIFT 3 | 112 | #define S5M_RTC_TIME_EN_SHIFT 3 |
113 | #define RTC_TIME_EN_MASK (1 << RTC_TIME_EN_SHIFT) | 113 | #define S5M_RTC_TIME_EN_MASK (1 << S5M_RTC_TIME_EN_SHIFT) |
114 | /* | ||
115 | * UDR_T field in S5M_RTC_UDR_CON register determines the time needed | ||
116 | * for updating alarm and time registers. Default is 7.32 ms. | ||
117 | */ | ||
118 | #define S5M_RTC_UDR_T_SHIFT 6 | ||
119 | #define S5M_RTC_UDR_T_MASK (0x3 << S5M_RTC_UDR_T_SHIFT) | ||
120 | #define S5M_RTC_UDR_T_7320_US (0x0 << S5M_RTC_UDR_T_SHIFT) | ||
121 | #define S5M_RTC_UDR_T_1830_US (0x1 << S5M_RTC_UDR_T_SHIFT) | ||
122 | #define S5M_RTC_UDR_T_3660_US (0x2 << S5M_RTC_UDR_T_SHIFT) | ||
123 | #define S5M_RTC_UDR_T_450_US (0x3 << S5M_RTC_UDR_T_SHIFT) | ||
114 | 124 | ||
115 | /* RTC Hour register */ | 125 | /* RTC Hour register */ |
116 | #define HOUR_PM_SHIFT 6 | 126 | #define HOUR_PM_SHIFT 6 |
diff --git a/kernel/gcov/base.c b/kernel/gcov/base.c index f45b75b713c0..b358a802fd18 100644 --- a/kernel/gcov/base.c +++ b/kernel/gcov/base.c | |||
@@ -85,6 +85,12 @@ void __gcov_merge_ior(gcov_type *counters, unsigned int n_counters) | |||
85 | } | 85 | } |
86 | EXPORT_SYMBOL(__gcov_merge_ior); | 86 | EXPORT_SYMBOL(__gcov_merge_ior); |
87 | 87 | ||
88 | void __gcov_merge_time_profile(gcov_type *counters, unsigned int n_counters) | ||
89 | { | ||
90 | /* Unused. */ | ||
91 | } | ||
92 | EXPORT_SYMBOL(__gcov_merge_time_profile); | ||
93 | |||
88 | /** | 94 | /** |
89 | * gcov_enable_events - enable event reporting through gcov_event() | 95 | * gcov_enable_events - enable event reporting through gcov_event() |
90 | * | 96 | * |
diff --git a/kernel/gcov/gcc_4_7.c b/kernel/gcov/gcc_4_7.c index 2c6e4631c814..826ba9fb5e32 100644 --- a/kernel/gcov/gcc_4_7.c +++ b/kernel/gcov/gcc_4_7.c | |||
@@ -18,7 +18,12 @@ | |||
18 | #include <linux/vmalloc.h> | 18 | #include <linux/vmalloc.h> |
19 | #include "gcov.h" | 19 | #include "gcov.h" |
20 | 20 | ||
21 | #if __GNUC__ == 4 && __GNUC_MINOR__ >= 9 | ||
22 | #define GCOV_COUNTERS 9 | ||
23 | #else | ||
21 | #define GCOV_COUNTERS 8 | 24 | #define GCOV_COUNTERS 8 |
25 | #endif | ||
26 | |||
22 | #define GCOV_TAG_FUNCTION_LENGTH 3 | 27 | #define GCOV_TAG_FUNCTION_LENGTH 3 |
23 | 28 | ||
24 | static struct gcov_info *gcov_info_head; | 29 | static struct gcov_info *gcov_info_head; |