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authorRoger Quadros <rogerq@ti.com>2014-08-15 09:08:36 -0400
committerTony Lindgren <tony@atomide.com>2014-11-24 10:55:27 -0500
commit9ec49b9f2b43a09f6263c955b84419467a1d64e0 (patch)
tree60a4d630937486ce4963437c0a79c7c3fa87e9c4
parentae3c0f75089fdfe0c1cd409cacc9ecd5122a78c6 (diff)
ARM: dts: DRA7: Add DCAN nodes
The SoC supports 2 DCAN nodes. Add them. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/dra7.dtsi21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 960b2c5e0df1..63bf99be1762 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -40,6 +40,8 @@
40 serial9 = &uart10; 40 serial9 = &uart10;
41 ethernet0 = &cpsw_emac0; 41 ethernet0 = &cpsw_emac0;
42 ethernet1 = &cpsw_emac1; 42 ethernet1 = &cpsw_emac1;
43 d_can0 = &dcan1;
44 d_can1 = &dcan2;
43 }; 45 };
44 46
45 timer { 47 timer {
@@ -1400,6 +1402,25 @@
1400 }; 1402 };
1401 }; 1403 };
1402 1404
1405 dcan1: can@481cc000 {
1406 compatible = "ti,dra7-d_can";
1407 ti,hwmods = "dcan1";
1408 reg = <0x4ae3c000 0x2000>;
1409 syscon-raminit = <&dra7_ctrl_core 0x558 0>;
1410 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1411 clocks = <&dcan1_sys_clk_mux>;
1412 status = "disabled";
1413 };
1414
1415 dcan2: can@481d0000 {
1416 compatible = "ti,dra7-d_can";
1417 ti,hwmods = "dcan2";
1418 reg = <0x48480000 0x2000>;
1419 syscon-raminit = <&dra7_ctrl_core 0x558 1>;
1420 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&sys_clkin1>;
1422 status = "disabled";
1423 };
1403 }; 1424 };
1404}; 1425};
1405 1426