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authorPhilippe Bergheaud <felix@linux.vnet.ibm.com>2018-03-02 04:56:12 -0500
committerMichael Ellerman <mpe@ellerman.id.au>2018-03-13 00:50:30 -0400
commit9dbcbfa1fe0c3b556e889ea213a73eb80d74307b (patch)
tree71042281315c1048a9f168b35f1f510bf94fa068
parentd6a90bb83b5084829558788ea5b8818c9be3da63 (diff)
cxl: read PHB indications from the device tree
Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-rw-r--r--drivers/misc/cxl/cxl.h2
-rw-r--r--drivers/misc/cxl/cxllib.c2
-rw-r--r--drivers/misc/cxl/pci.c48
3 files changed, 45 insertions, 7 deletions
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index 4949b8d5a748..a4c9c8297a6d 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -1069,7 +1069,7 @@ int cxl_psl_purge(struct cxl_afu *afu);
1069int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid, 1069int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
1070 u32 *phb_index, u64 *capp_unit_id); 1070 u32 *phb_index, u64 *capp_unit_id);
1071int cxl_slot_is_switched(struct pci_dev *dev); 1071int cxl_slot_is_switched(struct pci_dev *dev);
1072int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg); 1072int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg);
1073u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9); 1073u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
1074 1074
1075void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx); 1075void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
diff --git a/drivers/misc/cxl/cxllib.c b/drivers/misc/cxl/cxllib.c
index 30ccba436b3b..bea1eb004b49 100644
--- a/drivers/misc/cxl/cxllib.c
+++ b/drivers/misc/cxl/cxllib.c
@@ -99,7 +99,7 @@ int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg)
99 if (rc) 99 if (rc)
100 return rc; 100 return rc;
101 101
102 rc = cxl_get_xsl9_dsnctl(capp_unit_id, &cfg->dsnctl); 102 rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &cfg->dsnctl);
103 if (rc) 103 if (rc)
104 return rc; 104 return rc;
105 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 105 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 35f486912ddc..e7ac78e85494 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -407,21 +407,59 @@ int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
407 return 0; 407 return 0;
408} 408}
409 409
410int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg) 410static DEFINE_MUTEX(indications_mutex);
411
412static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
413 u64 *nbwind)
414{
415 static u64 nbw, asn, capi = 0;
416 struct device_node *np;
417 const __be32 *prop;
418
419 mutex_lock(&indications_mutex);
420 if (!capi) {
421 if (!(np = pnv_pci_get_phb_node(dev))) {
422 mutex_unlock(&indications_mutex);
423 return -ENODEV;
424 }
425
426 prop = of_get_property(np, "ibm,phb-indications", NULL);
427 if (!prop) {
428 nbw = 0x0300UL; /* legacy values */
429 asn = 0x0400UL;
430 capi = 0x0200UL;
431 } else {
432 nbw = (u64)be32_to_cpu(prop[2]);
433 asn = (u64)be32_to_cpu(prop[1]);
434 capi = (u64)be32_to_cpu(prop[0]);
435 }
436 of_node_put(np);
437 }
438 *capiind = capi;
439 *asnind = asn;
440 *nbwind = nbw;
441 mutex_unlock(&indications_mutex);
442 return 0;
443}
444
445int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
411{ 446{
412 u64 xsl_dsnctl; 447 u64 xsl_dsnctl;
448 u64 capiind, asnind, nbwind;
413 449
414 /* 450 /*
415 * CAPI Identifier bits [0:7] 451 * CAPI Identifier bits [0:7]
416 * bit 61:60 MSI bits --> 0 452 * bit 61:60 MSI bits --> 0
417 * bit 59 TVT selector --> 0 453 * bit 59 TVT selector --> 0
418 */ 454 */
455 if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
456 return -ENODEV;
419 457
420 /* 458 /*
421 * Tell XSL where to route data to. 459 * Tell XSL where to route data to.
422 * The field chipid should match the PHB CAPI_CMPM register 460 * The field chipid should match the PHB CAPI_CMPM register
423 */ 461 */
424 xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */ 462 xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
425 xsl_dsnctl |= (capp_unit_id << (63-15)); 463 xsl_dsnctl |= (capp_unit_id << (63-15));
426 464
427 /* nMMU_ID Defaults to: b’000001001’*/ 465 /* nMMU_ID Defaults to: b’000001001’*/
@@ -435,14 +473,14 @@ int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg)
435 * nbwind=0x03, bits [57:58], must include capi indicator. 473 * nbwind=0x03, bits [57:58], must include capi indicator.
436 * Not supported on P9 DD1. 474 * Not supported on P9 DD1.
437 */ 475 */
438 xsl_dsnctl |= ((u64)0x03 << (63-47)); 476 xsl_dsnctl |= (nbwind << (63-55));
439 477
440 /* 478 /*
441 * Upper 16b address bits of ASB_Notify messages sent to the 479 * Upper 16b address bits of ASB_Notify messages sent to the
442 * system. Need to match the PHB’s ASN Compare/Mask Register. 480 * system. Need to match the PHB’s ASN Compare/Mask Register.
443 * Not supported on P9 DD1. 481 * Not supported on P9 DD1.
444 */ 482 */
445 xsl_dsnctl |= ((u64)0x04 << (63-55)); 483 xsl_dsnctl |= asnind;
446 } 484 }
447 485
448 *reg = xsl_dsnctl; 486 *reg = xsl_dsnctl;
@@ -463,7 +501,7 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
463 if (rc) 501 if (rc)
464 return rc; 502 return rc;
465 503
466 rc = cxl_get_xsl9_dsnctl(capp_unit_id, &xsl_dsnctl); 504 rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
467 if (rc) 505 if (rc)
468 return rc; 506 return rc;
469 507