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authorOlof Johansson <olof@lixom.net>2014-07-21 13:49:46 -0400
committerOlof Johansson <olof@lixom.net>2014-07-21 13:49:46 -0400
commit9db58cc9f385457524d3f6548198532168aecd23 (patch)
treea3d68b81935e5f4f220db8a0f6bbaf9ca516e68f
parentf57c0e049aa189e9683e2f013594a63bcc4f083f (diff)
parent3db53918e306d3960bf9e12eea8b2fd3f7d0fd62 (diff)
Merge tag 'omap-for-v3.17/soc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
Merge "omap soc clean-up for v3.17 merge window" from Tony Lindgren: SoC specific omap clean-up for v3.17 merge window: - Changes to PRM and clock related code to help move things to drivers - Removal of unused ctrl module defines that no longer are needed with things moving to .dts files and drivers * tag 'omap-for-v3.17/soc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (23 commits) ARM: OMAP2+: clock/interface: remove some headers from clkt_iclk.c file ARM: OMAP2+: clock/dpll: remove unused header includes from dpll3xxx.c ARM: OMAP2+: clock/dpll: remove unused header includes from clkt_dpll.c ARM: OMAP2+: clock/interface: add a clk_features definition for idlest value ARM: OMAP2+: clock/dpll: add jitter correction behind clk_features ARM: OMAP2+: clock/dpll: convert bypass check to use clk_features ARM: OMAP2+: clock/dpll: add private API for checking if DPLL is in bypass ARM: OMAP2+: clock: add fint values to the ti_clk_features struct ARM: OMAP2+: clock: introduce ti_clk_features flags ARM: OMAP4+: dpll44xx: remove cm-regbits-44xx.h and clock44xx.h includes ARM: OMAP4+: dpll: remove cpu_is_omap44xx checks ARM: OMAP4+: clock: remove DEFINE_CLK_OMAP_HSDIVIDER macro ARM: OMAP4: Ctrl module register define diet ARM: OMAP3: control: isolate control module init to its own function ARM: OMAP3: PRM: move modem reset and iva2 idle to PRM driver ARM: OMAP3: control: add API for setting up the modem pads ARM: OMAP3: PRM: move PRM init code from PM core to the driver ARM: OMAP24xx: PRM: add API for clearing wakeup status bits ARM: OMAP3: PRM: add API for saving PRM scratchpad contents ARM: OMAP3: PRM: add API for checking and clearing cold reset status ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c98
-rw-r--r--arch/arm/mach-omap2/clkt_iclk.c8
-rw-r--r--arch/arm/mach-omap2/clock.c76
-rw-r--r--arch/arm/mach-omap2/clock.h44
-rw-r--r--arch/arm/mach-omap2/control.c60
-rw-r--r--arch/arm/mach-omap2/control.h40
-rw-r--r--arch/arm/mach-omap2/ctrl_module_core_44xx.h392
-rw-r--r--arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h1409
-rw-r--r--arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h236
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c7
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c19
-rw-r--r--arch/arm/mach-omap2/io.c2
-rw-r--r--arch/arm/mach-omap2/pm24xx.c31
-rw-r--r--arch/arm/mach-omap2/pm34xx.c218
-rw-r--r--arch/arm/mach-omap2/prm2xxx.c18
-rw-r--r--arch/arm/mach-omap2/prm2xxx.h1
-rw-r--r--arch/arm/mach-omap2/prm3xxx.c233
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h6
18 files changed, 516 insertions, 2382 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 67fd26a18441..b2ff6cd7ca9f 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -21,10 +21,7 @@
21 21
22#include <asm/div64.h> 22#include <asm/div64.h>
23 23
24#include "soc.h"
25#include "clock.h" 24#include "clock.h"
26#include "cm-regbits-24xx.h"
27#include "cm-regbits-34xx.h"
28 25
29/* DPLL rate rounding: minimum DPLL multiplier, divider values */ 26/* DPLL rate rounding: minimum DPLL multiplier, divider values */
30#define DPLL_MIN_MULTIPLIER 2 27#define DPLL_MIN_MULTIPLIER 2
@@ -44,20 +41,12 @@
44#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ 41#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
45 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 42 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
46 43
47/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
48#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
49#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
50#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
51#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
52
53/* 44/*
54 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. 45 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
55 * From device data manual section 4.3 "DPLL and DLL Specifications". 46 * From device data manual section 4.3 "DPLL and DLL Specifications".
56 */ 47 */
57#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 48#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
58#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 49#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
59#define OMAP3PLUS_DPLL_FINT_MIN 32000
60#define OMAP3PLUS_DPLL_FINT_MAX 52000000
61 50
62/* _dpll_test_fint() return codes */ 51/* _dpll_test_fint() return codes */
63#define DPLL_FINT_UNDERFLOW -1 52#define DPLL_FINT_UNDERFLOW -1
@@ -87,33 +76,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
87 /* DPLL divider must result in a valid jitter correction val */ 76 /* DPLL divider must result in a valid jitter correction val */
88 fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; 77 fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
89 78
90 if (cpu_is_omap24xx()) { 79 if (dd->flags & DPLL_J_TYPE) {
91 /* Should not be called for OMAP2, so warn if it is called */
92 WARN(1, "No fint limits available for OMAP2!\n");
93 return DPLL_FINT_INVALID;
94 } else if (cpu_is_omap3430()) {
95 fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
96 fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
97 } else if (dd->flags & DPLL_J_TYPE) {
98 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; 80 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
99 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; 81 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
100 } else { 82 } else {
101 fint_min = OMAP3PLUS_DPLL_FINT_MIN; 83 fint_min = ti_clk_features.fint_min;
102 fint_max = OMAP3PLUS_DPLL_FINT_MAX; 84 fint_max = ti_clk_features.fint_max;
103 } 85 }
104 86
105 if (fint < fint_min) { 87 if (!fint_min || !fint_max) {
88 WARN(1, "No fint limits available!\n");
89 return DPLL_FINT_INVALID;
90 }
91
92 if (fint < ti_clk_features.fint_min) {
106 pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", 93 pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
107 n); 94 n);
108 dd->max_divider = n; 95 dd->max_divider = n;
109 ret = DPLL_FINT_UNDERFLOW; 96 ret = DPLL_FINT_UNDERFLOW;
110 } else if (fint > fint_max) { 97 } else if (fint > ti_clk_features.fint_max) {
111 pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", 98 pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
112 n); 99 n);
113 dd->min_divider = n; 100 dd->min_divider = n;
114 ret = DPLL_FINT_INVALID; 101 ret = DPLL_FINT_INVALID;
115 } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX && 102 } else if (fint > ti_clk_features.fint_band1_max &&
116 fint < OMAP3430_DPLL_FINT_BAND2_MIN) { 103 fint < ti_clk_features.fint_band2_min) {
117 pr_debug("rejecting n=%d due to Fint failure\n", n); 104 pr_debug("rejecting n=%d due to Fint failure\n", n);
118 ret = DPLL_FINT_INVALID; 105 ret = DPLL_FINT_INVALID;
119 } 106 }
@@ -185,6 +172,34 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
185 return r; 172 return r;
186} 173}
187 174
175/**
176 * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
177 * @v: bitfield value of the DPLL enable
178 *
179 * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
180 * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
181 */
182static int _omap2_dpll_is_in_bypass(u32 v)
183{
184 u8 mask, val;
185
186 mask = ti_clk_features.dpll_bypass_vals;
187
188 /*
189 * Each set bit in the mask corresponds to a bypass value equal
190 * to the bitshift. Go through each set-bit in the mask and
191 * compare against the given register value.
192 */
193 while (mask) {
194 val = __ffs(mask);
195 mask ^= (1 << val);
196 if (v == val)
197 return 1;
198 }
199
200 return 0;
201}
202
188/* Public functions */ 203/* Public functions */
189u8 omap2_init_dpll_parent(struct clk_hw *hw) 204u8 omap2_init_dpll_parent(struct clk_hw *hw)
190{ 205{
@@ -201,20 +216,9 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
201 v >>= __ffs(dd->enable_mask); 216 v >>= __ffs(dd->enable_mask);
202 217
203 /* Reparent the struct clk in case the dpll is in bypass */ 218 /* Reparent the struct clk in case the dpll is in bypass */
204 if (cpu_is_omap24xx()) { 219 if (_omap2_dpll_is_in_bypass(v))
205 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 220 return 1;
206 v == OMAP2XXX_EN_DPLL_FRBYPASS) 221
207 return 1;
208 } else if (cpu_is_omap34xx()) {
209 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
210 v == OMAP3XXX_EN_DPLL_FRBYPASS)
211 return 1;
212 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
213 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
214 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
215 v == OMAP4XXX_EN_DPLL_MNBYPASS)
216 return 1;
217 }
218 return 0; 222 return 0;
219} 223}
220 224
@@ -247,20 +251,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
247 v &= dd->enable_mask; 251 v &= dd->enable_mask;
248 v >>= __ffs(dd->enable_mask); 252 v >>= __ffs(dd->enable_mask);
249 253
250 if (cpu_is_omap24xx()) { 254 if (_omap2_dpll_is_in_bypass(v))
251 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 255 return __clk_get_rate(dd->clk_bypass);
252 v == OMAP2XXX_EN_DPLL_FRBYPASS)
253 return __clk_get_rate(dd->clk_bypass);
254 } else if (cpu_is_omap34xx()) {
255 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
256 v == OMAP3XXX_EN_DPLL_FRBYPASS)
257 return __clk_get_rate(dd->clk_bypass);
258 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
259 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
260 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
261 v == OMAP4XXX_EN_DPLL_MNBYPASS)
262 return __clk_get_rate(dd->clk_bypass);
263 }
264 256
265 v = omap2_clk_readl(clk, dd->mult_div1_reg); 257 v = omap2_clk_readl(clk, dd->mult_div1_reg);
266 dpll_mult = v & dd->mult_mask; 258 dpll_mult = v & dd->mult_mask;
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index 333f0a666171..55eb579aeae1 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -14,11 +14,11 @@
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/io.h> 15#include <linux/io.h>
16 16
17
18#include "clock.h" 17#include "clock.h"
19#include "clock2xxx.h" 18
20#include "cm2xxx_3xxx.h" 19/* Register offsets */
21#include "cm-regbits-24xx.h" 20#define CM_AUTOIDLE 0x30
21#define CM_ICLKEN 0x10
22 22
23/* Private functions */ 23/* Private functions */
24 24
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 591581a66532..5a0cac93d9ec 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -47,6 +47,24 @@
47u16 cpu_mask; 47u16 cpu_mask;
48 48
49/* 49/*
50 * Clock features setup. Used instead of CPU type checks.
51 */
52struct ti_clk_features ti_clk_features;
53
54/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
55#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
56#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
57#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
58#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
59
60/*
61 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
62 * From device data manual section 4.3 "DPLL and DLL Specifications".
63 */
64#define OMAP3PLUS_DPLL_FINT_MIN 32000
65#define OMAP3PLUS_DPLL_FINT_MAX 52000000
66
67/*
50 * clkdm_control: if true, then when a clock is enabled in the 68 * clkdm_control: if true, then when a clock is enabled in the
51 * hardware, its clockdomain will first be enabled; and when a clock 69 * hardware, its clockdomain will first be enabled; and when a clock
52 * is disabled in the hardware, its clockdomain will be disabled 70 * is disabled in the hardware, its clockdomain will be disabled
@@ -287,13 +305,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
287 * 34xx reverses this, just to keep us on our toes 305 * 34xx reverses this, just to keep us on our toes
288 * AM35xx uses both, depending on the module. 306 * AM35xx uses both, depending on the module.
289 */ 307 */
290 if (cpu_is_omap24xx()) 308 *idlest_val = ti_clk_features.cm_idlest_val;
291 *idlest_val = OMAP24XX_CM_IDLEST_VAL;
292 else if (cpu_is_omap34xx())
293 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
294 else
295 BUG();
296
297} 309}
298 310
299/** 311/**
@@ -731,3 +743,53 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
731 (clk_get_rate(core_ck) / 1000000), 743 (clk_get_rate(core_ck) / 1000000),
732 (clk_get_rate(mpu_ck) / 1000000)); 744 (clk_get_rate(mpu_ck) / 1000000));
733} 745}
746
747/**
748 * ti_clk_init_features - init clock features struct for the SoC
749 *
750 * Initializes the clock features struct based on the SoC type.
751 */
752void __init ti_clk_init_features(void)
753{
754 /* Fint setup for DPLLs */
755 if (cpu_is_omap3430()) {
756 ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
757 ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
758 ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
759 ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
760 } else {
761 ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
762 ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
763 }
764
765 /* Bypass value setup for DPLLs */
766 if (cpu_is_omap24xx()) {
767 ti_clk_features.dpll_bypass_vals |=
768 (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
769 (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
770 } else if (cpu_is_omap34xx()) {
771 ti_clk_features.dpll_bypass_vals |=
772 (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
773 (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
774 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
775 soc_is_omap54xx() || soc_is_dra7xx()) {
776 ti_clk_features.dpll_bypass_vals |=
777 (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
778 (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
779 (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
780 }
781
782 /* Jitter correction only available on OMAP343X */
783 if (cpu_is_omap343x())
784 ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
785
786 /* Idlest value for interface clocks.
787 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
788 * 34xx reverses this, just to keep us on our toes
789 * AM35xx uses both, depending on the module.
790 */
791 if (cpu_is_omap24xx())
792 ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
793 else if (cpu_is_omap34xx())
794 ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
795}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 12f54d428d7c..0f100dc4e97f 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -101,31 +101,6 @@ struct clockdomain;
101 }; \ 101 }; \
102 DEFINE_STRUCT_CLK(_name, _parent_names, _ops); 102 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
103 103
104#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
105 _parent_ptr, _flags, \
106 _clksel_reg, _clksel_mask) \
107 static const struct clksel _name##_div[] = { \
108 { \
109 .parent = _parent_ptr, \
110 .rates = div31_1to31_rates \
111 }, \
112 { .parent = NULL }, \
113 }; \
114 static struct clk _name; \
115 static const char *_name##_parent_names[] = { \
116 _parent_name, \
117 }; \
118 static struct clk_hw_omap _name##_hw = { \
119 .hw = { \
120 .clk = &_name, \
121 }, \
122 .clksel = _name##_div, \
123 .clksel_reg = _clksel_reg, \
124 .clksel_mask = _clksel_mask, \
125 .ops = &clkhwops_omap4_dpllmx, \
126 }; \
127 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
128
129/* struct clksel_rate.flags possibilities */ 104/* struct clksel_rate.flags possibilities */
130#define RATE_IN_242X (1 << 0) 105#define RATE_IN_242X (1 << 0)
131#define RATE_IN_243X (1 << 1) 106#define RATE_IN_243X (1 << 1)
@@ -248,6 +223,23 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
248 223
249extern u16 cpu_mask; 224extern u16 cpu_mask;
250 225
226/*
227 * Clock features setup. Used instead of CPU type checks.
228 */
229struct ti_clk_features {
230 u32 flags;
231 long fint_min;
232 long fint_max;
233 long fint_band1_max;
234 long fint_band2_min;
235 u8 dpll_bypass_vals;
236 u8 cm_idlest_val;
237};
238
239#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0)
240
241extern struct ti_clk_features ti_clk_features;
242
251extern const struct clkops clkops_omap2_dflt_wait; 243extern const struct clkops clkops_omap2_dflt_wait;
252extern const struct clkops clkops_dummy; 244extern const struct clkops clkops_dummy;
253extern const struct clkops clkops_omap2_dflt; 245extern const struct clkops clkops_omap2_dflt;
@@ -286,4 +278,6 @@ extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
286extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 278extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
287 279
288extern void omap_clocks_register(struct omap_clk *oclks, int cnt); 280extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
281
282void __init ti_clk_init_features(void);
289#endif 283#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 751f3549bf6f..f4796c002070 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -44,8 +44,7 @@ struct omap3_scratchpad {
44}; 44};
45 45
46struct omap3_scratchpad_prcm_block { 46struct omap3_scratchpad_prcm_block {
47 u32 prm_clksrc_ctrl; 47 u32 prm_contents[2];
48 u32 prm_clksel;
49 u32 cm_contents[11]; 48 u32 cm_contents[11];
50 u32 prcm_block_size; 49 u32 prcm_block_size;
51}; 50};
@@ -282,13 +281,9 @@ void omap3_clear_scratchpad_contents(void)
282 void __iomem *v_addr; 281 void __iomem *v_addr;
283 u32 offset = 0; 282 u32 offset = 0;
284 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 283 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
285 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & 284 if (omap3xxx_prm_clear_global_cold_reset()) {
286 OMAP3430_GLOBAL_COLD_RST_MASK) {
287 for ( ; offset <= max_offset; offset += 0x4) 285 for ( ; offset <= max_offset; offset += 0x4)
288 writel_relaxed(0x0, (v_addr + offset)); 286 writel_relaxed(0x0, (v_addr + offset));
289 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
290 OMAP3430_GR_MOD,
291 OMAP3_PRM_RSTST_OFFSET);
292 } 287 }
293} 288}
294 289
@@ -331,13 +326,7 @@ void omap3_save_scratchpad_contents(void)
331 scratchpad_contents.sdrc_block_offset = 0x64; 326 scratchpad_contents.sdrc_block_offset = 0x64;
332 327
333 /* Populate the PRCM block contents */ 328 /* Populate the PRCM block contents */
334 prcm_block_contents.prm_clksrc_ctrl = 329 omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
335 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
336 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
337 prcm_block_contents.prm_clksel =
338 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
339 OMAP3_PRM_CLKSEL_OFFSET);
340
341 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); 330 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
342 331
343 prcm_block_contents.prcm_block_size = 0x0; 332 prcm_block_contents.prcm_block_size = 0x0;
@@ -575,9 +564,50 @@ int omap3_ctrl_save_padconf(void)
575 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to 564 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
576 * force disable IVA2 so that it does not prevent any low-power states. 565 * force disable IVA2 so that it does not prevent any low-power states.
577 */ 566 */
578void omap3_ctrl_set_iva_bootmode_idle(void) 567static void __init omap3_ctrl_set_iva_bootmode_idle(void)
579{ 568{
580 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 569 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
581 OMAP343X_CONTROL_IVA2_BOOTMOD); 570 OMAP343X_CONTROL_IVA2_BOOTMOD);
582} 571}
572
573/**
574 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
575 *
576 * Sets up the pads controlling the stacked modem in such way that the
577 * device can enter idle.
578 */
579static void __init omap3_ctrl_setup_d2d_padconf(void)
580{
581 u16 mask, padconf;
582
583 /*
584 * In a stand alone OMAP3430 where there is not a stacked
585 * modem for the D2D Idle Ack and D2D MStandby must be pulled
586 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
587 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
588 */
589 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
590 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
591 padconf |= mask;
592 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
593
594 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
595 padconf |= mask;
596 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
597}
598
599/**
600 * omap3_ctrl_init - does static initializations for control module
601 *
602 * Initializes system control module. This sets up the sysconfig autoidle,
603 * and sets up modem and iva2 so that they can be idled properly.
604 */
605void __init omap3_ctrl_init(void)
606{
607 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
608
609 omap3_ctrl_set_iva_bootmode_idle();
610
611 omap3_ctrl_setup_d2d_padconf();
612}
583#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 613#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index da054801b114..a3c013345c45 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -16,11 +16,6 @@
16#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H 16#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
17#define __ARCH_ARM_MACH_OMAP2_CONTROL_H 17#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
18 18
19#include "ctrl_module_core_44xx.h"
20#include "ctrl_module_wkup_44xx.h"
21#include "ctrl_module_pad_core_44xx.h"
22#include "ctrl_module_pad_wkup_44xx.h"
23
24#include "am33xx.h" 19#include "am33xx.h"
25 20
26#ifndef __ASSEMBLY__ 21#ifndef __ASSEMBLY__
@@ -254,6 +249,39 @@
254/* TI81XX CONTROL_DEVCONF register offsets */ 249/* TI81XX CONTROL_DEVCONF register offsets */
255#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) 250#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
256 251
252/* OMAP4 CONTROL MODULE */
253#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
254#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
255#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
256#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
257#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
258#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
259#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
260
261/* OMAP4 CONTROL_DSIPHY */
262#define OMAP4_DSI2_LANEENABLE_SHIFT 29
263#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
264#define OMAP4_DSI1_LANEENABLE_SHIFT 24
265#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
266#define OMAP4_DSI1_PIPD_SHIFT 19
267#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
268#define OMAP4_DSI2_PIPD_SHIFT 14
269#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
270
271/* OMAP4 CONTROL_CAMERA_RX */
272#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
273#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
274#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
275#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
276#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
277#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
278#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
279#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
280#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
281#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
282#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
283#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
284
257/* OMAP54XX CONTROL STATUS register */ 285/* OMAP54XX CONTROL STATUS register */
258#define OMAP5XXX_CONTROL_STATUS 0x134 286#define OMAP5XXX_CONTROL_STATUS 0x134
259#define OMAP5_DEVICETYPE_MASK (0x7 << 6) 287#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
@@ -427,7 +455,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
427extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); 455extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
428extern void omap3630_ctrl_disable_rta(void); 456extern void omap3630_ctrl_disable_rta(void);
429extern int omap3_ctrl_save_padconf(void); 457extern int omap3_ctrl_save_padconf(void);
430extern void omap3_ctrl_set_iva_bootmode_idle(void); 458void omap3_ctrl_init(void);
431extern void omap2_set_globals_control(void __iomem *ctrl, 459extern void omap2_set_globals_control(void __iomem *ctrl,
432 void __iomem *ctrl_pad); 460 void __iomem *ctrl_pad);
433#else 461#else
diff --git a/arch/arm/mach-omap2/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_core_44xx.h
deleted file mode 100644
index 01970824e0e5..000000000000
--- a/arch/arm/mach-omap2/ctrl_module_core_44xx.h
+++ /dev/null
@@ -1,392 +0,0 @@
1/*
2 * OMAP44xx CTRL_MODULE_CORE registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_CORE 0x4a002000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
32#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
33#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
34#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
35#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
36#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
37#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
38#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
39#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
40#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
41#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
42#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
43#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
44#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
45#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
46#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
47#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
48#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
49#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
50#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
51#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
52#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
53#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
54#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
55#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
56#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
57#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
58#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
59#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
60#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
61#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
62#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
63#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
64#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
65#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
66#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
67#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
68#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
69#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
70#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
71#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
72#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
73#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
74#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
75#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
76#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
77#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
78#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
79#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
80#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
81#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
82#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
83#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
84#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
85#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
86#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
87#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
88#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
89#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
90#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
91#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
92#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
93#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
94#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
95#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
96#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
97#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
98#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
99#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
100#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
101
102/* Registers shifts and masks */
103
104/* IP_REVISION */
105#define OMAP4_IP_REV_SCHEME_SHIFT 30
106#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
107#define OMAP4_IP_REV_FUNC_SHIFT 16
108#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
109#define OMAP4_IP_REV_RTL_SHIFT 11
110#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
111#define OMAP4_IP_REV_MAJOR_SHIFT 8
112#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
113#define OMAP4_IP_REV_CUSTOM_SHIFT 6
114#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
115#define OMAP4_IP_REV_MINOR_SHIFT 0
116#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
117
118/* IP_HWINFO */
119#define OMAP4_IP_HWINFO_SHIFT 0
120#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
121
122/* IP_SYSCONFIG */
123#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
124#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
125
126/* STD_FUSE_DIE_ID_0 */
127#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
128#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
129
130/* ID_CODE */
131#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
132#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
133
134/* STD_FUSE_DIE_ID_1 */
135#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
136#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
137
138/* STD_FUSE_DIE_ID_2 */
139#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
140#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
141
142/* STD_FUSE_DIE_ID_3 */
143#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
144#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
145
146/* STD_FUSE_PROD_ID_0 */
147#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
148#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
149
150/* STD_FUSE_PROD_ID_1 */
151#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
152#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
153
154/* STD_FUSE_USB_CONF */
155#define OMAP4_USB_PROD_ID_SHIFT 16
156#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
157#define OMAP4_USB_VENDOR_ID_SHIFT 0
158#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
159
160/* STD_FUSE_OPP_VDD_WKUP */
161#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
162#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
163
164/* STD_FUSE_OPP_BGAP */
165#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
166#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
167
168/* STD_FUSE_OPP_DPLL_0 */
169#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
170#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
171
172/* STD_FUSE_OPP_DPLL_1 */
173#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
174#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
175
176/* STATUS */
177#define OMAP4_ATTILA_CONF_SHIFT 11
178#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
179#define OMAP4_DEVICE_TYPE_SHIFT 8
180#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
181#define OMAP4_SYS_BOOT_SHIFT 0
182#define OMAP4_SYS_BOOT_MASK (0xff << 0)
183
184/* DEV_CONF */
185#define OMAP4_DEV_CONF_SHIFT 1
186#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
187#define OMAP4_USBPHY_PD_SHIFT 0
188#define OMAP4_USBPHY_PD_MASK (1 << 0)
189
190/* LDOVBB_IVA_VOLTAGE_CTRL */
191#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
192#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
193#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
194#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
195#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
196#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
197#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
198#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
199#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
200#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
201#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
202#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
203
204/* LDOVBB_MPU_VOLTAGE_CTRL */
205#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
206#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
207#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
208#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
209#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
210#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
211#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
212#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
213#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
214#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
215#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
216#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
217
218/* LDOSRAM_IVA_VOLTAGE_CTRL */
219#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
220#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
221#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
222#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
223#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
224#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
225#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
226#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
227#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
228#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
229#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
230#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
231
232/* LDOSRAM_MPU_VOLTAGE_CTRL */
233#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
234#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
235#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
236#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
237#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
238#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
239#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
240#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
241#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
242#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
243#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
244#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
245
246/* LDOSRAM_CORE_VOLTAGE_CTRL */
247#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
248#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
249#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
250#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
251#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
252#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
253#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
254#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
255#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
256#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
257#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
258#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
259
260/* TEMP_SENSOR */
261#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
262#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
263#define OMAP4_BGAP_TSHUT_SHIFT 11
264#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
265#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
266#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
267#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
268#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
269#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
270#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
271#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
272#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
273
274/* DPLL_NWELL_TRIM_0 */
275#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
276#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
277#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
278#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
279#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
280#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
281#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
282#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
283#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
284#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
285#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
286#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
287#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
288#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
289#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
290#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
291#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
292#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
293#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
294#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
295
296/* DPLL_NWELL_TRIM_1 */
297#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
298#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
299#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
300#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
301#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
302#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
303#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
304#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
305#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
306#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
307#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
308#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
309#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
310#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
311#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
312#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
313#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
314#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
315#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
316#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
317
318/* USBOTGHS_CONTROL */
319#define OMAP4_DISCHRGVBUS_SHIFT 8
320#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
321#define OMAP4_CHRGVBUS_SHIFT 7
322#define OMAP4_CHRGVBUS_MASK (1 << 7)
323#define OMAP4_DRVVBUS_SHIFT 6
324#define OMAP4_DRVVBUS_MASK (1 << 6)
325#define OMAP4_IDPULLUP_SHIFT 5
326#define OMAP4_IDPULLUP_MASK (1 << 5)
327#define OMAP4_IDDIG_SHIFT 4
328#define OMAP4_IDDIG_MASK (1 << 4)
329#define OMAP4_SESSEND_SHIFT 3
330#define OMAP4_SESSEND_MASK (1 << 3)
331#define OMAP4_VBUSVALID_SHIFT 2
332#define OMAP4_VBUSVALID_MASK (1 << 2)
333#define OMAP4_BVALID_SHIFT 1
334#define OMAP4_BVALID_MASK (1 << 1)
335#define OMAP4_AVALID_SHIFT 0
336#define OMAP4_AVALID_MASK (1 << 0)
337
338/* DSS_CONTROL */
339#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
340#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
341
342/* HWOBS_CONTROL */
343#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
344#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
345#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
346#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
347#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
348#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
349#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
350#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
351
352/* DEBOBS_FINAL_MUX_SEL */
353#define OMAP4_SELECT_SHIFT 0
354#define OMAP4_SELECT_MASK (0xffffffff << 0)
355
356/* DEBOBS_MMR_MPU */
357#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
358#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
359
360/* CONF_SDMA_REQ_SEL0 */
361#define OMAP4_MULT_SHIFT 0
362#define OMAP4_MULT_MASK (0x7f << 0)
363
364/* CONF_CLK_SEL0 */
365#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
366#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
367
368/* CONF_CLK_SEL1 */
369#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
370#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
371
372/* CONF_CLK_SEL2 */
373#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
374#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
375
376/* CONF_DPLL_FREQLOCK_SEL */
377#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
378#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
379
380/* CONF_DPLL_TINITZ_SEL */
381#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
382#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
383
384/* CONF_DPLL_PHASELOCK_SEL */
385#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
386#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
387
388/* CONF_DEBUG_SEL_TST_0 */
389#define OMAP4_MODE_SHIFT 0
390#define OMAP4_MODE_MASK (0xf << 0)
391
392#endif
diff --git a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
deleted file mode 100644
index c88420de1151..000000000000
--- a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
+++ /dev/null
@@ -1,1409 +0,0 @@
1/*
2 * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8
32#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc
33#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0
34#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4
35#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8
36#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec
37#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0
38#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0
39#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4
40#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8
41#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac
42#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0
43#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4
44#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8
45#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc
46#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0
47#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4
48#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8
49#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
50#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604
51#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
52#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c
53#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610
54#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614
55#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
56#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
57#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620
58#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
59#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
60#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c
61#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630
62#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634
63#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638
64#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c
65#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640
66#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644
67#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648
68#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c
69#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650
70#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654
71#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658
72#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c
73#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660
74#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664
75#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668
76#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700
77#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704
78#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708
79#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c
80
81/* Registers shifts and masks */
82
83/* IP_REVISION */
84#define OMAP4_IP_REV_SCHEME_SHIFT 30
85#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
86#define OMAP4_IP_REV_FUNC_SHIFT 16
87#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
88#define OMAP4_IP_REV_RTL_SHIFT 11
89#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
90#define OMAP4_IP_REV_MAJOR_SHIFT 8
91#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
92#define OMAP4_IP_REV_CUSTOM_SHIFT 6
93#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
94#define OMAP4_IP_REV_MINOR_SHIFT 0
95#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
96
97/* IP_HWINFO */
98#define OMAP4_IP_HWINFO_SHIFT 0
99#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
100
101/* IP_SYSCONFIG */
102#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
103#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
104
105/* PADCONF_WAKEUPEVENT_0 */
106#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31
107#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
108#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30
109#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
110#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29
111#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
112#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28
113#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
114#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27
115#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
116#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26
117#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
118#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25
119#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
120#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24
121#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
122#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23
123#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
124#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22
125#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
126#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21
127#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
128#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20
129#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
130#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19
131#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
132#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18
133#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
134#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17
135#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
136#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16
137#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
138#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15
139#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
140#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14
141#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
142#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13
143#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
144#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12
145#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
146#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11
147#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
148#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10
149#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
150#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9
151#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
152#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8
153#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
154#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7
155#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
156#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6
157#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
158#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5
159#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
160#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4
161#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
162#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3
163#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
164#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2
165#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
166#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1
167#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
168#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0
169#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
170
171/* PADCONF_WAKEUPEVENT_1 */
172#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31
173#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
174#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30
175#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
176#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29
177#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
178#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28
179#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
180#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27
181#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
182#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26
183#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
184#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25
185#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
186#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24
187#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
188#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23
189#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
190#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22
191#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
192#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21
193#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
194#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20
195#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
196#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19
197#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
198#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18
199#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
200#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17
201#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
202#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16
203#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
204#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15
205#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
206#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14
207#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
208#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13
209#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
210#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12
211#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
212#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11
213#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
214#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10
215#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
216#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9
217#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
218#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8
219#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
220#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7
221#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
222#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6
223#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
224#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5
225#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
226#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4
227#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
228#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3
229#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
230#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2
231#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
232#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1
233#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
234#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0
235#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
236
237/* PADCONF_WAKEUPEVENT_2 */
238#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31
239#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
240#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30
241#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
242#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29
243#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
244#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28
245#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
246#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27
247#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
248#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26
249#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
250#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25
251#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
252#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24
253#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
254#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23
255#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
256#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22
257#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
258#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21
259#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
260#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20
261#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
262#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19
263#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
264#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18
265#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
266#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17
267#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
268#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16
269#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
270#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15
271#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
272#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14
273#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
274#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13
275#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
276#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
277#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
278#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
279#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
280#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
281#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
282#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
283#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
284#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
285#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
286#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
287#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
288#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
289#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
290#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
291#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
292#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4
293#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
294#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3
295#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
296#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2
297#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
298#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
299#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
300#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0
301#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
302
303/* PADCONF_WAKEUPEVENT_3 */
304#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31
305#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
306#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30
307#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
308#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29
309#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
310#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28
311#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
312#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27
313#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
314#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26
315#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
316#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25
317#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
318#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24
319#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
320#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23
321#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
322#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22
323#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
324#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21
325#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
326#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20
327#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
328#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19
329#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
330#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18
331#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
332#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17
333#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
334#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16
335#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
336#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
337#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
338#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
339#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
340#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13
341#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
342#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12
343#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
344#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11
345#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
346#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10
347#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
348#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9
349#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
350#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8
351#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
352#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7
353#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
354#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6
355#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
356#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5
357#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
358#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4
359#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
360#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3
361#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
362#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2
363#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
364#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1
365#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
366#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0
367#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
368
369/* PADCONF_WAKEUPEVENT_4 */
370#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31
371#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
372#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30
373#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
374#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29
375#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
376#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28
377#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
378#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
379#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
380#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
381#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
382#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
383#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
384#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
385#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
386#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
387#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
388#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
389#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
390#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
391#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
392#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
393#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
394#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19
395#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
396#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18
397#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
398#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17
399#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
400#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16
401#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
402#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
403#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
404#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
405#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
406#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13
407#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
408#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12
409#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
410#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11
411#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
412#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10
413#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
414#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9
415#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
416#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8
417#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
418#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7
419#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
420#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6
421#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
422#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5
423#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
424#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4
425#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
426#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3
427#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
428#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2
429#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
430#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1
431#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
432#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0
433#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
434
435/* PADCONF_WAKEUPEVENT_5 */
436#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31
437#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
438#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30
439#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
440#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29
441#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
442#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28
443#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
444#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27
445#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
446#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26
447#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
448#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25
449#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
450#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24
451#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
452#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23
453#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
454#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22
455#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
456#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21
457#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
458#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20
459#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
460#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19
461#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
462#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18
463#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
464#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17
465#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
466#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16
467#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
468#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15
469#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
470#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14
471#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
472#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13
473#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
474#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12
475#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
476#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11
477#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
478#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
479#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
480#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9
481#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
482#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8
483#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
484#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7
485#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
486#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6
487#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
488#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5
489#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
490#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4
491#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
492#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3
493#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
494#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2
495#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
496#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1
497#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
498#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0
499#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
500
501/* PADCONF_WAKEUPEVENT_6 */
502#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7
503#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
504#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6
505#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
506#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5
507#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
508#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4
509#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
510#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3
511#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
512#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2
513#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
514#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1
515#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
516#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0
517#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
518
519/* CONTROL_PADCONF_GLOBAL */
520#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31
521#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31)
522
523/* CONTROL_PADCONF_MODE */
524#define OMAP4_VDDS_DV_BANK0_SHIFT 31
525#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31)
526#define OMAP4_VDDS_DV_BANK1_SHIFT 30
527#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30)
528#define OMAP4_VDDS_DV_BANK3_SHIFT 29
529#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29)
530#define OMAP4_VDDS_DV_BANK4_SHIFT 28
531#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28)
532#define OMAP4_VDDS_DV_BANK5_SHIFT 27
533#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27)
534#define OMAP4_VDDS_DV_BANK6_SHIFT 26
535#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26)
536#define OMAP4_VDDS_DV_C2C_SHIFT 25
537#define OMAP4_VDDS_DV_C2C_MASK (1 << 25)
538#define OMAP4_VDDS_DV_CAM_SHIFT 24
539#define OMAP4_VDDS_DV_CAM_MASK (1 << 24)
540#define OMAP4_VDDS_DV_GPMC_SHIFT 23
541#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23)
542#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22
543#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22)
544
545/* CONTROL_SMART1IO_PADCONF_0 */
546#define OMAP4_ABE_DR0_SC_SHIFT 30
547#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30)
548#define OMAP4_CAM_DR0_SC_SHIFT 28
549#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28)
550#define OMAP4_FREF_DR2_SC_SHIFT 26
551#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26)
552#define OMAP4_FREF_DR3_SC_SHIFT 24
553#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24)
554#define OMAP4_GPIO_DR8_SC_SHIFT 22
555#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22)
556#define OMAP4_GPIO_DR9_SC_SHIFT 20
557#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20)
558#define OMAP4_GPMC_DR2_SC_SHIFT 18
559#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18)
560#define OMAP4_GPMC_DR3_SC_SHIFT 16
561#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16)
562#define OMAP4_GPMC_DR6_SC_SHIFT 14
563#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14)
564#define OMAP4_HDMI_DR0_SC_SHIFT 12
565#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12)
566#define OMAP4_MCSPI1_DR0_SC_SHIFT 10
567#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10)
568#define OMAP4_UART1_DR0_SC_SHIFT 8
569#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8)
570#define OMAP4_UART3_DR0_SC_SHIFT 6
571#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6)
572#define OMAP4_UART3_DR1_SC_SHIFT 4
573#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4)
574#define OMAP4_UNIPRO_DR0_SC_SHIFT 2
575#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2)
576#define OMAP4_UNIPRO_DR1_SC_SHIFT 0
577#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0)
578
579/* CONTROL_SMART1IO_PADCONF_1 */
580#define OMAP4_ABE_DR0_LB_SHIFT 30
581#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30)
582#define OMAP4_CAM_DR0_LB_SHIFT 28
583#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28)
584#define OMAP4_FREF_DR2_LB_SHIFT 26
585#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26)
586#define OMAP4_FREF_DR3_LB_SHIFT 24
587#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24)
588#define OMAP4_GPIO_DR8_LB_SHIFT 22
589#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22)
590#define OMAP4_GPIO_DR9_LB_SHIFT 20
591#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20)
592#define OMAP4_GPMC_DR2_LB_SHIFT 18
593#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18)
594#define OMAP4_GPMC_DR3_LB_SHIFT 16
595#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16)
596#define OMAP4_GPMC_DR6_LB_SHIFT 14
597#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14)
598#define OMAP4_HDMI_DR0_LB_SHIFT 12
599#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12)
600#define OMAP4_MCSPI1_DR0_LB_SHIFT 10
601#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10)
602#define OMAP4_UART1_DR0_LB_SHIFT 8
603#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8)
604#define OMAP4_UART3_DR0_LB_SHIFT 6
605#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6)
606#define OMAP4_UART3_DR1_LB_SHIFT 4
607#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4)
608#define OMAP4_UNIPRO_DR0_LB_SHIFT 2
609#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2)
610#define OMAP4_UNIPRO_DR1_LB_SHIFT 0
611#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0)
612
613/* CONTROL_SMART2IO_PADCONF_0 */
614#define OMAP4_C2C_DR0_LB_SHIFT 31
615#define OMAP4_C2C_DR0_LB_MASK (1 << 31)
616#define OMAP4_DPM_DR1_LB_SHIFT 30
617#define OMAP4_DPM_DR1_LB_MASK (1 << 30)
618#define OMAP4_DPM_DR2_LB_SHIFT 29
619#define OMAP4_DPM_DR2_LB_MASK (1 << 29)
620#define OMAP4_DPM_DR3_LB_SHIFT 28
621#define OMAP4_DPM_DR3_LB_MASK (1 << 28)
622#define OMAP4_GPIO_DR0_LB_SHIFT 27
623#define OMAP4_GPIO_DR0_LB_MASK (1 << 27)
624#define OMAP4_GPIO_DR1_LB_SHIFT 26
625#define OMAP4_GPIO_DR1_LB_MASK (1 << 26)
626#define OMAP4_GPIO_DR10_LB_SHIFT 25
627#define OMAP4_GPIO_DR10_LB_MASK (1 << 25)
628#define OMAP4_GPIO_DR2_LB_SHIFT 24
629#define OMAP4_GPIO_DR2_LB_MASK (1 << 24)
630#define OMAP4_GPMC_DR0_LB_SHIFT 23
631#define OMAP4_GPMC_DR0_LB_MASK (1 << 23)
632#define OMAP4_GPMC_DR1_LB_SHIFT 22
633#define OMAP4_GPMC_DR1_LB_MASK (1 << 22)
634#define OMAP4_GPMC_DR4_LB_SHIFT 21
635#define OMAP4_GPMC_DR4_LB_MASK (1 << 21)
636#define OMAP4_GPMC_DR5_LB_SHIFT 20
637#define OMAP4_GPMC_DR5_LB_MASK (1 << 20)
638#define OMAP4_GPMC_DR7_LB_SHIFT 19
639#define OMAP4_GPMC_DR7_LB_MASK (1 << 19)
640#define OMAP4_HSI2_DR0_LB_SHIFT 18
641#define OMAP4_HSI2_DR0_LB_MASK (1 << 18)
642#define OMAP4_HSI2_DR1_LB_SHIFT 17
643#define OMAP4_HSI2_DR1_LB_MASK (1 << 17)
644#define OMAP4_HSI2_DR2_LB_SHIFT 16
645#define OMAP4_HSI2_DR2_LB_MASK (1 << 16)
646#define OMAP4_KPD_DR0_LB_SHIFT 15
647#define OMAP4_KPD_DR0_LB_MASK (1 << 15)
648#define OMAP4_KPD_DR1_LB_SHIFT 14
649#define OMAP4_KPD_DR1_LB_MASK (1 << 14)
650#define OMAP4_PDM_DR0_LB_SHIFT 13
651#define OMAP4_PDM_DR0_LB_MASK (1 << 13)
652#define OMAP4_SDMMC2_DR0_LB_SHIFT 12
653#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12)
654#define OMAP4_SDMMC3_DR0_LB_SHIFT 11
655#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11)
656#define OMAP4_SDMMC4_DR0_LB_SHIFT 10
657#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10)
658#define OMAP4_SDMMC4_DR1_LB_SHIFT 9
659#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9)
660#define OMAP4_SPI3_DR0_LB_SHIFT 8
661#define OMAP4_SPI3_DR0_LB_MASK (1 << 8)
662#define OMAP4_SPI3_DR1_LB_SHIFT 7
663#define OMAP4_SPI3_DR1_LB_MASK (1 << 7)
664#define OMAP4_UART3_DR2_LB_SHIFT 6
665#define OMAP4_UART3_DR2_LB_MASK (1 << 6)
666#define OMAP4_UART3_DR3_LB_SHIFT 5
667#define OMAP4_UART3_DR3_LB_MASK (1 << 5)
668#define OMAP4_UART3_DR4_LB_SHIFT 4
669#define OMAP4_UART3_DR4_LB_MASK (1 << 4)
670#define OMAP4_UART3_DR5_LB_SHIFT 3
671#define OMAP4_UART3_DR5_LB_MASK (1 << 3)
672#define OMAP4_USBA0_DR1_LB_SHIFT 2
673#define OMAP4_USBA0_DR1_LB_MASK (1 << 2)
674#define OMAP4_USBA_DR2_LB_SHIFT 1
675#define OMAP4_USBA_DR2_LB_MASK (1 << 1)
676
677/* CONTROL_SMART2IO_PADCONF_1 */
678#define OMAP4_USBB1_DR0_LB_SHIFT 31
679#define OMAP4_USBB1_DR0_LB_MASK (1 << 31)
680#define OMAP4_USBB2_DR0_LB_SHIFT 30
681#define OMAP4_USBB2_DR0_LB_MASK (1 << 30)
682#define OMAP4_USBA0_DR0_LB_SHIFT 29
683#define OMAP4_USBA0_DR0_LB_MASK (1 << 29)
684
685/* CONTROL_SMART3IO_PADCONF_0 */
686#define OMAP4_DMIC_DR0_MB_SHIFT 30
687#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30)
688#define OMAP4_GPIO_DR3_MB_SHIFT 28
689#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28)
690#define OMAP4_GPIO_DR4_MB_SHIFT 26
691#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26)
692#define OMAP4_GPIO_DR5_MB_SHIFT 24
693#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24)
694#define OMAP4_GPIO_DR6_MB_SHIFT 22
695#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22)
696#define OMAP4_HSI_DR1_MB_SHIFT 20
697#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20)
698#define OMAP4_HSI_DR2_MB_SHIFT 18
699#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18)
700#define OMAP4_HSI_DR3_MB_SHIFT 16
701#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16)
702#define OMAP4_MCBSP2_DR0_MB_SHIFT 14
703#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14)
704#define OMAP4_MCSPI4_DR0_MB_SHIFT 12
705#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12)
706#define OMAP4_MCSPI4_DR1_MB_SHIFT 10
707#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10)
708#define OMAP4_SDMMC3_DR0_MB_SHIFT 8
709#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8)
710#define OMAP4_SPI2_DR0_MB_SHIFT 0
711#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0)
712
713/* CONTROL_SMART3IO_PADCONF_1 */
714#define OMAP4_SPI2_DR1_MB_SHIFT 30
715#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30)
716#define OMAP4_SPI2_DR2_MB_SHIFT 28
717#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28)
718#define OMAP4_UART2_DR0_MB_SHIFT 26
719#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26)
720#define OMAP4_UART2_DR1_MB_SHIFT 24
721#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24)
722#define OMAP4_UART4_DR0_MB_SHIFT 22
723#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22)
724#define OMAP4_HSI_DR0_MB_SHIFT 20
725#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20)
726
727/* CONTROL_SMART3IO_PADCONF_2 */
728#define OMAP4_DMIC_DR0_LB_SHIFT 31
729#define OMAP4_DMIC_DR0_LB_MASK (1 << 31)
730#define OMAP4_GPIO_DR3_LB_SHIFT 30
731#define OMAP4_GPIO_DR3_LB_MASK (1 << 30)
732#define OMAP4_GPIO_DR4_LB_SHIFT 29
733#define OMAP4_GPIO_DR4_LB_MASK (1 << 29)
734#define OMAP4_GPIO_DR5_LB_SHIFT 28
735#define OMAP4_GPIO_DR5_LB_MASK (1 << 28)
736#define OMAP4_GPIO_DR6_LB_SHIFT 27
737#define OMAP4_GPIO_DR6_LB_MASK (1 << 27)
738#define OMAP4_HSI_DR1_LB_SHIFT 26
739#define OMAP4_HSI_DR1_LB_MASK (1 << 26)
740#define OMAP4_HSI_DR2_LB_SHIFT 25
741#define OMAP4_HSI_DR2_LB_MASK (1 << 25)
742#define OMAP4_HSI_DR3_LB_SHIFT 24
743#define OMAP4_HSI_DR3_LB_MASK (1 << 24)
744#define OMAP4_MCBSP2_DR0_LB_SHIFT 23
745#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23)
746#define OMAP4_MCSPI4_DR0_LB_SHIFT 22
747#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22)
748#define OMAP4_MCSPI4_DR1_LB_SHIFT 21
749#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21)
750#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18
751#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18)
752#define OMAP4_SPI2_DR0_LB_SHIFT 16
753#define OMAP4_SPI2_DR0_LB_MASK (1 << 16)
754#define OMAP4_SPI2_DR1_LB_SHIFT 15
755#define OMAP4_SPI2_DR1_LB_MASK (1 << 15)
756#define OMAP4_SPI2_DR2_LB_SHIFT 14
757#define OMAP4_SPI2_DR2_LB_MASK (1 << 14)
758#define OMAP4_UART2_DR0_LB_SHIFT 13
759#define OMAP4_UART2_DR0_LB_MASK (1 << 13)
760#define OMAP4_UART2_DR1_LB_SHIFT 12
761#define OMAP4_UART2_DR1_LB_MASK (1 << 12)
762#define OMAP4_UART4_DR0_LB_SHIFT 11
763#define OMAP4_UART4_DR0_LB_MASK (1 << 11)
764#define OMAP4_HSI_DR0_LB_SHIFT 10
765#define OMAP4_HSI_DR0_LB_MASK (1 << 10)
766
767/* CONTROL_USBB_HSIC */
768#define OMAP4_USBB2_DR1_SR_SHIFT 30
769#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)
770#define OMAP4_USBB2_DR1_I_SHIFT 27
771#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27)
772#define OMAP4_USBB1_DR1_SR_SHIFT 25
773#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25)
774#define OMAP4_USBB1_DR1_I_SHIFT 22
775#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22)
776#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20
777#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20)
778#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18
779#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18)
780#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16
781#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16)
782#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14
783#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14)
784#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13
785#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13)
786#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11
787#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11)
788#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10
789#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10)
790#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8
791#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8)
792#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7
793#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7)
794#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5
795#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5)
796#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4
797#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4)
798#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2
799#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2)
800
801/* CONTROL_SLIMBUS */
802#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30
803#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30)
804#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28
805#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28)
806#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26
807#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26)
808#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24
809#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24)
810#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22
811#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22)
812#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20
813#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20)
814#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19
815#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19)
816#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18
817#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18)
818
819/* CONTROL_PBIASLITE */
820#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31
821#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31)
822#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30
823#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30)
824#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29
825#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29)
826#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28
827#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28)
828#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27
829#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27)
830#define OMAP4_MMC1_PWRDNZ_SHIFT 26
831#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
832#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25
833#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25)
834#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24
835#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24)
836#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23
837#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
838#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22
839#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
840#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21
841#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
842#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20
843#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20)
844
845/* CONTROL_I2C_0 */
846#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31
847#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31)
848#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29
849#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29)
850#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28
851#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28)
852#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27
853#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27)
854#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25
855#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25)
856#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24
857#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24)
858#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23
859#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23)
860#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21
861#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21)
862#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20
863#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20)
864#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19
865#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19)
866#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17
867#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17)
868#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16
869#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16)
870#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15
871#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15)
872#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13
873#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13)
874#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12
875#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12)
876#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11
877#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11)
878#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9
879#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9)
880#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8
881#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8)
882#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7
883#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7)
884#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5
885#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5)
886#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4
887#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4)
888#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3
889#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3)
890#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1
891#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1)
892#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0
893#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0)
894
895/* CONTROL_CAMERA_RX */
896#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31
897#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31)
898#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
899#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
900#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
901#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
902#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22
903#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22)
904#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
905#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
906#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
907#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
908#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
909#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
910#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
911#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
912
913/* CONTROL_AVDAC */
914#define OMAP4_AVDAC_ACEN_SHIFT 31
915#define OMAP4_AVDAC_ACEN_MASK (1 << 31)
916#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30
917#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30)
918#define OMAP4_AVDAC_INPUTINV_SHIFT 29
919#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29)
920#define OMAP4_AVDAC_CTL_SHIFT 13
921#define OMAP4_AVDAC_CTL_MASK (0xffff << 13)
922#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12
923#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12)
924
925/* CONTROL_HDMI_TX_PHY */
926#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31
927#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31)
928#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30
929#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30)
930#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29
931#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29)
932#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28
933#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28)
934
935/* CONTROL_MMC2 */
936#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31
937#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31)
938
939/* CONTROL_DSIPHY */
940#define OMAP4_DSI2_LANEENABLE_SHIFT 29
941#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
942#define OMAP4_DSI1_LANEENABLE_SHIFT 24
943#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
944#define OMAP4_DSI1_PIPD_SHIFT 19
945#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
946#define OMAP4_DSI2_PIPD_SHIFT 14
947#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
948
949/* CONTROL_MCBSPLP */
950#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
951#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31)
952#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30
953#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30)
954#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29
955#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29)
956
957/* CONTROL_USB2PHYCORE */
958#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31
959#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31)
960#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30
961#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30)
962#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29
963#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29)
964#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28
965#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28)
966#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27
967#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27)
968#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26
969#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26)
970#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25
971#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25)
972#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24
973#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24)
974#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21
975#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21)
976#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20
977#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20)
978#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19
979#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19)
980#define OMAP4_USB2PHY_DATADET_SHIFT 18
981#define OMAP4_USB2PHY_DATADET_MASK (1 << 18)
982#define OMAP4_USB2PHY_SINKONDP_SHIFT 17
983#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17)
984#define OMAP4_USB2PHY_SRCONDM_SHIFT 16
985#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16)
986#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15
987#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15)
988#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14
989#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14)
990#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13
991#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13)
992#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12
993#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12)
994#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11
995#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11)
996#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10
997#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10)
998#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9
999#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9)
1000#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8
1001#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8)
1002#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7
1003#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7)
1004#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6
1005#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6)
1006#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5
1007#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5)
1008
1009/* CONTROL_I2C_1 */
1010#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31
1011#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31)
1012#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29
1013#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29)
1014#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28
1015#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
1016#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27
1017#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27)
1018#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25
1019#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25)
1020#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24
1021#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
1022#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23
1023#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23)
1024#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22
1025#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22)
1026#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21
1027#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21)
1028#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20
1029#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20)
1030
1031/* CONTROL_MMC1 */
1032#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31
1033#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
1034#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30
1035#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
1036#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29
1037#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
1038#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28
1039#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
1040#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27
1041#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
1042#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26
1043#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
1044#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25
1045#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
1046#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24
1047#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24)
1048#define OMAP4_USB_FD_CDEN_SHIFT 23
1049#define OMAP4_USB_FD_CDEN_MASK (1 << 23)
1050#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22
1051#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22)
1052#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21
1053#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21)
1054
1055/* CONTROL_HSI */
1056#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31
1057#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31)
1058#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30
1059#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30)
1060#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29
1061#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29)
1062#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28
1063#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28)
1064
1065/* CONTROL_USB */
1066#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31
1067#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31)
1068#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30
1069#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30)
1070
1071/* CONTROL_HDQ */
1072#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31
1073#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31)
1074
1075/* CONTROL_LPDDR2IO1_0 */
1076#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30
1077#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30)
1078#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27
1079#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27)
1080#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25
1081#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25)
1082#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22
1083#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22)
1084#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19
1085#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19)
1086#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17
1087#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17)
1088#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14
1089#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14)
1090#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11
1091#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11)
1092#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9
1093#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9)
1094#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6
1095#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6)
1096#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3
1097#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3)
1098#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1
1099#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1)
1100
1101/* CONTROL_LPDDR2IO1_1 */
1102#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30
1103#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30)
1104#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27
1105#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27)
1106#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25
1107#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25)
1108#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22
1109#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22)
1110#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19
1111#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19)
1112#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17
1113#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17)
1114#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14
1115#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14)
1116#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11
1117#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11)
1118#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9
1119#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9)
1120#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6
1121#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6)
1122#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3
1123#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3)
1124#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1
1125#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1)
1126
1127/* CONTROL_LPDDR2IO1_2 */
1128#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30
1129#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30)
1130#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27
1131#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27)
1132#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25
1133#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25)
1134#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22
1135#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22)
1136#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19
1137#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19)
1138#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17
1139#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17)
1140#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14
1141#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14)
1142#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11
1143#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11)
1144#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9
1145#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9)
1146
1147/* CONTROL_LPDDR2IO1_3 */
1148#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31
1149#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31)
1150#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30
1151#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30)
1152#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29
1153#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29)
1154#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28
1155#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28)
1156#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27
1157#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27)
1158#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26
1159#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26)
1160#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25
1161#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25)
1162#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24
1163#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24)
1164#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23
1165#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
1166#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22
1167#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
1168#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21
1169#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21)
1170#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20
1171#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20)
1172#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19
1173#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
1174#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18
1175#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
1176#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17
1177#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17)
1178#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16
1179#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16)
1180#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15
1181#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15)
1182#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14
1183#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14)
1184#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13
1185#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13)
1186#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12
1187#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12)
1188
1189/* CONTROL_LPDDR2IO2_0 */
1190#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30
1191#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30)
1192#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27
1193#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27)
1194#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25
1195#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25)
1196#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22
1197#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22)
1198#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19
1199#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19)
1200#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17
1201#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17)
1202#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14
1203#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14)
1204#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11
1205#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11)
1206#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9
1207#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9)
1208#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6
1209#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6)
1210#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3
1211#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3)
1212#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1
1213#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1)
1214
1215/* CONTROL_LPDDR2IO2_1 */
1216#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30
1217#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30)
1218#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27
1219#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27)
1220#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25
1221#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25)
1222#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22
1223#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22)
1224#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19
1225#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19)
1226#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17
1227#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17)
1228#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14
1229#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14)
1230#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11
1231#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11)
1232#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9
1233#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9)
1234#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6
1235#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6)
1236#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3
1237#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3)
1238#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1
1239#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1)
1240
1241/* CONTROL_LPDDR2IO2_2 */
1242#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30
1243#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30)
1244#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27
1245#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27)
1246#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25
1247#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25)
1248#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22
1249#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22)
1250#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19
1251#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19)
1252#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17
1253#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17)
1254#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14
1255#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14)
1256#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11
1257#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11)
1258#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9
1259#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9)
1260
1261/* CONTROL_LPDDR2IO2_3 */
1262#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31
1263#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31)
1264#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30
1265#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30)
1266#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29
1267#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29)
1268#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28
1269#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28)
1270#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27
1271#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27)
1272#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26
1273#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26)
1274#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25
1275#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25)
1276#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24
1277#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24)
1278#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23
1279#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
1280#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22
1281#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
1282#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21
1283#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21)
1284#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20
1285#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20)
1286#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19
1287#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
1288#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18
1289#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
1290#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17
1291#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17)
1292#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16
1293#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16)
1294#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15
1295#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15)
1296#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14
1297#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14)
1298#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13
1299#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13)
1300#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12
1301#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12)
1302
1303/* CONTROL_BUS_HOLD */
1304#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31
1305#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31)
1306#define OMAP4_MCSPI1_CS3_EN_SHIFT 30
1307#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30)
1308
1309/* CONTROL_C2C */
1310#define OMAP4_MIRROR_MODE_EN_SHIFT 31
1311#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31)
1312#define OMAP4_C2C_SPARE_SHIFT 24
1313#define OMAP4_C2C_SPARE_MASK (0x7f << 24)
1314
1315/* CORE_CONTROL_SPARE_RW */
1316#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0
1317#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
1318
1319/* CORE_CONTROL_SPARE_R */
1320#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0
1321#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0)
1322
1323/* CORE_CONTROL_SPARE_R_C0 */
1324#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31
1325#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31)
1326#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30
1327#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30)
1328#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29
1329#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29)
1330#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28
1331#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28)
1332#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27
1333#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27)
1334#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26
1335#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26)
1336#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25
1337#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25)
1338#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24
1339#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24)
1340
1341/* CONTROL_EFUSE_1 */
1342#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24
1343#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24)
1344#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16
1345#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16)
1346#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8
1347#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8)
1348#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0
1349#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0)
1350
1351/* CONTROL_EFUSE_2 */
1352#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31
1353#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31)
1354#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30
1355#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30)
1356#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29
1357#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29)
1358#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28
1359#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28)
1360#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27
1361#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27)
1362#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26
1363#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26)
1364#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25
1365#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25)
1366#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24
1367#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24)
1368#define OMAP4_LPDDR2_PTV_N1_SHIFT 23
1369#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23)
1370#define OMAP4_LPDDR2_PTV_N2_SHIFT 22
1371#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22)
1372#define OMAP4_LPDDR2_PTV_N3_SHIFT 21
1373#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21)
1374#define OMAP4_LPDDR2_PTV_N4_SHIFT 20
1375#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20)
1376#define OMAP4_LPDDR2_PTV_N5_SHIFT 19
1377#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19)
1378#define OMAP4_LPDDR2_PTV_P1_SHIFT 18
1379#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18)
1380#define OMAP4_LPDDR2_PTV_P2_SHIFT 17
1381#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17)
1382#define OMAP4_LPDDR2_PTV_P3_SHIFT 16
1383#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16)
1384#define OMAP4_LPDDR2_PTV_P4_SHIFT 15
1385#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15)
1386#define OMAP4_LPDDR2_PTV_P5_SHIFT 14
1387#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14)
1388
1389/* CONTROL_EFUSE_3 */
1390#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24
1391#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24)
1392#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16
1393#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16)
1394#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8
1395#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8)
1396#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0
1397#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0)
1398
1399/* CONTROL_EFUSE_4 */
1400#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24
1401#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24)
1402#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16
1403#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16)
1404#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8
1405#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8)
1406#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0
1407#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0)
1408
1409#endif
diff --git a/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
deleted file mode 100644
index 17c9b37042c0..000000000000
--- a/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
+++ /dev/null
@@ -1,236 +0,0 @@
1/*
2 * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
32#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
33#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
34#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
35#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
36#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
37#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
38#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
39#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
40#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
41#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
42#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
43
44/* Registers shifts and masks */
45
46/* IP_REVISION */
47#define OMAP4_IP_REV_SCHEME_SHIFT 30
48#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
49#define OMAP4_IP_REV_FUNC_SHIFT 16
50#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
51#define OMAP4_IP_REV_RTL_SHIFT 11
52#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
53#define OMAP4_IP_REV_MAJOR_SHIFT 8
54#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
55#define OMAP4_IP_REV_CUSTOM_SHIFT 6
56#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
57#define OMAP4_IP_REV_MINOR_SHIFT 0
58#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
59
60/* IP_HWINFO */
61#define OMAP4_IP_HWINFO_SHIFT 0
62#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
63
64/* IP_SYSCONFIG */
65#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
66#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
67
68/* PADCONF_WAKEUPEVENT_0 */
69#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
70#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
71#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
72#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
73#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
74#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
75#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
76#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
77#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
78#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
79#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
80#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
81#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
82#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
83#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
84#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
85#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
86#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
87#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
88#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
89#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
90#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
91#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
92#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
93#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
94#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
95#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
96#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
97#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
98#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
99#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
100#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
101#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
102#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
103#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
104#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
105#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
106#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
107#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
108#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
109#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
110#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
111#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
112#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
113#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
114#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
115#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
116#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
117#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
118#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
119
120/* CONTROL_SMART1NOPMIO_PADCONF_0 */
121#define OMAP4_FREF_DR0_SC_SHIFT 30
122#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
123#define OMAP4_FREF_DR1_SC_SHIFT 28
124#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
125#define OMAP4_FREF_DR4_SC_SHIFT 26
126#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
127#define OMAP4_FREF_DR5_SC_SHIFT 24
128#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
129#define OMAP4_FREF_DR6_SC_SHIFT 22
130#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
131#define OMAP4_FREF_DR7_SC_SHIFT 20
132#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
133#define OMAP4_GPIO_DR7_SC_SHIFT 18
134#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
135#define OMAP4_DPM_DR0_SC_SHIFT 14
136#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
137#define OMAP4_SIM_DR0_SC_SHIFT 12
138#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
139
140/* CONTROL_SMART1NOPMIO_PADCONF_1 */
141#define OMAP4_FREF_DR0_LB_SHIFT 30
142#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
143#define OMAP4_FREF_DR1_LB_SHIFT 28
144#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
145#define OMAP4_FREF_DR4_LB_SHIFT 26
146#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
147#define OMAP4_FREF_DR5_LB_SHIFT 24
148#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
149#define OMAP4_FREF_DR6_LB_SHIFT 22
150#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
151#define OMAP4_FREF_DR7_LB_SHIFT 20
152#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
153#define OMAP4_GPIO_DR7_LB_SHIFT 18
154#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
155#define OMAP4_DPM_DR0_LB_SHIFT 14
156#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
157#define OMAP4_SIM_DR0_LB_SHIFT 12
158#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
159
160/* CONTROL_PADCONF_MODE */
161#define OMAP4_VDDS_DV_FREF_SHIFT 31
162#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
163#define OMAP4_VDDS_DV_BANK2_SHIFT 30
164#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
165
166/* CONTROL_XTAL_OSCILLATOR */
167#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
168#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
169#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
170#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
171
172/* CONTROL_USIMIO */
173#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
174#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
175#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
176#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
177#define OMAP4_USIM_PWRDNZ_SHIFT 28
178#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
179
180/* CONTROL_I2C_2 */
181#define OMAP4_SR_SDA_GLFENB_SHIFT 31
182#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
183#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
184#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
185#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
186#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
187#define OMAP4_SR_SCL_GLFENB_SHIFT 27
188#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
189#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
190#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
191#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
192#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
193
194/* CONTROL_JTAG */
195#define OMAP4_JTAG_NTRST_EN_SHIFT 31
196#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
197#define OMAP4_JTAG_TCK_EN_SHIFT 30
198#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
199#define OMAP4_JTAG_RTCK_EN_SHIFT 29
200#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
201#define OMAP4_JTAG_TDI_EN_SHIFT 28
202#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
203#define OMAP4_JTAG_TDO_EN_SHIFT 27
204#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
205
206/* CONTROL_SYS */
207#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
208#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
209
210/* WKUP_CONTROL_SPARE_RW */
211#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
212#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
213
214/* WKUP_CONTROL_SPARE_R */
215#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
216#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
217
218/* WKUP_CONTROL_SPARE_R_C0 */
219#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
220#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
221#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
222#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
223#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
224#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
225#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
226#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
227#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
228#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
229#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
230#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
231#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
232#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
233#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
234#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
235
236#endif
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 6d7ba37e2257..cd5f3a0b97bd 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -28,11 +28,8 @@
28#include <linux/bitops.h> 28#include <linux/bitops.h>
29#include <linux/clkdev.h> 29#include <linux/clkdev.h>
30 30
31#include "soc.h"
32#include "clockdomain.h" 31#include "clockdomain.h"
33#include "clock.h" 32#include "clock.h"
34#include "cm2xxx_3xxx.h"
35#include "cm-regbits-34xx.h"
36 33
37/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ 34/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
38#define DPLL_AUTOIDLE_DISABLE 0x0 35#define DPLL_AUTOIDLE_DISABLE 0x0
@@ -310,7 +307,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
310 * Set jitter correction. Jitter correction applicable for OMAP343X 307 * Set jitter correction. Jitter correction applicable for OMAP343X
311 * only since freqsel field is no longer present on other devices. 308 * only since freqsel field is no longer present on other devices.
312 */ 309 */
313 if (cpu_is_omap343x()) { 310 if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
314 v = omap2_clk_readl(clk, dd->control_reg); 311 v = omap2_clk_readl(clk, dd->control_reg);
315 v &= ~dd->freqsel_mask; 312 v &= ~dd->freqsel_mask;
316 v |= freqsel << __ffs(dd->freqsel_mask); 313 v |= freqsel << __ffs(dd->freqsel_mask);
@@ -512,7 +509,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
512 return -EINVAL; 509 return -EINVAL;
513 510
514 /* Freqsel is available only on OMAP343X devices */ 511 /* Freqsel is available only on OMAP343X devices */
515 if (cpu_is_omap343x()) { 512 if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
516 freqsel = _omap3_dpll_compute_freqsel(clk, 513 freqsel = _omap3_dpll_compute_freqsel(clk,
517 dd->last_rounded_n); 514 dd->last_rounded_n);
518 WARN_ON(!freqsel); 515 WARN_ON(!freqsel);
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 52f9438b92f2..4613f1e86988 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -15,10 +15,7 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/bitops.h> 16#include <linux/bitops.h>
17 17
18#include "soc.h"
19#include "clock.h" 18#include "clock.h"
20#include "clock44xx.h"
21#include "cm-regbits-44xx.h"
22 19
23/* 20/*
24 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that 21 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
@@ -29,13 +26,23 @@
29#define OMAP4_DPLL_LP_FINT_MAX 1000000 26#define OMAP4_DPLL_LP_FINT_MAX 1000000
30#define OMAP4_DPLL_LP_FOUT_MAX 100000000 27#define OMAP4_DPLL_LP_FOUT_MAX 100000000
31 28
29/*
30 * Bitfield declarations
31 */
32#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
33#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
34#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
35
36/* Static rate multiplier for OMAP4 REGM4XEN clocks */
37#define OMAP4430_REGM4XEN_MULT 4
38
32/* Supported only on OMAP4 */ 39/* Supported only on OMAP4 */
33int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) 40int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
34{ 41{
35 u32 v; 42 u32 v;
36 u32 mask; 43 u32 mask;
37 44
38 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) 45 if (!clk || !clk->clksel_reg)
39 return -EINVAL; 46 return -EINVAL;
40 47
41 mask = clk->flags & CLOCK_CLKOUTX2 ? 48 mask = clk->flags & CLOCK_CLKOUTX2 ?
@@ -54,7 +61,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
54 u32 v; 61 u32 v;
55 u32 mask; 62 u32 mask;
56 63
57 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) 64 if (!clk || !clk->clksel_reg)
58 return; 65 return;
59 66
60 mask = clk->flags & CLOCK_CLKOUTX2 ? 67 mask = clk->flags & CLOCK_CLKOUTX2 ?
@@ -72,7 +79,7 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
72 u32 v; 79 u32 v;
73 u32 mask; 80 u32 mask;
74 81
75 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) 82 if (!clk || !clk->clksel_reg)
76 return; 83 return;
77 84
78 mask = clk->flags & CLOCK_CLKOUTX2 ? 85 mask = clk->flags & CLOCK_CLKOUTX2 ?
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 8f559450c876..1fae5c123f79 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -728,6 +728,8 @@ int __init omap_clk_init(void)
728 if (!omap_clk_soc_init) 728 if (!omap_clk_soc_init)
729 return 0; 729 return 0;
730 730
731 ti_clk_init_features();
732
731 ret = of_prcm_init(); 733 ret = of_prcm_init();
732 if (!ret) 734 if (!ret)
733 ret = omap_clk_soc_init(); 735 ret = omap_clk_soc_init();
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index a5ea988ff340..d76694b7a591 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
75 75
76 /* Clear old wake-up events */ 76 /* Clear old wake-up events */
77 /* REVISIT: These write to reserved bits? */ 77 /* REVISIT: These write to reserved bits? */
78 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); 78 omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
79 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); 79 omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
80 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); 80 omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
81 81
82 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); 82 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
83 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); 83 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
@@ -104,23 +104,18 @@ no_sleep:
104 clk_enable(osc_ck); 104 clk_enable(osc_ck);
105 105
106 /* clear CORE wake-up events */ 106 /* clear CORE wake-up events */
107 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); 107 omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
108 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); 108 omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
109 109
110 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ 110 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
111 omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); 111 omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
112 112
113 /* MPU domain wake events */ 113 /* MPU domain wake events */
114 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); 114 omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
115 if (l & 0x01) 115 0x1);
116 omap2_prm_write_mod_reg(0x01, OCP_MOD,
117 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
118 if (l & 0x20)
119 omap2_prm_write_mod_reg(0x20, OCP_MOD,
120 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
121 116
122 /* Mask future PRCM-to-MPU interrupts */ 117 omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
123 omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); 118 0x20);
124 119
125 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 120 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
126 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); 121 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
@@ -148,9 +143,9 @@ static void omap2_enter_mpu_retention(void)
148 * it is in retention mode. */ 143 * it is in retention mode. */
149 if (omap2_allow_mpu_retention()) { 144 if (omap2_allow_mpu_retention()) {
150 /* REVISIT: These write to reserved bits? */ 145 /* REVISIT: These write to reserved bits? */
151 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); 146 omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
152 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); 147 omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
153 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); 148 omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
154 149
155 /* Try to enter MPU retention */ 150 /* Try to enter MPU retention */
156 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); 151 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 507d8eeaab95..3f80929a5f7e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -133,60 +133,13 @@ static void omap3_save_secure_ram_context(void)
133 } 133 }
134} 134}
135 135
136/*
137 * PRCM Interrupt Handler Helper Function
138 *
139 * The purpose of this function is to clear any wake-up events latched
140 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
141 * may occur whilst attempting to clear a PM_WKST_x register and thus
142 * set another bit in this register. A while loop is used to ensure
143 * that any peripheral wake-up events occurring while attempting to
144 * clear the PM_WKST_x are detected and cleared.
145 */
146static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
147{
148 u32 wkst, fclk, iclk, clken;
149 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
150 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
151 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
152 u16 grpsel_off = (regs == 3) ?
153 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
154 int c = 0;
155
156 wkst = omap2_prm_read_mod_reg(module, wkst_off);
157 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
158 wkst &= ~ignore_bits;
159 if (wkst) {
160 iclk = omap2_cm_read_mod_reg(module, iclk_off);
161 fclk = omap2_cm_read_mod_reg(module, fclk_off);
162 while (wkst) {
163 clken = wkst;
164 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
165 /*
166 * For USBHOST, we don't know whether HOST1 or
167 * HOST2 woke us up, so enable both f-clocks
168 */
169 if (module == OMAP3430ES2_USBHOST_MOD)
170 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
171 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
172 omap2_prm_write_mod_reg(wkst, module, wkst_off);
173 wkst = omap2_prm_read_mod_reg(module, wkst_off);
174 wkst &= ~ignore_bits;
175 c++;
176 }
177 omap2_cm_write_mod_reg(iclk, module, iclk_off);
178 omap2_cm_write_mod_reg(fclk, module, fclk_off);
179 }
180
181 return c;
182}
183
184static irqreturn_t _prcm_int_handle_io(int irq, void *unused) 136static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
185{ 137{
186 int c; 138 int c;
187 139
188 c = prcm_clear_mod_irqs(WKUP_MOD, 1, 140 c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
189 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); 141 ~(OMAP3430_ST_IO_MASK |
142 OMAP3430_ST_IO_CHAIN_MASK));
190 143
191 return c ? IRQ_HANDLED : IRQ_NONE; 144 return c ? IRQ_HANDLED : IRQ_NONE;
192} 145}
@@ -200,13 +153,14 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
200 * these are handled in a separate handler to avoid acking 153 * these are handled in a separate handler to avoid acking
201 * IO events before parsing in mux code 154 * IO events before parsing in mux code
202 */ 155 */
203 c = prcm_clear_mod_irqs(WKUP_MOD, 1, 156 c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
204 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); 157 OMAP3430_ST_IO_MASK |
205 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); 158 OMAP3430_ST_IO_CHAIN_MASK);
206 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); 159 c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
160 c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
207 if (omap_rev() > OMAP3430_REV_ES1_0) { 161 if (omap_rev() > OMAP3430_REV_ES1_0) {
208 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); 162 c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
209 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); 163 c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
210 } 164 }
211 165
212 return c ? IRQ_HANDLED : IRQ_NONE; 166 return c ? IRQ_HANDLED : IRQ_NONE;
@@ -399,159 +353,11 @@ restore:
399#define omap3_pm_suspend NULL 353#define omap3_pm_suspend NULL
400#endif /* CONFIG_SUSPEND */ 354#endif /* CONFIG_SUSPEND */
401 355
402
403/**
404 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
405 * retention
406 *
407 * In cases where IVA2 is activated by bootcode, it may prevent
408 * full-chip retention or off-mode because it is not idle. This
409 * function forces the IVA2 into idle state so it can go
410 * into retention/off and thus allow full-chip retention/off.
411 *
412 **/
413static void __init omap3_iva_idle(void)
414{
415 /* ensure IVA2 clock is disabled */
416 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
417
418 /* if no clock activity, nothing else to do */
419 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
420 OMAP3430_CLKACTIVITY_IVA2_MASK))
421 return;
422
423 /* Reset IVA2 */
424 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
425 OMAP3430_RST2_IVA2_MASK |
426 OMAP3430_RST3_IVA2_MASK,
427 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
428
429 /* Enable IVA2 clock */
430 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
431 OMAP3430_IVA2_MOD, CM_FCLKEN);
432
433 /* Set IVA2 boot mode to 'idle' */
434 omap3_ctrl_set_iva_bootmode_idle();
435
436 /* Un-reset IVA2 */
437 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
438
439 /* Disable IVA2 clock */
440 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
441
442 /* Reset IVA2 */
443 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
444 OMAP3430_RST2_IVA2_MASK |
445 OMAP3430_RST3_IVA2_MASK,
446 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
447}
448
449static void __init omap3_d2d_idle(void)
450{
451 u16 mask, padconf;
452
453 /* In a stand alone OMAP3430 where there is not a stacked
454 * modem for the D2D Idle Ack and D2D MStandby must be pulled
455 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
456 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
457 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
458 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
459 padconf |= mask;
460 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
461
462 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
463 padconf |= mask;
464 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
465
466 /* reset modem */
467 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
468 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
469 CORE_MOD, OMAP2_RM_RSTCTRL);
470 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
471}
472
473static void __init prcm_setup_regs(void) 356static void __init prcm_setup_regs(void)
474{ 357{
475 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 358 omap3_ctrl_init();
476 OMAP3630_EN_UART4_MASK : 0;
477 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
478 OMAP3630_GRPSEL_UART4_MASK : 0;
479
480 /* XXX This should be handled by hwmod code or SCM init code */
481 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
482
483 /*
484 * Enable control of expternal oscillator through
485 * sys_clkreq. In the long run clock framework should
486 * take care of this.
487 */
488 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
489 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
490 OMAP3430_GR_MOD,
491 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
492
493 /* setup wakup source */
494 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
495 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
496 WKUP_MOD, PM_WKEN);
497 /* No need to write EN_IO, that is always enabled */
498 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
499 OMAP3430_GRPSEL_GPT1_MASK |
500 OMAP3430_GRPSEL_GPT12_MASK,
501 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
502
503 /* Enable PM_WKEN to support DSS LPR */
504 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
505 OMAP3430_DSS_MOD, PM_WKEN);
506
507 /* Enable wakeups in PER */
508 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
509 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
510 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
511 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
512 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
513 OMAP3430_EN_MCBSP4_MASK,
514 OMAP3430_PER_MOD, PM_WKEN);
515 /* and allow them to wake up MPU */
516 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
517 OMAP3430_GRPSEL_GPIO2_MASK |
518 OMAP3430_GRPSEL_GPIO3_MASK |
519 OMAP3430_GRPSEL_GPIO4_MASK |
520 OMAP3430_GRPSEL_GPIO5_MASK |
521 OMAP3430_GRPSEL_GPIO6_MASK |
522 OMAP3430_GRPSEL_UART3_MASK |
523 OMAP3430_GRPSEL_MCBSP2_MASK |
524 OMAP3430_GRPSEL_MCBSP3_MASK |
525 OMAP3430_GRPSEL_MCBSP4_MASK,
526 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
527
528 /* Don't attach IVA interrupts */
529 if (omap3_has_iva()) {
530 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
531 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
532 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
533 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
534 OMAP3430_PM_IVAGRPSEL);
535 }
536
537 /* Clear any pending 'reset' flags */
538 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
539 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
540 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
541 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
542 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
543 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
544 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
545
546 /* Clear any pending PRCM interrupts */
547 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
548
549 /*
550 * We need to idle iva2_pwrdm even on am3703 with no iva2.
551 */
552 omap3_iva_idle();
553 359
554 omap3_d2d_idle(); 360 omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
555} 361}
556 362
557void omap3_pm_off_mode_enable(int enable) 363void omap3_pm_off_mode_enable(int enable)
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index a3a3cca2bcc4..86958050547a 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -114,6 +114,24 @@ void omap2xxx_prm_dpll_reset(void)
114 omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL); 114 omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
115} 115}
116 116
117/**
118 * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module
119 * @module: PRM module to clear wakeups from
120 * @regs: register offset to clear
121 * @wkst_mask: wakeup status mask to clear
122 *
123 * Clears wakeup status bits for a given module, so that the device can
124 * re-enter idle.
125 */
126void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
127{
128 u32 wkst;
129
130 wkst = omap2_prm_read_mod_reg(module, regs);
131 wkst &= wkst_mask;
132 omap2_prm_write_mod_reg(wkst, module, regs);
133}
134
117int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) 135int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
118{ 136{
119 omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, 137 omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index d2cb6365716f..d73414139292 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -125,6 +125,7 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
125extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); 125extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
126 126
127extern void omap2xxx_prm_dpll_reset(void); 127extern void omap2xxx_prm_dpll_reset(void);
128void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
128 129
129extern int __init omap2xxx_prm_init(void); 130extern int __init omap2xxx_prm_init(void);
130 131
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 4bd7a2dca8af..2458be6fc67b 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -26,6 +26,8 @@
26#include "prm2xxx_3xxx.h" 26#include "prm2xxx_3xxx.h"
27#include "cm2xxx_3xxx.h" 27#include "cm2xxx_3xxx.h"
28#include "prm-regbits-34xx.h" 28#include "prm-regbits-34xx.h"
29#include "cm3xxx.h"
30#include "cm-regbits-34xx.h"
29 31
30static const struct omap_prcm_irq omap3_prcm_irqs[] = { 32static const struct omap_prcm_irq omap3_prcm_irqs[] = {
31 OMAP_PRCM_IRQ("wkup", 0, 0), 33 OMAP_PRCM_IRQ("wkup", 0, 0),
@@ -206,6 +208,167 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
206} 208}
207 209
208/** 210/**
211 * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
212 * @module: PRM module to clear wakeups from
213 * @regs: register set to clear, 1 or 3
214 * @ignore_bits: wakeup status bits to ignore
215 *
216 * The purpose of this function is to clear any wake-up events latched
217 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
218 * may occur whilst attempting to clear a PM_WKST_x register and thus
219 * set another bit in this register. A while loop is used to ensure
220 * that any peripheral wake-up events occurring while attempting to
221 * clear the PM_WKST_x are detected and cleared.
222 */
223int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
224{
225 u32 wkst, fclk, iclk, clken;
226 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
227 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
228 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
229 u16 grpsel_off = (regs == 3) ?
230 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
231 int c = 0;
232
233 wkst = omap2_prm_read_mod_reg(module, wkst_off);
234 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
235 wkst &= ~ignore_bits;
236 if (wkst) {
237 iclk = omap2_cm_read_mod_reg(module, iclk_off);
238 fclk = omap2_cm_read_mod_reg(module, fclk_off);
239 while (wkst) {
240 clken = wkst;
241 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
242 /*
243 * For USBHOST, we don't know whether HOST1 or
244 * HOST2 woke us up, so enable both f-clocks
245 */
246 if (module == OMAP3430ES2_USBHOST_MOD)
247 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
248 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
249 omap2_prm_write_mod_reg(wkst, module, wkst_off);
250 wkst = omap2_prm_read_mod_reg(module, wkst_off);
251 wkst &= ~ignore_bits;
252 c++;
253 }
254 omap2_cm_write_mod_reg(iclk, module, iclk_off);
255 omap2_cm_write_mod_reg(fclk, module, fclk_off);
256 }
257
258 return c;
259}
260
261/**
262 * omap3_prm_reset_modem - toggle reset signal for modem
263 *
264 * Toggles the reset signal to modem IP block. Required to allow
265 * OMAP3430 without stacked modem to idle properly.
266 */
267void __init omap3_prm_reset_modem(void)
268{
269 omap2_prm_write_mod_reg(
270 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
271 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
272 CORE_MOD, OMAP2_RM_RSTCTRL);
273 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
274}
275
276/**
277 * omap3_prm_init_pm - initialize PM related registers for PRM
278 * @has_uart4: SoC has UART4
279 * @has_iva: SoC has IVA
280 *
281 * Initializes PRM registers for PM use. Called from PM init.
282 */
283void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
284{
285 u32 en_uart4_mask;
286 u32 grpsel_uart4_mask;
287
288 /*
289 * Enable control of expternal oscillator through
290 * sys_clkreq. In the long run clock framework should
291 * take care of this.
292 */
293 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
294 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
295 OMAP3430_GR_MOD,
296 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
297
298 /* setup wakup source */
299 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
300 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
301 WKUP_MOD, PM_WKEN);
302 /* No need to write EN_IO, that is always enabled */
303 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
304 OMAP3430_GRPSEL_GPT1_MASK |
305 OMAP3430_GRPSEL_GPT12_MASK,
306 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
307
308 /* Enable PM_WKEN to support DSS LPR */
309 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
310 OMAP3430_DSS_MOD, PM_WKEN);
311
312 if (has_uart4) {
313 en_uart4_mask = OMAP3630_EN_UART4_MASK;
314 grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK;
315 }
316
317 /* Enable wakeups in PER */
318 omap2_prm_write_mod_reg(en_uart4_mask |
319 OMAP3430_EN_GPIO2_MASK |
320 OMAP3430_EN_GPIO3_MASK |
321 OMAP3430_EN_GPIO4_MASK |
322 OMAP3430_EN_GPIO5_MASK |
323 OMAP3430_EN_GPIO6_MASK |
324 OMAP3430_EN_UART3_MASK |
325 OMAP3430_EN_MCBSP2_MASK |
326 OMAP3430_EN_MCBSP3_MASK |
327 OMAP3430_EN_MCBSP4_MASK,
328 OMAP3430_PER_MOD, PM_WKEN);
329
330 /* and allow them to wake up MPU */
331 omap2_prm_write_mod_reg(grpsel_uart4_mask |
332 OMAP3430_GRPSEL_GPIO2_MASK |
333 OMAP3430_GRPSEL_GPIO3_MASK |
334 OMAP3430_GRPSEL_GPIO4_MASK |
335 OMAP3430_GRPSEL_GPIO5_MASK |
336 OMAP3430_GRPSEL_GPIO6_MASK |
337 OMAP3430_GRPSEL_UART3_MASK |
338 OMAP3430_GRPSEL_MCBSP2_MASK |
339 OMAP3430_GRPSEL_MCBSP3_MASK |
340 OMAP3430_GRPSEL_MCBSP4_MASK,
341 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
342
343 /* Don't attach IVA interrupts */
344 if (has_iva) {
345 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
346 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
347 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
348 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
349 OMAP3430_PM_IVAGRPSEL);
350 }
351
352 /* Clear any pending 'reset' flags */
353 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
354 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
355 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
356 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
357 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
358 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
359 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
360 OMAP2_RM_RSTST);
361
362 /* Clear any pending PRCM interrupts */
363 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
364
365 /* We need to idle iva2_pwrdm even on am3703 with no iva2. */
366 omap3xxx_prm_iva_idle();
367
368 omap3_prm_reset_modem();
369}
370
371/**
209 * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain 372 * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
210 * 373 *
211 * Clear any previously-latched I/O wakeup events and ensure that the 374 * Clear any previously-latched I/O wakeup events and ensure that the
@@ -276,6 +439,76 @@ static u32 omap3xxx_prm_read_reset_sources(void)
276 return r; 439 return r;
277} 440}
278 441
442/**
443 * omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention
444 *
445 * In cases where IVA2 is activated by bootcode, it may prevent
446 * full-chip retention or off-mode because it is not idle. This
447 * function forces the IVA2 into idle state so it can go
448 * into retention/off and thus allow full-chip retention/off.
449 */
450void omap3xxx_prm_iva_idle(void)
451{
452 /* ensure IVA2 clock is disabled */
453 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
454
455 /* if no clock activity, nothing else to do */
456 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
457 OMAP3430_CLKACTIVITY_IVA2_MASK))
458 return;
459
460 /* Reset IVA2 */
461 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
462 OMAP3430_RST2_IVA2_MASK |
463 OMAP3430_RST3_IVA2_MASK,
464 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
465
466 /* Enable IVA2 clock */
467 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
468 OMAP3430_IVA2_MOD, CM_FCLKEN);
469
470 /* Un-reset IVA2 */
471 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
472
473 /* Disable IVA2 clock */
474 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
475
476 /* Reset IVA2 */
477 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
478 OMAP3430_RST2_IVA2_MASK |
479 OMAP3430_RST3_IVA2_MASK,
480 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
481}
482
483/**
484 * omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status
485 * and clears it if asserted
486 *
487 * Checks if cold-reset has occurred and clears the status bit if yes. Returns
488 * 1 if cold-reset has occurred, 0 otherwise.
489 */
490int omap3xxx_prm_clear_global_cold_reset(void)
491{
492 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
493 OMAP3430_GLOBAL_COLD_RST_MASK) {
494 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
495 OMAP3430_GR_MOD,
496 OMAP3_PRM_RSTST_OFFSET);
497 return 1;
498 }
499
500 return 0;
501}
502
503void omap3_prm_save_scratchpad_contents(u32 *ptr)
504{
505 *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
506 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
507
508 *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
509 OMAP3_PRM_CLKSEL_OFFSET);
510}
511
279/* Powerdomain low-level functions */ 512/* Powerdomain low-level functions */
280 513
281static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 514static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 1dacfc5b1959..bc37d42a8704 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -162,6 +162,12 @@ extern void omap3xxx_prm_dpll3_reset(void);
162 162
163extern int __init omap3xxx_prm_init(void); 163extern int __init omap3xxx_prm_init(void);
164extern u32 omap3xxx_prm_get_reset_sources(void); 164extern u32 omap3xxx_prm_get_reset_sources(void);
165int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
166void omap3xxx_prm_iva_idle(void);
167void omap3_prm_reset_modem(void);
168int omap3xxx_prm_clear_global_cold_reset(void);
169void omap3_prm_save_scratchpad_contents(u32 *ptr);
170void omap3_prm_init_pm(bool has_uart4, bool has_iva);
165 171
166#endif /* __ASSEMBLER */ 172#endif /* __ASSEMBLER */
167 173
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