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authorGal Pressman <galp@mellanox.com>2018-03-28 10:46:54 -0400
committerDavid S. Miller <davem@davemloft.net>2018-03-30 09:58:59 -0400
commit9daae9bd47cff82a2a06aca23c458d6c79d09d52 (patch)
tree68e4ed71bac84b9f51e1c2d64a8b41b31195a7a0
parent004c3cf1a18becf5ce56f43e8821835e34c15865 (diff)
net: Call add/kill vid ndo on vlan filter feature toggling
NETIF_F_HW_VLAN_[CS]TAG_FILTER features require more than just a bit flip in dev->features in order to keep the driver in a consistent state. These features notify the driver of each added/removed vlan, but toggling of vlan-filter does not notify the driver accordingly for each of the existing vlans. This patch implements a similar solution to NETIF_F_RX_UDP_TUNNEL_PORT behavior (which notifies the driver about UDP ports in the same manner that vids are reported). Each toggling of the features propagates to the 8021q module, which iterates over the vlans and call add/kill ndo accordingly. Signed-off-by: Gal Pressman <galp@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--include/linux/if_vlan.h24
-rw-r--r--include/linux/netdevice.h4
-rw-r--r--net/8021q/vlan.c21
-rw-r--r--net/8021q/vlan.h3
-rw-r--r--net/8021q/vlan_core.c101
-rw-r--r--net/core/dev.c20
6 files changed, 148 insertions, 25 deletions
diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h
index c4a1cff9c768..24d1976c1e61 100644
--- a/include/linux/if_vlan.h
+++ b/include/linux/if_vlan.h
@@ -83,6 +83,30 @@ static inline bool is_vlan_dev(const struct net_device *dev)
83#define skb_vlan_tag_get_id(__skb) ((__skb)->vlan_tci & VLAN_VID_MASK) 83#define skb_vlan_tag_get_id(__skb) ((__skb)->vlan_tci & VLAN_VID_MASK)
84#define skb_vlan_tag_get_prio(__skb) ((__skb)->vlan_tci & VLAN_PRIO_MASK) 84#define skb_vlan_tag_get_prio(__skb) ((__skb)->vlan_tci & VLAN_PRIO_MASK)
85 85
86static inline int vlan_get_rx_ctag_filter_info(struct net_device *dev)
87{
88 ASSERT_RTNL();
89 return notifier_to_errno(call_netdevice_notifiers(NETDEV_CVLAN_FILTER_PUSH_INFO, dev));
90}
91
92static inline void vlan_drop_rx_ctag_filter_info(struct net_device *dev)
93{
94 ASSERT_RTNL();
95 call_netdevice_notifiers(NETDEV_CVLAN_FILTER_DROP_INFO, dev);
96}
97
98static inline int vlan_get_rx_stag_filter_info(struct net_device *dev)
99{
100 ASSERT_RTNL();
101 return notifier_to_errno(call_netdevice_notifiers(NETDEV_SVLAN_FILTER_PUSH_INFO, dev));
102}
103
104static inline void vlan_drop_rx_stag_filter_info(struct net_device *dev)
105{
106 ASSERT_RTNL();
107 call_netdevice_notifiers(NETDEV_SVLAN_FILTER_DROP_INFO, dev);
108}
109
86/** 110/**
87 * struct vlan_pcpu_stats - VLAN percpu rx/tx stats 111 * struct vlan_pcpu_stats - VLAN percpu rx/tx stats
88 * @rx_packets: number of received packets 112 * @rx_packets: number of received packets
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 2a2d9cf50aa2..da44dab492e3 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -2349,6 +2349,10 @@ enum netdev_cmd {
2349 NETDEV_UDP_TUNNEL_PUSH_INFO, 2349 NETDEV_UDP_TUNNEL_PUSH_INFO,
2350 NETDEV_UDP_TUNNEL_DROP_INFO, 2350 NETDEV_UDP_TUNNEL_DROP_INFO,
2351 NETDEV_CHANGE_TX_QUEUE_LEN, 2351 NETDEV_CHANGE_TX_QUEUE_LEN,
2352 NETDEV_CVLAN_FILTER_PUSH_INFO,
2353 NETDEV_CVLAN_FILTER_DROP_INFO,
2354 NETDEV_SVLAN_FILTER_PUSH_INFO,
2355 NETDEV_SVLAN_FILTER_DROP_INFO,
2352}; 2356};
2353const char *netdev_cmd_to_name(enum netdev_cmd cmd); 2357const char *netdev_cmd_to_name(enum netdev_cmd cmd);
2354 2358
diff --git a/net/8021q/vlan.c b/net/8021q/vlan.c
index bad01b14a4ad..5505ee6ebdbe 100644
--- a/net/8021q/vlan.c
+++ b/net/8021q/vlan.c
@@ -360,6 +360,7 @@ static int vlan_device_event(struct notifier_block *unused, unsigned long event,
360 struct vlan_dev_priv *vlan; 360 struct vlan_dev_priv *vlan;
361 bool last = false; 361 bool last = false;
362 LIST_HEAD(list); 362 LIST_HEAD(list);
363 int err;
363 364
364 if (is_vlan_dev(dev)) { 365 if (is_vlan_dev(dev)) {
365 int err = __vlan_device_event(dev, event); 366 int err = __vlan_device_event(dev, event);
@@ -489,6 +490,26 @@ static int vlan_device_event(struct notifier_block *unused, unsigned long event,
489 vlan_group_for_each_dev(grp, i, vlandev) 490 vlan_group_for_each_dev(grp, i, vlandev)
490 call_netdevice_notifiers(event, vlandev); 491 call_netdevice_notifiers(event, vlandev);
491 break; 492 break;
493
494 case NETDEV_CVLAN_FILTER_PUSH_INFO:
495 err = vlan_filter_push_vids(vlan_info, htons(ETH_P_8021Q));
496 if (err)
497 return notifier_from_errno(err);
498 break;
499
500 case NETDEV_CVLAN_FILTER_DROP_INFO:
501 vlan_filter_drop_vids(vlan_info, htons(ETH_P_8021Q));
502 break;
503
504 case NETDEV_SVLAN_FILTER_PUSH_INFO:
505 err = vlan_filter_push_vids(vlan_info, htons(ETH_P_8021AD));
506 if (err)
507 return notifier_from_errno(err);
508 break;
509
510 case NETDEV_SVLAN_FILTER_DROP_INFO:
511 vlan_filter_drop_vids(vlan_info, htons(ETH_P_8021AD));
512 break;
492 } 513 }
493 514
494out: 515out:
diff --git a/net/8021q/vlan.h b/net/8021q/vlan.h
index a8ba51030b75..e23aac3e4d37 100644
--- a/net/8021q/vlan.h
+++ b/net/8021q/vlan.h
@@ -97,6 +97,9 @@ static inline struct net_device *vlan_find_dev(struct net_device *real_dev,
97 if (((dev) = __vlan_group_get_device((grp), (i) / VLAN_N_VID, \ 97 if (((dev) = __vlan_group_get_device((grp), (i) / VLAN_N_VID, \
98 (i) % VLAN_N_VID))) 98 (i) % VLAN_N_VID)))
99 99
100int vlan_filter_push_vids(struct vlan_info *vlan_info, __be16 proto);
101void vlan_filter_drop_vids(struct vlan_info *vlan_info, __be16 proto);
102
100/* found in vlan_dev.c */ 103/* found in vlan_dev.c */
101void vlan_dev_set_ingress_priority(const struct net_device *dev, 104void vlan_dev_set_ingress_priority(const struct net_device *dev,
102 u32 skb_prio, u16 vlan_prio); 105 u32 skb_prio, u16 vlan_prio);
diff --git a/net/8021q/vlan_core.c b/net/8021q/vlan_core.c
index 45c9bf5ff3a0..c8d7abdc0463 100644
--- a/net/8021q/vlan_core.c
+++ b/net/8021q/vlan_core.c
@@ -165,13 +165,12 @@ struct vlan_vid_info {
165 int refcount; 165 int refcount;
166}; 166};
167 167
168static bool vlan_hw_filter_capable(const struct net_device *dev, 168bool vlan_hw_filter_capable(const struct net_device *dev, __be16 proto)
169 const struct vlan_vid_info *vid_info)
170{ 169{
171 if (vid_info->proto == htons(ETH_P_8021Q) && 170 if (proto == htons(ETH_P_8021Q) &&
172 dev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 171 dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
173 return true; 172 return true;
174 if (vid_info->proto == htons(ETH_P_8021AD) && 173 if (proto == htons(ETH_P_8021AD) &&
175 dev->features & NETIF_F_HW_VLAN_STAG_FILTER) 174 dev->features & NETIF_F_HW_VLAN_STAG_FILTER)
176 return true; 175 return true;
177 return false; 176 return false;
@@ -202,11 +201,73 @@ static struct vlan_vid_info *vlan_vid_info_alloc(__be16 proto, u16 vid)
202 return vid_info; 201 return vid_info;
203} 202}
204 203
204static int vlan_add_rx_filter_info(struct net_device *dev, __be16 proto, u16 vid)
205{
206 if (!vlan_hw_filter_capable(dev, proto))
207 return 0;
208
209 if (netif_device_present(dev))
210 return dev->netdev_ops->ndo_vlan_rx_add_vid(dev, proto, vid);
211 else
212 return -ENODEV;
213}
214
215static int vlan_kill_rx_filter_info(struct net_device *dev, __be16 proto, u16 vid)
216{
217 if (!vlan_hw_filter_capable(dev, proto))
218 return 0;
219
220 if (netif_device_present(dev))
221 return dev->netdev_ops->ndo_vlan_rx_kill_vid(dev, proto, vid);
222 else
223 return -ENODEV;
224}
225
226int vlan_filter_push_vids(struct vlan_info *vlan_info, __be16 proto)
227{
228 struct net_device *real_dev = vlan_info->real_dev;
229 struct vlan_vid_info *vlan_vid_info;
230 int err;
231
232 list_for_each_entry(vlan_vid_info, &vlan_info->vid_list, list) {
233 if (vlan_vid_info->proto == proto) {
234 err = vlan_add_rx_filter_info(real_dev, proto,
235 vlan_vid_info->vid);
236 if (err)
237 goto unwind;
238 }
239 }
240
241 return 0;
242
243unwind:
244 list_for_each_entry_continue_reverse(vlan_vid_info,
245 &vlan_info->vid_list, list) {
246 if (vlan_vid_info->proto == proto)
247 vlan_kill_rx_filter_info(real_dev, proto,
248 vlan_vid_info->vid);
249 }
250
251 return err;
252}
253EXPORT_SYMBOL(vlan_filter_push_vids);
254
255void vlan_filter_drop_vids(struct vlan_info *vlan_info, __be16 proto)
256{
257 struct vlan_vid_info *vlan_vid_info;
258
259 list_for_each_entry(vlan_vid_info, &vlan_info->vid_list, list)
260 if (vlan_vid_info->proto == proto)
261 vlan_kill_rx_filter_info(vlan_info->real_dev,
262 vlan_vid_info->proto,
263 vlan_vid_info->vid);
264}
265EXPORT_SYMBOL(vlan_filter_drop_vids);
266
205static int __vlan_vid_add(struct vlan_info *vlan_info, __be16 proto, u16 vid, 267static int __vlan_vid_add(struct vlan_info *vlan_info, __be16 proto, u16 vid,
206 struct vlan_vid_info **pvid_info) 268 struct vlan_vid_info **pvid_info)
207{ 269{
208 struct net_device *dev = vlan_info->real_dev; 270 struct net_device *dev = vlan_info->real_dev;
209 const struct net_device_ops *ops = dev->netdev_ops;
210 struct vlan_vid_info *vid_info; 271 struct vlan_vid_info *vid_info;
211 int err; 272 int err;
212 273
@@ -214,16 +275,12 @@ static int __vlan_vid_add(struct vlan_info *vlan_info, __be16 proto, u16 vid,
214 if (!vid_info) 275 if (!vid_info)
215 return -ENOMEM; 276 return -ENOMEM;
216 277
217 if (vlan_hw_filter_capable(dev, vid_info)) { 278 err = vlan_add_rx_filter_info(dev, proto, vid);
218 if (netif_device_present(dev)) 279 if (err) {
219 err = ops->ndo_vlan_rx_add_vid(dev, proto, vid); 280 kfree(vid_info);
220 else 281 return err;
221 err = -ENODEV;
222 if (err) {
223 kfree(vid_info);
224 return err;
225 }
226 } 282 }
283
227 list_add(&vid_info->list, &vlan_info->vid_list); 284 list_add(&vid_info->list, &vlan_info->vid_list);
228 vlan_info->nr_vids++; 285 vlan_info->nr_vids++;
229 *pvid_info = vid_info; 286 *pvid_info = vid_info;
@@ -270,21 +327,15 @@ static void __vlan_vid_del(struct vlan_info *vlan_info,
270 struct vlan_vid_info *vid_info) 327 struct vlan_vid_info *vid_info)
271{ 328{
272 struct net_device *dev = vlan_info->real_dev; 329 struct net_device *dev = vlan_info->real_dev;
273 const struct net_device_ops *ops = dev->netdev_ops;
274 __be16 proto = vid_info->proto; 330 __be16 proto = vid_info->proto;
275 u16 vid = vid_info->vid; 331 u16 vid = vid_info->vid;
276 int err; 332 int err;
277 333
278 if (vlan_hw_filter_capable(dev, vid_info)) { 334 err = vlan_kill_rx_filter_info(dev, proto, vid);
279 if (netif_device_present(dev)) 335 if (err)
280 err = ops->ndo_vlan_rx_kill_vid(dev, proto, vid); 336 pr_warn("failed to kill vid %04x/%d for device %s\n",
281 else 337 proto, vid, dev->name);
282 err = -ENODEV; 338
283 if (err) {
284 pr_warn("failed to kill vid %04x/%d for device %s\n",
285 proto, vid, dev->name);
286 }
287 }
288 list_del(&vid_info->list); 339 list_del(&vid_info->list);
289 kfree(vid_info); 340 kfree(vid_info);
290 vlan_info->nr_vids--; 341 vlan_info->nr_vids--;
diff --git a/net/core/dev.c b/net/core/dev.c
index eca5458b2753..1ddb6b9c58a8 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -1584,6 +1584,8 @@ const char *netdev_cmd_to_name(enum netdev_cmd cmd)
1584 N(RESEND_IGMP) N(PRECHANGEMTU) N(CHANGEINFODATA) N(BONDING_INFO) 1584 N(RESEND_IGMP) N(PRECHANGEMTU) N(CHANGEINFODATA) N(BONDING_INFO)
1585 N(PRECHANGEUPPER) N(CHANGELOWERSTATE) N(UDP_TUNNEL_PUSH_INFO) 1585 N(PRECHANGEUPPER) N(CHANGELOWERSTATE) N(UDP_TUNNEL_PUSH_INFO)
1586 N(UDP_TUNNEL_DROP_INFO) N(CHANGE_TX_QUEUE_LEN) 1586 N(UDP_TUNNEL_DROP_INFO) N(CHANGE_TX_QUEUE_LEN)
1587 N(CVLAN_FILTER_PUSH_INFO) N(CVLAN_FILTER_DROP_INFO)
1588 N(SVLAN_FILTER_PUSH_INFO) N(SVLAN_FILTER_DROP_INFO)
1587 }; 1589 };
1588#undef N 1590#undef N
1589 return "UNKNOWN_NETDEV_EVENT"; 1591 return "UNKNOWN_NETDEV_EVENT";
@@ -7665,6 +7667,24 @@ sync_lower:
7665 } 7667 }
7666 } 7668 }
7667 7669
7670 if (diff & NETIF_F_HW_VLAN_CTAG_FILTER) {
7671 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
7672 dev->features = features;
7673 err |= vlan_get_rx_ctag_filter_info(dev);
7674 } else {
7675 vlan_drop_rx_ctag_filter_info(dev);
7676 }
7677 }
7678
7679 if (diff & NETIF_F_HW_VLAN_STAG_FILTER) {
7680 if (features & NETIF_F_HW_VLAN_STAG_FILTER) {
7681 dev->features = features;
7682 err |= vlan_get_rx_stag_filter_info(dev);
7683 } else {
7684 vlan_drop_rx_stag_filter_info(dev);
7685 }
7686 }
7687
7668 dev->features = features; 7688 dev->features = features;
7669 } 7689 }
7670 7690
2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546
/*
 * Definitions for the new Marvell Yukon / SysKonenct driver.
 */
#ifndef _SKGE_H
#define _SKGE_H

/* PCI config registers */
#define PCI_DEV_REG1	0x40
#define  PCI_PHY_COMA	0x8000000
#define  PCI_VIO	0x2000000
#define PCI_DEV_REG2	0x44
#define  PCI_REV_DESC	 0x4

#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
			       PCI_STATUS_SIG_SYSTEM_ERROR | \
			       PCI_STATUS_REC_MASTER_ABORT | \
			       PCI_STATUS_REC_TARGET_ABORT | \
			       PCI_STATUS_PARITY)

enum csr_regs {
	B0_RAP	= 0x0000,
	B0_CTST	= 0x0004,
	B0_LED	= 0x0006,
	B0_POWER_CTRL	= 0x0007,
	B0_ISRC	= 0x0008,
	B0_IMSK	= 0x000c,
	B0_HWE_ISRC	= 0x0010,
	B0_HWE_IMSK	= 0x0014,
	B0_SP_ISRC	= 0x0018,
	B0_XM1_IMSK	= 0x0020,
	B0_XM1_ISRC	= 0x0028,
	B0_XM1_PHY_ADDR	= 0x0030,
	B0_XM1_PHY_DATA	= 0x0034,
	B0_XM2_IMSK	= 0x0040,
	B0_XM2_ISRC	= 0x0048,
	B0_XM2_PHY_ADDR	= 0x0050,
	B0_XM2_PHY_DATA	= 0x0054,
	B0_R1_CSR	= 0x0060,
	B0_R2_CSR	= 0x0064,
	B0_XS1_CSR	= 0x0068,
	B0_XA1_CSR	= 0x006c,
	B0_XS2_CSR	= 0x0070,
	B0_XA2_CSR	= 0x0074,

	B2_MAC_1	= 0x0100,
	B2_MAC_2	= 0x0108,
	B2_MAC_3	= 0x0110,
	B2_CONN_TYP	= 0x0118,
	B2_PMD_TYP	= 0x0119,
	B2_MAC_CFG	= 0x011a,
	B2_CHIP_ID	= 0x011b,
	B2_E_0		= 0x011c,
	B2_E_1		= 0x011d,
	B2_E_2		= 0x011e,
	B2_E_3		= 0x011f,
	B2_FAR		= 0x0120,
	B2_FDP		= 0x0124,
	B2_LD_CTRL	= 0x0128,
	B2_LD_TEST	= 0x0129,
	B2_TI_INI	= 0x0130,
	B2_TI_VAL	= 0x0134,
	B2_TI_CTRL	= 0x0138,
	B2_TI_TEST	= 0x0139,
	B2_IRQM_INI	= 0x0140,
	B2_IRQM_VAL	= 0x0144,
	B2_IRQM_CTRL	= 0x0148,
	B2_IRQM_TEST	= 0x0149,
	B2_IRQM_MSK	= 0x014c,
	B2_IRQM_HWE_MSK	= 0x0150,
	B2_TST_CTRL1	= 0x0158,
	B2_TST_CTRL2	= 0x0159,
	B2_GP_IO	= 0x015c,
	B2_I2C_CTRL	= 0x0160,
	B2_I2C_DATA	= 0x0164,
	B2_I2C_IRQ	= 0x0168,
	B2_I2C_SW	= 0x016c,
	B2_BSC_INI	= 0x0170,
	B2_BSC_VAL	= 0x0174,
	B2_BSC_CTRL	= 0x0178,
	B2_BSC_STAT	= 0x0179,
	B2_BSC_TST	= 0x017a,

	B3_RAM_ADDR	= 0x0180,
	B3_RAM_DATA_LO	= 0x0184,
	B3_RAM_DATA_HI	= 0x0188,
	B3_RI_WTO_R1	= 0x0190,
	B3_RI_WTO_XA1	= 0x0191,
	B3_RI_WTO_XS1	= 0x0192,
	B3_RI_RTO_R1	= 0x0193,
	B3_RI_RTO_XA1	= 0x0194,
	B3_RI_RTO_XS1	= 0x0195,
	B3_RI_WTO_R2	= 0x0196,
	B3_RI_WTO_XA2	= 0x0197,
	B3_RI_WTO_XS2	= 0x0198,
	B3_RI_RTO_R2	= 0x0199,
	B3_RI_RTO_XA2	= 0x019a,
	B3_RI_RTO_XS2	= 0x019b,
	B3_RI_TO_VAL	= 0x019c,
	B3_RI_CTRL	= 0x01a0,
	B3_RI_TEST	= 0x01a2,
	B3_MA_TOINI_RX1	= 0x01b0,
	B3_MA_TOINI_RX2	= 0x01b1,
	B3_MA_TOINI_TX1	= 0x01b2,
	B3_MA_TOINI_TX2	= 0x01b3,
	B3_MA_TOVAL_RX1	= 0x01b4,
	B3_MA_TOVAL_RX2	= 0x01b5,
	B3_MA_TOVAL_TX1	= 0x01b6,
	B3_MA_TOVAL_TX2	= 0x01b7,
	B3_MA_TO_CTRL	= 0x01b8,
	B3_MA_TO_TEST	= 0x01ba,
	B3_MA_RCINI_RX1	= 0x01c0,
	B3_MA_RCINI_RX2	= 0x01c1,
	B3_MA_RCINI_TX1	= 0x01c2,
	B3_MA_RCINI_TX2	= 0x01c3,
	B3_MA_RCVAL_RX1	= 0x01c4,
	B3_MA_RCVAL_RX2	= 0x01c5,
	B3_MA_RCVAL_TX1	= 0x01c6,
	B3_MA_RCVAL_TX2	= 0x01c7,
	B3_MA_RC_CTRL	= 0x01c8,
	B3_MA_RC_TEST	= 0x01ca,
	B3_PA_TOINI_RX1	= 0x01d0,
	B3_PA_TOINI_RX2	= 0x01d4,
	B3_PA_TOINI_TX1	= 0x01d8,
	B3_PA_TOINI_TX2	= 0x01dc,
	B3_PA_TOVAL_RX1	= 0x01e0,
	B3_PA_TOVAL_RX2	= 0x01e4,
	B3_PA_TOVAL_TX1	= 0x01e8,
	B3_PA_TOVAL_TX2	= 0x01ec,
	B3_PA_CTRL	= 0x01f0,
	B3_PA_TEST	= 0x01f2,
};

/*	B0_CTST			16 bit	Control/Status register */
enum {
	CS_CLK_RUN_HOT	= 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
	CS_CLK_RUN_RST	= 1<<12,/* CLK_RUN reset  (YUKON-Lite only) */
	CS_CLK_RUN_ENA	= 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
	CS_VAUX_AVAIL	= 1<<10,/* VAUX available (YUKON only) */
	CS_BUS_CLOCK	= 1<<9,	/* Bus Clock 0/1 = 33/66 MHz */
	CS_BUS_SLOT_SZ	= 1<<8,	/* Slot Size 0/1 = 32/64 bit slot */
	CS_ST_SW_IRQ	= 1<<7,	/* Set IRQ SW Request */
	CS_CL_SW_IRQ	= 1<<6,	/* Clear IRQ SW Request */
	CS_STOP_DONE	= 1<<5,	/* Stop Master is finished */
	CS_STOP_MAST	= 1<<4,	/* Command Bit to stop the master */
	CS_MRST_CLR	= 1<<3,	/* Clear Master reset	*/
	CS_MRST_SET	= 1<<2,	/* Set Master reset	*/
	CS_RST_CLR	= 1<<1,	/* Clear Software reset	*/
	CS_RST_SET	= 1,	/* Set   Software reset	*/

/*	B0_LED			 8 Bit	LED register */
/* Bit  7.. 2:	reserved */
	LED_STAT_ON	= 1<<1,	/* Status LED on	*/
	LED_STAT_OFF	= 1,		/* Status LED off	*/

/*	B0_POWER_CTRL	 8 Bit	Power Control reg (YUKON only) */
	PC_VAUX_ENA	= 1<<7,	/* Switch VAUX Enable  */
	PC_VAUX_DIS	= 1<<6,	/* Switch VAUX Disable */
	PC_VCC_ENA	= 1<<5,	/* Switch VCC Enable  */
	PC_VCC_DIS	= 1<<4,	/* Switch VCC Disable */
	PC_VAUX_ON	= 1<<3,	/* Switch VAUX On  */
	PC_VAUX_OFF	= 1<<2,	/* Switch VAUX Off */
	PC_VCC_ON	= 1<<1,	/* Switch VCC On  */
	PC_VCC_OFF	= 1<<0,	/* Switch VCC Off */
};

/*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */
enum {
	IS_ALL_MSK	= 0xbffffffful,	/* All Interrupt bits */
	IS_HW_ERR	= 1<<31,	/* Interrupt HW Error */
					/* Bit 30:	reserved */
	IS_PA_TO_RX1	= 1<<29,	/* Packet Arb Timeout Rx1 */
	IS_PA_TO_RX2	= 1<<28,	/* Packet Arb Timeout Rx2 */
	IS_PA_TO_TX1	= 1<<27,	/* Packet Arb Timeout Tx1 */
	IS_PA_TO_TX2	= 1<<26,	/* Packet Arb Timeout Tx2 */
	IS_I2C_READY	= 1<<25,	/* IRQ on end of I2C Tx */
	IS_IRQ_SW	= 1<<24,	/* SW forced IRQ	*/
	IS_EXT_REG	= 1<<23,	/* IRQ from LM80 or PHY (GENESIS only) */
					/* IRQ from PHY (YUKON only) */
	IS_TIMINT	= 1<<22,	/* IRQ from Timer	*/
	IS_MAC1		= 1<<21,	/* IRQ from MAC 1	*/
	IS_LNK_SYNC_M1	= 1<<20,	/* Link Sync Cnt wrap MAC 1 */
	IS_MAC2		= 1<<19,	/* IRQ from MAC 2	*/
	IS_LNK_SYNC_M2	= 1<<18,	/* Link Sync Cnt wrap MAC 2 */
/* Receive Queue 1 */
	IS_R1_B		= 1<<17,	/* Q_R1 End of Buffer */
	IS_R1_F		= 1<<16,	/* Q_R1 End of Frame */
	IS_R1_C		= 1<<15,	/* Q_R1 Encoding Error */
/* Receive Queue 2 */
	IS_R2_B		= 1<<14,	/* Q_R2 End of Buffer */
	IS_R2_F		= 1<<13,	/* Q_R2 End of Frame */
	IS_R2_C		= 1<<12,	/* Q_R2 Encoding Error */
/* Synchronous Transmit Queue 1 */
	IS_XS1_B	= 1<<11,	/* Q_XS1 End of Buffer */
	IS_XS1_F	= 1<<10,	/* Q_XS1 End of Frame */
	IS_XS1_C	= 1<<9,		/* Q_XS1 Encoding Error */
/* Asynchronous Transmit Queue 1 */
	IS_XA1_B	= 1<<8,		/* Q_XA1 End of Buffer */
	IS_XA1_F	= 1<<7,		/* Q_XA1 End of Frame */
	IS_XA1_C	= 1<<6,		/* Q_XA1 Encoding Error */
/* Synchronous Transmit Queue 2 */
	IS_XS2_B	= 1<<5,		/* Q_XS2 End of Buffer */
	IS_XS2_F	= 1<<4,		/* Q_XS2 End of Frame */
	IS_XS2_C	= 1<<3,		/* Q_XS2 Encoding Error */
/* Asynchronous Transmit Queue 2 */
	IS_XA2_B	= 1<<2,		/* Q_XA2 End of Buffer */
	IS_XA2_F	= 1<<1,		/* Q_XA2 End of Frame */
	IS_XA2_C	= 1<<0,		/* Q_XA2 Encoding Error */

	IS_TO_PORT1	= IS_PA_TO_RX1 | IS_PA_TO_TX1,
	IS_TO_PORT2	= IS_PA_TO_RX2 | IS_PA_TO_TX2,

	IS_PORT_1	= IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
	IS_PORT_2	= IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
};


/*	B2_IRQM_HWE_MSK	32 bit	IRQ Moderation HW Error Mask */
enum {
	IS_IRQ_TIST_OV	= 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
	IS_IRQ_SENSOR	= 1<<12, /* IRQ from Sensor (YUKON only) */
	IS_IRQ_MST_ERR	= 1<<11, /* IRQ master error detected */
	IS_IRQ_STAT	= 1<<10, /* IRQ status exception */
	IS_NO_STAT_M1	= 1<<9,	/* No Rx Status from MAC 1 */
	IS_NO_STAT_M2	= 1<<8,	/* No Rx Status from MAC 2 */
	IS_NO_TIST_M1	= 1<<7,	/* No Time Stamp from MAC 1 */
	IS_NO_TIST_M2	= 1<<6,	/* No Time Stamp from MAC 2 */
	IS_RAM_RD_PAR	= 1<<5,	/* RAM Read  Parity Error */
	IS_RAM_WR_PAR	= 1<<4,	/* RAM Write Parity Error */
	IS_M1_PAR_ERR	= 1<<3,	/* MAC 1 Parity Error */
	IS_M2_PAR_ERR	= 1<<2,	/* MAC 2 Parity Error */
	IS_R1_PAR_ERR	= 1<<1,	/* Queue R1 Parity Error */
	IS_R2_PAR_ERR	= 1<<0,	/* Queue R2 Parity Error */

	IS_ERR_MSK	= IS_IRQ_MST_ERR | IS_IRQ_STAT
			| IS_NO_STAT_M1 | IS_NO_STAT_M2
			| IS_RAM_RD_PAR | IS_RAM_WR_PAR
			| IS_M1_PAR_ERR | IS_M2_PAR_ERR
			| IS_R1_PAR_ERR | IS_R2_PAR_ERR,
};

/*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */
enum {
	TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
	TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
	TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
	TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
	TST_FRC_APERR_M	 = 1<<3, /* force ADDRPERR on MST */
	TST_FRC_APERR_T	 = 1<<2, /* force ADDRPERR on TRG */
	TST_CFG_WRITE_ON = 1<<1, /* Enable  Config Reg WR */
	TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
};

/*	B2_MAC_CFG		 8 bit	MAC Configuration / Chip Revision */
enum {
	CFG_CHIP_R_MSK	  = 0xf<<4,	/* Bit 7.. 4: Chip Revision */
					/* Bit 3.. 2:	reserved */
	CFG_DIS_M2_CLK	  = 1<<1,	/* Disable Clock for 2nd MAC */
	CFG_SNG_MAC	  = 1<<0,	/* MAC Config: 0=2 MACs / 1=1 MAC*/
};

/*	B2_CHIP_ID		 8 bit 	Chip Identification Number */
enum {
	CHIP_ID_GENESIS	   = 0x0a, /* Chip ID for GENESIS */
	CHIP_ID_YUKON	   = 0xb0, /* Chip ID for YUKON */
	CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
	CHIP_ID_YUKON_LP   = 0xb2, /* Chip ID for YUKON-LP */
	CHIP_ID_YUKON_XL   = 0xb3, /* Chip ID for YUKON-2 XL */
	CHIP_ID_YUKON_EC   = 0xb6, /* Chip ID for YUKON-2 EC */
 	CHIP_ID_YUKON_FE   = 0xb7, /* Chip ID for YUKON-2 FE */

	CHIP_REV_YU_LITE_A1  = 3,	/* Chip Rev. for YUKON-Lite A1,A2 */
	CHIP_REV_YU_LITE_A3  = 7,	/* Chip Rev. for YUKON-Lite A3 */
};

/*	B2_TI_CTRL		 8 bit	Timer control */
/*	B2_IRQM_CTRL	 8 bit	IRQ Moderation Timer Control */
enum {
	TIM_START	= 1<<2,	/* Start Timer */
	TIM_STOP	= 1<<1,	/* Stop  Timer */
	TIM_CLR_IRQ	= 1<<0,	/* Clear Timer IRQ (!IRQM) */
};

/*	B2_TI_TEST		 8 Bit	Timer Test */
/*	B2_IRQM_TEST	 8 bit	IRQ Moderation Timer Test */
/*	B28_DPT_TST		 8 bit	Descriptor Poll Timer Test Reg */
enum {
	TIM_T_ON	= 1<<2,	/* Test mode on */
	TIM_T_OFF	= 1<<1,	/* Test mode off */
	TIM_T_STEP	= 1<<0,	/* Test step */
};

/*	B2_GP_IO		32 bit	General Purpose I/O Register */
enum {
	GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
	GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
	GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
	GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
	GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
	GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
	GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
	GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
	GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
	GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */

	GP_IO_9	= 1<<9,	/* IO_9 pin */
	GP_IO_8	= 1<<8,	/* IO_8 pin */
	GP_IO_7	= 1<<7,	/* IO_7 pin */
	GP_IO_6	= 1<<6,	/* IO_6 pin */
	GP_IO_5	= 1<<5,	/* IO_5 pin */
	GP_IO_4	= 1<<4,	/* IO_4 pin */
	GP_IO_3	= 1<<3,	/* IO_3 pin */
	GP_IO_2	= 1<<2,	/* IO_2 pin */
	GP_IO_1	= 1<<1,	/* IO_1 pin */
	GP_IO_0	= 1<<0,	/* IO_0 pin */
};

/* Descriptor Bit Definition */
/*	TxCtrl		Transmit Buffer Control Field */
/*	RxCtrl		Receive  Buffer Control Field */
enum {
	BMU_OWN		= 1<<31, /* OWN bit: 0=host/1=BMU */
	BMU_STF		= 1<<30, /* Start of Frame */
	BMU_EOF		= 1<<29, /* End of Frame */
	BMU_IRQ_EOB	= 1<<28, /* Req "End of Buffer" IRQ */
	BMU_IRQ_EOF	= 1<<27, /* Req "End of Frame" IRQ */
				/* TxCtrl specific bits */
	BMU_STFWD	= 1<<26, /* (Tx)	Store & Forward Frame */
	BMU_NO_FCS	= 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
	BMU_SW	= 1<<24, /* (Tx)	1 bit res. for SW use */
				/* RxCtrl specific bits */
	BMU_DEV_0	= 1<<26, /* (Rx)	Transfer data to Dev0 */
	BMU_STAT_VAL	= 1<<25, /* (Rx)	Rx Status Valid */
	BMU_TIST_VAL	= 1<<24, /* (Rx)	Rx TimeStamp Valid */
			/* Bit 23..16:	BMU Check Opcodes */
	BMU_CHECK	= 0x55<<16, /* Default BMU check */
	BMU_TCP_CHECK	= 0x56<<16, /* Descr with TCP ext */
	BMU_UDP_CHECK	= 0x57<<16, /* Descr with UDP ext (YUKON only) */
	BMU_BBC		= 0xffffL, /* Bit 15.. 0:	Buffer Byte Counter */
};

/*	B2_BSC_CTRL		 8 bit	Blink Source Counter Control */
enum {
	 BSC_START	= 1<<1,	/* Start Blink Source Counter */
	 BSC_STOP	= 1<<0,	/* Stop  Blink Source Counter */
};

/*	B2_BSC_STAT		 8 bit	Blink Source Counter Status */
enum {
	BSC_SRC		= 1<<0,	/* Blink Source, 0=Off / 1=On */
};