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authorJohn Youn <John.Youn@synopsys.com>2017-01-17 23:30:27 -0500
committerFelipe Balbi <felipe.balbi@linux.intel.com>2017-01-24 04:04:18 -0500
commit9da5197475a09e51a467388308f14dcbdcee8ba9 (patch)
treeb1c4aa514bacc1abbd33b6cdffcb04db3e0b1908
parent33e4c1a9987a1fc3b42c3b534100b5b006d55c61 (diff)
usb: dwc2: Cleanup some checkpatch issues
This commmit is the result of running checkpatch --fix. The results were verified for correctness. Some of the fixes result in line over 80 char which we will fix manually later. The following is a summary of what was done by checkpatch: * Remove externs on function prototypes. * Replace symbolic permissions with octal. * Align code to open parens. * Replace 'unsigned' with 'unsigned int'. * Remove unneccessary blank lines. * Add blank lines after declarations. * Add spaces around operators. * Remove unnecessary spaces after casts. * Replace 'x == NULL' with '!x'. * Replace kzalloc() with kcalloc(). * Concatenate multi-line strings. * Use the BIT() macro. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat
-rw-r--r--drivers/usb/dwc2/core.c22
-rw-r--r--drivers/usb/dwc2/core.h69
-rw-r--r--drivers/usb/dwc2/core_intr.c6
-rw-r--r--drivers/usb/dwc2/debug.h4
-rw-r--r--drivers/usb/dwc2/debugfs.c26
-rw-r--r--drivers/usb/dwc2/gadget.c142
-rw-r--r--drivers/usb/dwc2/hcd.c35
-rw-r--r--drivers/usb/dwc2/hcd.h76
-rw-r--r--drivers/usb/dwc2/hcd_ddma.c11
-rw-r--r--drivers/usb/dwc2/hcd_intr.c23
-rw-r--r--drivers/usb/dwc2/hcd_queue.c20
-rw-r--r--drivers/usb/dwc2/hw.h596
-rw-r--r--drivers/usb/dwc2/params.c14
-rw-r--r--drivers/usb/dwc2/pci.c2
-rw-r--r--drivers/usb/dwc2/platform.c2
15 files changed, 521 insertions, 527 deletions
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 11d8ae9aead1..0446f3d6d54a 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -104,7 +104,7 @@ static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
104 gr = &hsotg->gr_backup; 104 gr = &hsotg->gr_backup;
105 if (!gr->valid) { 105 if (!gr->valid) {
106 dev_err(hsotg->dev, "%s: no global registers to restore\n", 106 dev_err(hsotg->dev, "%s: no global registers to restore\n",
107 __func__); 107 __func__);
108 return -EINVAL; 108 return -EINVAL;
109 } 109 }
110 gr->valid = false; 110 gr->valid = false;
@@ -155,21 +155,21 @@ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
155 ret = dwc2_restore_global_registers(hsotg); 155 ret = dwc2_restore_global_registers(hsotg);
156 if (ret) { 156 if (ret) {
157 dev_err(hsotg->dev, "%s: failed to restore registers\n", 157 dev_err(hsotg->dev, "%s: failed to restore registers\n",
158 __func__); 158 __func__);
159 return ret; 159 return ret;
160 } 160 }
161 if (dwc2_is_host_mode(hsotg)) { 161 if (dwc2_is_host_mode(hsotg)) {
162 ret = dwc2_restore_host_registers(hsotg); 162 ret = dwc2_restore_host_registers(hsotg);
163 if (ret) { 163 if (ret) {
164 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 164 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
165 __func__); 165 __func__);
166 return ret; 166 return ret;
167 } 167 }
168 } else { 168 } else {
169 ret = dwc2_restore_device_registers(hsotg); 169 ret = dwc2_restore_device_registers(hsotg);
170 if (ret) { 170 if (ret) {
171 dev_err(hsotg->dev, "%s: failed to restore device registers\n", 171 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
172 __func__); 172 __func__);
173 return ret; 173 return ret;
174 } 174 }
175 } 175 }
@@ -195,7 +195,7 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
195 ret = dwc2_backup_global_registers(hsotg); 195 ret = dwc2_backup_global_registers(hsotg);
196 if (ret) { 196 if (ret) {
197 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 197 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
198 __func__); 198 __func__);
199 return ret; 199 return ret;
200 } 200 }
201 201
@@ -203,14 +203,14 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
203 ret = dwc2_backup_host_registers(hsotg); 203 ret = dwc2_backup_host_registers(hsotg);
204 if (ret) { 204 if (ret) {
205 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 205 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
206 __func__); 206 __func__);
207 return ret; 207 return ret;
208 } 208 }
209 } else { 209 } else {
210 ret = dwc2_backup_device_registers(hsotg); 210 ret = dwc2_backup_device_registers(hsotg);
211 if (ret) { 211 if (ret) {
212 dev_err(hsotg->dev, "%s: failed to backup device registers\n", 212 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
213 __func__); 213 __func__);
214 return ret; 214 return ret;
215 } 215 }
216 } 216 }
@@ -793,7 +793,7 @@ void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
793} 793}
794 794
795/* Returns the controller's GHWCFG2.OTG_MODE. */ 795/* Returns the controller's GHWCFG2.OTG_MODE. */
796unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg) 796unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
797{ 797{
798 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 798 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
799 799
@@ -804,7 +804,7 @@ unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg)
804/* Returns true if the controller is capable of DRD. */ 804/* Returns true if the controller is capable of DRD. */
805bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) 805bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
806{ 806{
807 unsigned op_mode = dwc2_op_mode(hsotg); 807 unsigned int op_mode = dwc2_op_mode(hsotg);
808 808
809 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || 809 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
810 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || 810 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
@@ -814,7 +814,7 @@ bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
814/* Returns true if the controller is host-only. */ 814/* Returns true if the controller is host-only. */
815bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) 815bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
816{ 816{
817 unsigned op_mode = dwc2_op_mode(hsotg); 817 unsigned int op_mode = dwc2_op_mode(hsotg);
818 818
819 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || 819 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
820 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); 820 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
@@ -823,7 +823,7 @@ bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
823/* Returns true if the controller is device-only. */ 823/* Returns true if the controller is device-only. */
824bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) 824bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
825{ 825{
826 unsigned op_mode = dwc2_op_mode(hsotg); 826 unsigned int op_mode = dwc2_op_mode(hsotg);
827 827
828 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || 828 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
829 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); 829 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 302b8f5f7d27..ddc4654e0096 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -1101,37 +1101,37 @@ static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1101 * The following functions support initialization of the core driver component 1101 * The following functions support initialization of the core driver component
1102 * and the DWC_otg controller 1102 * and the DWC_otg controller
1103 */ 1103 */
1104extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); 1104int dwc2_core_reset(struct dwc2_hsotg *hsotg);
1105extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 1105int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
1106extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 1106int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1107extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 1107int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
1108 1108
1109bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host); 1109bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
1110void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg); 1110void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
1111void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1111void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1112 1112
1113extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1113bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1114 1114
1115/* 1115/*
1116 * Common core Functions. 1116 * Common core Functions.
1117 * The following functions support managing the DWC_otg controller in either 1117 * The following functions support managing the DWC_otg controller in either
1118 * device or host mode. 1118 * device or host mode.
1119 */ 1119 */
1120extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1120void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1121extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1121void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1122extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1122void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1123 1123
1124extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1124void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1125extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1125void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1126 1126
1127/* This function should be called on every hardware interrupt. */ 1127/* This function should be called on every hardware interrupt. */
1128extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1128irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1129 1129
1130/* The device ID match table */ 1130/* The device ID match table */
1131extern const struct of_device_id dwc2_of_match_table[]; 1131extern const struct of_device_id dwc2_of_match_table[];
1132 1132
1133extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1133int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1134extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1134int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1135 1135
1136/* Parameters */ 1136/* Parameters */
1137int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1137int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
@@ -1145,7 +1145,7 @@ int dwc2_init_params(struct dwc2_hsotg *hsotg);
1145 * are read in and cached so they always read directly from the 1145 * are read in and cached so they always read directly from the
1146 * GHWCFG2 register. 1146 * GHWCFG2 register.
1147 */ 1147 */
1148unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); 1148unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1149bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1149bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1150bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1150bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1151bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1151bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
@@ -1157,6 +1157,7 @@ static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1157{ 1157{
1158 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1158 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1159} 1159}
1160
1160static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1161static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1161{ 1162{
1162 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1163 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
@@ -1165,26 +1166,26 @@ static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1165/* 1166/*
1166 * Dump core registers and SPRAM 1167 * Dump core registers and SPRAM
1167 */ 1168 */
1168extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1169void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1169extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1170void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1170extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1171void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1171 1172
1172/* 1173/*
1173 * Return OTG version - either 1.3 or 2.0 1174 * Return OTG version - either 1.3 or 2.0
1174 */ 1175 */
1175extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1176u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1176 1177
1177/* Gadget defines */ 1178/* Gadget defines */
1178#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1179#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1179extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1180int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1180extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1181int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1181extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1182int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1182extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1183int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1183extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1184void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1184 bool reset); 1185 bool reset);
1185extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1186void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1186extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1187void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1187extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1188int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1188#define dwc2_is_device_connected(hsotg) (hsotg->connected) 1189#define dwc2_is_device_connected(hsotg) (hsotg->connected)
1189int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1190int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1190int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); 1191int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
@@ -1198,11 +1199,11 @@ static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1198static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1199static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1199{ return 0; } 1200{ return 0; }
1200static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1201static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1201 bool reset) {} 1202 bool reset) {}
1202static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1203static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1203static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1204static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1204static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1205static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1205 int testmode) 1206 int testmode)
1206{ return 0; } 1207{ return 0; }
1207#define dwc2_is_device_connected(hsotg) (0) 1208#define dwc2_is_device_connected(hsotg) (0)
1208static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1209static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
@@ -1212,11 +1213,11 @@ static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1212#endif 1213#endif
1213 1214
1214#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1215#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1215extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1216int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1216extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1217int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1217extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1218void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1218extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1219void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1219extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1220void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1220int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1221int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1221int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1222int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1222#else 1223#else
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index 5b228ba6045f..0d4a2aaaa5dd 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -317,7 +317,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
317 dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); 317 dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
318 318
319 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n", 319 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
320 hsotg->lx_state); 320 hsotg->lx_state);
321 321
322 if (dwc2_is_device_mode(hsotg)) { 322 if (dwc2_is_device_mode(hsotg)) {
323 if (hsotg->lx_state == DWC2_L2) { 323 if (hsotg->lx_state == DWC2_L2) {
@@ -437,7 +437,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
437 /* Ignore suspend request before enumeration */ 437 /* Ignore suspend request before enumeration */
438 if (!dwc2_is_device_connected(hsotg)) { 438 if (!dwc2_is_device_connected(hsotg)) {
439 dev_dbg(hsotg->dev, 439 dev_dbg(hsotg->dev,
440 "ignore suspend request before enumeration\n"); 440 "ignore suspend request before enumeration\n");
441 return; 441 return;
442 } 442 }
443 443
@@ -445,7 +445,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
445 if (ret) { 445 if (ret) {
446 if (ret != -ENOTSUPP) 446 if (ret != -ENOTSUPP)
447 dev_err(hsotg->dev, 447 dev_err(hsotg->dev,
448 "enter hibernation failed\n"); 448 "enter hibernation failed\n");
449 goto skip_power_saving; 449 goto skip_power_saving;
450 } 450 }
451 451
diff --git a/drivers/usb/dwc2/debug.h b/drivers/usb/dwc2/debug.h
index 12dbd1daec87..d3e52dd32f57 100644
--- a/drivers/usb/dwc2/debug.h
+++ b/drivers/usb/dwc2/debug.h
@@ -17,8 +17,8 @@
17#include "core.h" 17#include "core.h"
18 18
19#ifdef CONFIG_DEBUG_FS 19#ifdef CONFIG_DEBUG_FS
20extern int dwc2_debugfs_init(struct dwc2_hsotg *); 20int dwc2_debugfs_init(struct dwc2_hsotg *);
21extern void dwc2_debugfs_exit(struct dwc2_hsotg *); 21void dwc2_debugfs_exit(struct dwc2_hsotg *);
22#else 22#else
23static inline int dwc2_debugfs_init(struct dwc2_hsotg *hsotg) 23static inline int dwc2_debugfs_init(struct dwc2_hsotg *hsotg)
24{ return 0; } 24{ return 0; }
diff --git a/drivers/usb/dwc2/debugfs.c b/drivers/usb/dwc2/debugfs.c
index 0a130916a91c..cad621f02972 100644
--- a/drivers/usb/dwc2/debugfs.c
+++ b/drivers/usb/dwc2/debugfs.c
@@ -137,7 +137,7 @@ static int state_show(struct seq_file *seq, void *v)
137 int idx; 137 int idx;
138 138
139 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", 139 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
140 dwc2_readl(regs + DCFG), 140 dwc2_readl(regs + DCFG),
141 dwc2_readl(regs + DCTL), 141 dwc2_readl(regs + DCTL),
142 dwc2_readl(regs + DSTS)); 142 dwc2_readl(regs + DSTS));
143 143
@@ -338,23 +338,23 @@ static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg)
338{ 338{
339 struct dentry *root; 339 struct dentry *root;
340 struct dentry *file; 340 struct dentry *file;
341 unsigned epidx; 341 unsigned int epidx;
342 342
343 root = hsotg->debug_root; 343 root = hsotg->debug_root;
344 344
345 /* create general state file */ 345 /* create general state file */
346 346
347 file = debugfs_create_file("state", S_IRUGO, root, hsotg, &state_fops); 347 file = debugfs_create_file("state", 0444, root, hsotg, &state_fops);
348 if (IS_ERR(file)) 348 if (IS_ERR(file))
349 dev_err(hsotg->dev, "%s: failed to create state\n", __func__); 349 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
350 350
351 file = debugfs_create_file("testmode", S_IRUGO | S_IWUSR, root, hsotg, 351 file = debugfs_create_file("testmode", 0644, root, hsotg,
352 &testmode_fops); 352 &testmode_fops);
353 if (IS_ERR(file)) 353 if (IS_ERR(file))
354 dev_err(hsotg->dev, "%s: failed to create testmode\n", 354 dev_err(hsotg->dev, "%s: failed to create testmode\n",
355 __func__); 355 __func__);
356 356
357 file = debugfs_create_file("fifo", S_IRUGO, root, hsotg, &fifo_fops); 357 file = debugfs_create_file("fifo", 0444, root, hsotg, &fifo_fops);
358 if (IS_ERR(file)) 358 if (IS_ERR(file))
359 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__); 359 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
360 360
@@ -364,8 +364,8 @@ static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg)
364 364
365 ep = hsotg->eps_out[epidx]; 365 ep = hsotg->eps_out[epidx];
366 if (ep) { 366 if (ep) {
367 file = debugfs_create_file(ep->name, S_IRUGO, 367 file = debugfs_create_file(ep->name, 0444,
368 root, ep, &ep_fops); 368 root, ep, &ep_fops);
369 if (IS_ERR(file)) 369 if (IS_ERR(file))
370 dev_err(hsotg->dev, "failed to create %s debug file\n", 370 dev_err(hsotg->dev, "failed to create %s debug file\n",
371 ep->name); 371 ep->name);
@@ -377,8 +377,8 @@ static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg)
377 377
378 ep = hsotg->eps_in[epidx]; 378 ep = hsotg->eps_in[epidx];
379 if (ep) { 379 if (ep) {
380 file = debugfs_create_file(ep->name, S_IRUGO, 380 file = debugfs_create_file(ep->name, 0444,
381 root, ep, &ep_fops); 381 root, ep, &ep_fops);
382 if (IS_ERR(file)) 382 if (IS_ERR(file))
383 dev_err(hsotg->dev, "failed to create %s debug file\n", 383 dev_err(hsotg->dev, "failed to create %s debug file\n",
384 ep->name); 384 ep->name);
@@ -750,8 +750,8 @@ int dwc2_debugfs_init(struct dwc2_hsotg *hsotg)
750 hsotg->regset->nregs = ARRAY_SIZE(dwc2_regs); 750 hsotg->regset->nregs = ARRAY_SIZE(dwc2_regs);
751 hsotg->regset->base = hsotg->regs; 751 hsotg->regset->base = hsotg->regs;
752 752
753 file = debugfs_create_regset32("regdump", S_IRUGO, hsotg->debug_root, 753 file = debugfs_create_regset32("regdump", 0444, hsotg->debug_root,
754 hsotg->regset); 754 hsotg->regset);
755 if (!file) { 755 if (!file) {
756 ret = -ENOMEM; 756 ret = -ENOMEM;
757 goto err1; 757 goto err1;
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index c55db4aa54d6..c6485ca97656 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -171,7 +171,7 @@ static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
171 * request. 171 * request.
172 */ 172 */
173static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, 173static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
174 unsigned int ep, unsigned int dir_in, 174 unsigned int ep, unsigned int dir_in,
175 unsigned int en) 175 unsigned int en)
176{ 176{
177 unsigned long flags; 177 unsigned long flags;
@@ -277,7 +277,7 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
277 * Allocate a new USB request structure appropriate for the specified endpoint 277 * Allocate a new USB request structure appropriate for the specified endpoint
278 */ 278 */
279static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, 279static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
280 gfp_t flags) 280 gfp_t flags)
281{ 281{
282 struct dwc2_hsotg_req *req; 282 struct dwc2_hsotg_req *req;
283 283
@@ -312,10 +312,11 @@ static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
312 * of a request to ensure the buffer is ready for access by the caller. 312 * of a request to ensure the buffer is ready for access by the caller.
313 */ 313 */
314static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, 314static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
315 struct dwc2_hsotg_ep *hs_ep, 315 struct dwc2_hsotg_ep *hs_ep,
316 struct dwc2_hsotg_req *hs_req) 316 struct dwc2_hsotg_req *hs_req)
317{ 317{
318 struct usb_request *req = &hs_req->req; 318 struct usb_request *req = &hs_req->req;
319
319 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); 320 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
320} 321}
321 322
@@ -384,7 +385,7 @@ fail:
384 * This routine is only needed for PIO 385 * This routine is only needed for PIO
385 */ 386 */
386static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, 387static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
387 struct dwc2_hsotg_ep *hs_ep, 388 struct dwc2_hsotg_ep *hs_ep,
388 struct dwc2_hsotg_req *hs_req) 389 struct dwc2_hsotg_req *hs_req)
389{ 390{
390 bool periodic = is_ep_periodic(hs_ep); 391 bool periodic = is_ep_periodic(hs_ep);
@@ -466,7 +467,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
466 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; 467 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
467 468
468 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", 469 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
469 __func__, gnptxsts, can_write, to_write, max_transfer); 470 __func__, gnptxsts, can_write, to_write, max_transfer);
470 471
471 /* 472 /*
472 * limit to 512 bytes of data, it seems at least on the non-periodic 473 * limit to 512 bytes of data, it seems at least on the non-periodic
@@ -487,7 +488,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
487 /* it's needed only when we do not use dedicated fifos */ 488 /* it's needed only when we do not use dedicated fifos */
488 if (!hsotg->dedicated_fifos) 489 if (!hsotg->dedicated_fifos)
489 dwc2_hsotg_en_gsint(hsotg, 490 dwc2_hsotg_en_gsint(hsotg,
490 periodic ? GINTSTS_PTXFEMP : 491 periodic ? GINTSTS_PTXFEMP :
491 GINTSTS_NPTXFEMP); 492 GINTSTS_NPTXFEMP);
492 } 493 }
493 494
@@ -516,12 +517,12 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
516 /* it's needed only when we do not use dedicated fifos */ 517 /* it's needed only when we do not use dedicated fifos */
517 if (!hsotg->dedicated_fifos) 518 if (!hsotg->dedicated_fifos)
518 dwc2_hsotg_en_gsint(hsotg, 519 dwc2_hsotg_en_gsint(hsotg,
519 periodic ? GINTSTS_PTXFEMP : 520 periodic ? GINTSTS_PTXFEMP :
520 GINTSTS_NPTXFEMP); 521 GINTSTS_NPTXFEMP);
521 } 522 }
522 523
523 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", 524 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
524 to_write, hs_req->req.length, can_write, buf_pos); 525 to_write, hs_req->req.length, can_write, buf_pos);
525 526
526 if (to_write <= 0) 527 if (to_write <= 0)
527 return -ENOSPC; 528 return -ENOSPC;
@@ -547,17 +548,17 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
547 * Return the maximum data that can be queued in one go on a given endpoint 548 * Return the maximum data that can be queued in one go on a given endpoint
548 * so that transfers that are too long can be split. 549 * so that transfers that are too long can be split.
549 */ 550 */
550static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep) 551static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
551{ 552{
552 int index = hs_ep->index; 553 int index = hs_ep->index;
553 unsigned maxsize; 554 unsigned int maxsize;
554 unsigned maxpkt; 555 unsigned int maxpkt;
555 556
556 if (index != 0) { 557 if (index != 0) {
557 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; 558 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
558 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; 559 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
559 } else { 560 } else {
560 maxsize = 64+64; 561 maxsize = 64 + 64;
561 if (hs_ep->dir_in) 562 if (hs_ep->dir_in)
562 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; 563 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
563 else 564 else
@@ -874,7 +875,7 @@ static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
874 * appropriately, and writing any data to the FIFOs. 875 * appropriately, and writing any data to the FIFOs.
875 */ 876 */
876static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, 877static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
877 struct dwc2_hsotg_ep *hs_ep, 878 struct dwc2_hsotg_ep *hs_ep,
878 struct dwc2_hsotg_req *hs_req, 879 struct dwc2_hsotg_req *hs_req,
879 bool continuing) 880 bool continuing)
880{ 881{
@@ -885,9 +886,9 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
885 u32 epsize_reg; 886 u32 epsize_reg;
886 u32 epsize; 887 u32 epsize;
887 u32 ctrl; 888 u32 ctrl;
888 unsigned length; 889 unsigned int length;
889 unsigned packets; 890 unsigned int packets;
890 unsigned maxreq; 891 unsigned int maxreq;
891 unsigned int dma_reg; 892 unsigned int dma_reg;
892 893
893 if (index != 0) { 894 if (index != 0) {
@@ -966,7 +967,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
966 if (dir_in && ureq->zero && !continuing) { 967 if (dir_in && ureq->zero && !continuing) {
967 /* Test if zlp is actually required. */ 968 /* Test if zlp is actually required. */
968 if ((ureq->length >= hs_ep->ep.maxpacket) && 969 if ((ureq->length >= hs_ep->ep.maxpacket) &&
969 !(ureq->length % hs_ep->ep.maxpacket)) 970 !(ureq->length % hs_ep->ep.maxpacket))
970 hs_ep->send_zlp = 1; 971 hs_ep->send_zlp = 1;
971 } 972 }
972 973
@@ -1070,7 +1071,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1070 /* check ep is enabled */ 1071 /* check ep is enabled */
1071 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) 1072 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1072 dev_dbg(hsotg->dev, 1073 dev_dbg(hsotg->dev,
1073 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", 1074 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1074 index, dwc2_readl(hsotg->regs + epctrl_reg)); 1075 index, dwc2_readl(hsotg->regs + epctrl_reg));
1075 1076
1076 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", 1077 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
@@ -1093,7 +1094,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1093 * cleanup on completion. 1094 * cleanup on completion.
1094 */ 1095 */
1095static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, 1096static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1096 struct dwc2_hsotg_ep *hs_ep, 1097 struct dwc2_hsotg_ep *hs_ep,
1097 struct usb_request *req) 1098 struct usb_request *req)
1098{ 1099{
1099 int ret; 1100 int ret;
@@ -1112,7 +1113,7 @@ dma_error:
1112} 1113}
1113 1114
1114static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, 1115static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1115 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) 1116 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
1116{ 1117{
1117 void *req_buf = hs_req->req.buf; 1118 void *req_buf = hs_req->req.buf;
1118 1119
@@ -1123,7 +1124,7 @@ static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1123 WARN_ON(hs_req->saved_req_buf); 1124 WARN_ON(hs_req->saved_req_buf);
1124 1125
1125 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, 1126 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1126 hs_ep->ep.name, req_buf, hs_req->req.length); 1127 hs_ep->ep.name, req_buf, hs_req->req.length);
1127 1128
1128 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); 1129 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1129 if (!hs_req->req.buf) { 1130 if (!hs_req->req.buf) {
@@ -1143,7 +1144,7 @@ static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1143} 1144}
1144 1145
1145static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, 1146static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1146 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) 1147 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
1147{ 1148{
1148 /* If dma is not being used or buffer was aligned */ 1149 /* If dma is not being used or buffer was aligned */
1149 if (!using_dma(hsotg) || !hs_req->saved_req_buf) 1150 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
@@ -1155,7 +1156,7 @@ static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1155 /* Copy data from bounce buffer on successful out transfer */ 1156 /* Copy data from bounce buffer on successful out transfer */
1156 if (!hs_ep->dir_in && !hs_req->req.status) 1157 if (!hs_ep->dir_in && !hs_req->req.status)
1157 memcpy(hs_req->saved_req_buf, hs_req->req.buf, 1158 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1158 hs_req->req.actual); 1159 hs_req->req.actual);
1159 1160
1160 /* Free bounce buffer */ 1161 /* Free bounce buffer */
1161 kfree(hs_req->req.buf); 1162 kfree(hs_req->req.buf);
@@ -1224,7 +1225,7 @@ static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1224} 1225}
1225 1226
1226static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, 1227static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1227 gfp_t gfp_flags) 1228 gfp_t gfp_flags)
1228{ 1229{
1229 struct dwc2_hsotg_req *hs_req = our_req(req); 1230 struct dwc2_hsotg_req *hs_req = our_req(req);
1230 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1231 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
@@ -1239,7 +1240,7 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1239 /* Prevent new request submission when controller is suspended */ 1240 /* Prevent new request submission when controller is suspended */
1240 if (hs->lx_state == DWC2_L2) { 1241 if (hs->lx_state == DWC2_L2) {
1241 dev_dbg(hs->dev, "%s: don't submit request while suspended\n", 1242 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
1242 __func__); 1243 __func__);
1243 return -EAGAIN; 1244 return -EAGAIN;
1244 } 1245 }
1245 1246
@@ -1300,7 +1301,7 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1300} 1301}
1301 1302
1302static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, 1303static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1303 gfp_t gfp_flags) 1304 gfp_t gfp_flags)
1304{ 1305{
1305 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1306 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1306 struct dwc2_hsotg *hs = hs_ep->parent; 1307 struct dwc2_hsotg *hs = hs_ep->parent;
@@ -1315,7 +1316,7 @@ static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1315} 1316}
1316 1317
1317static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, 1318static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1318 struct usb_request *req) 1319 struct usb_request *req)
1319{ 1320{
1320 struct dwc2_hsotg_req *hs_req = our_req(req); 1321 struct dwc2_hsotg_req *hs_req = our_req(req);
1321 1322
@@ -1331,7 +1332,7 @@ static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1331 * submitted that need cleaning up. 1332 * submitted that need cleaning up.
1332 */ 1333 */
1333static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, 1334static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1334 struct usb_request *req) 1335 struct usb_request *req)
1335{ 1336{
1336 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1337 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1337 struct dwc2_hsotg *hsotg = hs_ep->parent; 1338 struct dwc2_hsotg *hsotg = hs_ep->parent;
@@ -1350,7 +1351,7 @@ static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1350 * structure, or return NULL if it is not a valid endpoint. 1351 * structure, or return NULL if it is not a valid endpoint.
1351 */ 1352 */
1352static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, 1353static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1353 u32 windex) 1354 u32 windex)
1354{ 1355{
1355 struct dwc2_hsotg_ep *ep; 1356 struct dwc2_hsotg_ep *ep;
1356 int dir = (windex & USB_DIR_IN) ? 1 : 0; 1357 int dir = (windex & USB_DIR_IN) ? 1 : 0;
@@ -1407,7 +1408,7 @@ int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1407 * an internal method of sending replies to certain control requests, etc. 1408 * an internal method of sending replies to certain control requests, etc.
1408 */ 1409 */
1409static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, 1410static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1410 struct dwc2_hsotg_ep *ep, 1411 struct dwc2_hsotg_ep *ep,
1411 void *buff, 1412 void *buff,
1412 int length) 1413 int length)
1413{ 1414{
@@ -1450,7 +1451,7 @@ static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1450 * @ctrl: USB control request 1451 * @ctrl: USB control request
1451 */ 1452 */
1452static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, 1453static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1453 struct usb_ctrlrequest *ctrl) 1454 struct usb_ctrlrequest *ctrl)
1454{ 1455{
1455 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 1456 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1456 struct dwc2_hsotg_ep *ep; 1457 struct dwc2_hsotg_ep *ep;
@@ -1555,7 +1556,7 @@ static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1555 * @ctrl: USB control request 1556 * @ctrl: USB control request
1556 */ 1557 */
1557static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, 1558static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1558 struct usb_ctrlrequest *ctrl) 1559 struct usb_ctrlrequest *ctrl)
1559{ 1560{
1560 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 1561 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1561 struct dwc2_hsotg_req *hs_req; 1562 struct dwc2_hsotg_req *hs_req;
@@ -1705,7 +1706,7 @@ static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1705 * gadget driver). 1706 * gadget driver).
1706 */ 1707 */
1707static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, 1708static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1708 struct usb_ctrlrequest *ctrl) 1709 struct usb_ctrlrequest *ctrl)
1709{ 1710{
1710 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 1711 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1711 int ret = 0; 1712 int ret = 0;
@@ -1781,7 +1782,7 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1781 * EP0 setup packets 1782 * EP0 setup packets
1782 */ 1783 */
1783static void dwc2_hsotg_complete_setup(struct usb_ep *ep, 1784static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1784 struct usb_request *req) 1785 struct usb_request *req)
1785{ 1786{
1786 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1787 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1787 struct dwc2_hsotg *hsotg = hs_ep->parent; 1788 struct dwc2_hsotg *hsotg = hs_ep->parent;
@@ -1839,7 +1840,7 @@ static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1839} 1840}
1840 1841
1841static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, 1842static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1842 struct dwc2_hsotg_ep *hs_ep) 1843 struct dwc2_hsotg_ep *hs_ep)
1843{ 1844{
1844 u32 ctrl; 1845 u32 ctrl;
1845 u8 index = hs_ep->index; 1846 u8 index = hs_ep->index;
@@ -1885,11 +1886,10 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1885 * Note, expects the ep to already be locked as appropriate. 1886 * Note, expects the ep to already be locked as appropriate.
1886 */ 1887 */
1887static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, 1888static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1888 struct dwc2_hsotg_ep *hs_ep, 1889 struct dwc2_hsotg_ep *hs_ep,
1889 struct dwc2_hsotg_req *hs_req, 1890 struct dwc2_hsotg_req *hs_req,
1890 int result) 1891 int result)
1891{ 1892{
1892
1893 if (!hs_req) { 1893 if (!hs_req) {
1894 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); 1894 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1895 return; 1895 return;
@@ -2068,13 +2068,12 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2068 int max_req; 2068 int max_req;
2069 int read_ptr; 2069 int read_ptr;
2070 2070
2071
2072 if (!hs_req) { 2071 if (!hs_req) {
2073 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); 2072 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
2074 int ptr; 2073 int ptr;
2075 2074
2076 dev_dbg(hsotg->dev, 2075 dev_dbg(hsotg->dev,
2077 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", 2076 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2078 __func__, size, ep_idx, epctl); 2077 __func__, size, ep_idx, epctl);
2079 2078
2080 /* dump the data from the FIFO, we've nothing we can do */ 2079 /* dump the data from the FIFO, we've nothing we can do */
@@ -2134,7 +2133,7 @@ static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2134} 2133}
2135 2134
2136static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, 2135static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2137 u32 epctl_reg) 2136 u32 epctl_reg)
2138{ 2137{
2139 u32 ctrl; 2138 u32 ctrl;
2140 2139
@@ -2191,7 +2190,7 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2191 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; 2190 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2192 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2191 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2193 struct usb_request *req = &hs_req->req; 2192 struct usb_request *req = &hs_req->req;
2194 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); 2193 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2195 int result = 0; 2194 int result = 0;
2196 2195
2197 if (!hs_req) { 2196 if (!hs_req) {
@@ -2210,7 +2209,7 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2210 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); 2209 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2211 2210
2212 if (using_dma(hsotg)) { 2211 if (using_dma(hsotg)) {
2213 unsigned size_done; 2212 unsigned int size_done;
2214 2213
2215 /* 2214 /*
2216 * Calculate the size of the transfer by checking how much 2215 * Calculate the size of the transfer by checking how much
@@ -2295,7 +2294,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2295 size >>= GRXSTS_BYTECNT_SHIFT; 2294 size >>= GRXSTS_BYTECNT_SHIFT;
2296 2295
2297 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", 2296 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2298 __func__, grxstsr, size, epnum); 2297 __func__, grxstsr, size, epnum);
2299 2298
2300 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { 2299 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2301 case GRXSTS_PKTSTS_GLOBALOUTNAK: 2300 case GRXSTS_PKTSTS_GLOBALOUTNAK:
@@ -2470,7 +2469,7 @@ static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2470 * make an attempt to write data into the FIFO. 2469 * make an attempt to write data into the FIFO.
2471 */ 2470 */
2472static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, 2471static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2473 struct dwc2_hsotg_ep *hs_ep) 2472 struct dwc2_hsotg_ep *hs_ep)
2474{ 2473{
2475 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2474 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2476 2475
@@ -2481,7 +2480,7 @@ static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2481 */ 2480 */
2482 if (hs_ep->index != 0) 2481 if (hs_ep->index != 0)
2483 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, 2482 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2484 hs_ep->dir_in, 0); 2483 hs_ep->dir_in, 0);
2485 return 0; 2484 return 0;
2486 } 2485 }
2487 2486
@@ -2503,7 +2502,7 @@ static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2503 * call the relevant completion routines. 2502 * call the relevant completion routines.
2504 */ 2503 */
2505static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, 2504static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2506 struct dwc2_hsotg_ep *hs_ep) 2505 struct dwc2_hsotg_ep *hs_ep)
2507{ 2506{
2508 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2507 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2509 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); 2508 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
@@ -2531,7 +2530,7 @@ static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2531 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); 2530 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2532 if (ret < 0) { 2531 if (ret < 0) {
2533 dev_dbg(hsotg->dev, "Invalid Test #%d\n", 2532 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2534 hsotg->test_mode); 2533 hsotg->test_mode);
2535 dwc2_hsotg_stall_ep0(hsotg); 2534 dwc2_hsotg_stall_ep0(hsotg);
2536 return; 2535 return;
2537 } 2536 }
@@ -2807,7 +2806,7 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2807 * Process and clear any interrupt pending for an individual endpoint 2806 * Process and clear any interrupt pending for an individual endpoint
2808 */ 2807 */
2809static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, 2808static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2810 int dir_in) 2809 int dir_in)
2811{ 2810{
2812 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); 2811 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2813 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); 2812 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
@@ -2824,7 +2823,7 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2824 2823
2825 if (!hs_ep) { 2824 if (!hs_ep) {
2826 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", 2825 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2827 __func__, idx, dir_in ? "in" : "out"); 2826 __func__, idx, dir_in ? "in" : "out");
2828 return; 2827 return;
2829 } 2828 }
2830 2829
@@ -3059,13 +3058,13 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg,
3059 int result) 3058 int result)
3060{ 3059{
3061 struct dwc2_hsotg_req *req, *treq; 3060 struct dwc2_hsotg_req *req, *treq;
3062 unsigned size; 3061 unsigned int size;
3063 3062
3064 ep->req = NULL; 3063 ep->req = NULL;
3065 3064
3066 list_for_each_entry_safe(req, treq, &ep->queue, queue) 3065 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3067 dwc2_hsotg_complete_request(hsotg, ep, req, 3066 dwc2_hsotg_complete_request(hsotg, ep, req,
3068 result); 3067 result);
3069 3068
3070 if (!hsotg->dedicated_fifos) 3069 if (!hsotg->dedicated_fifos)
3071 return; 3070 return;
@@ -3084,7 +3083,7 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg,
3084 */ 3083 */
3085void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) 3084void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3086{ 3085{
3087 unsigned ep; 3086 unsigned int ep;
3088 3087
3089 if (!hsotg->connected) 3088 if (!hsotg->connected)
3090 return; 3089 return;
@@ -3095,10 +3094,10 @@ void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3095 for (ep = 0; ep < hsotg->num_of_eps; ep++) { 3094 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3096 if (hsotg->eps_in[ep]) 3095 if (hsotg->eps_in[ep])
3097 kill_all_requests(hsotg, hsotg->eps_in[ep], 3096 kill_all_requests(hsotg, hsotg->eps_in[ep],
3098 -ESHUTDOWN); 3097 -ESHUTDOWN);
3099 if (hsotg->eps_out[ep]) 3098 if (hsotg->eps_out[ep])
3100 kill_all_requests(hsotg, hsotg->eps_out[ep], 3099 kill_all_requests(hsotg, hsotg->eps_out[ep],
3101 -ESHUTDOWN); 3100 -ESHUTDOWN);
3102 } 3101 }
3103 3102
3104 call_gadget(hsotg, disconnect); 3103 call_gadget(hsotg, disconnect);
@@ -3147,7 +3146,7 @@ static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3147 * Issue a soft reset to the core, and await the core finishing it. 3146 * Issue a soft reset to the core, and await the core finishing it.
3148 */ 3147 */
3149void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, 3148void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3150 bool is_usb_reset) 3149 bool is_usb_reset)
3151{ 3150{
3152 u32 intmsk; 3151 u32 intmsk;
3153 u32 val; 3152 u32 val;
@@ -3462,7 +3461,6 @@ irq_retry:
3462 } 3461 }
3463 3462
3464 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { 3463 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3465
3466 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); 3464 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
3467 u32 connected = hsotg->connected; 3465 u32 connected = hsotg->connected;
3468 3466
@@ -3705,7 +3703,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3705 * This is called from the USB gadget code's usb_ep_enable(). 3703 * This is called from the USB gadget code's usb_ep_enable().
3706 */ 3704 */
3707static int dwc2_hsotg_ep_enable(struct usb_ep *ep, 3705static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3708 const struct usb_endpoint_descriptor *desc) 3706 const struct usb_endpoint_descriptor *desc)
3709{ 3707{
3710 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 3708 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3711 struct dwc2_hsotg *hsotg = hs_ep->parent; 3709 struct dwc2_hsotg *hsotg = hs_ep->parent;
@@ -3827,12 +3825,13 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3827 if (dir_in && hsotg->dedicated_fifos) { 3825 if (dir_in && hsotg->dedicated_fifos) {
3828 u32 fifo_index = 0; 3826 u32 fifo_index = 0;
3829 u32 fifo_size = UINT_MAX; 3827 u32 fifo_size = UINT_MAX;
3830 size = hs_ep->ep.maxpacket*hs_ep->mc; 3828
3829 size = hs_ep->ep.maxpacket * hs_ep->mc;
3831 for (i = 1; i < hsotg->num_of_eps; ++i) { 3830 for (i = 1; i < hsotg->num_of_eps; ++i) {
3832 if (hsotg->fifo_map & (1<<i)) 3831 if (hsotg->fifo_map & (1 << i))
3833 continue; 3832 continue;
3834 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 3833 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
3835 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; 3834 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3836 if (val < size) 3835 if (val < size)
3837 continue; 3836 continue;
3838 /* Search for smallest acceptable fifo */ 3837 /* Search for smallest acceptable fifo */
@@ -4041,12 +4040,11 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4041 epctl &= ~DXEPCTL_STALL; 4040 epctl &= ~DXEPCTL_STALL;
4042 xfertype = epctl & DXEPCTL_EPTYPE_MASK; 4041 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4043 if (xfertype == DXEPCTL_EPTYPE_BULK || 4042 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4044 xfertype == DXEPCTL_EPTYPE_INTERRUPT) 4043 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4045 epctl |= DXEPCTL_SETD0PID; 4044 epctl |= DXEPCTL_SETD0PID;
4046 } 4045 }
4047 dwc2_writel(epctl, hs->regs + epreg); 4046 dwc2_writel(epctl, hs->regs + epreg);
4048 } else { 4047 } else {
4049
4050 epreg = DOEPCTL(index); 4048 epreg = DOEPCTL(index);
4051 epctl = dwc2_readl(hs->regs + epreg); 4049 epctl = dwc2_readl(hs->regs + epreg);
4052 4050
@@ -4056,7 +4054,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4056 epctl &= ~DXEPCTL_STALL; 4054 epctl &= ~DXEPCTL_STALL;
4057 xfertype = epctl & DXEPCTL_EPTYPE_MASK; 4055 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4058 if (xfertype == DXEPCTL_EPTYPE_BULK || 4056 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4059 xfertype == DXEPCTL_EPTYPE_INTERRUPT) 4057 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4060 epctl |= DXEPCTL_SETD0PID; 4058 epctl |= DXEPCTL_SETD0PID;
4061 } 4059 }
4062 dwc2_writel(epctl, hs->regs + epreg); 4060 dwc2_writel(epctl, hs->regs + epreg);
@@ -4098,7 +4096,7 @@ static struct usb_ep_ops dwc2_hsotg_ep_ops = {
4098}; 4096};
4099 4097
4100/** 4098/**
4101 * dwc2_hsotg_init - initalize the usb core 4099 * dwc2_hsotg_init - initialize the usb core
4102 * @hsotg: The driver state 4100 * @hsotg: The driver state
4103 */ 4101 */
4104static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) 4102static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
@@ -4152,7 +4150,7 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4152 * to work. 4150 * to work.
4153 */ 4151 */
4154static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, 4152static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4155 struct usb_gadget_driver *driver) 4153 struct usb_gadget_driver *driver)
4156{ 4154{
4157 struct dwc2_hsotg *hsotg = to_hsotg(gadget); 4155 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4158 unsigned long flags; 4156 unsigned long flags;
@@ -4275,7 +4273,7 @@ static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4275 unsigned long flags = 0; 4273 unsigned long flags = 0;
4276 4274
4277 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, 4275 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4278 hsotg->op_state); 4276 hsotg->op_state);
4279 4277
4280 /* Don't modify pullup state while in host mode */ 4278 /* Don't modify pullup state while in host mode */
4281 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { 4279 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
@@ -4337,7 +4335,7 @@ static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4337 * 4335 *
4338 * Report how much power the device may consume to the phy. 4336 * Report how much power the device may consume to the phy.
4339 */ 4337 */
4340static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) 4338static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4341{ 4339{
4342 struct dwc2_hsotg *hsotg = to_hsotg(gadget); 4340 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4343 4341
@@ -4366,7 +4364,7 @@ static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4366 * direction information and other state that may be required. 4364 * direction information and other state that may be required.
4367 */ 4365 */
4368static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, 4366static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4369 struct dwc2_hsotg_ep *hs_ep, 4367 struct dwc2_hsotg_ep *hs_ep,
4370 int epnum, 4368 int epnum,
4371 bool dir_in) 4369 bool dir_in)
4372{ 4370{
@@ -4423,6 +4421,7 @@ static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4423 4421
4424 if (using_dma(hsotg)) { 4422 if (using_dma(hsotg)) {
4425 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); 4423 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4424
4426 if (dir_in) 4425 if (dir_in)
4427 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); 4426 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
4428 else 4427 else
@@ -4529,7 +4528,6 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4529 idx, dwc2_readl(regs + DOEPCTL(idx)), 4528 idx, dwc2_readl(regs + DOEPCTL(idx)),
4530 dwc2_readl(regs + DOEPTSIZ(idx)), 4529 dwc2_readl(regs + DOEPTSIZ(idx)),
4531 dwc2_readl(regs + DOEPDMA(idx))); 4530 dwc2_readl(regs + DOEPDMA(idx)));
4532
4533 } 4531 }
4534 4532
4535 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", 4533 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
@@ -4584,7 +4582,7 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
4584 } 4582 }
4585 4583
4586 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, 4584 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
4587 dev_name(hsotg->dev), hsotg); 4585 dev_name(hsotg->dev), hsotg);
4588 if (ret < 0) { 4586 if (ret < 0) {
4589 dev_err(dev, "cannot claim IRQ for gadget\n"); 4587 dev_err(dev, "cannot claim IRQ for gadget\n");
4590 return ret; 4588 return ret;
@@ -4615,10 +4613,10 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
4615 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { 4613 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4616 if (hsotg->eps_in[epnum]) 4614 if (hsotg->eps_in[epnum])
4617 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], 4615 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4618 epnum, 1); 4616 epnum, 1);
4619 if (hsotg->eps_out[epnum]) 4617 if (hsotg->eps_out[epnum])
4620 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], 4618 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4621 epnum, 0); 4619 epnum, 0);
4622 } 4620 }
4623 4621
4624 ret = usb_add_gadget_udc(dev, &hsotg->gadget); 4622 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index dcfab67019fd..181890f8cfc7 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -2577,7 +2577,7 @@ static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2577 return; 2577 return;
2578 2578
2579 temp = container_of(urb->transfer_buffer, 2579 temp = container_of(urb->transfer_buffer,
2580 struct dma_aligned_buffer, data); 2580 struct dma_aligned_buffer, data);
2581 2581
2582 if (usb_urb_dir_in(urb)) 2582 if (usb_urb_dir_in(urb))
2583 memcpy(temp->old_xfer_buffer, temp->data, 2583 memcpy(temp->old_xfer_buffer, temp->data,
@@ -2621,7 +2621,7 @@ static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2621} 2621}
2622 2622
2623static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2623static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2624 gfp_t mem_flags) 2624 gfp_t mem_flags)
2625{ 2625{
2626 int ret; 2626 int ret;
2627 2627
@@ -2718,7 +2718,7 @@ static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2718 chan->multi_count = 1; 2718 chan->multi_count = 1;
2719 2719
2720 if (urb->actual_length > urb->length && 2720 if (urb->actual_length > urb->length &&
2721 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2721 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2722 urb->actual_length = urb->length; 2722 urb->actual_length = urb->length;
2723 2723
2724 if (hsotg->params.host_dma > 0) 2724 if (hsotg->params.host_dma > 0)
@@ -2989,7 +2989,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2989 * the middle of multiple high-bandwidth packets getting queued. 2989 * the middle of multiple high-bandwidth packets getting queued.
2990 */ 2990 */
2991 if (hsotg->params.host_dma <= 0 && 2991 if (hsotg->params.host_dma <= 0 &&
2992 qh->channel->multi_count > 1) 2992 qh->channel->multi_count > 1)
2993 hsotg->queuing_high_bandwidth = 1; 2993 hsotg->queuing_high_bandwidth = 1;
2994 2994
2995 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2995 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
@@ -4047,7 +4047,7 @@ static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4047{ 4047{
4048 struct wrapper_priv_data *p; 4048 struct wrapper_priv_data *p;
4049 4049
4050 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 4050 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4051 return p->hsotg; 4051 return p->hsotg;
4052} 4052}
4053 4053
@@ -4082,7 +4082,7 @@ struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4082 *ttport = urb->dev->ttport; 4082 *ttport = urb->dev->ttport;
4083 4083
4084 dwc_tt = urb->dev->tt->hcpriv; 4084 dwc_tt = urb->dev->tt->hcpriv;
4085 if (dwc_tt == NULL) { 4085 if (!dwc_tt) {
4086 size_t bitmap_size; 4086 size_t bitmap_size;
4087 4087
4088 /* 4088 /*
@@ -4096,7 +4096,7 @@ struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4096 4096
4097 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4097 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4098 mem_flags); 4098 mem_flags);
4099 if (dwc_tt == NULL) 4099 if (!dwc_tt)
4100 return NULL; 4100 return NULL;
4101 4101
4102 dwc_tt->usb_tt = urb->dev->tt; 4102 dwc_tt->usb_tt = urb->dev->tt;
@@ -4123,7 +4123,7 @@ struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4123void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4123void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4124{ 4124{
4125 /* Model kfree and make put of NULL a no-op */ 4125 /* Model kfree and make put of NULL a no-op */
4126 if (dwc_tt == NULL) 4126 if (!dwc_tt)
4127 return; 4127 return;
4128 4128
4129 WARN_ON(dwc_tt->refcount < 1); 4129 WARN_ON(dwc_tt->refcount < 1);
@@ -4206,7 +4206,6 @@ void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4206 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4206 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4207 urb->actual_length); 4207 urb->actual_length);
4208 4208
4209
4210 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4209 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4211 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4210 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4212 for (i = 0; i < urb->number_of_packets; ++i) { 4211 for (i = 0; i < urb->number_of_packets; ++i) {
@@ -4237,7 +4236,7 @@ void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4237 4236
4238 if (ep) 4237 if (ep)
4239 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4238 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4240 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4239 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4241 urb); 4240 urb);
4242 } 4241 }
4243 4242
@@ -4584,7 +4583,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4584 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4583 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4585 } 4584 }
4586 4585
4587 if (ep == NULL) 4586 if (!ep)
4588 return -EINVAL; 4587 return -EINVAL;
4589 4588
4590 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4589 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
@@ -4654,7 +4653,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4654 urb->iso_frame_desc[i].length); 4653 urb->iso_frame_desc[i].length);
4655 4654
4656 urb->hcpriv = dwc2_urb; 4655 urb->hcpriv = dwc2_urb;
4657 qh = (struct dwc2_qh *) ep->hcpriv; 4656 qh = (struct dwc2_qh *)ep->hcpriv;
4658 /* Create QH for the endpoint if it doesn't exist */ 4657 /* Create QH for the endpoint if it doesn't exist */
4659 if (!qh) { 4658 if (!qh) {
4660 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4659 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
@@ -4683,7 +4682,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4683 4682
4684 if (alloc_bandwidth) { 4683 if (alloc_bandwidth) {
4685 dwc2_allocate_bus_bandwidth(hcd, 4684 dwc2_allocate_bus_bandwidth(hcd,
4686 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4685 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4687 urb); 4686 urb);
4688 } 4687 }
4689 4688
@@ -4709,7 +4708,7 @@ fail1:
4709 dwc2_hcd_qh_unlink(hsotg, qh); 4708 dwc2_hcd_qh_unlink(hsotg, qh);
4710 /* Free each QTD in the QH's QTD list */ 4709 /* Free each QTD in the QH's QTD list */
4711 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4710 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4712 qtd_list_entry) 4711 qtd_list_entry)
4713 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4712 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4714 dwc2_hcd_qh_free(hsotg, qh); 4713 dwc2_hcd_qh_free(hsotg, qh);
4715 } 4714 }
@@ -4908,7 +4907,7 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4908 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 4907 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
4909 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 4908 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
4910 4909
4911 if (chan != NULL) { 4910 if (chan) {
4912 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 4911 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
4913 i, chan); 4912 i, chan);
4914 hsotg->hc_ptr_array[i] = NULL; 4913 hsotg->hc_ptr_array[i] = NULL;
@@ -4997,7 +4996,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
4997 4996
4998 /* Check if the bus driver or platform code has setup a dma_mask */ 4997 /* Check if the bus driver or platform code has setup a dma_mask */
4999 if (hsotg->params.host_dma > 0 && 4998 if (hsotg->params.host_dma > 0 &&
5000 hsotg->dev->dma_mask == NULL) { 4999 !hsotg->dev->dma_mask) {
5001 dev_warn(hsotg->dev, 5000 dev_warn(hsotg->dev,
5002 "dma_mask not set, disabling DMA\n"); 5001 "dma_mask not set, disabling DMA\n");
5003 hsotg->params.host_dma = false; 5002 hsotg->params.host_dma = false;
@@ -5021,7 +5020,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
5021 5020
5022 hcd->has_tt = 1; 5021 hcd->has_tt = 1;
5023 5022
5024 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 5023 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5025 hsotg->priv = hcd; 5024 hsotg->priv = hcd;
5026 5025
5027 /* 5026 /*
@@ -5069,7 +5068,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
5069 5068
5070 for (i = 0; i < num_channels; i++) { 5069 for (i = 0; i < num_channels; i++) {
5071 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5070 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5072 if (channel == NULL) 5071 if (!channel)
5073 goto error3; 5072 goto error3;
5074 channel->hc_num = i; 5073 channel->hc_num = i;
5075 INIT_LIST_HEAD(&channel->split_order_list_entry); 5074 INIT_LIST_HEAD(&channel->split_order_list_entry);
diff --git a/drivers/usb/dwc2/hcd.h b/drivers/usb/dwc2/hcd.h
index 1ed5fa2beff4..58bfe9f531e7 100644
--- a/drivers/usb/dwc2/hcd.h
+++ b/drivers/usb/dwc2/hcd.h
@@ -521,29 +521,29 @@ static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
521 return !dwc2_hcd_is_pipe_in(pipe); 521 return !dwc2_hcd_is_pipe_in(pipe);
522} 522}
523 523
524extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq); 524int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq);
525extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 525void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
526 526
527/* Transaction Execution Functions */ 527/* Transaction Execution Functions */
528extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 528enum dwc2_transaction_type dwc2_hcd_select_transactions(
529 struct dwc2_hsotg *hsotg); 529 struct dwc2_hsotg *hsotg);
530extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 530void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
531 enum dwc2_transaction_type tr_type); 531 enum dwc2_transaction_type tr_type);
532 532
533/* Schedule Queue Functions */ 533/* Schedule Queue Functions */
534/* Implemented in hcd_queue.c */ 534/* Implemented in hcd_queue.c */
535extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 535struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
536 struct dwc2_hcd_urb *urb, 536 struct dwc2_hcd_urb *urb,
537 gfp_t mem_flags); 537 gfp_t mem_flags);
538extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 538void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
539extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 539int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
540extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 540void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
541extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 541void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
542 int sched_csplit); 542 int sched_csplit);
543 543
544extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 544void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
545extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 545int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
546 struct dwc2_qh *qh); 546 struct dwc2_qh *qh);
547 547
548/* Unlinks and frees a QTD */ 548/* Unlinks and frees a QTD */
549static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 549static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
@@ -556,15 +556,15 @@ static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
556} 556}
557 557
558/* Descriptor DMA support functions */ 558/* Descriptor DMA support functions */
559extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 559void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
560 struct dwc2_qh *qh); 560 struct dwc2_qh *qh);
561extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 561void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
562 struct dwc2_host_chan *chan, int chnum, 562 struct dwc2_host_chan *chan, int chnum,
563 enum dwc2_halt_status halt_status); 563 enum dwc2_halt_status halt_status);
564 564
565extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 565int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
566 gfp_t mem_flags); 566 gfp_t mem_flags);
567extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 567void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
568 568
569/* Check if QH is non-periodic */ 569/* Check if QH is non-periodic */
570#define dwc2_qh_is_non_per(_qh_ptr_) \ 570#define dwc2_qh_is_non_per(_qh_ptr_) \
@@ -732,8 +732,8 @@ static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
732 return qh->host_us; 732 return qh->host_us;
733} 733}
734 734
735extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 735void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
736 struct dwc2_host_chan *chan, int chnum, 736 struct dwc2_host_chan *chan, int chnum,
737 struct dwc2_qtd *qtd); 737 struct dwc2_qtd *qtd);
738 738
739/* HCD Core API */ 739/* HCD Core API */
@@ -746,14 +746,14 @@ extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
746 * Returns IRQ_HANDLED if interrupt is handled 746 * Returns IRQ_HANDLED if interrupt is handled
747 * Return IRQ_NONE if interrupt is not handled 747 * Return IRQ_NONE if interrupt is not handled
748 */ 748 */
749extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 749irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
750 750
751/** 751/**
752 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 752 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
753 * 753 *
754 * @hsotg: The DWC2 HCD 754 * @hsotg: The DWC2 HCD
755 */ 755 */
756extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 756void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
757 757
758/** 758/**
759 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 759 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
@@ -761,7 +761,7 @@ extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
761 * 761 *
762 * @hsotg: The DWC2 HCD 762 * @hsotg: The DWC2 HCD
763 */ 763 */
764extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 764int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
765 765
766/** 766/**
767 * dwc2_hcd_dump_state() - Dumps hsotg state 767 * dwc2_hcd_dump_state() - Dumps hsotg state
@@ -771,7 +771,7 @@ extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
771 * NOTE: This function will be removed once the peripheral controller code 771 * NOTE: This function will be removed once the peripheral controller code
772 * is integrated and the driver is stable 772 * is integrated and the driver is stable
773 */ 773 */
774extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 774void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
775 775
776/** 776/**
777 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 777 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF
@@ -784,7 +784,7 @@ extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
784 * NOTE: This function will be removed once the peripheral controller code 784 * NOTE: This function will be removed once the peripheral controller code
785 * is integrated and the driver is stable 785 * is integrated and the driver is stable
786 */ 786 */
787extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 787void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
788 788
789/* URB interface */ 789/* URB interface */
790 790
@@ -793,15 +793,15 @@ extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
793#define URB_SEND_ZERO_PACKET 0x2 793#define URB_SEND_ZERO_PACKET 0x2
794 794
795/* Host driver callbacks */ 795/* Host driver callbacks */
796extern struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, 796struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg,
797 void *context, gfp_t mem_flags, 797 void *context, gfp_t mem_flags,
798 int *ttport); 798 int *ttport);
799 799
800extern void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, 800void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg,
801 struct dwc2_tt *dwc_tt); 801 struct dwc2_tt *dwc_tt);
802extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 802int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
803extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 803void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
804 int status); 804 int status);
805 805
806#ifdef DEBUG 806#ifdef DEBUG
807/* 807/*
diff --git a/drivers/usb/dwc2/hcd_ddma.c b/drivers/usb/dwc2/hcd_ddma.c
index cf0367768cb3..db4876c9b5d6 100644
--- a/drivers/usb/dwc2/hcd_ddma.c
+++ b/drivers/usb/dwc2/hcd_ddma.c
@@ -106,7 +106,7 @@ static int dwc2_desc_list_alloc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
106 qh->desc_list_sz, 106 qh->desc_list_sz,
107 DMA_TO_DEVICE); 107 DMA_TO_DEVICE);
108 108
109 qh->n_bytes = kzalloc(sizeof(u32) * dwc2_max_desc_num(qh), flags); 109 qh->n_bytes = kcalloc(dwc2_max_desc_num(qh), sizeof(u32), flags);
110 if (!qh->n_bytes) { 110 if (!qh->n_bytes) {
111 dma_unmap_single(hsotg->dev, qh->desc_list_dma, 111 dma_unmap_single(hsotg->dev, qh->desc_list_dma,
112 qh->desc_list_sz, 112 qh->desc_list_sz,
@@ -175,7 +175,6 @@ static void dwc2_frame_list_free(struct dwc2_hsotg *hsotg)
175 hsotg->frame_list = NULL; 175 hsotg->frame_list = NULL;
176 176
177 spin_unlock_irqrestore(&hsotg->lock, flags); 177 spin_unlock_irqrestore(&hsotg->lock, flags);
178
179} 178}
180 179
181static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en) 180static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)
@@ -570,7 +569,7 @@ static void dwc2_fill_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
570#endif 569#endif
571 570
572 dma_sync_single_for_device(hsotg->dev, 571 dma_sync_single_for_device(hsotg->dev,
573 qh->desc_list_dma + 572 qh->desc_list_dma +
574 (idx * sizeof(struct dwc2_dma_desc)), 573 (idx * sizeof(struct dwc2_dma_desc)),
575 sizeof(struct dwc2_dma_desc), 574 sizeof(struct dwc2_dma_desc),
576 DMA_TO_DEVICE); 575 DMA_TO_DEVICE);
@@ -776,7 +775,7 @@ static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg,
776 n_desc - 1, 775 n_desc - 1,
777 &qh->desc_list[n_desc - 1]); 776 &qh->desc_list[n_desc - 1]);
778 dma_sync_single_for_device(hsotg->dev, 777 dma_sync_single_for_device(hsotg->dev,
779 qh->desc_list_dma + 778 qh->desc_list_dma +
780 ((n_desc - 1) * 779 ((n_desc - 1) *
781 sizeof(struct dwc2_dma_desc)), 780 sizeof(struct dwc2_dma_desc)),
782 sizeof(struct dwc2_dma_desc), 781 sizeof(struct dwc2_dma_desc),
@@ -816,7 +815,7 @@ static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg,
816 dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n", 815 dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n",
817 &qh->desc_list[0]); 816 &qh->desc_list[0]);
818 dma_sync_single_for_device(hsotg->dev, 817 dma_sync_single_for_device(hsotg->dev,
819 qh->desc_list_dma, 818 qh->desc_list_dma,
820 sizeof(struct dwc2_dma_desc), 819 sizeof(struct dwc2_dma_desc),
821 DMA_TO_DEVICE); 820 DMA_TO_DEVICE);
822 } 821 }
@@ -1064,7 +1063,7 @@ stop_scan:
1064} 1063}
1065 1064
1066static int dwc2_update_non_isoc_urb_state_ddma(struct dwc2_hsotg *hsotg, 1065static int dwc2_update_non_isoc_urb_state_ddma(struct dwc2_hsotg *hsotg,
1067 struct dwc2_host_chan *chan, 1066 struct dwc2_host_chan *chan,
1068 struct dwc2_qtd *qtd, 1067 struct dwc2_qtd *qtd,
1069 struct dwc2_dma_desc *dma_desc, 1068 struct dwc2_dma_desc *dma_desc,
1070 enum dwc2_halt_status halt_status, 1069 enum dwc2_halt_status halt_status,
diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index b8f4b6aaf1d0..d719c2f9c570 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -60,7 +60,7 @@ static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
60 60
61 if (expected != curr_frame_number) 61 if (expected != curr_frame_number)
62 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n", 62 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
63 expected, curr_frame_number); 63 expected, curr_frame_number);
64 64
65#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 65#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
66 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) { 66 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
@@ -163,7 +163,7 @@ static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
163 * (micro)frame 163 * (micro)frame
164 */ 164 */
165 list_move_tail(&qh->qh_list_entry, 165 list_move_tail(&qh->qh_list_entry,
166 &hsotg->periodic_sched_ready); 166 &hsotg->periodic_sched_ready);
167 } 167 }
168 } 168 }
169 tr_type = dwc2_hcd_select_transactions(hsotg); 169 tr_type = dwc2_hcd_select_transactions(hsotg);
@@ -442,7 +442,7 @@ static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
442 count = (hctsiz & TSIZ_XFERSIZE_MASK) >> 442 count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
443 TSIZ_XFERSIZE_SHIFT; 443 TSIZ_XFERSIZE_SHIFT;
444 length = chan->xfer_len - count; 444 length = chan->xfer_len - count;
445 if (short_read != NULL) 445 if (short_read)
446 *short_read = (count != 0); 446 *short_read = (count != 0);
447 } else if (chan->qh->do_split) { 447 } else if (chan->qh->do_split) {
448 length = qtd->ssplit_out_xfer_count; 448 length = qtd->ssplit_out_xfer_count;
@@ -823,7 +823,7 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
823 * processed. 823 * processed.
824 */ 824 */
825 list_move_tail(&chan->qh->qh_list_entry, 825 list_move_tail(&chan->qh->qh_list_entry,
826 &hsotg->periodic_sched_assigned); 826 &hsotg->periodic_sched_assigned);
827 827
828 /* 828 /*
829 * Make sure the Periodic Tx FIFO Empty interrupt is 829 * Make sure the Periodic Tx FIFO Empty interrupt is
@@ -1078,7 +1078,7 @@ static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
1078 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n"); 1078 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1079 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL) 1079 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1080 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, 1080 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1081 chnum, qtd, DWC2_HC_XFER_COMPLETE); 1081 chnum, qtd, DWC2_HC_XFER_COMPLETE);
1082 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, 1082 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1083 halt_status); 1083 halt_status);
1084 break; 1084 break;
@@ -1369,7 +1369,7 @@ static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1369 DWC2_HC_XFER_URB_COMPLETE); 1369 DWC2_HC_XFER_URB_COMPLETE);
1370 } else { 1370 } else {
1371 dwc2_release_channel(hsotg, chan, qtd, 1371 dwc2_release_channel(hsotg, chan, qtd,
1372 DWC2_HC_XFER_NO_HALT_STATUS); 1372 DWC2_HC_XFER_NO_HALT_STATUS);
1373 } 1373 }
1374 goto handle_nyet_done; 1374 goto handle_nyet_done;
1375 } 1375 }
@@ -1485,7 +1485,7 @@ static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1485 enum dwc2_halt_status halt_status; 1485 enum dwc2_halt_status halt_status;
1486 1486
1487 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, 1487 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1488 qtd, DWC2_HC_XFER_BABBLE_ERR); 1488 qtd, DWC2_HC_XFER_BABBLE_ERR);
1489 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1489 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1490 } 1490 }
1491 1491
@@ -1620,7 +1620,6 @@ static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1620 case USB_ENDPOINT_XFER_BULK: 1620 case USB_ENDPOINT_XFER_BULK:
1621 qtd->error_count++; 1621 qtd->error_count++;
1622 if (!chan->qh->ping_state) { 1622 if (!chan->qh->ping_state) {
1623
1624 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, 1623 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1625 qtd, DWC2_HC_XFER_XACT_ERR); 1624 qtd, DWC2_HC_XFER_XACT_ERR);
1626 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1625 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
@@ -1645,7 +1644,7 @@ static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1645 enum dwc2_halt_status halt_status; 1644 enum dwc2_halt_status halt_status;
1646 1645
1647 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, 1646 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1648 chnum, qtd, DWC2_HC_XFER_XACT_ERR); 1647 chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1649 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1648 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1650 } 1649 }
1651 break; 1650 break;
@@ -1680,7 +1679,7 @@ static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1680 break; 1679 break;
1681 case USB_ENDPOINT_XFER_ISOC: 1680 case USB_ENDPOINT_XFER_ISOC:
1682 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, 1681 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1683 qtd, DWC2_HC_XFER_FRAME_OVERRUN); 1682 qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1684 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1683 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1685 break; 1684 break;
1686 } 1685 }
@@ -1906,7 +1905,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1906 "%s: Halt channel %d (assume incomplete periodic transfer)\n", 1905 "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1907 __func__, chnum); 1906 __func__, chnum);
1908 dwc2_halt_channel(hsotg, chan, qtd, 1907 dwc2_halt_channel(hsotg, chan, qtd,
1909 DWC2_HC_XFER_PERIODIC_INCOMPLETE); 1908 DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1910 } else { 1909 } else {
1911 dev_err(hsotg->dev, 1910 dev_err(hsotg->dev,
1912 "%s: Channel %d - ChHltd set, but reason is unknown\n", 1911 "%s: Channel %d - ChHltd set, but reason is unknown\n",
@@ -1970,7 +1969,7 @@ static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1970{ 1969{
1971 struct dwc2_qtd *cur_head; 1970 struct dwc2_qtd *cur_head;
1972 1971
1973 if (qh == NULL) 1972 if (!qh)
1974 return false; 1973 return false;
1975 1974
1976 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd, 1975 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c
index 5713f03a4e56..06d036f608f1 100644
--- a/drivers/usb/dwc2/hcd_queue.c
+++ b/drivers/usb/dwc2/hcd_queue.c
@@ -82,8 +82,8 @@ static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
82 status = 0; 82 status = 0;
83 } else { 83 } else {
84 dev_dbg(hsotg->dev, 84 dev_dbg(hsotg->dev,
85 "%s: Total channels: %d, Periodic: %d, " 85 "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
86 "Non-periodic: %d\n", __func__, num_channels, 86 __func__, num_channels,
87 hsotg->periodic_channels, hsotg->non_periodic_channels); 87 hsotg->periodic_channels, hsotg->non_periodic_channels);
88 status = -ENOSPC; 88 status = -ENOSPC;
89 } 89 }
@@ -485,7 +485,6 @@ static void pmap_print(unsigned long *map, int bits_per_period,
485 } 485 }
486} 486}
487 487
488
489struct dwc2_qh_print_data { 488struct dwc2_qh_print_data {
490 struct dwc2_hsotg *hsotg; 489 struct dwc2_hsotg *hsotg;
491 struct dwc2_qh *qh; 490 struct dwc2_qh *qh;
@@ -587,7 +586,7 @@ static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
587 unsigned long *map = dwc2_get_ls_map(hsotg, qh); 586 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
588 int slice; 587 int slice;
589 588
590 if (map == NULL) 589 if (!map)
591 return -EINVAL; 590 return -EINVAL;
592 591
593 /* 592 /*
@@ -626,7 +625,7 @@ static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
626 unsigned long *map = dwc2_get_ls_map(hsotg, qh); 625 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
627 626
628 /* Schedule should have failed, so no worries about no error code */ 627 /* Schedule should have failed, so no worries about no error code */
629 if (map == NULL) 628 if (!map)
630 return; 629 return;
631 630
632 pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 631 pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
@@ -1182,7 +1181,7 @@ exit:
1182 qh->start_active_frame = next_active_frame; 1181 qh->start_active_frame = next_active_frame;
1183 1182
1184 dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n", 1183 dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
1185 qh, frame_number, qh->next_active_frame); 1184 qh, frame_number, qh->next_active_frame);
1186} 1185}
1187 1186
1188/** 1187/**
@@ -1501,7 +1500,6 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1501 device_ns += dwc_tt->usb_tt->think_time; 1500 device_ns += dwc_tt->usb_tt->think_time;
1502 qh->device_us = NS_TO_US(device_ns); 1501 qh->device_us = NS_TO_US(device_ns);
1503 1502
1504
1505 qh->device_interval = urb->interval; 1503 qh->device_interval = urb->interval;
1506 qh->host_interval = urb->interval * (do_split ? 8 : 1); 1504 qh->host_interval = urb->interval * (do_split ? 8 : 1);
1507 1505
@@ -1587,7 +1585,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1587 * Return: Pointer to the newly allocated QH, or NULL on error 1585 * Return: Pointer to the newly allocated QH, or NULL on error
1588 */ 1586 */
1589struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 1587struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
1590 struct dwc2_hcd_urb *urb, 1588 struct dwc2_hcd_urb *urb,
1591 gfp_t mem_flags) 1589 gfp_t mem_flags)
1592{ 1590{
1593 struct dwc2_qh *qh; 1591 struct dwc2_qh *qh;
@@ -1741,7 +1739,7 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1741 * Return: number missed by (or 0 if we didn't miss). 1739 * Return: number missed by (or 0 if we didn't miss).
1742 */ 1740 */
1743static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg, 1741static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1744 struct dwc2_qh *qh, u16 frame_number) 1742 struct dwc2_qh *qh, u16 frame_number)
1745{ 1743{
1746 u16 old_frame = qh->next_active_frame; 1744 u16 old_frame = qh->next_active_frame;
1747 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1); 1745 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
@@ -1804,7 +1802,7 @@ static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1804 * Return: number missed by (or 0 if we didn't miss). 1802 * Return: number missed by (or 0 if we didn't miss).
1805 */ 1803 */
1806static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg, 1804static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1807 struct dwc2_qh *qh, u16 frame_number) 1805 struct dwc2_qh *qh, u16 frame_number)
1808{ 1806{
1809 int missed = 0; 1807 int missed = 0;
1810 u16 interval = qh->host_interval; 1808 u16 interval = qh->host_interval;
@@ -1926,7 +1924,7 @@ void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1926 missed = dwc2_next_periodic_start(hsotg, qh, frame_number); 1924 missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
1927 1925
1928 dwc2_sch_vdbg(hsotg, 1926 dwc2_sch_vdbg(hsotg,
1929 "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n", 1927 "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
1930 qh, sched_next_periodic_split, frame_number, old_frame, 1928 qh, sched_next_periodic_split, frame_number, old_frame,
1931 qh->next_active_frame, 1929 qh->next_active_frame,
1932 dwc2_frame_num_dec(qh->next_active_frame, old_frame), 1930 dwc2_frame_num_dec(qh->next_active_frame, old_frame),
diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h
index 5be056b39e5c..bde72489ae66 100644
--- a/drivers/usb/dwc2/hw.h
+++ b/drivers/usb/dwc2/hw.h
@@ -40,37 +40,37 @@
40#define HSOTG_REG(x) (x) 40#define HSOTG_REG(x) (x)
41 41
42#define GOTGCTL HSOTG_REG(0x000) 42#define GOTGCTL HSOTG_REG(0x000)
43#define GOTGCTL_CHIRPEN (1 << 27) 43#define GOTGCTL_CHIRPEN BIT(27)
44#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22) 44#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
45#define GOTGCTL_MULT_VALID_BC_SHIFT 22 45#define GOTGCTL_MULT_VALID_BC_SHIFT 22
46#define GOTGCTL_OTGVER (1 << 20) 46#define GOTGCTL_OTGVER BIT(20)
47#define GOTGCTL_BSESVLD (1 << 19) 47#define GOTGCTL_BSESVLD BIT(19)
48#define GOTGCTL_ASESVLD (1 << 18) 48#define GOTGCTL_ASESVLD BIT(18)
49#define GOTGCTL_DBNC_SHORT (1 << 17) 49#define GOTGCTL_DBNC_SHORT BIT(17)
50#define GOTGCTL_CONID_B (1 << 16) 50#define GOTGCTL_CONID_B BIT(16)
51#define GOTGCTL_DBNCE_FLTR_BYPASS (1 << 15) 51#define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
52#define GOTGCTL_DEVHNPEN (1 << 11) 52#define GOTGCTL_DEVHNPEN BIT(11)
53#define GOTGCTL_HSTSETHNPEN (1 << 10) 53#define GOTGCTL_HSTSETHNPEN BIT(10)
54#define GOTGCTL_HNPREQ (1 << 9) 54#define GOTGCTL_HNPREQ BIT(9)
55#define GOTGCTL_HSTNEGSCS (1 << 8) 55#define GOTGCTL_HSTNEGSCS BIT(8)
56#define GOTGCTL_SESREQ (1 << 1) 56#define GOTGCTL_SESREQ BIT(1)
57#define GOTGCTL_SESREQSCS (1 << 0) 57#define GOTGCTL_SESREQSCS BIT(0)
58 58
59#define GOTGINT HSOTG_REG(0x004) 59#define GOTGINT HSOTG_REG(0x004)
60#define GOTGINT_DBNCE_DONE (1 << 19) 60#define GOTGINT_DBNCE_DONE BIT(19)
61#define GOTGINT_A_DEV_TOUT_CHG (1 << 18) 61#define GOTGINT_A_DEV_TOUT_CHG BIT(18)
62#define GOTGINT_HST_NEG_DET (1 << 17) 62#define GOTGINT_HST_NEG_DET BIT(17)
63#define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9) 63#define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
64#define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8) 64#define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
65#define GOTGINT_SES_END_DET (1 << 2) 65#define GOTGINT_SES_END_DET BIT(2)
66 66
67#define GAHBCFG HSOTG_REG(0x008) 67#define GAHBCFG HSOTG_REG(0x008)
68#define GAHBCFG_AHB_SINGLE (1 << 23) 68#define GAHBCFG_AHB_SINGLE BIT(23)
69#define GAHBCFG_NOTI_ALL_DMA_WRIT (1 << 22) 69#define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
70#define GAHBCFG_REM_MEM_SUPP (1 << 21) 70#define GAHBCFG_REM_MEM_SUPP BIT(21)
71#define GAHBCFG_P_TXF_EMP_LVL (1 << 8) 71#define GAHBCFG_P_TXF_EMP_LVL BIT(8)
72#define GAHBCFG_NP_TXF_EMP_LVL (1 << 7) 72#define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
73#define GAHBCFG_DMA_EN (1 << 5) 73#define GAHBCFG_DMA_EN BIT(5)
74#define GAHBCFG_HBSTLEN_MASK (0xf << 1) 74#define GAHBCFG_HBSTLEN_MASK (0xf << 1)
75#define GAHBCFG_HBSTLEN_SHIFT 1 75#define GAHBCFG_HBSTLEN_SHIFT 1
76#define GAHBCFG_HBSTLEN_SINGLE 0 76#define GAHBCFG_HBSTLEN_SINGLE 0
@@ -78,38 +78,38 @@
78#define GAHBCFG_HBSTLEN_INCR4 3 78#define GAHBCFG_HBSTLEN_INCR4 3
79#define GAHBCFG_HBSTLEN_INCR8 5 79#define GAHBCFG_HBSTLEN_INCR8 5
80#define GAHBCFG_HBSTLEN_INCR16 7 80#define GAHBCFG_HBSTLEN_INCR16 7
81#define GAHBCFG_GLBL_INTR_EN (1 << 0) 81#define GAHBCFG_GLBL_INTR_EN BIT(0)
82#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ 82#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
83 GAHBCFG_NP_TXF_EMP_LVL | \ 83 GAHBCFG_NP_TXF_EMP_LVL | \
84 GAHBCFG_DMA_EN | \ 84 GAHBCFG_DMA_EN | \
85 GAHBCFG_GLBL_INTR_EN) 85 GAHBCFG_GLBL_INTR_EN)
86 86
87#define GUSBCFG HSOTG_REG(0x00C) 87#define GUSBCFG HSOTG_REG(0x00C)
88#define GUSBCFG_FORCEDEVMODE (1 << 30) 88#define GUSBCFG_FORCEDEVMODE BIT(30)
89#define GUSBCFG_FORCEHOSTMODE (1 << 29) 89#define GUSBCFG_FORCEHOSTMODE BIT(29)
90#define GUSBCFG_TXENDDELAY (1 << 28) 90#define GUSBCFG_TXENDDELAY BIT(28)
91#define GUSBCFG_ICTRAFFICPULLREMOVE (1 << 27) 91#define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
92#define GUSBCFG_ICUSBCAP (1 << 26) 92#define GUSBCFG_ICUSBCAP BIT(26)
93#define GUSBCFG_ULPI_INT_PROT_DIS (1 << 25) 93#define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
94#define GUSBCFG_INDICATORPASSTHROUGH (1 << 24) 94#define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
95#define GUSBCFG_INDICATORCOMPLEMENT (1 << 23) 95#define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
96#define GUSBCFG_TERMSELDLPULSE (1 << 22) 96#define GUSBCFG_TERMSELDLPULSE BIT(22)
97#define GUSBCFG_ULPI_INT_VBUS_IND (1 << 21) 97#define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
98#define GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20) 98#define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
99#define GUSBCFG_ULPI_CLK_SUSP_M (1 << 19) 99#define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
100#define GUSBCFG_ULPI_AUTO_RES (1 << 18) 100#define GUSBCFG_ULPI_AUTO_RES BIT(18)
101#define GUSBCFG_ULPI_FS_LS (1 << 17) 101#define GUSBCFG_ULPI_FS_LS BIT(17)
102#define GUSBCFG_OTG_UTMI_FS_SEL (1 << 16) 102#define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
103#define GUSBCFG_PHY_LP_CLK_SEL (1 << 15) 103#define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
104#define GUSBCFG_USBTRDTIM_MASK (0xf << 10) 104#define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
105#define GUSBCFG_USBTRDTIM_SHIFT 10 105#define GUSBCFG_USBTRDTIM_SHIFT 10
106#define GUSBCFG_HNPCAP (1 << 9) 106#define GUSBCFG_HNPCAP BIT(9)
107#define GUSBCFG_SRPCAP (1 << 8) 107#define GUSBCFG_SRPCAP BIT(8)
108#define GUSBCFG_DDRSEL (1 << 7) 108#define GUSBCFG_DDRSEL BIT(7)
109#define GUSBCFG_PHYSEL (1 << 6) 109#define GUSBCFG_PHYSEL BIT(6)
110#define GUSBCFG_FSINTF (1 << 5) 110#define GUSBCFG_FSINTF BIT(5)
111#define GUSBCFG_ULPI_UTMI_SEL (1 << 4) 111#define GUSBCFG_ULPI_UTMI_SEL BIT(4)
112#define GUSBCFG_PHYIF16 (1 << 3) 112#define GUSBCFG_PHYIF16 BIT(3)
113#define GUSBCFG_PHYIF8 (0 << 3) 113#define GUSBCFG_PHYIF8 (0 << 3)
114#define GUSBCFG_TOUTCAL_MASK (0x7 << 0) 114#define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
115#define GUSBCFG_TOUTCAL_SHIFT 0 115#define GUSBCFG_TOUTCAL_SHIFT 0
@@ -117,54 +117,54 @@
117#define GUSBCFG_TOUTCAL(_x) ((_x) << 0) 117#define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
118 118
119#define GRSTCTL HSOTG_REG(0x010) 119#define GRSTCTL HSOTG_REG(0x010)
120#define GRSTCTL_AHBIDLE (1 << 31) 120#define GRSTCTL_AHBIDLE BIT(31)
121#define GRSTCTL_DMAREQ (1 << 30) 121#define GRSTCTL_DMAREQ BIT(30)
122#define GRSTCTL_TXFNUM_MASK (0x1f << 6) 122#define GRSTCTL_TXFNUM_MASK (0x1f << 6)
123#define GRSTCTL_TXFNUM_SHIFT 6 123#define GRSTCTL_TXFNUM_SHIFT 6
124#define GRSTCTL_TXFNUM_LIMIT 0x1f 124#define GRSTCTL_TXFNUM_LIMIT 0x1f
125#define GRSTCTL_TXFNUM(_x) ((_x) << 6) 125#define GRSTCTL_TXFNUM(_x) ((_x) << 6)
126#define GRSTCTL_TXFFLSH (1 << 5) 126#define GRSTCTL_TXFFLSH BIT(5)
127#define GRSTCTL_RXFFLSH (1 << 4) 127#define GRSTCTL_RXFFLSH BIT(4)
128#define GRSTCTL_IN_TKNQ_FLSH (1 << 3) 128#define GRSTCTL_IN_TKNQ_FLSH BIT(3)
129#define GRSTCTL_FRMCNTRRST (1 << 2) 129#define GRSTCTL_FRMCNTRRST BIT(2)
130#define GRSTCTL_HSFTRST (1 << 1) 130#define GRSTCTL_HSFTRST BIT(1)
131#define GRSTCTL_CSFTRST (1 << 0) 131#define GRSTCTL_CSFTRST BIT(0)
132 132
133#define GINTSTS HSOTG_REG(0x014) 133#define GINTSTS HSOTG_REG(0x014)
134#define GINTMSK HSOTG_REG(0x018) 134#define GINTMSK HSOTG_REG(0x018)
135#define GINTSTS_WKUPINT (1 << 31) 135#define GINTSTS_WKUPINT BIT(31)
136#define GINTSTS_SESSREQINT (1 << 30) 136#define GINTSTS_SESSREQINT BIT(30)
137#define GINTSTS_DISCONNINT (1 << 29) 137#define GINTSTS_DISCONNINT BIT(29)
138#define GINTSTS_CONIDSTSCHNG (1 << 28) 138#define GINTSTS_CONIDSTSCHNG BIT(28)
139#define GINTSTS_LPMTRANRCVD (1 << 27) 139#define GINTSTS_LPMTRANRCVD BIT(27)
140#define GINTSTS_PTXFEMP (1 << 26) 140#define GINTSTS_PTXFEMP BIT(26)
141#define GINTSTS_HCHINT (1 << 25) 141#define GINTSTS_HCHINT BIT(25)
142#define GINTSTS_PRTINT (1 << 24) 142#define GINTSTS_PRTINT BIT(24)
143#define GINTSTS_RESETDET (1 << 23) 143#define GINTSTS_RESETDET BIT(23)
144#define GINTSTS_FET_SUSP (1 << 22) 144#define GINTSTS_FET_SUSP BIT(22)
145#define GINTSTS_INCOMPL_IP (1 << 21) 145#define GINTSTS_INCOMPL_IP BIT(21)
146#define GINTSTS_INCOMPL_SOOUT (1 << 21) 146#define GINTSTS_INCOMPL_SOOUT BIT(21)
147#define GINTSTS_INCOMPL_SOIN (1 << 20) 147#define GINTSTS_INCOMPL_SOIN BIT(20)
148#define GINTSTS_OEPINT (1 << 19) 148#define GINTSTS_OEPINT BIT(19)
149#define GINTSTS_IEPINT (1 << 18) 149#define GINTSTS_IEPINT BIT(18)
150#define GINTSTS_EPMIS (1 << 17) 150#define GINTSTS_EPMIS BIT(17)
151#define GINTSTS_RESTOREDONE (1 << 16) 151#define GINTSTS_RESTOREDONE BIT(16)
152#define GINTSTS_EOPF (1 << 15) 152#define GINTSTS_EOPF BIT(15)
153#define GINTSTS_ISOUTDROP (1 << 14) 153#define GINTSTS_ISOUTDROP BIT(14)
154#define GINTSTS_ENUMDONE (1 << 13) 154#define GINTSTS_ENUMDONE BIT(13)
155#define GINTSTS_USBRST (1 << 12) 155#define GINTSTS_USBRST BIT(12)
156#define GINTSTS_USBSUSP (1 << 11) 156#define GINTSTS_USBSUSP BIT(11)
157#define GINTSTS_ERLYSUSP (1 << 10) 157#define GINTSTS_ERLYSUSP BIT(10)
158#define GINTSTS_I2CINT (1 << 9) 158#define GINTSTS_I2CINT BIT(9)
159#define GINTSTS_ULPI_CK_INT (1 << 8) 159#define GINTSTS_ULPI_CK_INT BIT(8)
160#define GINTSTS_GOUTNAKEFF (1 << 7) 160#define GINTSTS_GOUTNAKEFF BIT(7)
161#define GINTSTS_GINNAKEFF (1 << 6) 161#define GINTSTS_GINNAKEFF BIT(6)
162#define GINTSTS_NPTXFEMP (1 << 5) 162#define GINTSTS_NPTXFEMP BIT(5)
163#define GINTSTS_RXFLVL (1 << 4) 163#define GINTSTS_RXFLVL BIT(4)
164#define GINTSTS_SOF (1 << 3) 164#define GINTSTS_SOF BIT(3)
165#define GINTSTS_OTGINT (1 << 2) 165#define GINTSTS_OTGINT BIT(2)
166#define GINTSTS_MODEMIS (1 << 1) 166#define GINTSTS_MODEMIS BIT(1)
167#define GINTSTS_CURMODE_HOST (1 << 0) 167#define GINTSTS_CURMODE_HOST BIT(0)
168 168
169#define GRXSTSR HSOTG_REG(0x01C) 169#define GRXSTSR HSOTG_REG(0x01C)
170#define GRXSTSP HSOTG_REG(0x020) 170#define GRXSTSP HSOTG_REG(0x020)
@@ -208,14 +208,14 @@
208#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff) 208#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
209 209
210#define GI2CCTL HSOTG_REG(0x0030) 210#define GI2CCTL HSOTG_REG(0x0030)
211#define GI2CCTL_BSYDNE (1 << 31) 211#define GI2CCTL_BSYDNE BIT(31)
212#define GI2CCTL_RW (1 << 30) 212#define GI2CCTL_RW BIT(30)
213#define GI2CCTL_I2CDATSE0 (1 << 28) 213#define GI2CCTL_I2CDATSE0 BIT(28)
214#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) 214#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
215#define GI2CCTL_I2CDEVADDR_SHIFT 26 215#define GI2CCTL_I2CDEVADDR_SHIFT 26
216#define GI2CCTL_I2CSUSPCTL (1 << 25) 216#define GI2CCTL_I2CSUSPCTL BIT(25)
217#define GI2CCTL_ACK (1 << 24) 217#define GI2CCTL_ACK BIT(24)
218#define GI2CCTL_I2CEN (1 << 23) 218#define GI2CCTL_I2CEN BIT(23)
219#define GI2CCTL_ADDR_MASK (0x7f << 16) 219#define GI2CCTL_ADDR_MASK (0x7f << 16)
220#define GI2CCTL_ADDR_SHIFT 16 220#define GI2CCTL_ADDR_SHIFT 16
221#define GI2CCTL_REGADDR_MASK (0xff << 8) 221#define GI2CCTL_REGADDR_MASK (0xff << 8)
@@ -230,16 +230,16 @@
230#define GHWCFG1 HSOTG_REG(0x0044) 230#define GHWCFG1 HSOTG_REG(0x0044)
231 231
232#define GHWCFG2 HSOTG_REG(0x0048) 232#define GHWCFG2 HSOTG_REG(0x0048)
233#define GHWCFG2_OTG_ENABLE_IC_USB (1 << 31) 233#define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
234#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26) 234#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
235#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26 235#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
236#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) 236#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
237#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24 237#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
238#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) 238#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
239#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22 239#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
240#define GHWCFG2_MULTI_PROC_INT (1 << 20) 240#define GHWCFG2_MULTI_PROC_INT BIT(20)
241#define GHWCFG2_DYNAMIC_FIFO (1 << 19) 241#define GHWCFG2_DYNAMIC_FIFO BIT(19)
242#define GHWCFG2_PERIO_EP_SUPPORTED (1 << 18) 242#define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
243#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) 243#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
244#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14 244#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
245#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10) 245#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
@@ -256,7 +256,7 @@
256#define GHWCFG2_HS_PHY_TYPE_UTMI 1 256#define GHWCFG2_HS_PHY_TYPE_UTMI 1
257#define GHWCFG2_HS_PHY_TYPE_ULPI 2 257#define GHWCFG2_HS_PHY_TYPE_ULPI 2
258#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 258#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
259#define GHWCFG2_POINT2POINT (1 << 5) 259#define GHWCFG2_POINT2POINT BIT(5)
260#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3) 260#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
261#define GHWCFG2_ARCHITECTURE_SHIFT 3 261#define GHWCFG2_ARCHITECTURE_SHIFT 3
262#define GHWCFG2_SLAVE_ONLY_ARCH 0 262#define GHWCFG2_SLAVE_ONLY_ARCH 0
@@ -276,32 +276,32 @@
276#define GHWCFG3 HSOTG_REG(0x004c) 276#define GHWCFG3 HSOTG_REG(0x004c)
277#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16) 277#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
278#define GHWCFG3_DFIFO_DEPTH_SHIFT 16 278#define GHWCFG3_DFIFO_DEPTH_SHIFT 16
279#define GHWCFG3_OTG_LPM_EN (1 << 15) 279#define GHWCFG3_OTG_LPM_EN BIT(15)
280#define GHWCFG3_BC_SUPPORT (1 << 14) 280#define GHWCFG3_BC_SUPPORT BIT(14)
281#define GHWCFG3_OTG_ENABLE_HSIC (1 << 13) 281#define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
282#define GHWCFG3_ADP_SUPP (1 << 12) 282#define GHWCFG3_ADP_SUPP BIT(12)
283#define GHWCFG3_SYNCH_RESET_TYPE (1 << 11) 283#define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
284#define GHWCFG3_OPTIONAL_FEATURES (1 << 10) 284#define GHWCFG3_OPTIONAL_FEATURES BIT(10)
285#define GHWCFG3_VENDOR_CTRL_IF (1 << 9) 285#define GHWCFG3_VENDOR_CTRL_IF BIT(9)
286#define GHWCFG3_I2C (1 << 8) 286#define GHWCFG3_I2C BIT(8)
287#define GHWCFG3_OTG_FUNC (1 << 7) 287#define GHWCFG3_OTG_FUNC BIT(7)
288#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) 288#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
289#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4 289#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
290#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0) 290#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
291#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0 291#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
292 292
293#define GHWCFG4 HSOTG_REG(0x0050) 293#define GHWCFG4 HSOTG_REG(0x0050)
294#define GHWCFG4_DESC_DMA_DYN (1 << 31) 294#define GHWCFG4_DESC_DMA_DYN BIT(31)
295#define GHWCFG4_DESC_DMA (1 << 30) 295#define GHWCFG4_DESC_DMA BIT(30)
296#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) 296#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
297#define GHWCFG4_NUM_IN_EPS_SHIFT 26 297#define GHWCFG4_NUM_IN_EPS_SHIFT 26
298#define GHWCFG4_DED_FIFO_EN (1 << 25) 298#define GHWCFG4_DED_FIFO_EN BIT(25)
299#define GHWCFG4_DED_FIFO_SHIFT 25 299#define GHWCFG4_DED_FIFO_SHIFT 25
300#define GHWCFG4_SESSION_END_FILT_EN (1 << 24) 300#define GHWCFG4_SESSION_END_FILT_EN BIT(24)
301#define GHWCFG4_B_VALID_FILT_EN (1 << 23) 301#define GHWCFG4_B_VALID_FILT_EN BIT(23)
302#define GHWCFG4_A_VALID_FILT_EN (1 << 22) 302#define GHWCFG4_A_VALID_FILT_EN BIT(22)
303#define GHWCFG4_VBUS_VALID_FILT_EN (1 << 21) 303#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
304#define GHWCFG4_IDDIG_FILT_EN (1 << 20) 304#define GHWCFG4_IDDIG_FILT_EN BIT(20)
305#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) 305#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
306#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 306#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
307#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) 307#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
@@ -309,64 +309,64 @@
309#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 309#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
310#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 310#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
311#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 311#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
312#define GHWCFG4_XHIBER (1 << 7) 312#define GHWCFG4_XHIBER BIT(7)
313#define GHWCFG4_HIBER (1 << 6) 313#define GHWCFG4_HIBER BIT(6)
314#define GHWCFG4_MIN_AHB_FREQ (1 << 5) 314#define GHWCFG4_MIN_AHB_FREQ BIT(5)
315#define GHWCFG4_POWER_OPTIMIZ (1 << 4) 315#define GHWCFG4_POWER_OPTIMIZ BIT(4)
316#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) 316#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
317#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0 317#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
318 318
319#define GLPMCFG HSOTG_REG(0x0054) 319#define GLPMCFG HSOTG_REG(0x0054)
320#define GLPMCFG_INV_SEL_HSIC (1 << 31) 320#define GLPMCFG_INV_SEL_HSIC BIT(31)
321#define GLPMCFG_HSIC_CONNECT (1 << 30) 321#define GLPMCFG_HSIC_CONNECT BIT(30)
322#define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25) 322#define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25)
323#define GLPMCFG_RETRY_COUNT_STS_SHIFT 25 323#define GLPMCFG_RETRY_COUNT_STS_SHIFT 25
324#define GLPMCFG_SEND_LPM (1 << 24) 324#define GLPMCFG_SEND_LPM BIT(24)
325#define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21) 325#define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21)
326#define GLPMCFG_RETRY_COUNT_SHIFT 21 326#define GLPMCFG_RETRY_COUNT_SHIFT 21
327#define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17) 327#define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17)
328#define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17 328#define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17
329#define GLPMCFG_SLEEP_STATE_RESUMEOK (1 << 16) 329#define GLPMCFG_SLEEP_STATE_RESUMEOK BIT(16)
330#define GLPMCFG_PRT_SLEEP_STS (1 << 15) 330#define GLPMCFG_PRT_SLEEP_STS BIT(15)
331#define GLPMCFG_LPM_RESP_MASK (0x3 << 13) 331#define GLPMCFG_LPM_RESP_MASK (0x3 << 13)
332#define GLPMCFG_LPM_RESP_SHIFT 13 332#define GLPMCFG_LPM_RESP_SHIFT 13
333#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8) 333#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
334#define GLPMCFG_HIRD_THRES_SHIFT 8 334#define GLPMCFG_HIRD_THRES_SHIFT 8
335#define GLPMCFG_HIRD_THRES_EN (0x10 << 8) 335#define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
336#define GLPMCFG_EN_UTMI_SLEEP (1 << 7) 336#define GLPMCFG_EN_UTMI_SLEEP BIT(7)
337#define GLPMCFG_REM_WKUP_EN (1 << 6) 337#define GLPMCFG_REM_WKUP_EN BIT(6)
338#define GLPMCFG_HIRD_MASK (0xf << 2) 338#define GLPMCFG_HIRD_MASK (0xf << 2)
339#define GLPMCFG_HIRD_SHIFT 2 339#define GLPMCFG_HIRD_SHIFT 2
340#define GLPMCFG_APPL_RESP (1 << 1) 340#define GLPMCFG_APPL_RESP BIT(1)
341#define GLPMCFG_LPM_CAP_EN (1 << 0) 341#define GLPMCFG_LPM_CAP_EN BIT(0)
342 342
343#define GPWRDN HSOTG_REG(0x0058) 343#define GPWRDN HSOTG_REG(0x0058)
344#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24) 344#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
345#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24 345#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
346#define GPWRDN_ADP_INT (1 << 23) 346#define GPWRDN_ADP_INT BIT(23)
347#define GPWRDN_BSESSVLD (1 << 22) 347#define GPWRDN_BSESSVLD BIT(22)
348#define GPWRDN_IDSTS (1 << 21) 348#define GPWRDN_IDSTS BIT(21)
349#define GPWRDN_LINESTATE_MASK (0x3 << 19) 349#define GPWRDN_LINESTATE_MASK (0x3 << 19)
350#define GPWRDN_LINESTATE_SHIFT 19 350#define GPWRDN_LINESTATE_SHIFT 19
351#define GPWRDN_STS_CHGINT_MSK (1 << 18) 351#define GPWRDN_STS_CHGINT_MSK BIT(18)
352#define GPWRDN_STS_CHGINT (1 << 17) 352#define GPWRDN_STS_CHGINT BIT(17)
353#define GPWRDN_SRP_DET_MSK (1 << 16) 353#define GPWRDN_SRP_DET_MSK BIT(16)
354#define GPWRDN_SRP_DET (1 << 15) 354#define GPWRDN_SRP_DET BIT(15)
355#define GPWRDN_CONNECT_DET_MSK (1 << 14) 355#define GPWRDN_CONNECT_DET_MSK BIT(14)
356#define GPWRDN_CONNECT_DET (1 << 13) 356#define GPWRDN_CONNECT_DET BIT(13)
357#define GPWRDN_DISCONN_DET_MSK (1 << 12) 357#define GPWRDN_DISCONN_DET_MSK BIT(12)
358#define GPWRDN_DISCONN_DET (1 << 11) 358#define GPWRDN_DISCONN_DET BIT(11)
359#define GPWRDN_RST_DET_MSK (1 << 10) 359#define GPWRDN_RST_DET_MSK BIT(10)
360#define GPWRDN_RST_DET (1 << 9) 360#define GPWRDN_RST_DET BIT(9)
361#define GPWRDN_LNSTSCHG_MSK (1 << 8) 361#define GPWRDN_LNSTSCHG_MSK BIT(8)
362#define GPWRDN_LNSTSCHG (1 << 7) 362#define GPWRDN_LNSTSCHG BIT(7)
363#define GPWRDN_DIS_VBUS (1 << 6) 363#define GPWRDN_DIS_VBUS BIT(6)
364#define GPWRDN_PWRDNSWTCH (1 << 5) 364#define GPWRDN_PWRDNSWTCH BIT(5)
365#define GPWRDN_PWRDNRSTN (1 << 4) 365#define GPWRDN_PWRDNRSTN BIT(4)
366#define GPWRDN_PWRDNCLMP (1 << 3) 366#define GPWRDN_PWRDNCLMP BIT(3)
367#define GPWRDN_RESTORE (1 << 2) 367#define GPWRDN_RESTORE BIT(2)
368#define GPWRDN_PMUACTV (1 << 1) 368#define GPWRDN_PMUACTV BIT(1)
369#define GPWRDN_PMUINTSEL (1 << 0) 369#define GPWRDN_PMUINTSEL BIT(0)
370 370
371#define GDFIFOCFG HSOTG_REG(0x005c) 371#define GDFIFOCFG HSOTG_REG(0x005c)
372#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) 372#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
@@ -377,16 +377,16 @@
377#define ADPCTL HSOTG_REG(0x0060) 377#define ADPCTL HSOTG_REG(0x0060)
378#define ADPCTL_AR_MASK (0x3 << 27) 378#define ADPCTL_AR_MASK (0x3 << 27)
379#define ADPCTL_AR_SHIFT 27 379#define ADPCTL_AR_SHIFT 27
380#define ADPCTL_ADP_TMOUT_INT_MSK (1 << 26) 380#define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
381#define ADPCTL_ADP_SNS_INT_MSK (1 << 25) 381#define ADPCTL_ADP_SNS_INT_MSK BIT(25)
382#define ADPCTL_ADP_PRB_INT_MSK (1 << 24) 382#define ADPCTL_ADP_PRB_INT_MSK BIT(24)
383#define ADPCTL_ADP_TMOUT_INT (1 << 23) 383#define ADPCTL_ADP_TMOUT_INT BIT(23)
384#define ADPCTL_ADP_SNS_INT (1 << 22) 384#define ADPCTL_ADP_SNS_INT BIT(22)
385#define ADPCTL_ADP_PRB_INT (1 << 21) 385#define ADPCTL_ADP_PRB_INT BIT(21)
386#define ADPCTL_ADPENA (1 << 20) 386#define ADPCTL_ADPENA BIT(20)
387#define ADPCTL_ADPRES (1 << 19) 387#define ADPCTL_ADPRES BIT(19)
388#define ADPCTL_ENASNS (1 << 18) 388#define ADPCTL_ENASNS BIT(18)
389#define ADPCTL_ENAPRB (1 << 17) 389#define ADPCTL_ENAPRB BIT(17)
390#define ADPCTL_RTIM_MASK (0x7ff << 6) 390#define ADPCTL_RTIM_MASK (0x7ff << 6)
391#define ADPCTL_RTIM_SHIFT 6 391#define ADPCTL_RTIM_SHIFT 6
392#define ADPCTL_PRB_PER_MASK (0x3 << 4) 392#define ADPCTL_PRB_PER_MASK (0x3 << 4)
@@ -412,7 +412,7 @@
412/* Device mode registers */ 412/* Device mode registers */
413 413
414#define DCFG HSOTG_REG(0x800) 414#define DCFG HSOTG_REG(0x800)
415#define DCFG_DESCDMA_EN (1 << 23) 415#define DCFG_DESCDMA_EN BIT(23)
416#define DCFG_EPMISCNT_MASK (0x1f << 18) 416#define DCFG_EPMISCNT_MASK (0x1f << 18)
417#define DCFG_EPMISCNT_SHIFT 18 417#define DCFG_EPMISCNT_SHIFT 18
418#define DCFG_EPMISCNT_LIMIT 0x1f 418#define DCFG_EPMISCNT_LIMIT 0x1f
@@ -425,7 +425,7 @@
425#define DCFG_DEVADDR_SHIFT 4 425#define DCFG_DEVADDR_SHIFT 4
426#define DCFG_DEVADDR_LIMIT 0x7f 426#define DCFG_DEVADDR_LIMIT 0x7f
427#define DCFG_DEVADDR(_x) ((_x) << 4) 427#define DCFG_DEVADDR(_x) ((_x) << 4)
428#define DCFG_NZ_STS_OUT_HSHK (1 << 2) 428#define DCFG_NZ_STS_OUT_HSHK BIT(2)
429#define DCFG_DEVSPD_MASK (0x3 << 0) 429#define DCFG_DEVSPD_MASK (0x3 << 0)
430#define DCFG_DEVSPD_SHIFT 0 430#define DCFG_DEVSPD_SHIFT 0
431#define DCFG_DEVSPD_HS 0 431#define DCFG_DEVSPD_HS 0
@@ -434,54 +434,54 @@
434#define DCFG_DEVSPD_FS48 3 434#define DCFG_DEVSPD_FS48 3
435 435
436#define DCTL HSOTG_REG(0x804) 436#define DCTL HSOTG_REG(0x804)
437#define DCTL_PWRONPRGDONE (1 << 11) 437#define DCTL_PWRONPRGDONE BIT(11)
438#define DCTL_CGOUTNAK (1 << 10) 438#define DCTL_CGOUTNAK BIT(10)
439#define DCTL_SGOUTNAK (1 << 9) 439#define DCTL_SGOUTNAK BIT(9)
440#define DCTL_CGNPINNAK (1 << 8) 440#define DCTL_CGNPINNAK BIT(8)
441#define DCTL_SGNPINNAK (1 << 7) 441#define DCTL_SGNPINNAK BIT(7)
442#define DCTL_TSTCTL_MASK (0x7 << 4) 442#define DCTL_TSTCTL_MASK (0x7 << 4)
443#define DCTL_TSTCTL_SHIFT 4 443#define DCTL_TSTCTL_SHIFT 4
444#define DCTL_GOUTNAKSTS (1 << 3) 444#define DCTL_GOUTNAKSTS BIT(3)
445#define DCTL_GNPINNAKSTS (1 << 2) 445#define DCTL_GNPINNAKSTS BIT(2)
446#define DCTL_SFTDISCON (1 << 1) 446#define DCTL_SFTDISCON BIT(1)
447#define DCTL_RMTWKUPSIG (1 << 0) 447#define DCTL_RMTWKUPSIG BIT(0)
448 448
449#define DSTS HSOTG_REG(0x808) 449#define DSTS HSOTG_REG(0x808)
450#define DSTS_SOFFN_MASK (0x3fff << 8) 450#define DSTS_SOFFN_MASK (0x3fff << 8)
451#define DSTS_SOFFN_SHIFT 8 451#define DSTS_SOFFN_SHIFT 8
452#define DSTS_SOFFN_LIMIT 0x3fff 452#define DSTS_SOFFN_LIMIT 0x3fff
453#define DSTS_SOFFN(_x) ((_x) << 8) 453#define DSTS_SOFFN(_x) ((_x) << 8)
454#define DSTS_ERRATICERR (1 << 3) 454#define DSTS_ERRATICERR BIT(3)
455#define DSTS_ENUMSPD_MASK (0x3 << 1) 455#define DSTS_ENUMSPD_MASK (0x3 << 1)
456#define DSTS_ENUMSPD_SHIFT 1 456#define DSTS_ENUMSPD_SHIFT 1
457#define DSTS_ENUMSPD_HS 0 457#define DSTS_ENUMSPD_HS 0
458#define DSTS_ENUMSPD_FS 1 458#define DSTS_ENUMSPD_FS 1
459#define DSTS_ENUMSPD_LS 2 459#define DSTS_ENUMSPD_LS 2
460#define DSTS_ENUMSPD_FS48 3 460#define DSTS_ENUMSPD_FS48 3
461#define DSTS_SUSPSTS (1 << 0) 461#define DSTS_SUSPSTS BIT(0)
462 462
463#define DIEPMSK HSOTG_REG(0x810) 463#define DIEPMSK HSOTG_REG(0x810)
464#define DIEPMSK_NAKMSK (1 << 13) 464#define DIEPMSK_NAKMSK BIT(13)
465#define DIEPMSK_BNAININTRMSK (1 << 9) 465#define DIEPMSK_BNAININTRMSK BIT(9)
466#define DIEPMSK_TXFIFOUNDRNMSK (1 << 8) 466#define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
467#define DIEPMSK_TXFIFOEMPTY (1 << 7) 467#define DIEPMSK_TXFIFOEMPTY BIT(7)
468#define DIEPMSK_INEPNAKEFFMSK (1 << 6) 468#define DIEPMSK_INEPNAKEFFMSK BIT(6)
469#define DIEPMSK_INTKNEPMISMSK (1 << 5) 469#define DIEPMSK_INTKNEPMISMSK BIT(5)
470#define DIEPMSK_INTKNTXFEMPMSK (1 << 4) 470#define DIEPMSK_INTKNTXFEMPMSK BIT(4)
471#define DIEPMSK_TIMEOUTMSK (1 << 3) 471#define DIEPMSK_TIMEOUTMSK BIT(3)
472#define DIEPMSK_AHBERRMSK (1 << 2) 472#define DIEPMSK_AHBERRMSK BIT(2)
473#define DIEPMSK_EPDISBLDMSK (1 << 1) 473#define DIEPMSK_EPDISBLDMSK BIT(1)
474#define DIEPMSK_XFERCOMPLMSK (1 << 0) 474#define DIEPMSK_XFERCOMPLMSK BIT(0)
475 475
476#define DOEPMSK HSOTG_REG(0x814) 476#define DOEPMSK HSOTG_REG(0x814)
477#define DOEPMSK_BNAMSK (1 << 9) 477#define DOEPMSK_BNAMSK BIT(9)
478#define DOEPMSK_BACK2BACKSETUP (1 << 6) 478#define DOEPMSK_BACK2BACKSETUP BIT(6)
479#define DOEPMSK_STSPHSERCVDMSK (1 << 5) 479#define DOEPMSK_STSPHSERCVDMSK BIT(5)
480#define DOEPMSK_OUTTKNEPDISMSK (1 << 4) 480#define DOEPMSK_OUTTKNEPDISMSK BIT(4)
481#define DOEPMSK_SETUPMSK (1 << 3) 481#define DOEPMSK_SETUPMSK BIT(3)
482#define DOEPMSK_AHBERRMSK (1 << 2) 482#define DOEPMSK_AHBERRMSK BIT(2)
483#define DOEPMSK_EPDISBLDMSK (1 << 1) 483#define DOEPMSK_EPDISBLDMSK BIT(1)
484#define DOEPMSK_XFERCOMPLMSK (1 << 0) 484#define DOEPMSK_XFERCOMPLMSK BIT(0)
485 485
486#define DAINT HSOTG_REG(0x818) 486#define DAINT HSOTG_REG(0x818)
487#define DAINTMSK HSOTG_REG(0x81C) 487#define DAINTMSK HSOTG_REG(0x81C)
@@ -516,30 +516,30 @@
516#define D0EPCTL_MPS_16 2 516#define D0EPCTL_MPS_16 2
517#define D0EPCTL_MPS_8 3 517#define D0EPCTL_MPS_8 3
518 518
519#define DXEPCTL_EPENA (1 << 31) 519#define DXEPCTL_EPENA BIT(31)
520#define DXEPCTL_EPDIS (1 << 30) 520#define DXEPCTL_EPDIS BIT(30)
521#define DXEPCTL_SETD1PID (1 << 29) 521#define DXEPCTL_SETD1PID BIT(29)
522#define DXEPCTL_SETODDFR (1 << 29) 522#define DXEPCTL_SETODDFR BIT(29)
523#define DXEPCTL_SETD0PID (1 << 28) 523#define DXEPCTL_SETD0PID BIT(28)
524#define DXEPCTL_SETEVENFR (1 << 28) 524#define DXEPCTL_SETEVENFR BIT(28)
525#define DXEPCTL_SNAK (1 << 27) 525#define DXEPCTL_SNAK BIT(27)
526#define DXEPCTL_CNAK (1 << 26) 526#define DXEPCTL_CNAK BIT(26)
527#define DXEPCTL_TXFNUM_MASK (0xf << 22) 527#define DXEPCTL_TXFNUM_MASK (0xf << 22)
528#define DXEPCTL_TXFNUM_SHIFT 22 528#define DXEPCTL_TXFNUM_SHIFT 22
529#define DXEPCTL_TXFNUM_LIMIT 0xf 529#define DXEPCTL_TXFNUM_LIMIT 0xf
530#define DXEPCTL_TXFNUM(_x) ((_x) << 22) 530#define DXEPCTL_TXFNUM(_x) ((_x) << 22)
531#define DXEPCTL_STALL (1 << 21) 531#define DXEPCTL_STALL BIT(21)
532#define DXEPCTL_SNP (1 << 20) 532#define DXEPCTL_SNP BIT(20)
533#define DXEPCTL_EPTYPE_MASK (0x3 << 18) 533#define DXEPCTL_EPTYPE_MASK (0x3 << 18)
534#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) 534#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
535#define DXEPCTL_EPTYPE_ISO (0x1 << 18) 535#define DXEPCTL_EPTYPE_ISO (0x1 << 18)
536#define DXEPCTL_EPTYPE_BULK (0x2 << 18) 536#define DXEPCTL_EPTYPE_BULK (0x2 << 18)
537#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) 537#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
538 538
539#define DXEPCTL_NAKSTS (1 << 17) 539#define DXEPCTL_NAKSTS BIT(17)
540#define DXEPCTL_DPID (1 << 16) 540#define DXEPCTL_DPID BIT(16)
541#define DXEPCTL_EOFRNUM (1 << 16) 541#define DXEPCTL_EOFRNUM BIT(16)
542#define DXEPCTL_USBACTEP (1 << 15) 542#define DXEPCTL_USBACTEP BIT(15)
543#define DXEPCTL_NEXTEP_MASK (0xf << 11) 543#define DXEPCTL_NEXTEP_MASK (0xf << 11)
544#define DXEPCTL_NEXTEP_SHIFT 11 544#define DXEPCTL_NEXTEP_SHIFT 11
545#define DXEPCTL_NEXTEP_LIMIT 0xf 545#define DXEPCTL_NEXTEP_LIMIT 0xf
@@ -551,26 +551,26 @@
551 551
552#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) 552#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
553#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) 553#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
554#define DXEPINT_SETUP_RCVD (1 << 15) 554#define DXEPINT_SETUP_RCVD BIT(15)
555#define DXEPINT_NYETINTRPT (1 << 14) 555#define DXEPINT_NYETINTRPT BIT(14)
556#define DXEPINT_NAKINTRPT (1 << 13) 556#define DXEPINT_NAKINTRPT BIT(13)
557#define DXEPINT_BBLEERRINTRPT (1 << 12) 557#define DXEPINT_BBLEERRINTRPT BIT(12)
558#define DXEPINT_PKTDRPSTS (1 << 11) 558#define DXEPINT_PKTDRPSTS BIT(11)
559#define DXEPINT_BNAINTR (1 << 9) 559#define DXEPINT_BNAINTR BIT(9)
560#define DXEPINT_TXFIFOUNDRN (1 << 8) 560#define DXEPINT_TXFIFOUNDRN BIT(8)
561#define DXEPINT_OUTPKTERR (1 << 8) 561#define DXEPINT_OUTPKTERR BIT(8)
562#define DXEPINT_TXFEMP (1 << 7) 562#define DXEPINT_TXFEMP BIT(7)
563#define DXEPINT_INEPNAKEFF (1 << 6) 563#define DXEPINT_INEPNAKEFF BIT(6)
564#define DXEPINT_BACK2BACKSETUP (1 << 6) 564#define DXEPINT_BACK2BACKSETUP BIT(6)
565#define DXEPINT_INTKNEPMIS (1 << 5) 565#define DXEPINT_INTKNEPMIS BIT(5)
566#define DXEPINT_STSPHSERCVD (1 << 5) 566#define DXEPINT_STSPHSERCVD BIT(5)
567#define DXEPINT_INTKNTXFEMP (1 << 4) 567#define DXEPINT_INTKNTXFEMP BIT(4)
568#define DXEPINT_OUTTKNEPDIS (1 << 4) 568#define DXEPINT_OUTTKNEPDIS BIT(4)
569#define DXEPINT_TIMEOUT (1 << 3) 569#define DXEPINT_TIMEOUT BIT(3)
570#define DXEPINT_SETUP (1 << 3) 570#define DXEPINT_SETUP BIT(3)
571#define DXEPINT_AHBERR (1 << 2) 571#define DXEPINT_AHBERR BIT(2)
572#define DXEPINT_EPDISBLD (1 << 1) 572#define DXEPINT_EPDISBLD BIT(1)
573#define DXEPINT_XFERCOMPL (1 << 0) 573#define DXEPINT_XFERCOMPL BIT(0)
574 574
575#define DIEPTSIZ0 HSOTG_REG(0x910) 575#define DIEPTSIZ0 HSOTG_REG(0x910)
576#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19) 576#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
@@ -587,7 +587,7 @@
587#define DOEPTSIZ0_SUPCNT_SHIFT 29 587#define DOEPTSIZ0_SUPCNT_SHIFT 29
588#define DOEPTSIZ0_SUPCNT_LIMIT 0x3 588#define DOEPTSIZ0_SUPCNT_LIMIT 0x3
589#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) 589#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
590#define DOEPTSIZ0_PKTCNT (1 << 19) 590#define DOEPTSIZ0_PKTCNT BIT(19)
591#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) 591#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
592#define DOEPTSIZ0_XFERSIZE_SHIFT 0 592#define DOEPTSIZ0_XFERSIZE_SHIFT 0
593 593
@@ -614,55 +614,55 @@
614#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) 614#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
615 615
616#define PCGCTL HSOTG_REG(0x0e00) 616#define PCGCTL HSOTG_REG(0x0e00)
617#define PCGCTL_IF_DEV_MODE (1 << 31) 617#define PCGCTL_IF_DEV_MODE BIT(31)
618#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29) 618#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
619#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 619#define PCGCTL_P2HD_PRT_SPD_SHIFT 29
620#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27) 620#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
621#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 621#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
622#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20) 622#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
623#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 623#define PCGCTL_MAC_DEV_ADDR_SHIFT 20
624#define PCGCTL_MAX_TERMSEL (1 << 19) 624#define PCGCTL_MAX_TERMSEL BIT(19)
625#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17) 625#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
626#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 626#define PCGCTL_MAX_XCVRSELECT_SHIFT 17
627#define PCGCTL_PORT_POWER (1 << 16) 627#define PCGCTL_PORT_POWER BIT(16)
628#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14) 628#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
629#define PCGCTL_PRT_CLK_SEL_SHIFT 14 629#define PCGCTL_PRT_CLK_SEL_SHIFT 14
630#define PCGCTL_ESS_REG_RESTORED (1 << 13) 630#define PCGCTL_ESS_REG_RESTORED BIT(13)
631#define PCGCTL_EXTND_HIBER_SWITCH (1 << 12) 631#define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
632#define PCGCTL_EXTND_HIBER_PWRCLMP (1 << 11) 632#define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
633#define PCGCTL_ENBL_EXTND_HIBER (1 << 10) 633#define PCGCTL_ENBL_EXTND_HIBER BIT(10)
634#define PCGCTL_RESTOREMODE (1 << 9) 634#define PCGCTL_RESTOREMODE BIT(9)
635#define PCGCTL_RESETAFTSUSP (1 << 8) 635#define PCGCTL_RESETAFTSUSP BIT(8)
636#define PCGCTL_DEEP_SLEEP (1 << 7) 636#define PCGCTL_DEEP_SLEEP BIT(7)
637#define PCGCTL_PHY_IN_SLEEP (1 << 6) 637#define PCGCTL_PHY_IN_SLEEP BIT(6)
638#define PCGCTL_ENBL_SLEEP_GATING (1 << 5) 638#define PCGCTL_ENBL_SLEEP_GATING BIT(5)
639#define PCGCTL_RSTPDWNMODULE (1 << 3) 639#define PCGCTL_RSTPDWNMODULE BIT(3)
640#define PCGCTL_PWRCLMP (1 << 2) 640#define PCGCTL_PWRCLMP BIT(2)
641#define PCGCTL_GATEHCLK (1 << 1) 641#define PCGCTL_GATEHCLK BIT(1)
642#define PCGCTL_STOPPCLK (1 << 0) 642#define PCGCTL_STOPPCLK BIT(0)
643 643
644#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) 644#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
645 645
646/* Host Mode Registers */ 646/* Host Mode Registers */
647 647
648#define HCFG HSOTG_REG(0x0400) 648#define HCFG HSOTG_REG(0x0400)
649#define HCFG_MODECHTIMEN (1 << 31) 649#define HCFG_MODECHTIMEN BIT(31)
650#define HCFG_PERSCHEDENA (1 << 26) 650#define HCFG_PERSCHEDENA BIT(26)
651#define HCFG_FRLISTEN_MASK (0x3 << 24) 651#define HCFG_FRLISTEN_MASK (0x3 << 24)
652#define HCFG_FRLISTEN_SHIFT 24 652#define HCFG_FRLISTEN_SHIFT 24
653#define HCFG_FRLISTEN_8 (0 << 24) 653#define HCFG_FRLISTEN_8 (0 << 24)
654#define FRLISTEN_8_SIZE 8 654#define FRLISTEN_8_SIZE 8
655#define HCFG_FRLISTEN_16 (1 << 24) 655#define HCFG_FRLISTEN_16 BIT(24)
656#define FRLISTEN_16_SIZE 16 656#define FRLISTEN_16_SIZE 16
657#define HCFG_FRLISTEN_32 (2 << 24) 657#define HCFG_FRLISTEN_32 (2 << 24)
658#define FRLISTEN_32_SIZE 32 658#define FRLISTEN_32_SIZE 32
659#define HCFG_FRLISTEN_64 (3 << 24) 659#define HCFG_FRLISTEN_64 (3 << 24)
660#define FRLISTEN_64_SIZE 64 660#define FRLISTEN_64_SIZE 64
661#define HCFG_DESCDMA (1 << 23) 661#define HCFG_DESCDMA BIT(23)
662#define HCFG_RESVALID_MASK (0xff << 8) 662#define HCFG_RESVALID_MASK (0xff << 8)
663#define HCFG_RESVALID_SHIFT 8 663#define HCFG_RESVALID_SHIFT 8
664#define HCFG_ENA32KHZ (1 << 7) 664#define HCFG_ENA32KHZ BIT(7)
665#define HCFG_FSLSSUPP (1 << 2) 665#define HCFG_FSLSSUPP BIT(2)
666#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0) 666#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
667#define HCFG_FSLSPCLKSEL_SHIFT 0 667#define HCFG_FSLSPCLKSEL_SHIFT 0
668#define HCFG_FSLSPCLKSEL_30_60_MHZ 0 668#define HCFG_FSLSPCLKSEL_30_60_MHZ 0
@@ -672,7 +672,7 @@
672#define HFIR HSOTG_REG(0x0404) 672#define HFIR HSOTG_REG(0x0404)
673#define HFIR_FRINT_MASK (0xffff << 0) 673#define HFIR_FRINT_MASK (0xffff << 0)
674#define HFIR_FRINT_SHIFT 0 674#define HFIR_FRINT_SHIFT 0
675#define HFIR_RLDCTRL (1 << 16) 675#define HFIR_RLDCTRL BIT(16)
676 676
677#define HFNUM HSOTG_REG(0x0408) 677#define HFNUM HSOTG_REG(0x0408)
678#define HFNUM_FRREM_MASK (0xffff << 16) 678#define HFNUM_FRREM_MASK (0xffff << 16)
@@ -682,12 +682,12 @@
682#define HFNUM_MAX_FRNUM 0x3fff 682#define HFNUM_MAX_FRNUM 0x3fff
683 683
684#define HPTXSTS HSOTG_REG(0x0410) 684#define HPTXSTS HSOTG_REG(0x0410)
685#define TXSTS_QTOP_ODD (1 << 31) 685#define TXSTS_QTOP_ODD BIT(31)
686#define TXSTS_QTOP_CHNEP_MASK (0xf << 27) 686#define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
687#define TXSTS_QTOP_CHNEP_SHIFT 27 687#define TXSTS_QTOP_CHNEP_SHIFT 27
688#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25) 688#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
689#define TXSTS_QTOP_TOKEN_SHIFT 25 689#define TXSTS_QTOP_TOKEN_SHIFT 25
690#define TXSTS_QTOP_TERMINATE (1 << 24) 690#define TXSTS_QTOP_TERMINATE BIT(24)
691#define TXSTS_QSPCAVAIL_MASK (0xff << 16) 691#define TXSTS_QSPCAVAIL_MASK (0xff << 16)
692#define TXSTS_QSPCAVAIL_SHIFT 16 692#define TXSTS_QSPCAVAIL_SHIFT 16
693#define TXSTS_FSPCAVAIL_MASK (0xffff << 0) 693#define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
@@ -705,39 +705,39 @@
705#define HPRT0_SPD_LOW_SPEED 2 705#define HPRT0_SPD_LOW_SPEED 2
706#define HPRT0_TSTCTL_MASK (0xf << 13) 706#define HPRT0_TSTCTL_MASK (0xf << 13)
707#define HPRT0_TSTCTL_SHIFT 13 707#define HPRT0_TSTCTL_SHIFT 13
708#define HPRT0_PWR (1 << 12) 708#define HPRT0_PWR BIT(12)
709#define HPRT0_LNSTS_MASK (0x3 << 10) 709#define HPRT0_LNSTS_MASK (0x3 << 10)
710#define HPRT0_LNSTS_SHIFT 10 710#define HPRT0_LNSTS_SHIFT 10
711#define HPRT0_RST (1 << 8) 711#define HPRT0_RST BIT(8)
712#define HPRT0_SUSP (1 << 7) 712#define HPRT0_SUSP BIT(7)
713#define HPRT0_RES (1 << 6) 713#define HPRT0_RES BIT(6)
714#define HPRT0_OVRCURRCHG (1 << 5) 714#define HPRT0_OVRCURRCHG BIT(5)
715#define HPRT0_OVRCURRACT (1 << 4) 715#define HPRT0_OVRCURRACT BIT(4)
716#define HPRT0_ENACHG (1 << 3) 716#define HPRT0_ENACHG BIT(3)
717#define HPRT0_ENA (1 << 2) 717#define HPRT0_ENA BIT(2)
718#define HPRT0_CONNDET (1 << 1) 718#define HPRT0_CONNDET BIT(1)
719#define HPRT0_CONNSTS (1 << 0) 719#define HPRT0_CONNSTS BIT(0)
720 720
721#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch)) 721#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
722#define HCCHAR_CHENA (1 << 31) 722#define HCCHAR_CHENA BIT(31)
723#define HCCHAR_CHDIS (1 << 30) 723#define HCCHAR_CHDIS BIT(30)
724#define HCCHAR_ODDFRM (1 << 29) 724#define HCCHAR_ODDFRM BIT(29)
725#define HCCHAR_DEVADDR_MASK (0x7f << 22) 725#define HCCHAR_DEVADDR_MASK (0x7f << 22)
726#define HCCHAR_DEVADDR_SHIFT 22 726#define HCCHAR_DEVADDR_SHIFT 22
727#define HCCHAR_MULTICNT_MASK (0x3 << 20) 727#define HCCHAR_MULTICNT_MASK (0x3 << 20)
728#define HCCHAR_MULTICNT_SHIFT 20 728#define HCCHAR_MULTICNT_SHIFT 20
729#define HCCHAR_EPTYPE_MASK (0x3 << 18) 729#define HCCHAR_EPTYPE_MASK (0x3 << 18)
730#define HCCHAR_EPTYPE_SHIFT 18 730#define HCCHAR_EPTYPE_SHIFT 18
731#define HCCHAR_LSPDDEV (1 << 17) 731#define HCCHAR_LSPDDEV BIT(17)
732#define HCCHAR_EPDIR (1 << 15) 732#define HCCHAR_EPDIR BIT(15)
733#define HCCHAR_EPNUM_MASK (0xf << 11) 733#define HCCHAR_EPNUM_MASK (0xf << 11)
734#define HCCHAR_EPNUM_SHIFT 11 734#define HCCHAR_EPNUM_SHIFT 11
735#define HCCHAR_MPS_MASK (0x7ff << 0) 735#define HCCHAR_MPS_MASK (0x7ff << 0)
736#define HCCHAR_MPS_SHIFT 0 736#define HCCHAR_MPS_SHIFT 0
737 737
738#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch)) 738#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
739#define HCSPLT_SPLTENA (1 << 31) 739#define HCSPLT_SPLTENA BIT(31)
740#define HCSPLT_COMPSPLT (1 << 16) 740#define HCSPLT_COMPSPLT BIT(16)
741#define HCSPLT_XACTPOS_MASK (0x3 << 14) 741#define HCSPLT_XACTPOS_MASK (0x3 << 14)
742#define HCSPLT_XACTPOS_SHIFT 14 742#define HCSPLT_XACTPOS_SHIFT 14
743#define HCSPLT_XACTPOS_MID 0 743#define HCSPLT_XACTPOS_MID 0
@@ -752,23 +752,23 @@
752#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch)) 752#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
753#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch)) 753#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
754#define HCINTMSK_RESERVED14_31 (0x3ffff << 14) 754#define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
755#define HCINTMSK_FRM_LIST_ROLL (1 << 13) 755#define HCINTMSK_FRM_LIST_ROLL BIT(13)
756#define HCINTMSK_XCS_XACT (1 << 12) 756#define HCINTMSK_XCS_XACT BIT(12)
757#define HCINTMSK_BNA (1 << 11) 757#define HCINTMSK_BNA BIT(11)
758#define HCINTMSK_DATATGLERR (1 << 10) 758#define HCINTMSK_DATATGLERR BIT(10)
759#define HCINTMSK_FRMOVRUN (1 << 9) 759#define HCINTMSK_FRMOVRUN BIT(9)
760#define HCINTMSK_BBLERR (1 << 8) 760#define HCINTMSK_BBLERR BIT(8)
761#define HCINTMSK_XACTERR (1 << 7) 761#define HCINTMSK_XACTERR BIT(7)
762#define HCINTMSK_NYET (1 << 6) 762#define HCINTMSK_NYET BIT(6)
763#define HCINTMSK_ACK (1 << 5) 763#define HCINTMSK_ACK BIT(5)
764#define HCINTMSK_NAK (1 << 4) 764#define HCINTMSK_NAK BIT(4)
765#define HCINTMSK_STALL (1 << 3) 765#define HCINTMSK_STALL BIT(3)
766#define HCINTMSK_AHBERR (1 << 2) 766#define HCINTMSK_AHBERR BIT(2)
767#define HCINTMSK_CHHLTD (1 << 1) 767#define HCINTMSK_CHHLTD BIT(1)
768#define HCINTMSK_XFERCOMPL (1 << 0) 768#define HCINTMSK_XFERCOMPL BIT(0)
769 769
770#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch)) 770#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
771#define TSIZ_DOPNG (1 << 31) 771#define TSIZ_DOPNG BIT(31)
772#define TSIZ_SC_MC_PID_MASK (0x3 << 29) 772#define TSIZ_SC_MC_PID_MASK (0x3 << 29)
773#define TSIZ_SC_MC_PID_SHIFT 29 773#define TSIZ_SC_MC_PID_SHIFT 29
774#define TSIZ_SC_MC_PID_DATA0 0 774#define TSIZ_SC_MC_PID_DATA0 0
@@ -808,14 +808,14 @@ struct dwc2_dma_desc {
808 808
809/* Host Mode DMA descriptor status quadlet */ 809/* Host Mode DMA descriptor status quadlet */
810 810
811#define HOST_DMA_A (1 << 31) 811#define HOST_DMA_A BIT(31)
812#define HOST_DMA_STS_MASK (0x3 << 28) 812#define HOST_DMA_STS_MASK (0x3 << 28)
813#define HOST_DMA_STS_SHIFT 28 813#define HOST_DMA_STS_SHIFT 28
814#define HOST_DMA_STS_PKTERR (1 << 28) 814#define HOST_DMA_STS_PKTERR BIT(28)
815#define HOST_DMA_EOL (1 << 26) 815#define HOST_DMA_EOL BIT(26)
816#define HOST_DMA_IOC (1 << 25) 816#define HOST_DMA_IOC BIT(25)
817#define HOST_DMA_SUP (1 << 24) 817#define HOST_DMA_SUP BIT(24)
818#define HOST_DMA_ALT_QTD (1 << 23) 818#define HOST_DMA_ALT_QTD BIT(23)
819#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17) 819#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
820#define HOST_DMA_QTD_OFFSET_SHIFT 17 820#define HOST_DMA_QTD_OFFSET_SHIFT 17
821#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0) 821#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
@@ -837,11 +837,11 @@ struct dwc2_dma_desc {
837#define DEV_DMA_STS_SUCC 0 837#define DEV_DMA_STS_SUCC 0
838#define DEV_DMA_STS_BUFF_FLUSH 1 838#define DEV_DMA_STS_BUFF_FLUSH 1
839#define DEV_DMA_STS_BUFF_ERR 3 839#define DEV_DMA_STS_BUFF_ERR 3
840#define DEV_DMA_L (1 << 27) 840#define DEV_DMA_L BIT(27)
841#define DEV_DMA_SHORT (1 << 26) 841#define DEV_DMA_SHORT BIT(26)
842#define DEV_DMA_IOC (1 << 25) 842#define DEV_DMA_IOC BIT(25)
843#define DEV_DMA_SR (1 << 24) 843#define DEV_DMA_SR BIT(24)
844#define DEV_DMA_MTRF (1 << 23) 844#define DEV_DMA_MTRF BIT(23)
845#define DEV_DMA_ISOC_PID_MASK (0x3 << 23) 845#define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
846#define DEV_DMA_ISOC_PID_SHIFT 23 846#define DEV_DMA_ISOC_PID_SHIFT 23
847#define DEV_DMA_ISOC_PID_DATA0 0 847#define DEV_DMA_ISOC_PID_DATA0 0
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index bcd1e19b4076..1efabdc24f64 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -1131,27 +1131,27 @@ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1131 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable); 1131 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
1132 1132
1133 dwc2_set_param_host_support_fs_ls_low_power(hsotg, 1133 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
1134 params->host_support_fs_ls_low_power); 1134 params->host_support_fs_ls_low_power);
1135 dwc2_set_param_enable_dynamic_fifo(hsotg, 1135 dwc2_set_param_enable_dynamic_fifo(hsotg,
1136 params->enable_dynamic_fifo); 1136 params->enable_dynamic_fifo);
1137 dwc2_set_param_max_transfer_size(hsotg, 1137 dwc2_set_param_max_transfer_size(hsotg,
1138 params->max_transfer_size); 1138 params->max_transfer_size);
1139 dwc2_set_param_max_packet_count(hsotg, 1139 dwc2_set_param_max_packet_count(hsotg,
1140 params->max_packet_count); 1140 params->max_packet_count);
1141 dwc2_set_param_host_channels(hsotg, params->host_channels); 1141 dwc2_set_param_host_channels(hsotg, params->host_channels);
1142 dwc2_set_param_phy_type(hsotg, params->phy_type); 1142 dwc2_set_param_phy_type(hsotg, params->phy_type);
1143 dwc2_set_param_speed(hsotg, params->speed); 1143 dwc2_set_param_speed(hsotg, params->speed);
1144 dwc2_set_param_host_ls_low_power_phy_clk(hsotg, 1144 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
1145 params->host_ls_low_power_phy_clk); 1145 params->host_ls_low_power_phy_clk);
1146 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); 1146 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
1147 dwc2_set_param_phy_ulpi_ext_vbus(hsotg, 1147 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
1148 params->phy_ulpi_ext_vbus); 1148 params->phy_ulpi_ext_vbus);
1149 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); 1149 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
1150 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); 1150 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
1151 dwc2_set_param_ts_dline(hsotg, params->ts_dline); 1151 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
1152 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); 1152 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
1153 dwc2_set_param_en_multiple_tx_fifo(hsotg, 1153 dwc2_set_param_en_multiple_tx_fifo(hsotg,
1154 params->en_multiple_tx_fifo); 1154 params->en_multiple_tx_fifo);
1155 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); 1155 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
1156 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); 1156 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
1157 dwc2_set_param_otg_ver(hsotg, params->otg_ver); 1157 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
diff --git a/drivers/usb/dwc2/pci.c b/drivers/usb/dwc2/pci.c
index a23329e3d7cd..fdeb8c7bf30a 100644
--- a/drivers/usb/dwc2/pci.c
+++ b/drivers/usb/dwc2/pci.c
@@ -87,7 +87,7 @@ static void dwc2_pci_remove(struct pci_dev *pci)
87} 87}
88 88
89static int dwc2_pci_probe(struct pci_dev *pci, 89static int dwc2_pci_probe(struct pci_dev *pci,
90 const struct pci_device_id *id) 90 const struct pci_device_id *id)
91{ 91{
92 struct resource res[2]; 92 struct resource res[2];
93 struct platform_device *dwc2; 93 struct platform_device *dwc2;
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 4fc8c603afb8..649d7b9a714b 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -111,7 +111,7 @@ static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
111 111
112 if (mode != hsotg->dr_mode) { 112 if (mode != hsotg->dr_mode) {
113 dev_warn(hsotg->dev, 113 dev_warn(hsotg->dev,
114 "Configuration mismatch. dr_mode forced to %s\n", 114 "Configuration mismatch. dr_mode forced to %s\n",
115 mode == USB_DR_MODE_HOST ? "host" : "device"); 115 mode == USB_DR_MODE_HOST ? "host" : "device");
116 116
117 hsotg->dr_mode = mode; 117 hsotg->dr_mode = mode;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 07:11:07 -0400