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authorChristoph Hellwig <hch@lst.de>2015-10-02 09:25:49 -0400
committerJens Axboe <axboe@fb.com>2015-10-09 12:40:37 -0400
commit9d99a8dda154f38307d43d9c9aa504bd3703d596 (patch)
treea46c7d299552272d3f6d054e7495c2a5e584977c
parentf11bb3e244c4b14e2d0a3b9d7e41895752997170 (diff)
nvme: move hardware structures out of the uapi version of nvme.h
Currently all NVMe command and completion structures are exposed to userspace through the uapi version of nvme.h. They are not an ABI between the kernel and userspace, and will change in C-incompatible way for future versions of the spec. Move them to the kernel version of the file and rename the uapi header to nvme_ioctl.h so that userspace can easily detect the presence of the new clean header. Nvme-cli already carries a local copy of the header, so it won't be affected by this move. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Jens Axboe <axboe@fb.com>
Diffstat
-rw-r--r--drivers/block/nvme-core.c1
-rw-r--r--include/linux/nvme.h526
-rw-r--r--include/uapi/linux/nvme.h589
-rw-r--r--include/uapi/linux/nvme_ioctl.h65
4 files changed, 590 insertions, 591 deletions
diff --git a/drivers/block/nvme-core.c b/drivers/block/nvme-core.c
index a20f66a44b96..a526696d684d 100644
--- a/drivers/block/nvme-core.c
+++ b/drivers/block/nvme-core.c
@@ -42,6 +42,7 @@
42#include <scsi/sg.h> 42#include <scsi/sg.h>
43#include <asm-generic/io-64-nonatomic-lo-hi.h> 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44 44
45#include <uapi/linux/nvme_ioctl.h>
45#include "nvme.h" 46#include "nvme.h"
46 47
47#define NVME_MINORS (1U << MINORBITS) 48#define NVME_MINORS (1U << MINORBITS)
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 364cb9adbbbc..91a805437876 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -15,8 +15,6 @@
15#ifndef _LINUX_NVME_H 15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H 16#define _LINUX_NVME_H
17 17
18#include <uapi/linux/nvme.h>
19
20struct nvme_bar { 18struct nvme_bar {
21 __u64 cap; /* Controller Capabilities */ 19 __u64 cap; /* Controller Capabilities */
22 __u32 vs; /* Version */ 20 __u32 vs; /* Version */
@@ -73,4 +71,528 @@ enum {
73 NVME_CSTS_SHST_MASK = 3 << 2, 71 NVME_CSTS_SHST_MASK = 3 << 2,
74}; 72};
75 73
74struct nvme_id_power_state {
75 __le16 max_power; /* centiwatts */
76 __u8 rsvd2;
77 __u8 flags;
78 __le32 entry_lat; /* microseconds */
79 __le32 exit_lat; /* microseconds */
80 __u8 read_tput;
81 __u8 read_lat;
82 __u8 write_tput;
83 __u8 write_lat;
84 __le16 idle_power;
85 __u8 idle_scale;
86 __u8 rsvd19;
87 __le16 active_power;
88 __u8 active_work_scale;
89 __u8 rsvd23[9];
90};
91
92enum {
93 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
94 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
95};
96
97struct nvme_id_ctrl {
98 __le16 vid;
99 __le16 ssvid;
100 char sn[20];
101 char mn[40];
102 char fr[8];
103 __u8 rab;
104 __u8 ieee[3];
105 __u8 mic;
106 __u8 mdts;
107 __u16 cntlid;
108 __u32 ver;
109 __u8 rsvd84[172];
110 __le16 oacs;
111 __u8 acl;
112 __u8 aerl;
113 __u8 frmw;
114 __u8 lpa;
115 __u8 elpe;
116 __u8 npss;
117 __u8 avscc;
118 __u8 apsta;
119 __le16 wctemp;
120 __le16 cctemp;
121 __u8 rsvd270[242];
122 __u8 sqes;
123 __u8 cqes;
124 __u8 rsvd514[2];
125 __le32 nn;
126 __le16 oncs;
127 __le16 fuses;
128 __u8 fna;
129 __u8 vwc;
130 __le16 awun;
131 __le16 awupf;
132 __u8 nvscc;
133 __u8 rsvd531;
134 __le16 acwu;
135 __u8 rsvd534[2];
136 __le32 sgls;
137 __u8 rsvd540[1508];
138 struct nvme_id_power_state psd[32];
139 __u8 vs[1024];
140};
141
142enum {
143 NVME_CTRL_ONCS_COMPARE = 1 << 0,
144 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
145 NVME_CTRL_ONCS_DSM = 1 << 2,
146 NVME_CTRL_VWC_PRESENT = 1 << 0,
147};
148
149struct nvme_lbaf {
150 __le16 ms;
151 __u8 ds;
152 __u8 rp;
153};
154
155struct nvme_id_ns {
156 __le64 nsze;
157 __le64 ncap;
158 __le64 nuse;
159 __u8 nsfeat;
160 __u8 nlbaf;
161 __u8 flbas;
162 __u8 mc;
163 __u8 dpc;
164 __u8 dps;
165 __u8 nmic;
166 __u8 rescap;
167 __u8 fpi;
168 __u8 rsvd33;
169 __le16 nawun;
170 __le16 nawupf;
171 __le16 nacwu;
172 __le16 nabsn;
173 __le16 nabo;
174 __le16 nabspf;
175 __u16 rsvd46;
176 __le64 nvmcap[2];
177 __u8 rsvd64[40];
178 __u8 nguid[16];
179 __u8 eui64[8];
180 struct nvme_lbaf lbaf[16];
181 __u8 rsvd192[192];
182 __u8 vs[3712];
183};
184
185enum {
186 NVME_NS_FEAT_THIN = 1 << 0,
187 NVME_NS_FLBAS_LBA_MASK = 0xf,
188 NVME_NS_FLBAS_META_EXT = 0x10,
189 NVME_LBAF_RP_BEST = 0,
190 NVME_LBAF_RP_BETTER = 1,
191 NVME_LBAF_RP_GOOD = 2,
192 NVME_LBAF_RP_DEGRADED = 3,
193 NVME_NS_DPC_PI_LAST = 1 << 4,
194 NVME_NS_DPC_PI_FIRST = 1 << 3,
195 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
196 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
197 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
198 NVME_NS_DPS_PI_FIRST = 1 << 3,
199 NVME_NS_DPS_PI_MASK = 0x7,
200 NVME_NS_DPS_PI_TYPE1 = 1,
201 NVME_NS_DPS_PI_TYPE2 = 2,
202 NVME_NS_DPS_PI_TYPE3 = 3,
203};
204
205struct nvme_smart_log {
206 __u8 critical_warning;
207 __u8 temperature[2];
208 __u8 avail_spare;
209 __u8 spare_thresh;
210 __u8 percent_used;
211 __u8 rsvd6[26];
212 __u8 data_units_read[16];
213 __u8 data_units_written[16];
214 __u8 host_reads[16];
215 __u8 host_writes[16];
216 __u8 ctrl_busy_time[16];
217 __u8 power_cycles[16];
218 __u8 power_on_hours[16];
219 __u8 unsafe_shutdowns[16];
220 __u8 media_errors[16];
221 __u8 num_err_log_entries[16];
222 __le32 warning_temp_time;
223 __le32 critical_comp_time;
224 __le16 temp_sensor[8];
225 __u8 rsvd216[296];
226};
227
228enum {
229 NVME_SMART_CRIT_SPARE = 1 << 0,
230 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
231 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
232 NVME_SMART_CRIT_MEDIA = 1 << 3,
233 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
234};
235
236enum {
237 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
238};
239
240struct nvme_lba_range_type {
241 __u8 type;
242 __u8 attributes;
243 __u8 rsvd2[14];
244 __u64 slba;
245 __u64 nlb;
246 __u8 guid[16];
247 __u8 rsvd48[16];
248};
249
250enum {
251 NVME_LBART_TYPE_FS = 0x01,
252 NVME_LBART_TYPE_RAID = 0x02,
253 NVME_LBART_TYPE_CACHE = 0x03,
254 NVME_LBART_TYPE_SWAP = 0x04,
255
256 NVME_LBART_ATTRIB_TEMP = 1 << 0,
257 NVME_LBART_ATTRIB_HIDE = 1 << 1,
258};
259
260struct nvme_reservation_status {
261 __le32 gen;
262 __u8 rtype;
263 __u8 regctl[2];
264 __u8 resv5[2];
265 __u8 ptpls;
266 __u8 resv10[13];
267 struct {
268 __le16 cntlid;
269 __u8 rcsts;
270 __u8 resv3[5];
271 __le64 hostid;
272 __le64 rkey;
273 } regctl_ds[];
274};
275
276/* I/O commands */
277
278enum nvme_opcode {
279 nvme_cmd_flush = 0x00,
280 nvme_cmd_write = 0x01,
281 nvme_cmd_read = 0x02,
282 nvme_cmd_write_uncor = 0x04,
283 nvme_cmd_compare = 0x05,
284 nvme_cmd_write_zeroes = 0x08,
285 nvme_cmd_dsm = 0x09,
286 nvme_cmd_resv_register = 0x0d,
287 nvme_cmd_resv_report = 0x0e,
288 nvme_cmd_resv_acquire = 0x11,
289 nvme_cmd_resv_release = 0x15,
290};
291
292struct nvme_common_command {
293 __u8 opcode;
294 __u8 flags;
295 __u16 command_id;
296 __le32 nsid;
297 __le32 cdw2[2];
298 __le64 metadata;
299 __le64 prp1;
300 __le64 prp2;
301 __le32 cdw10[6];
302};
303
304struct nvme_rw_command {
305 __u8 opcode;
306 __u8 flags;
307 __u16 command_id;
308 __le32 nsid;
309 __u64 rsvd2;
310 __le64 metadata;
311 __le64 prp1;
312 __le64 prp2;
313 __le64 slba;
314 __le16 length;
315 __le16 control;
316 __le32 dsmgmt;
317 __le32 reftag;
318 __le16 apptag;
319 __le16 appmask;
320};
321
322enum {
323 NVME_RW_LR = 1 << 15,
324 NVME_RW_FUA = 1 << 14,
325 NVME_RW_DSM_FREQ_UNSPEC = 0,
326 NVME_RW_DSM_FREQ_TYPICAL = 1,
327 NVME_RW_DSM_FREQ_RARE = 2,
328 NVME_RW_DSM_FREQ_READS = 3,
329 NVME_RW_DSM_FREQ_WRITES = 4,
330 NVME_RW_DSM_FREQ_RW = 5,
331 NVME_RW_DSM_FREQ_ONCE = 6,
332 NVME_RW_DSM_FREQ_PREFETCH = 7,
333 NVME_RW_DSM_FREQ_TEMP = 8,
334 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
335 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
336 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
337 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
338 NVME_RW_DSM_SEQ_REQ = 1 << 6,
339 NVME_RW_DSM_COMPRESSED = 1 << 7,
340 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
341 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
342 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
343 NVME_RW_PRINFO_PRACT = 1 << 13,
344};
345
346struct nvme_dsm_cmd {
347 __u8 opcode;
348 __u8 flags;
349 __u16 command_id;
350 __le32 nsid;
351 __u64 rsvd2[2];
352 __le64 prp1;
353 __le64 prp2;
354 __le32 nr;
355 __le32 attributes;
356 __u32 rsvd12[4];
357};
358
359enum {
360 NVME_DSMGMT_IDR = 1 << 0,
361 NVME_DSMGMT_IDW = 1 << 1,
362 NVME_DSMGMT_AD = 1 << 2,
363};
364
365struct nvme_dsm_range {
366 __le32 cattr;
367 __le32 nlb;
368 __le64 slba;
369};
370
371/* Admin commands */
372
373enum nvme_admin_opcode {
374 nvme_admin_delete_sq = 0x00,
375 nvme_admin_create_sq = 0x01,
376 nvme_admin_get_log_page = 0x02,
377 nvme_admin_delete_cq = 0x04,
378 nvme_admin_create_cq = 0x05,
379 nvme_admin_identify = 0x06,
380 nvme_admin_abort_cmd = 0x08,
381 nvme_admin_set_features = 0x09,
382 nvme_admin_get_features = 0x0a,
383 nvme_admin_async_event = 0x0c,
384 nvme_admin_activate_fw = 0x10,
385 nvme_admin_download_fw = 0x11,
386 nvme_admin_format_nvm = 0x80,
387 nvme_admin_security_send = 0x81,
388 nvme_admin_security_recv = 0x82,
389};
390
391enum {
392 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
393 NVME_CQ_IRQ_ENABLED = (1 << 1),
394 NVME_SQ_PRIO_URGENT = (0 << 1),
395 NVME_SQ_PRIO_HIGH = (1 << 1),
396 NVME_SQ_PRIO_MEDIUM = (2 << 1),
397 NVME_SQ_PRIO_LOW = (3 << 1),
398 NVME_FEAT_ARBITRATION = 0x01,
399 NVME_FEAT_POWER_MGMT = 0x02,
400 NVME_FEAT_LBA_RANGE = 0x03,
401 NVME_FEAT_TEMP_THRESH = 0x04,
402 NVME_FEAT_ERR_RECOVERY = 0x05,
403 NVME_FEAT_VOLATILE_WC = 0x06,
404 NVME_FEAT_NUM_QUEUES = 0x07,
405 NVME_FEAT_IRQ_COALESCE = 0x08,
406 NVME_FEAT_IRQ_CONFIG = 0x09,
407 NVME_FEAT_WRITE_ATOMIC = 0x0a,
408 NVME_FEAT_ASYNC_EVENT = 0x0b,
409 NVME_FEAT_AUTO_PST = 0x0c,
410 NVME_FEAT_SW_PROGRESS = 0x80,
411 NVME_FEAT_HOST_ID = 0x81,
412 NVME_FEAT_RESV_MASK = 0x82,
413 NVME_FEAT_RESV_PERSIST = 0x83,
414 NVME_LOG_ERROR = 0x01,
415 NVME_LOG_SMART = 0x02,
416 NVME_LOG_FW_SLOT = 0x03,
417 NVME_LOG_RESERVATION = 0x80,
418 NVME_FWACT_REPL = (0 << 3),
419 NVME_FWACT_REPL_ACTV = (1 << 3),
420 NVME_FWACT_ACTV = (2 << 3),
421};
422
423struct nvme_identify {
424 __u8 opcode;
425 __u8 flags;
426 __u16 command_id;
427 __le32 nsid;
428 __u64 rsvd2[2];
429 __le64 prp1;
430 __le64 prp2;
431 __le32 cns;
432 __u32 rsvd11[5];
433};
434
435struct nvme_features {
436 __u8 opcode;
437 __u8 flags;
438 __u16 command_id;
439 __le32 nsid;
440 __u64 rsvd2[2];
441 __le64 prp1;
442 __le64 prp2;
443 __le32 fid;
444 __le32 dword11;
445 __u32 rsvd12[4];
446};
447
448struct nvme_create_cq {
449 __u8 opcode;
450 __u8 flags;
451 __u16 command_id;
452 __u32 rsvd1[5];
453 __le64 prp1;
454 __u64 rsvd8;
455 __le16 cqid;
456 __le16 qsize;
457 __le16 cq_flags;
458 __le16 irq_vector;
459 __u32 rsvd12[4];
460};
461
462struct nvme_create_sq {
463 __u8 opcode;
464 __u8 flags;
465 __u16 command_id;
466 __u32 rsvd1[5];
467 __le64 prp1;
468 __u64 rsvd8;
469 __le16 sqid;
470 __le16 qsize;
471 __le16 sq_flags;
472 __le16 cqid;
473 __u32 rsvd12[4];
474};
475
476struct nvme_delete_queue {
477 __u8 opcode;
478 __u8 flags;
479 __u16 command_id;
480 __u32 rsvd1[9];
481 __le16 qid;
482 __u16 rsvd10;
483 __u32 rsvd11[5];
484};
485
486struct nvme_abort_cmd {
487 __u8 opcode;
488 __u8 flags;
489 __u16 command_id;
490 __u32 rsvd1[9];
491 __le16 sqid;
492 __u16 cid;
493 __u32 rsvd11[5];
494};
495
496struct nvme_download_firmware {
497 __u8 opcode;
498 __u8 flags;
499 __u16 command_id;
500 __u32 rsvd1[5];
501 __le64 prp1;
502 __le64 prp2;
503 __le32 numd;
504 __le32 offset;
505 __u32 rsvd12[4];
506};
507
508struct nvme_format_cmd {
509 __u8 opcode;
510 __u8 flags;
511 __u16 command_id;
512 __le32 nsid;
513 __u64 rsvd2[4];
514 __le32 cdw10;
515 __u32 rsvd11[5];
516};
517
518struct nvme_command {
519 union {
520 struct nvme_common_command common;
521 struct nvme_rw_command rw;
522 struct nvme_identify identify;
523 struct nvme_features features;
524 struct nvme_create_cq create_cq;
525 struct nvme_create_sq create_sq;
526 struct nvme_delete_queue delete_queue;
527 struct nvme_download_firmware dlfw;
528 struct nvme_format_cmd format;
529 struct nvme_dsm_cmd dsm;
530 struct nvme_abort_cmd abort;
531 };
532};
533
534enum {
535 NVME_SC_SUCCESS = 0x0,
536 NVME_SC_INVALID_OPCODE = 0x1,
537 NVME_SC_INVALID_FIELD = 0x2,
538 NVME_SC_CMDID_CONFLICT = 0x3,
539 NVME_SC_DATA_XFER_ERROR = 0x4,
540 NVME_SC_POWER_LOSS = 0x5,
541 NVME_SC_INTERNAL = 0x6,
542 NVME_SC_ABORT_REQ = 0x7,
543 NVME_SC_ABORT_QUEUE = 0x8,
544 NVME_SC_FUSED_FAIL = 0x9,
545 NVME_SC_FUSED_MISSING = 0xa,
546 NVME_SC_INVALID_NS = 0xb,
547 NVME_SC_CMD_SEQ_ERROR = 0xc,
548 NVME_SC_SGL_INVALID_LAST = 0xd,
549 NVME_SC_SGL_INVALID_COUNT = 0xe,
550 NVME_SC_SGL_INVALID_DATA = 0xf,
551 NVME_SC_SGL_INVALID_METADATA = 0x10,
552 NVME_SC_SGL_INVALID_TYPE = 0x11,
553 NVME_SC_LBA_RANGE = 0x80,
554 NVME_SC_CAP_EXCEEDED = 0x81,
555 NVME_SC_NS_NOT_READY = 0x82,
556 NVME_SC_RESERVATION_CONFLICT = 0x83,
557 NVME_SC_CQ_INVALID = 0x100,
558 NVME_SC_QID_INVALID = 0x101,
559 NVME_SC_QUEUE_SIZE = 0x102,
560 NVME_SC_ABORT_LIMIT = 0x103,
561 NVME_SC_ABORT_MISSING = 0x104,
562 NVME_SC_ASYNC_LIMIT = 0x105,
563 NVME_SC_FIRMWARE_SLOT = 0x106,
564 NVME_SC_FIRMWARE_IMAGE = 0x107,
565 NVME_SC_INVALID_VECTOR = 0x108,
566 NVME_SC_INVALID_LOG_PAGE = 0x109,
567 NVME_SC_INVALID_FORMAT = 0x10a,
568 NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b,
569 NVME_SC_INVALID_QUEUE = 0x10c,
570 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
571 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
572 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
573 NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110,
574 NVME_SC_BAD_ATTRIBUTES = 0x180,
575 NVME_SC_INVALID_PI = 0x181,
576 NVME_SC_READ_ONLY = 0x182,
577 NVME_SC_WRITE_FAULT = 0x280,
578 NVME_SC_READ_ERROR = 0x281,
579 NVME_SC_GUARD_CHECK = 0x282,
580 NVME_SC_APPTAG_CHECK = 0x283,
581 NVME_SC_REFTAG_CHECK = 0x284,
582 NVME_SC_COMPARE_FAILED = 0x285,
583 NVME_SC_ACCESS_DENIED = 0x286,
584 NVME_SC_DNR = 0x4000,
585};
586
587struct nvme_completion {
588 __le32 result; /* Used by admin commands to return data */
589 __u32 rsvd;
590 __le16 sq_head; /* how much of this queue may be reclaimed */
591 __le16 sq_id; /* submission queue that generated this entry */
592 __u16 command_id; /* of the command which completed */
593 __le16 status; /* did the command fail, and if so, why? */
594};
595
596#define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
597
76#endif /* _LINUX_NVME_H */ 598#endif /* _LINUX_NVME_H */
diff --git a/include/uapi/linux/nvme.h b/include/uapi/linux/nvme.h
deleted file mode 100644
index 8864194a4151..000000000000
--- a/include/uapi/linux/nvme.h
+++ /dev/null
@@ -1,589 +0,0 @@
1/*
2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _UAPI_LINUX_NVME_H
16#define _UAPI_LINUX_NVME_H
17
18#include <linux/types.h>
19
20struct nvme_id_power_state {
21 __le16 max_power; /* centiwatts */
22 __u8 rsvd2;
23 __u8 flags;
24 __le32 entry_lat; /* microseconds */
25 __le32 exit_lat; /* microseconds */
26 __u8 read_tput;
27 __u8 read_lat;
28 __u8 write_tput;
29 __u8 write_lat;
30 __le16 idle_power;
31 __u8 idle_scale;
32 __u8 rsvd19;
33 __le16 active_power;
34 __u8 active_work_scale;
35 __u8 rsvd23[9];
36};
37
38enum {
39 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
40 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
41};
42
43struct nvme_id_ctrl {
44 __le16 vid;
45 __le16 ssvid;
46 char sn[20];
47 char mn[40];
48 char fr[8];
49 __u8 rab;
50 __u8 ieee[3];
51 __u8 mic;
52 __u8 mdts;
53 __u16 cntlid;
54 __u32 ver;
55 __u8 rsvd84[172];
56 __le16 oacs;
57 __u8 acl;
58 __u8 aerl;
59 __u8 frmw;
60 __u8 lpa;
61 __u8 elpe;
62 __u8 npss;
63 __u8 avscc;
64 __u8 apsta;
65 __le16 wctemp;
66 __le16 cctemp;
67 __u8 rsvd270[242];
68 __u8 sqes;
69 __u8 cqes;
70 __u8 rsvd514[2];
71 __le32 nn;
72 __le16 oncs;
73 __le16 fuses;
74 __u8 fna;
75 __u8 vwc;
76 __le16 awun;
77 __le16 awupf;
78 __u8 nvscc;
79 __u8 rsvd531;
80 __le16 acwu;
81 __u8 rsvd534[2];
82 __le32 sgls;
83 __u8 rsvd540[1508];
84 struct nvme_id_power_state psd[32];
85 __u8 vs[1024];
86};
87
88enum {
89 NVME_CTRL_ONCS_COMPARE = 1 << 0,
90 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
91 NVME_CTRL_ONCS_DSM = 1 << 2,
92 NVME_CTRL_VWC_PRESENT = 1 << 0,
93};
94
95struct nvme_lbaf {
96 __le16 ms;
97 __u8 ds;
98 __u8 rp;
99};
100
101struct nvme_id_ns {
102 __le64 nsze;
103 __le64 ncap;
104 __le64 nuse;
105 __u8 nsfeat;
106 __u8 nlbaf;
107 __u8 flbas;
108 __u8 mc;
109 __u8 dpc;
110 __u8 dps;
111 __u8 nmic;
112 __u8 rescap;
113 __u8 fpi;
114 __u8 rsvd33;
115 __le16 nawun;
116 __le16 nawupf;
117 __le16 nacwu;
118 __le16 nabsn;
119 __le16 nabo;
120 __le16 nabspf;
121 __u16 rsvd46;
122 __le64 nvmcap[2];
123 __u8 rsvd64[40];
124 __u8 nguid[16];
125 __u8 eui64[8];
126 struct nvme_lbaf lbaf[16];
127 __u8 rsvd192[192];
128 __u8 vs[3712];
129};
130
131enum {
132 NVME_NS_FEAT_THIN = 1 << 0,
133 NVME_NS_FLBAS_LBA_MASK = 0xf,
134 NVME_NS_FLBAS_META_EXT = 0x10,
135 NVME_LBAF_RP_BEST = 0,
136 NVME_LBAF_RP_BETTER = 1,
137 NVME_LBAF_RP_GOOD = 2,
138 NVME_LBAF_RP_DEGRADED = 3,
139 NVME_NS_DPC_PI_LAST = 1 << 4,
140 NVME_NS_DPC_PI_FIRST = 1 << 3,
141 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
142 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
143 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
144 NVME_NS_DPS_PI_FIRST = 1 << 3,
145 NVME_NS_DPS_PI_MASK = 0x7,
146 NVME_NS_DPS_PI_TYPE1 = 1,
147 NVME_NS_DPS_PI_TYPE2 = 2,
148 NVME_NS_DPS_PI_TYPE3 = 3,
149};
150
151struct nvme_smart_log {
152 __u8 critical_warning;
153 __u8 temperature[2];
154 __u8 avail_spare;
155 __u8 spare_thresh;
156 __u8 percent_used;
157 __u8 rsvd6[26];
158 __u8 data_units_read[16];
159 __u8 data_units_written[16];
160 __u8 host_reads[16];
161 __u8 host_writes[16];
162 __u8 ctrl_busy_time[16];
163 __u8 power_cycles[16];
164 __u8 power_on_hours[16];
165 __u8 unsafe_shutdowns[16];
166 __u8 media_errors[16];
167 __u8 num_err_log_entries[16];
168 __le32 warning_temp_time;
169 __le32 critical_comp_time;
170 __le16 temp_sensor[8];
171 __u8 rsvd216[296];
172};
173
174enum {
175 NVME_SMART_CRIT_SPARE = 1 << 0,
176 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
177 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
178 NVME_SMART_CRIT_MEDIA = 1 << 3,
179 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
180};
181
182enum {
183 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
184};
185
186struct nvme_lba_range_type {
187 __u8 type;
188 __u8 attributes;
189 __u8 rsvd2[14];
190 __u64 slba;
191 __u64 nlb;
192 __u8 guid[16];
193 __u8 rsvd48[16];
194};
195
196enum {
197 NVME_LBART_TYPE_FS = 0x01,
198 NVME_LBART_TYPE_RAID = 0x02,
199 NVME_LBART_TYPE_CACHE = 0x03,
200 NVME_LBART_TYPE_SWAP = 0x04,
201
202 NVME_LBART_ATTRIB_TEMP = 1 << 0,
203 NVME_LBART_ATTRIB_HIDE = 1 << 1,
204};
205
206struct nvme_reservation_status {
207 __le32 gen;
208 __u8 rtype;
209 __u8 regctl[2];
210 __u8 resv5[2];
211 __u8 ptpls;
212 __u8 resv10[13];
213 struct {
214 __le16 cntlid;
215 __u8 rcsts;
216 __u8 resv3[5];
217 __le64 hostid;
218 __le64 rkey;
219 } regctl_ds[];
220};
221
222/* I/O commands */
223
224enum nvme_opcode {
225 nvme_cmd_flush = 0x00,
226 nvme_cmd_write = 0x01,
227 nvme_cmd_read = 0x02,
228 nvme_cmd_write_uncor = 0x04,
229 nvme_cmd_compare = 0x05,
230 nvme_cmd_write_zeroes = 0x08,
231 nvme_cmd_dsm = 0x09,
232 nvme_cmd_resv_register = 0x0d,
233 nvme_cmd_resv_report = 0x0e,
234 nvme_cmd_resv_acquire = 0x11,
235 nvme_cmd_resv_release = 0x15,
236};
237
238struct nvme_common_command {
239 __u8 opcode;
240 __u8 flags;
241 __u16 command_id;
242 __le32 nsid;
243 __le32 cdw2[2];
244 __le64 metadata;
245 __le64 prp1;
246 __le64 prp2;
247 __le32 cdw10[6];
248};
249
250struct nvme_rw_command {
251 __u8 opcode;
252 __u8 flags;
253 __u16 command_id;
254 __le32 nsid;
255 __u64 rsvd2;
256 __le64 metadata;
257 __le64 prp1;
258 __le64 prp2;
259 __le64 slba;
260 __le16 length;
261 __le16 control;
262 __le32 dsmgmt;
263 __le32 reftag;
264 __le16 apptag;
265 __le16 appmask;
266};
267
268enum {
269 NVME_RW_LR = 1 << 15,
270 NVME_RW_FUA = 1 << 14,
271 NVME_RW_DSM_FREQ_UNSPEC = 0,
272 NVME_RW_DSM_FREQ_TYPICAL = 1,
273 NVME_RW_DSM_FREQ_RARE = 2,
274 NVME_RW_DSM_FREQ_READS = 3,
275 NVME_RW_DSM_FREQ_WRITES = 4,
276 NVME_RW_DSM_FREQ_RW = 5,
277 NVME_RW_DSM_FREQ_ONCE = 6,
278 NVME_RW_DSM_FREQ_PREFETCH = 7,
279 NVME_RW_DSM_FREQ_TEMP = 8,
280 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
281 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
282 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
283 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
284 NVME_RW_DSM_SEQ_REQ = 1 << 6,
285 NVME_RW_DSM_COMPRESSED = 1 << 7,
286 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
287 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
288 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
289 NVME_RW_PRINFO_PRACT = 1 << 13,
290};
291
292struct nvme_dsm_cmd {
293 __u8 opcode;
294 __u8 flags;
295 __u16 command_id;
296 __le32 nsid;
297 __u64 rsvd2[2];
298 __le64 prp1;
299 __le64 prp2;
300 __le32 nr;
301 __le32 attributes;
302 __u32 rsvd12[4];
303};
304
305enum {
306 NVME_DSMGMT_IDR = 1 << 0,
307 NVME_DSMGMT_IDW = 1 << 1,
308 NVME_DSMGMT_AD = 1 << 2,
309};
310
311struct nvme_dsm_range {
312 __le32 cattr;
313 __le32 nlb;
314 __le64 slba;
315};
316
317/* Admin commands */
318
319enum nvme_admin_opcode {
320 nvme_admin_delete_sq = 0x00,
321 nvme_admin_create_sq = 0x01,
322 nvme_admin_get_log_page = 0x02,
323 nvme_admin_delete_cq = 0x04,
324 nvme_admin_create_cq = 0x05,
325 nvme_admin_identify = 0x06,
326 nvme_admin_abort_cmd = 0x08,
327 nvme_admin_set_features = 0x09,
328 nvme_admin_get_features = 0x0a,
329 nvme_admin_async_event = 0x0c,
330 nvme_admin_activate_fw = 0x10,
331 nvme_admin_download_fw = 0x11,
332 nvme_admin_format_nvm = 0x80,
333 nvme_admin_security_send = 0x81,
334 nvme_admin_security_recv = 0x82,
335};
336
337enum {
338 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
339 NVME_CQ_IRQ_ENABLED = (1 << 1),
340 NVME_SQ_PRIO_URGENT = (0 << 1),
341 NVME_SQ_PRIO_HIGH = (1 << 1),
342 NVME_SQ_PRIO_MEDIUM = (2 << 1),
343 NVME_SQ_PRIO_LOW = (3 << 1),
344 NVME_FEAT_ARBITRATION = 0x01,
345 NVME_FEAT_POWER_MGMT = 0x02,
346 NVME_FEAT_LBA_RANGE = 0x03,
347 NVME_FEAT_TEMP_THRESH = 0x04,
348 NVME_FEAT_ERR_RECOVERY = 0x05,
349 NVME_FEAT_VOLATILE_WC = 0x06,
350 NVME_FEAT_NUM_QUEUES = 0x07,
351 NVME_FEAT_IRQ_COALESCE = 0x08,
352 NVME_FEAT_IRQ_CONFIG = 0x09,
353 NVME_FEAT_WRITE_ATOMIC = 0x0a,
354 NVME_FEAT_ASYNC_EVENT = 0x0b,
355 NVME_FEAT_AUTO_PST = 0x0c,
356 NVME_FEAT_SW_PROGRESS = 0x80,
357 NVME_FEAT_HOST_ID = 0x81,
358 NVME_FEAT_RESV_MASK = 0x82,
359 NVME_FEAT_RESV_PERSIST = 0x83,
360 NVME_LOG_ERROR = 0x01,
361 NVME_LOG_SMART = 0x02,
362 NVME_LOG_FW_SLOT = 0x03,
363 NVME_LOG_RESERVATION = 0x80,
364 NVME_FWACT_REPL = (0 << 3),
365 NVME_FWACT_REPL_ACTV = (1 << 3),
366 NVME_FWACT_ACTV = (2 << 3),
367};
368
369struct nvme_identify {
370 __u8 opcode;
371 __u8 flags;
372 __u16 command_id;
373 __le32 nsid;
374 __u64 rsvd2[2];
375 __le64 prp1;
376 __le64 prp2;
377 __le32 cns;
378 __u32 rsvd11[5];
379};
380
381struct nvme_features {
382 __u8 opcode;
383 __u8 flags;
384 __u16 command_id;
385 __le32 nsid;
386 __u64 rsvd2[2];
387 __le64 prp1;
388 __le64 prp2;
389 __le32 fid;
390 __le32 dword11;
391 __u32 rsvd12[4];
392};
393
394struct nvme_create_cq {
395 __u8 opcode;
396 __u8 flags;
397 __u16 command_id;
398 __u32 rsvd1[5];
399 __le64 prp1;
400 __u64 rsvd8;
401 __le16 cqid;
402 __le16 qsize;
403 __le16 cq_flags;
404 __le16 irq_vector;
405 __u32 rsvd12[4];
406};
407
408struct nvme_create_sq {
409 __u8 opcode;
410 __u8 flags;
411 __u16 command_id;
412 __u32 rsvd1[5];
413 __le64 prp1;
414 __u64 rsvd8;
415 __le16 sqid;
416 __le16 qsize;
417 __le16 sq_flags;
418 __le16 cqid;
419 __u32 rsvd12[4];
420};
421
422struct nvme_delete_queue {
423 __u8 opcode;
424 __u8 flags;
425 __u16 command_id;
426 __u32 rsvd1[9];
427 __le16 qid;
428 __u16 rsvd10;
429 __u32 rsvd11[5];
430};
431
432struct nvme_abort_cmd {
433 __u8 opcode;
434 __u8 flags;
435 __u16 command_id;
436 __u32 rsvd1[9];
437 __le16 sqid;
438 __u16 cid;
439 __u32 rsvd11[5];
440};
441
442struct nvme_download_firmware {
443 __u8 opcode;
444 __u8 flags;
445 __u16 command_id;
446 __u32 rsvd1[5];
447 __le64 prp1;
448 __le64 prp2;
449 __le32 numd;
450 __le32 offset;
451 __u32 rsvd12[4];
452};
453
454struct nvme_format_cmd {
455 __u8 opcode;
456 __u8 flags;
457 __u16 command_id;
458 __le32 nsid;
459 __u64 rsvd2[4];
460 __le32 cdw10;
461 __u32 rsvd11[5];
462};
463
464struct nvme_command {
465 union {
466 struct nvme_common_command common;
467 struct nvme_rw_command rw;
468 struct nvme_identify identify;
469 struct nvme_features features;
470 struct nvme_create_cq create_cq;
471 struct nvme_create_sq create_sq;
472 struct nvme_delete_queue delete_queue;
473 struct nvme_download_firmware dlfw;
474 struct nvme_format_cmd format;
475 struct nvme_dsm_cmd dsm;
476 struct nvme_abort_cmd abort;
477 };
478};
479
480enum {
481 NVME_SC_SUCCESS = 0x0,
482 NVME_SC_INVALID_OPCODE = 0x1,
483 NVME_SC_INVALID_FIELD = 0x2,
484 NVME_SC_CMDID_CONFLICT = 0x3,
485 NVME_SC_DATA_XFER_ERROR = 0x4,
486 NVME_SC_POWER_LOSS = 0x5,
487 NVME_SC_INTERNAL = 0x6,
488 NVME_SC_ABORT_REQ = 0x7,
489 NVME_SC_ABORT_QUEUE = 0x8,
490 NVME_SC_FUSED_FAIL = 0x9,
491 NVME_SC_FUSED_MISSING = 0xa,
492 NVME_SC_INVALID_NS = 0xb,
493 NVME_SC_CMD_SEQ_ERROR = 0xc,
494 NVME_SC_SGL_INVALID_LAST = 0xd,
495 NVME_SC_SGL_INVALID_COUNT = 0xe,
496 NVME_SC_SGL_INVALID_DATA = 0xf,
497 NVME_SC_SGL_INVALID_METADATA = 0x10,
498 NVME_SC_SGL_INVALID_TYPE = 0x11,
499 NVME_SC_LBA_RANGE = 0x80,
500 NVME_SC_CAP_EXCEEDED = 0x81,
501 NVME_SC_NS_NOT_READY = 0x82,
502 NVME_SC_RESERVATION_CONFLICT = 0x83,
503 NVME_SC_CQ_INVALID = 0x100,
504 NVME_SC_QID_INVALID = 0x101,
505 NVME_SC_QUEUE_SIZE = 0x102,
506 NVME_SC_ABORT_LIMIT = 0x103,
507 NVME_SC_ABORT_MISSING = 0x104,
508 NVME_SC_ASYNC_LIMIT = 0x105,
509 NVME_SC_FIRMWARE_SLOT = 0x106,
510 NVME_SC_FIRMWARE_IMAGE = 0x107,
511 NVME_SC_INVALID_VECTOR = 0x108,
512 NVME_SC_INVALID_LOG_PAGE = 0x109,
513 NVME_SC_INVALID_FORMAT = 0x10a,
514 NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b,
515 NVME_SC_INVALID_QUEUE = 0x10c,
516 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
517 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
518 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
519 NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110,
520 NVME_SC_BAD_ATTRIBUTES = 0x180,
521 NVME_SC_INVALID_PI = 0x181,
522 NVME_SC_READ_ONLY = 0x182,
523 NVME_SC_WRITE_FAULT = 0x280,
524 NVME_SC_READ_ERROR = 0x281,
525 NVME_SC_GUARD_CHECK = 0x282,
526 NVME_SC_APPTAG_CHECK = 0x283,
527 NVME_SC_REFTAG_CHECK = 0x284,
528 NVME_SC_COMPARE_FAILED = 0x285,
529 NVME_SC_ACCESS_DENIED = 0x286,
530 NVME_SC_DNR = 0x4000,
531};
532
533struct nvme_completion {
534 __le32 result; /* Used by admin commands to return data */
535 __u32 rsvd;
536 __le16 sq_head; /* how much of this queue may be reclaimed */
537 __le16 sq_id; /* submission queue that generated this entry */
538 __u16 command_id; /* of the command which completed */
539 __le16 status; /* did the command fail, and if so, why? */
540};
541
542struct nvme_user_io {
543 __u8 opcode;
544 __u8 flags;
545 __u16 control;
546 __u16 nblocks;
547 __u16 rsvd;
548 __u64 metadata;
549 __u64 addr;
550 __u64 slba;
551 __u32 dsmgmt;
552 __u32 reftag;
553 __u16 apptag;
554 __u16 appmask;
555};
556
557struct nvme_passthru_cmd {
558 __u8 opcode;
559 __u8 flags;
560 __u16 rsvd1;
561 __u32 nsid;
562 __u32 cdw2;
563 __u32 cdw3;
564 __u64 metadata;
565 __u64 addr;
566 __u32 metadata_len;
567 __u32 data_len;
568 __u32 cdw10;
569 __u32 cdw11;
570 __u32 cdw12;
571 __u32 cdw13;
572 __u32 cdw14;
573 __u32 cdw15;
574 __u32 timeout_ms;
575 __u32 result;
576};
577
578#define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
579
580#define nvme_admin_cmd nvme_passthru_cmd
581
582#define NVME_IOCTL_ID _IO('N', 0x40)
583#define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
584#define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
585#define NVME_IOCTL_IO_CMD _IOWR('N', 0x43, struct nvme_passthru_cmd)
586#define NVME_IOCTL_RESET _IO('N', 0x44)
587#define NVME_IOCTL_SUBSYS_RESET _IO('N', 0x45)
588
589#endif /* _UAPI_LINUX_NVME_H */
diff --git a/include/uapi/linux/nvme_ioctl.h b/include/uapi/linux/nvme_ioctl.h
new file mode 100644
index 000000000000..c4b2a3f90829
--- /dev/null
+++ b/include/uapi/linux/nvme_ioctl.h
@@ -0,0 +1,65 @@
1/*
2 * Definitions for the NVM Express ioctl interface
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _UAPI_LINUX_NVME_IOCTL_H
16#define _UAPI_LINUX_NVME_IOCTL_H
17
18#include <linux/types.h>
19
20struct nvme_user_io {
21 __u8 opcode;
22 __u8 flags;
23 __u16 control;
24 __u16 nblocks;
25 __u16 rsvd;
26 __u64 metadata;
27 __u64 addr;
28 __u64 slba;
29 __u32 dsmgmt;
30 __u32 reftag;
31 __u16 apptag;
32 __u16 appmask;
33};
34
35struct nvme_passthru_cmd {
36 __u8 opcode;
37 __u8 flags;
38 __u16 rsvd1;
39 __u32 nsid;
40 __u32 cdw2;
41 __u32 cdw3;
42 __u64 metadata;
43 __u64 addr;
44 __u32 metadata_len;
45 __u32 data_len;
46 __u32 cdw10;
47 __u32 cdw11;
48 __u32 cdw12;
49 __u32 cdw13;
50 __u32 cdw14;
51 __u32 cdw15;
52 __u32 timeout_ms;
53 __u32 result;
54};
55
56#define nvme_admin_cmd nvme_passthru_cmd
57
58#define NVME_IOCTL_ID _IO('N', 0x40)
59#define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
60#define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
61#define NVME_IOCTL_IO_CMD _IOWR('N', 0x43, struct nvme_passthru_cmd)
62#define NVME_IOCTL_RESET _IO('N', 0x44)
63#define NVME_IOCTL_SUBSYS_RESET _IO('N', 0x45)
64
65#endif /* _UAPI_LINUX_NVME_IOCTL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 18:03:44 -0400