perf/x86: Fix incorrect PEBS_REGS

PEBS_REGS used as mask for the supported registers for large PEBS.
However, the mask cannot filter the sample_regs_user/sample_regs_intr
correctly.

(1ULL << PERF_REG_X86_*) should be used to replace PERF_REG_X86_*, which
is only the index.

Rename PEBS_REGS to PEBS_GP_REGS, because the mask is only for general
purpose registers.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: <stable@vger.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: acme@kernel.org
Cc: jolsa@kernel.org
Fixes: 2fe1bc1f501d ("perf/x86: Enable free running PEBS for REGS_USER/INTR")
Link: https://lkml.kernel.org/r/20190402194509.2832-2-kan.liang@linux.intel.com
[ Renamed it to PEBS_GP_REGS - as 'GPRS' is used elsewhere ;-) ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>

2 files changed, 20 insertions, 20 deletions

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index f61dcbef20ff..f9451566cd9b 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3131,7 +3131,7 @@ static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
                 flags &= ~PERF_SAMPLE_TIME;
         if (!event->attr.exclude_kernel)
                 flags &= ~PERF_SAMPLE_REGS_USER;
-        if (event->attr.sample_regs_user & ~PEBS_REGS)
+        if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
                 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
         return flags;
 }
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index a75955741c50..1e98a42b560a 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -96,25 +96,25 @@ struct amd_nb {
         PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
         PERF_SAMPLE_PERIOD)
 
-#define PEBS_REGS \
-        (PERF_REG_X86_AX | \
-         PERF_REG_X86_BX | \
-         PERF_REG_X86_CX | \
-         PERF_REG_X86_DX | \
-         PERF_REG_X86_DI | \
-         PERF_REG_X86_SI | \
-         PERF_REG_X86_SP | \
-         PERF_REG_X86_BP | \
-         PERF_REG_X86_IP | \
-         PERF_REG_X86_FLAGS | \
-         PERF_REG_X86_R8 | \
-         PERF_REG_X86_R9 | \
-         PERF_REG_X86_R10 | \
-         PERF_REG_X86_R11 | \
-         PERF_REG_X86_R12 | \
-         PERF_REG_X86_R13 | \
-         PERF_REG_X86_R14 | \
-         PERF_REG_X86_R15)
+#define PEBS_GP_REGS                    \
+        ((1ULL << PERF_REG_X86_AX)    | \
+         (1ULL << PERF_REG_X86_BX)    | \
+         (1ULL << PERF_REG_X86_CX)    | \
+         (1ULL << PERF_REG_X86_DX)    | \
+         (1ULL << PERF_REG_X86_DI)    | \
+         (1ULL << PERF_REG_X86_SI)    | \
+         (1ULL << PERF_REG_X86_SP)    | \
+         (1ULL << PERF_REG_X86_BP)    | \
+         (1ULL << PERF_REG_X86_IP)    | \
+         (1ULL << PERF_REG_X86_FLAGS) | \
+         (1ULL << PERF_REG_X86_R8)    | \
+         (1ULL << PERF_REG_X86_R9)    | \
+         (1ULL << PERF_REG_X86_R10)   | \
+         (1ULL << PERF_REG_X86_R11)   | \
+         (1ULL << PERF_REG_X86_R12)   | \
+         (1ULL << PERF_REG_X86_R13)   | \
+         (1ULL << PERF_REG_X86_R14)   | \
+         (1ULL << PERF_REG_X86_R15))
 
 /*
  * Per register state.