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authorPing-Ke Shih <pkshih@realtek.com>2017-08-17 13:46:49 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-08-20 14:13:12 -0400
commit9ce99b04b5b82fdf11e4c76b60a5f82c1e541297 (patch)
treed3f297b3ebd84eaf89e5f99124d981b8935a1472
parent938a0447f094233e269f7f5ded474b13f3de8d80 (diff)
staging: r8822be: Add phydm mini driver
The RTL8822BE, an 802.11ac wireless network card, is now appearing in new computers. Its driver is being placed in staging to reduce the time that users of this new card will have access to in-kernel drivers. New Realtek wireless devices have a new method for PHY control and dynamic management. The RTL8822BE is the first of these devices, thus there is additional code required. In the final version, this code will be a separate module; however, it is combined with the r8822be driver to minimize the interference with the drivers in the wireless tree. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: Yan-Hsuan Chuang <yhchuang@realtek.com> Cc: Birming Chiu <birming@realtek.com> Cc: Shaofu <shaofu@realtek.com> Cc: Steven Ting <steventing@realtek.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat
-rw-r--r--drivers/staging/rtlwifi/phydm/halphyrf_ce.c965
-rw-r--r--drivers/staging/rtlwifi/phydm/halphyrf_ce.h85
-rw-r--r--drivers/staging/rtlwifi/phydm/mp_precomp.h24
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm.c1986
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm.h946
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_acs.c200
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_acs.h57
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_adaptivity.c941
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_adaptivity.h119
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_adc_sampling.c628
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_adc_sampling.h96
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_antdiv.c83
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_antdiv.h301
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_beamforming.h48
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_ccx.c457
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_ccx.h83
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_cfotracking.c343
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_cfotracking.h60
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_debug.c2910
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_debug.h175
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_dfs.h59
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_dig.c1535
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_dig.h241
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_dynamic_rx_path.h37
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_dynamicbbpowersaving.c129
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_dynamicbbpowersaving.h50
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_dynamictxpower.c102
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_dynamictxpower.h64
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.c139
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.h44
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_features.h33
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_hwconfig.c1928
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_hwconfig.h510
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_interface.c341
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_interface.h205
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_iqk.h76
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_kfree.c228
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_kfree.h42
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_noisemonitor.c330
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_noisemonitor.h46
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_powertracking_ce.c644
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_powertracking_ce.h293
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_pre_define.h613
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_precomp.h85
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_psd.c422
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_psd.h67
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_rainfo.c1208
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_rainfo.h269
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_reg.h151
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_regdefine11ac.h94
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_regdefine11n.h213
-rw-r--r--drivers/staging/rtlwifi/phydm/phydm_types.h130
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_bb.c1969
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_bb.h54
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_mac.c222
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_mac.h38
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_rf.c4744
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_rf.h129
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/halphyrf_8822b.c351
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/halphyrf_8822b.h45
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/phydm_hal_api8822b.c1815
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/phydm_hal_api8822b.h84
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/phydm_iqk_8822b.c1410
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/phydm_iqk_8822b.h48
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/phydm_regconfig8822b.c168
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/phydm_regconfig8822b.h54
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/phydm_rtl8822b.c225
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/phydm_rtl8822b.h30
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl8822b/version_rtl8822b.h34
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl_phydm.c874
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl_phydm.h45
-rw-r--r--drivers/staging/rtlwifi/phydm/txbf/halcomtxbf.h67
-rw-r--r--drivers/staging/rtlwifi/phydm/txbf/haltxbf8822b.h39
-rw-r--r--drivers/staging/rtlwifi/phydm/txbf/haltxbfinterface.h38
-rw-r--r--drivers/staging/rtlwifi/phydm/txbf/haltxbfjaguar.h36
-rw-r--r--drivers/staging/rtlwifi/phydm/txbf/phydm_hal_txbf_api.h41
76 files changed, 33395 insertions, 0 deletions
diff --git a/drivers/staging/rtlwifi/phydm/halphyrf_ce.c b/drivers/staging/rtlwifi/phydm/halphyrf_ce.c
new file mode 100644
index 000000000000..684e383201d6
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/halphyrf_ce.c
@@ -0,0 +1,965 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "mp_precomp.h"
27#include "phydm_precomp.h"
28
29#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, \
30 _delta_thermal) \
31 do { \
32 for (_offset = 0; _offset < _size; _offset++) { \
33 if (_delta_thermal < \
34 thermal_threshold[_direction][_offset]) { \
35 if (_offset != 0) \
36 _offset--; \
37 break; \
38 } \
39 } \
40 if (_offset >= _size) \
41 _offset = _size - 1; \
42 } while (0)
43
44static inline void phydm_set_calibrate_info_up(
45 struct phy_dm_struct *dm, struct txpwrtrack_cfg *c, u8 delta,
46 struct dm_rf_calibration_struct *cali_info,
47 u8 *delta_swing_table_idx_tup_a, u8 *delta_swing_table_idx_tup_b,
48 u8 *delta_swing_table_idx_tup_c, u8 *delta_swing_table_idx_tup_d)
49{
50 u8 p = 0;
51
52 for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++) {
53 cali_info->delta_power_index_last[p] =
54 cali_info->delta_power_index
55 [p]; /*recording poer index offset*/
56 switch (p) {
57 case ODM_RF_PATH_B:
58 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
59 "delta_swing_table_idx_tup_b[%d] = %d\n",
60 delta, delta_swing_table_idx_tup_b[delta]);
61
62 cali_info->delta_power_index[p] =
63 delta_swing_table_idx_tup_b[delta];
64 /*Record delta swing for mix mode pwr tracking*/
65 cali_info->absolute_ofdm_swing_idx[p] =
66 delta_swing_table_idx_tup_b[delta];
67 ODM_RT_TRACE(
68 dm, ODM_COMP_TX_PWR_TRACK,
69 "******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n",
70 cali_info->absolute_ofdm_swing_idx[p]);
71 break;
72
73 case ODM_RF_PATH_C:
74 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
75 "delta_swing_table_idx_tup_c[%d] = %d\n",
76 delta, delta_swing_table_idx_tup_c[delta]);
77
78 cali_info->delta_power_index[p] =
79 delta_swing_table_idx_tup_c[delta];
80 /*Record delta swing for mix mode pwr tracking*/
81 cali_info->absolute_ofdm_swing_idx[p] =
82 delta_swing_table_idx_tup_c[delta];
83 ODM_RT_TRACE(
84 dm, ODM_COMP_TX_PWR_TRACK,
85 "******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n",
86 cali_info->absolute_ofdm_swing_idx[p]);
87 break;
88
89 case ODM_RF_PATH_D:
90 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
91 "delta_swing_table_idx_tup_d[%d] = %d\n",
92 delta, delta_swing_table_idx_tup_d[delta]);
93
94 cali_info->delta_power_index[p] =
95 delta_swing_table_idx_tup_d[delta];
96 /*Record delta swing for mix mode pwr tracking*/
97 cali_info->absolute_ofdm_swing_idx[p] =
98 delta_swing_table_idx_tup_d[delta];
99 ODM_RT_TRACE(
100 dm, ODM_COMP_TX_PWR_TRACK,
101 "******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n",
102 cali_info->absolute_ofdm_swing_idx[p]);
103 break;
104
105 default:
106 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
107 "delta_swing_table_idx_tup_a[%d] = %d\n",
108 delta, delta_swing_table_idx_tup_a[delta]);
109
110 cali_info->delta_power_index[p] =
111 delta_swing_table_idx_tup_a[delta];
112 /*Record delta swing for mix mode pwr tracking*/
113 cali_info->absolute_ofdm_swing_idx[p] =
114 delta_swing_table_idx_tup_a[delta];
115 ODM_RT_TRACE(
116 dm, ODM_COMP_TX_PWR_TRACK,
117 "******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n",
118 cali_info->absolute_ofdm_swing_idx[p]);
119 break;
120 }
121 }
122}
123
124static inline void phydm_set_calibrate_info_down(
125 struct phy_dm_struct *dm, struct txpwrtrack_cfg *c, u8 delta,
126 struct dm_rf_calibration_struct *cali_info,
127 u8 *delta_swing_table_idx_tdown_a, u8 *delta_swing_table_idx_tdown_b,
128 u8 *delta_swing_table_idx_tdown_c, u8 *delta_swing_table_idx_tdown_d)
129{
130 u8 p = 0;
131
132 for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++) {
133 cali_info->delta_power_index_last[p] =
134 cali_info->delta_power_index
135 [p]; /*recording poer index offset*/
136
137 switch (p) {
138 case ODM_RF_PATH_B:
139 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
140 "delta_swing_table_idx_tdown_b[%d] = %d\n",
141 delta,
142 delta_swing_table_idx_tdown_b[delta]);
143 cali_info->delta_power_index[p] =
144 -1 * delta_swing_table_idx_tdown_b[delta];
145 /*Record delta swing for mix mode pwr tracking*/
146 cali_info->absolute_ofdm_swing_idx[p] =
147 -1 * delta_swing_table_idx_tdown_b[delta];
148 ODM_RT_TRACE(
149 dm, ODM_COMP_TX_PWR_TRACK,
150 "******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n",
151 cali_info->absolute_ofdm_swing_idx[p]);
152 break;
153
154 case ODM_RF_PATH_C:
155 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
156 "delta_swing_table_idx_tdown_c[%d] = %d\n",
157 delta,
158 delta_swing_table_idx_tdown_c[delta]);
159 cali_info->delta_power_index[p] =
160 -1 * delta_swing_table_idx_tdown_c[delta];
161 /*Record delta swing for mix mode pwr tracking*/
162 cali_info->absolute_ofdm_swing_idx[p] =
163 -1 * delta_swing_table_idx_tdown_c[delta];
164 ODM_RT_TRACE(
165 dm, ODM_COMP_TX_PWR_TRACK,
166 "******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n",
167 cali_info->absolute_ofdm_swing_idx[p]);
168 break;
169
170 case ODM_RF_PATH_D:
171 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
172 "delta_swing_table_idx_tdown_d[%d] = %d\n",
173 delta,
174 delta_swing_table_idx_tdown_d[delta]);
175 cali_info->delta_power_index[p] =
176 -1 * delta_swing_table_idx_tdown_d[delta];
177 /*Record delta swing for mix mode pwr tracking*/
178 cali_info->absolute_ofdm_swing_idx[p] =
179 -1 * delta_swing_table_idx_tdown_d[delta];
180 ODM_RT_TRACE(
181 dm, ODM_COMP_TX_PWR_TRACK,
182 "******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n",
183 cali_info->absolute_ofdm_swing_idx[p]);
184 break;
185
186 default:
187 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
188 "delta_swing_table_idx_tdown_a[%d] = %d\n",
189 delta,
190 delta_swing_table_idx_tdown_a[delta]);
191 cali_info->delta_power_index[p] =
192 -1 * delta_swing_table_idx_tdown_a[delta];
193 /*Record delta swing for mix mode pwr tracking*/
194 cali_info->absolute_ofdm_swing_idx[p] =
195 -1 * delta_swing_table_idx_tdown_a[delta];
196 ODM_RT_TRACE(
197 dm, ODM_COMP_TX_PWR_TRACK,
198 "******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n",
199 cali_info->absolute_ofdm_swing_idx[p]);
200 break;
201 }
202 }
203}
204
205static inline void phydm_odm_tx_power_set(struct phy_dm_struct *dm,
206 struct txpwrtrack_cfg *c,
207 u8 indexforchannel, u8 flag)
208{
209 u8 p = 0;
210
211 if (dm->support_ic_type == ODM_RTL8188E ||
212 dm->support_ic_type == ODM_RTL8192E ||
213 dm->support_ic_type == ODM_RTL8821 ||
214 dm->support_ic_type == ODM_RTL8812 ||
215 dm->support_ic_type == ODM_RTL8723B ||
216 dm->support_ic_type == ODM_RTL8814A ||
217 dm->support_ic_type == ODM_RTL8703B ||
218 dm->support_ic_type == ODM_RTL8188F ||
219 dm->support_ic_type == ODM_RTL8822B ||
220 dm->support_ic_type == ODM_RTL8723D ||
221 dm->support_ic_type == ODM_RTL8821C ||
222 dm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */
223
224 ODM_RT_TRACE(
225 dm, ODM_COMP_TX_PWR_TRACK,
226 "**********Enter POWER Tracking MIX_MODE**********\n");
227 for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++) {
228 if (flag == 0)
229 (*c->odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
230 0);
231 else
232 (*c->odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
233 indexforchannel);
234 }
235 } else {
236 ODM_RT_TRACE(
237 dm, ODM_COMP_TX_PWR_TRACK,
238 "**********Enter POWER Tracking BBSWING_MODE**********\n");
239 for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++)
240 (*c->odm_tx_pwr_track_set_pwr)(dm, BBSWING, p,
241 indexforchannel);
242 }
243}
244
245void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config)
246{
247 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
248
249 /* JJ ADD 20161014 */
250
251 if (dm->support_ic_type == ODM_RTL8822B)
252 configure_txpower_track_8822b(config);
253}
254
255/* **********************************************************************
256 * <20121113, Kordan> This function should be called when tx_agc changed.
257 * Otherwise the previous compensation is gone, because we record the
258 * delta of temperature between two TxPowerTracking watch dogs.
259 *
260 * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
261 * need to call this function.
262 * ***********************************************************************/
263void odm_clear_txpowertracking_state(void *dm_void)
264{
265 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
266 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
267 struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
268 u8 p = 0;
269 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
270
271 cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
272 cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
273 dm->rf_calibrate_info.CCK_index = 0;
274
275 for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
276 cali_info->bb_swing_idx_ofdm_base[p] =
277 cali_info->default_ofdm_index;
278 cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
279 cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
280
281 cali_info->power_index_offset[p] = 0;
282 cali_info->delta_power_index[p] = 0;
283 cali_info->delta_power_index_last[p] = 0;
284
285 cali_info->absolute_ofdm_swing_idx[p] =
286 0; /* Initial Mix mode power tracking*/
287 cali_info->remnant_ofdm_swing_idx[p] = 0;
288 cali_info->kfree_offset[p] = 0;
289 }
290
291 cali_info->modify_tx_agc_flag_path_a =
292 false; /*Initial at Modify Tx Scaling mode*/
293 cali_info->modify_tx_agc_flag_path_b =
294 false; /*Initial at Modify Tx Scaling mode*/
295 cali_info->modify_tx_agc_flag_path_c =
296 false; /*Initial at Modify Tx Scaling mode*/
297 cali_info->modify_tx_agc_flag_path_d =
298 false; /*Initial at Modify Tx Scaling mode*/
299 cali_info->remnant_cck_swing_idx = 0;
300 cali_info->thermal_value = rtlefu->eeprom_thermalmeter;
301
302 cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
303 cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
304}
305
306void odm_txpowertracking_callback_thermal_meter(void *dm_void)
307{
308 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
309 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
310 struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
311 void *adapter = dm->adapter;
312
313 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
314
315 u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
316 s8 diff_DPK[4]; /* use 'for..loop' to initialize */
317 u8 thermal_value_avg_count = 0;
318 u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
319
320 /* OFDM BB Swing should be less than +3.0dB (required by Arthur) */
321 u8 OFDM_min_index = 0;
322 /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
323 u8 indexforchannel = 0;
324 u8 power_tracking_type = 0; /* no specify type */
325 u8 xtal_offset_eanble = 0;
326
327 struct txpwrtrack_cfg c;
328
329 /* 4 1. The following TWO tables decide the final index of
330 * OFDM/CCK swing table.
331 */
332 u8 *delta_swing_table_idx_tup_a = NULL;
333 u8 *delta_swing_table_idx_tdown_a = NULL;
334 u8 *delta_swing_table_idx_tup_b = NULL;
335 u8 *delta_swing_table_idx_tdown_b = NULL;
336 /*for 8814 add by Yu Chen*/
337 u8 *delta_swing_table_idx_tup_c = NULL;
338 u8 *delta_swing_table_idx_tdown_c = NULL;
339 u8 *delta_swing_table_idx_tup_d = NULL;
340 u8 *delta_swing_table_idx_tdown_d = NULL;
341 /*for Xtal Offset by James.Tung*/
342 s8 *delta_swing_table_xtal_up = NULL;
343 s8 *delta_swing_table_xtal_down = NULL;
344
345 /* 4 2. Initialization ( 7 steps in total ) */
346
347 configure_txpower_track(dm, &c);
348
349 (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a,
350 (u8 **)&delta_swing_table_idx_tdown_a,
351 (u8 **)&delta_swing_table_idx_tup_b,
352 (u8 **)&delta_swing_table_idx_tdown_b);
353
354 if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
355 (*c.get_delta_swing_table8814only)(
356 dm, (u8 **)&delta_swing_table_idx_tup_c,
357 (u8 **)&delta_swing_table_idx_tdown_c,
358 (u8 **)&delta_swing_table_idx_tup_d,
359 (u8 **)&delta_swing_table_idx_tdown_d);
360 /* JJ ADD 20161014 */
361 if (dm->support_ic_type &
362 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/
363 (*c.get_delta_swing_xtal_table)(
364 dm, (s8 **)&delta_swing_table_xtal_up,
365 (s8 **)&delta_swing_table_xtal_down);
366
367 cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
368 cali_info->is_txpowertracking_init = true;
369
370 /*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
371 *<Kordan> We should keep updating ctrl variable according to HalData.
372 *<Kordan> rf_calibrate_info.rega24 will be initialized when
373 *ODM HW configuring, but MP configures with para files.
374 */
375 if (dm->mp_mode)
376 cali_info->rega24 = 0x090e1317;
377
378 ODM_RT_TRACE(
379 dm, ODM_COMP_TX_PWR_TRACK,
380 "===>%s\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
381 __func__, cali_info->bb_swing_idx_cck_base,
382 cali_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A],
383 cali_info->default_ofdm_index);
384
385 ODM_RT_TRACE(
386 dm, ODM_COMP_TX_PWR_TRACK,
387 "cali_info->txpowertrack_control=%d, rtlefu->eeprom_thermalmeter %d\n",
388 cali_info->txpowertrack_control, rtlefu->eeprom_thermalmeter);
389
390 thermal_value =
391 (u8)odm_get_rf_reg(dm, ODM_RF_PATH_A, c.thermal_reg_addr,
392 0xfc00); /* 0x42: RF Reg[15:10] 88E */
393
394 /*add log by zhao he, check c80/c94/c14/ca0 value*/
395 if (dm->support_ic_type == ODM_RTL8723D) {
396 regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
397 regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
398 regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
399 regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
400 ODM_RT_TRACE(
401 dm, ODM_COMP_CALIBRATION,
402 "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n",
403 regc80, regcd0, regcd4, regab4);
404 }
405 /* JJ ADD 20161014 */
406 if (dm->support_ic_type == ODM_RTL8710B) {
407 regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
408 regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
409 regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
410 regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
411 ODM_RT_TRACE(
412 dm, ODM_COMP_CALIBRATION,
413 "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n",
414 regc80, regcd0, regcd4, regab4);
415 }
416
417 if (!cali_info->txpowertrack_control)
418 return;
419
420 /*4 3. Initialize ThermalValues of rf_calibrate_info*/
421
422 if (cali_info->is_reloadtxpowerindex)
423 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
424 "reload ofdm index for band switch\n");
425
426 /*4 4. Calculate average thermal meter*/
427
428 cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] =
429 thermal_value;
430 cali_info->thermal_value_avg_index++;
431 if (cali_info->thermal_value_avg_index ==
432 c.average_thermal_num) /*Average times = c.average_thermal_num*/
433 cali_info->thermal_value_avg_index = 0;
434
435 for (i = 0; i < c.average_thermal_num; i++) {
436 if (cali_info->thermal_value_avg[i]) {
437 thermal_value_avg += cali_info->thermal_value_avg[i];
438 thermal_value_avg_count++;
439 }
440 }
441
442 if (thermal_value_avg_count) {
443 /* Calculate Average thermal_value after average enough times */
444 thermal_value =
445 (u8)(thermal_value_avg / thermal_value_avg_count);
446 cali_info->thermal_value_delta =
447 thermal_value - rtlefu->eeprom_thermalmeter;
448 ODM_RT_TRACE(
449 dm, ODM_COMP_TX_PWR_TRACK,
450 "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n",
451 thermal_value, rtlefu->eeprom_thermalmeter);
452 }
453
454 /* 4 5. Calculate delta, delta_LCK, delta_IQK. */
455
456 /* "delta" is used to determine whether thermal value changes or not*/
457 delta = (thermal_value > cali_info->thermal_value) ?
458 (thermal_value - cali_info->thermal_value) :
459 (cali_info->thermal_value - thermal_value);
460 delta_LCK = (thermal_value > cali_info->thermal_value_lck) ?
461 (thermal_value - cali_info->thermal_value_lck) :
462 (cali_info->thermal_value_lck - thermal_value);
463 delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ?
464 (thermal_value - cali_info->thermal_value_iqk) :
465 (cali_info->thermal_value_iqk - thermal_value);
466
467 if (cali_info->thermal_value_iqk ==
468 0xff) { /*no PG, use thermal value for IQK*/
469 cali_info->thermal_value_iqk = thermal_value;
470 delta_IQK =
471 (thermal_value > cali_info->thermal_value_iqk) ?
472 (thermal_value - cali_info->thermal_value_iqk) :
473 (cali_info->thermal_value_iqk - thermal_value);
474 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
475 "no PG, use thermal_value for IQK\n");
476 }
477
478 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
479 diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
480
481 /*4 6. If necessary, do LCK.*/
482
483 if (!(dm->support_ic_type &
484 ODM_RTL8821)) { /*no PG, do LCK at initial status*/
485 if (cali_info->thermal_value_lck == 0xff) {
486 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
487 "no PG, do LCK\n");
488 cali_info->thermal_value_lck = thermal_value;
489
490 /*Use RTLCK, so close power tracking driver LCK*/
491 if (!(dm->support_ic_type & ODM_RTL8814A) &&
492 c.phy_lc_calibrate)
493 (*c.phy_lc_calibrate)(dm);
494
495 delta_LCK =
496 (thermal_value > cali_info->thermal_value_lck) ?
497 (thermal_value -
498 cali_info->thermal_value_lck) :
499 (cali_info->thermal_value_lck -
500 thermal_value);
501 }
502
503 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
504 "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n",
505 delta, delta_LCK, delta_IQK);
506
507 /*Delta temperature is equal to or larger than 20 centigrade.*/
508 if (delta_LCK >= c.threshold_iqk) {
509 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
510 "delta_LCK(%d) >= threshold_iqk(%d)\n",
511 delta_LCK, c.threshold_iqk);
512 cali_info->thermal_value_lck = thermal_value;
513
514 /*Use RTLCK, so close power tracking driver LCK*/
515 if (!(dm->support_ic_type & ODM_RTL8814A) &&
516 c.phy_lc_calibrate)
517 (*c.phy_lc_calibrate)(dm);
518 }
519 }
520
521 /*3 7. If necessary, move the index of swing table to adjust Tx power.*/
522
523 if (delta > 0 && cali_info->txpowertrack_control) {
524 /* "delta" here is used to record the abs value of difference.*/
525 delta = thermal_value > rtlefu->eeprom_thermalmeter ?
526 (thermal_value - rtlefu->eeprom_thermalmeter) :
527 (rtlefu->eeprom_thermalmeter - thermal_value);
528 if (delta >= TXPWR_TRACK_TABLE_SIZE)
529 delta = TXPWR_TRACK_TABLE_SIZE - 1;
530
531 /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
532
533 if (thermal_value > rtlefu->eeprom_thermalmeter) {
534 phydm_set_calibrate_info_up(
535 dm, &c, delta, cali_info,
536 delta_swing_table_idx_tup_a,
537 delta_swing_table_idx_tup_b,
538 delta_swing_table_idx_tup_c,
539 delta_swing_table_idx_tup_d);
540 /* JJ ADD 20161014 */
541 if (dm->support_ic_type &
542 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
543 /*Save xtal_offset from Xtal table*/
544
545 /*recording last Xtal offset*/
546 cali_info->xtal_offset_last =
547 cali_info->xtal_offset;
548 ODM_RT_TRACE(
549 dm, ODM_COMP_TX_PWR_TRACK,
550 "[Xtal] delta_swing_table_xtal_up[%d] = %d\n",
551 delta,
552 delta_swing_table_xtal_up[delta]);
553 cali_info->xtal_offset =
554 delta_swing_table_xtal_up[delta];
555 xtal_offset_eanble =
556 (cali_info->xtal_offset_last ==
557 cali_info->xtal_offset) ?
558 0 :
559 1;
560 }
561
562 } else {
563 phydm_set_calibrate_info_down(
564 dm, &c, delta, cali_info,
565 delta_swing_table_idx_tdown_a,
566 delta_swing_table_idx_tdown_b,
567 delta_swing_table_idx_tdown_c,
568 delta_swing_table_idx_tdown_d);
569 /* JJ ADD 20161014 */
570 if (dm->support_ic_type &
571 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
572 /*Save xtal_offset from Xtal table*/
573
574 /*recording last Xtal offset*/
575 cali_info->xtal_offset_last =
576 cali_info->xtal_offset;
577 ODM_RT_TRACE(
578 dm, ODM_COMP_TX_PWR_TRACK,
579 "[Xtal] delta_swing_table_xtal_down[%d] = %d\n",
580 delta,
581 delta_swing_table_xtal_down[delta]);
582 cali_info->xtal_offset =
583 delta_swing_table_xtal_down[delta];
584 xtal_offset_eanble =
585 (cali_info->xtal_offset_last ==
586 cali_info->xtal_offset) ?
587 0 :
588 1;
589 }
590 }
591
592 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
593 ODM_RT_TRACE(
594 dm, ODM_COMP_TX_PWR_TRACK,
595 "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n",
596 p);
597
598 if (cali_info->delta_power_index[p] ==
599 cali_info->delta_power_index_last[p]) {
600 /* If Thermal value changes but lookup table
601 * value still the same
602 */
603 cali_info->power_index_offset[p] = 0;
604 } else {
605 /*Power idx diff between 2 times Pwr Tracking*/
606 cali_info->power_index_offset[p] =
607 cali_info->delta_power_index[p] -
608 cali_info->delta_power_index_last[p];
609 }
610
611 ODM_RT_TRACE(
612 dm, ODM_COMP_TX_PWR_TRACK,
613 "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n",
614 p, cali_info->power_index_offset[p],
615 cali_info->delta_power_index[p],
616 cali_info->delta_power_index_last[p]);
617
618 cali_info->OFDM_index[p] =
619 cali_info->bb_swing_idx_ofdm_base[p] +
620 cali_info->power_index_offset[p];
621 cali_info->CCK_index =
622 cali_info->bb_swing_idx_cck_base +
623 cali_info->power_index_offset[p];
624
625 cali_info->bb_swing_idx_cck = cali_info->CCK_index;
626 cali_info->bb_swing_idx_ofdm[p] =
627 cali_info->OFDM_index[p];
628
629 /*******Print BB Swing base and index Offset**********/
630
631 ODM_RT_TRACE(
632 dm, ODM_COMP_TX_PWR_TRACK,
633 "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n",
634 cali_info->bb_swing_idx_cck,
635 cali_info->bb_swing_idx_cck_base,
636 cali_info->power_index_offset[p]);
637 ODM_RT_TRACE(
638 dm, ODM_COMP_TX_PWR_TRACK,
639 "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n",
640 cali_info->bb_swing_idx_ofdm[p], p,
641 cali_info->bb_swing_idx_ofdm_base[p],
642 cali_info->power_index_offset[p]);
643
644 /*4 7.1 Handle boundary conditions of index.*/
645
646 if (cali_info->OFDM_index[p] >
647 c.swing_table_size_ofdm - 1)
648 cali_info->OFDM_index[p] =
649 c.swing_table_size_ofdm - 1;
650 else if (cali_info->OFDM_index[p] <= OFDM_min_index)
651 cali_info->OFDM_index[p] = OFDM_min_index;
652 }
653
654 ODM_RT_TRACE(
655 dm, ODM_COMP_TX_PWR_TRACK,
656 "\n\n========================================================================================================\n");
657
658 if (cali_info->CCK_index > c.swing_table_size_cck - 1)
659 cali_info->CCK_index = c.swing_table_size_cck - 1;
660 else if (cali_info->CCK_index <= 0)
661 cali_info->CCK_index = 0;
662 } else {
663 ODM_RT_TRACE(
664 dm, ODM_COMP_TX_PWR_TRACK,
665 "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
666 cali_info->txpowertrack_control, thermal_value,
667 cali_info->thermal_value);
668
669 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
670 cali_info->power_index_offset[p] = 0;
671 }
672
673 /*Print Swing base & current*/
674 ODM_RT_TRACE(
675 dm, ODM_COMP_TX_PWR_TRACK,
676 "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
677 cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);
678
679 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
680 ODM_RT_TRACE(
681 dm, ODM_COMP_TX_PWR_TRACK,
682 "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
683 cali_info->OFDM_index[p], p,
684 cali_info->bb_swing_idx_ofdm_base[p]);
685
686 if ((dm->support_ic_type & ODM_RTL8814A)) {
687 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
688 "power_tracking_type=%d\n", power_tracking_type);
689
690 if (power_tracking_type == 0) {
691 ODM_RT_TRACE(
692 dm, ODM_COMP_TX_PWR_TRACK,
693 "**********Enter POWER Tracking MIX_MODE**********\n");
694 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
695 (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
696 0);
697 } else if (power_tracking_type == 1) {
698 ODM_RT_TRACE(
699 dm, ODM_COMP_TX_PWR_TRACK,
700 "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
701 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
702 (*c.odm_tx_pwr_track_set_pwr)(
703 dm, MIX_2G_TSSI_5G_MODE, p, 0);
704 } else if (power_tracking_type == 2) {
705 ODM_RT_TRACE(
706 dm, ODM_COMP_TX_PWR_TRACK,
707 "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
708 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
709 (*c.odm_tx_pwr_track_set_pwr)(
710 dm, MIX_5G_TSSI_2G_MODE, p, 0);
711 } else if (power_tracking_type == 3) {
712 ODM_RT_TRACE(
713 dm, ODM_COMP_TX_PWR_TRACK,
714 "**********Enter POWER Tracking TSSI MODE**********\n");
715 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
716 (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p,
717 0);
718 }
719 /*Record last Power Tracking Thermal value*/
720 cali_info->thermal_value = thermal_value;
721
722 } else if ((cali_info->power_index_offset[ODM_RF_PATH_A] != 0 ||
723 cali_info->power_index_offset[ODM_RF_PATH_B] != 0 ||
724 cali_info->power_index_offset[ODM_RF_PATH_C] != 0 ||
725 cali_info->power_index_offset[ODM_RF_PATH_D] != 0) &&
726 cali_info->txpowertrack_control &&
727 (rtlefu->eeprom_thermalmeter != 0xff)) {
728 /* 4 7.2 Configure the Swing Table to adjust Tx Power. */
729
730 /*Always true after Tx Power is adjusted by power tracking.*/
731 cali_info->is_tx_power_changed = true;
732 /* 2012/04/23 MH According to Luke's suggestion, we can not
733 * write BB digital to increase TX power. Otherwise, EVM will
734 * be bad.
735 */
736 /* 2012/04/25 MH Add for tx power tracking to set tx power in
737 * tx agc for 88E.
738 */
739 if (thermal_value > cali_info->thermal_value) {
740 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
741 /* print temperature increasing */
742 ODM_RT_TRACE(
743 dm, ODM_COMP_TX_PWR_TRACK,
744 "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
745 p, cali_info->power_index_offset[p],
746 delta, thermal_value,
747 rtlefu->eeprom_thermalmeter,
748 cali_info->thermal_value);
749 }
750 } else if (thermal_value <
751 cali_info->thermal_value) { /*Low temperature*/
752 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
753 /* print temperature decreasing */
754 ODM_RT_TRACE(
755 dm, ODM_COMP_TX_PWR_TRACK,
756 "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
757 p, cali_info->power_index_offset[p],
758 delta, thermal_value,
759 rtlefu->eeprom_thermalmeter,
760 cali_info->thermal_value);
761 }
762 }
763
764 if (thermal_value > rtlefu->eeprom_thermalmeter) {
765 ODM_RT_TRACE(
766 dm, ODM_COMP_TX_PWR_TRACK,
767 "Temperature(%d) higher than PG value(%d)\n",
768 thermal_value, rtlefu->eeprom_thermalmeter);
769
770 phydm_odm_tx_power_set(dm, &c, indexforchannel, 0);
771 } else {
772 ODM_RT_TRACE(
773 dm, ODM_COMP_TX_PWR_TRACK,
774 "Temperature(%d) lower than PG value(%d)\n",
775 thermal_value, rtlefu->eeprom_thermalmeter);
776 phydm_odm_tx_power_set(dm, &c, indexforchannel, 1);
777 }
778
779 /*Record last time Power Tracking result as base.*/
780 cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
781
782 for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
783 cali_info->bb_swing_idx_ofdm_base[p] =
784 cali_info->bb_swing_idx_ofdm[p];
785
786 ODM_RT_TRACE(
787 dm, ODM_COMP_TX_PWR_TRACK,
788 "cali_info->thermal_value = %d thermal_value= %d\n",
789 cali_info->thermal_value, thermal_value);
790
791 /*Record last Power Tracking Thermal value*/
792 cali_info->thermal_value = thermal_value;
793 }
794
795 if (dm->support_ic_type == ODM_RTL8703B ||
796 dm->support_ic_type == ODM_RTL8723D ||
797 dm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */
798
799 if (xtal_offset_eanble != 0 &&
800 cali_info->txpowertrack_control &&
801 (rtlefu->eeprom_thermalmeter != 0xff)) {
802 ODM_RT_TRACE(
803 dm, ODM_COMP_TX_PWR_TRACK,
804 "**********Enter Xtal Tracking**********\n");
805
806 if (thermal_value > rtlefu->eeprom_thermalmeter) {
807 ODM_RT_TRACE(
808 dm, ODM_COMP_TX_PWR_TRACK,
809 "Temperature(%d) higher than PG value(%d)\n",
810 thermal_value,
811 rtlefu->eeprom_thermalmeter);
812 (*c.odm_txxtaltrack_set_xtal)(dm);
813 } else {
814 ODM_RT_TRACE(
815 dm, ODM_COMP_TX_PWR_TRACK,
816 "Temperature(%d) lower than PG value(%d)\n",
817 thermal_value,
818 rtlefu->eeprom_thermalmeter);
819 (*c.odm_txxtaltrack_set_xtal)(dm);
820 }
821 }
822 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
823 "**********End Xtal Tracking**********\n");
824 }
825
826 if (!IS_HARDWARE_TYPE_8723B(adapter)) {
827 /* Delta temperature is equal to or larger than 20 centigrade
828 * (When threshold is 8).
829 */
830 if (delta_IQK >= c.threshold_iqk) {
831 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
832 "delta_IQK(%d) >= threshold_iqk(%d)\n",
833 delta_IQK, c.threshold_iqk);
834 if (!cali_info->is_iqk_in_progress)
835 (*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
836 }
837 }
838 if (cali_info->dpk_thermal[ODM_RF_PATH_A] != 0) {
839 if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) {
840 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
841 odm_set_bb_reg(
842 dm, 0xcc4,
843 BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10),
844 (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk));
845 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
846 } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) {
847 s32 value = 0x20 +
848 (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk);
849
850 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
851 odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) |
852 BIT(11) | BIT(10),
853 value);
854 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
855 } else {
856 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
857 odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) |
858 BIT(11) | BIT(10),
859 0);
860 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
861 }
862 }
863 if (cali_info->dpk_thermal[ODM_RF_PATH_B] != 0) {
864 if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) {
865 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
866 odm_set_bb_reg(
867 dm, 0xec4,
868 BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10),
869 (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk));
870 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
871 } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) {
872 s32 value = 0x20 +
873 (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk);
874
875 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
876 odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) |
877 BIT(11) | BIT(10),
878 value);
879 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
880 } else {
881 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
882 odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) |
883 BIT(11) | BIT(10),
884 0);
885 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
886 }
887 }
888
889 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK, "<===%s\n", __func__);
890
891 cali_info->tx_powercount = 0;
892}
893
894/* 3============================================================
895 * 3 IQ Calibration
896 * 3============================================================
897 */
898
899void odm_reset_iqk_result(void *dm_void) { return; }
900
901u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
902{
903 u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
904 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
905 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
906 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
907 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136,
908 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165};
909 u8 place = chnl;
910
911 if (chnl > 14) {
912 for (place = 14; place < sizeof(channel_all); place++) {
913 if (channel_all[place] == chnl)
914 return place - 13;
915 }
916 }
917 return 0;
918}
919
920static void odm_iq_calibrate(struct phy_dm_struct *dm)
921{
922 void *adapter = dm->adapter;
923
924 if (IS_HARDWARE_TYPE_8812AU(adapter))
925 return;
926
927 if (dm->is_linked) {
928 if ((*dm->channel != dm->pre_channel) &&
929 (!*dm->is_scan_in_process)) {
930 dm->pre_channel = *dm->channel;
931 dm->linked_interval = 0;
932 }
933
934 if (dm->linked_interval < 3)
935 dm->linked_interval++;
936
937 if (dm->linked_interval == 2) {
938 if (IS_HARDWARE_TYPE_8814A(adapter))
939 ;
940
941 else if (IS_HARDWARE_TYPE_8822B(adapter))
942 phy_iq_calibrate_8822b(dm, false);
943 }
944 } else {
945 dm->linked_interval = 0;
946 }
947}
948
949void phydm_rf_init(void *dm_void)
950{
951 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
952
953 odm_txpowertracking_init(dm);
954
955 odm_clear_txpowertracking_state(dm);
956}
957
958void phydm_rf_watchdog(void *dm_void)
959{
960 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
961
962 odm_txpowertracking_check(dm);
963 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
964 odm_iq_calibrate(dm);
965}
diff --git a/drivers/staging/rtlwifi/phydm/halphyrf_ce.h b/drivers/staging/rtlwifi/phydm/halphyrf_ce.h
new file mode 100644
index 000000000000..e5d6257efb2b
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/halphyrf_ce.h
@@ -0,0 +1,85 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __HAL_PHY_RF_H__
27#define __HAL_PHY_RF_H__
28
29#include "phydm_kfree.h"
30
31#include "rtl8822b/phydm_iqk_8822b.h"
32
33#include "phydm_powertracking_ce.h"
34
35enum spur_cal_method { PLL_RESET, AFE_PHASE_SEL };
36
37enum pwrtrack_method {
38 BBSWING,
39 TXAGC,
40 MIX_MODE,
41 TSSI_MODE,
42 MIX_2G_TSSI_5G_MODE,
43 MIX_5G_TSSI_2G_MODE
44};
45
46typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
47typedef void (*func_iqk)(void *, u8, u8, u8);
48typedef void (*func_lck)(void *);
49typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
50typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
51typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
52typedef void (*func_set_xtal)(void *);
53
54struct txpwrtrack_cfg {
55 u8 swing_table_size_cck;
56 u8 swing_table_size_ofdm;
57 u8 threshold_iqk;
58 u8 threshold_dpk;
59 u8 average_thermal_num;
60 u8 rf_path_count;
61 u32 thermal_reg_addr;
62 func_set_pwr odm_tx_pwr_track_set_pwr;
63 func_iqk do_iqk;
64 func_lck phy_lc_calibrate;
65 func_swing get_delta_swing_table;
66 func_swing8814only get_delta_swing_table8814only;
67 func_swing_xtal get_delta_swing_xtal_table;
68 func_set_xtal odm_txxtaltrack_set_xtal;
69};
70
71void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
72
73void odm_clear_txpowertracking_state(void *dm_void);
74
75void odm_txpowertracking_callback_thermal_meter(void *dm);
76
77#define ODM_TARGET_CHNL_NUM_2G_5G 59
78
79void odm_reset_iqk_result(void *dm_void);
80u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
81
82void phydm_rf_init(void *dm_void);
83void phydm_rf_watchdog(void *dm_void);
84
85#endif /* #ifndef __HAL_PHY_RF_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/mp_precomp.h b/drivers/staging/rtlwifi/phydm/mp_precomp.h
new file mode 100644
index 000000000000..b313de511ed6
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/mp_precomp.h
@@ -0,0 +1,24 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
diff --git a/drivers/staging/rtlwifi/phydm/phydm.c b/drivers/staging/rtlwifi/phydm/phydm.c
new file mode 100644
index 000000000000..37888c3087a4
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm.c
@@ -0,0 +1,1986 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29
30#include "mp_precomp.h"
31#include "phydm_precomp.h"
32
33static const u16 db_invert_table[12][8] = {
34 {1, 1, 1, 2, 2, 2, 2, 3},
35 {3, 3, 4, 4, 4, 5, 6, 6},
36 {7, 8, 9, 10, 11, 13, 14, 16},
37 {18, 20, 22, 25, 28, 32, 35, 40},
38 {45, 50, 56, 63, 71, 79, 89, 100},
39 {112, 126, 141, 158, 178, 200, 224, 251},
40 {282, 316, 355, 398, 447, 501, 562, 631},
41 {708, 794, 891, 1000, 1122, 1259, 1413, 1585},
42 {1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
43 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000},
44 {11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119},
45 {28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535},
46};
47
48/* ************************************************************
49 * Local Function predefine.
50 * *************************************************************/
51
52/* START------------COMMON INFO RELATED--------------- */
53
54static void odm_update_power_training_state(struct phy_dm_struct *dm);
55
56/* ************************************************************
57 * 3 Export Interface
58 * *************************************************************/
59
60/*Y = 10*log(X)*/
61s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)
62{
63 s32 Y, integer = 0, decimal = 0;
64 u32 i;
65
66 if (X == 0)
67 X = 1; /* log2(x), x can't be 0 */
68
69 for (i = (total_bit - 1); i > 0; i--) {
70 if (X & BIT(i)) {
71 integer = i;
72 if (i > 0) {
73 /* decimal is 0.5dB*3=1.5dB~=2dB */
74 decimal = (X & BIT(i - 1)) ? 2 : 0;
75 }
76 break;
77 }
78 }
79
80 Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */
81
82 return Y;
83}
84
85s32 odm_sign_conversion(s32 value, u32 total_bit)
86{
87 if (value & BIT(total_bit - 1))
88 value -= BIT(total_bit);
89 return value;
90}
91
92void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
93 u8 seq_length)
94{
95 u8 i = 0, j = 0;
96 u32 tmp_a, tmp_b;
97 u32 tmp_idx_a, tmp_idx_b;
98
99 for (i = 0; i < seq_length; i++) {
100 rank_idx[i] = i;
101 /**/
102 }
103
104 for (i = 0; i < (seq_length - 1); i++) {
105 for (j = 0; j < (seq_length - 1 - i); j++) {
106 tmp_a = value[j];
107 tmp_b = value[j + 1];
108
109 tmp_idx_a = rank_idx[j];
110 tmp_idx_b = rank_idx[j + 1];
111
112 if (tmp_a < tmp_b) {
113 value[j] = tmp_b;
114 value[j + 1] = tmp_a;
115
116 rank_idx[j] = tmp_idx_b;
117 rank_idx[j + 1] = tmp_idx_a;
118 }
119 }
120 }
121
122 for (i = 0; i < seq_length; i++) {
123 idx_out[rank_idx[i]] = i + 1;
124 /**/
125 }
126}
127
128void odm_init_mp_driver_status(struct phy_dm_struct *dm)
129{
130 dm->mp_mode = false;
131}
132
133static void odm_update_mp_driver_status(struct phy_dm_struct *dm)
134{
135 /* Do nothing. */
136}
137
138static void phydm_init_trx_antenna_setting(struct phy_dm_struct *dm)
139{
140 /*#if (RTL8814A_SUPPORT == 1)*/
141
142 if (dm->support_ic_type & (ODM_RTL8814A)) {
143 u8 rx_ant = 0, tx_ant = 0;
144
145 rx_ant = (u8)odm_get_bb_reg(dm, ODM_REG(BB_RX_PATH, dm),
146 ODM_BIT(BB_RX_PATH, dm));
147 tx_ant = (u8)odm_get_bb_reg(dm, ODM_REG(BB_TX_PATH, dm),
148 ODM_BIT(BB_TX_PATH, dm));
149 dm->tx_ant_status = (tx_ant & 0xf);
150 dm->rx_ant_status = (rx_ant & 0xf);
151 } else if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C |
152 ODM_RTL8710B)) { /* JJ ADD 20161014 */
153 dm->tx_ant_status = 0x1;
154 dm->rx_ant_status = 0x1;
155 }
156 /*#endif*/
157}
158
159static void phydm_traffic_load_decision(void *dm_void)
160{
161 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
162
163 /*---TP & Trafic-load calculation---*/
164
165 if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
166 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
167
168 if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
169 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
170
171 dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
172 dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
173 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
174 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
175
176 dm->tx_tp = ((dm->tx_tp) >> 1) +
177 (u32)(((dm->cur_tx_ok_cnt) >> 18) >>
178 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
179 dm->rx_tp = ((dm->rx_tp) >> 1) +
180 (u32)(((dm->cur_rx_ok_cnt) >> 18) >>
181 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
182 dm->total_tp = dm->tx_tp + dm->rx_tp;
183
184 dm->pre_traffic_load = dm->traffic_load;
185
186 if (dm->cur_tx_ok_cnt > 1875000 ||
187 dm->cur_rx_ok_cnt >
188 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
189
190 dm->traffic_load = TRAFFIC_HIGH;
191 /**/
192 } else if (
193 dm->cur_tx_ok_cnt > 500000 ||
194 dm->cur_rx_ok_cnt >
195 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
196
197 dm->traffic_load = TRAFFIC_MID;
198 /**/
199 } else if (
200 dm->cur_tx_ok_cnt > 100000 ||
201 dm->cur_rx_ok_cnt >
202 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
203
204 dm->traffic_load = TRAFFIC_LOW;
205 /**/
206 } else {
207 dm->traffic_load = TRAFFIC_ULTRA_LOW;
208 /**/
209 }
210}
211
212static void phydm_config_ofdm_tx_path(struct phy_dm_struct *dm, u32 path) {}
213
214void phydm_config_ofdm_rx_path(struct phy_dm_struct *dm, u32 path)
215{
216 u8 ofdm_rx_path = 0;
217
218 if (dm->support_ic_type & (ODM_RTL8192E)) {
219 } else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
220 if (path == PHYDM_A) {
221 ofdm_rx_path = 1;
222 /**/
223 } else if (path == PHYDM_B) {
224 ofdm_rx_path = 2;
225 /**/
226 } else if (path == PHYDM_AB) {
227 ofdm_rx_path = 3;
228 /**/
229 }
230
231 odm_set_bb_reg(dm, 0x808, MASKBYTE0,
232 ((ofdm_rx_path << 4) | ofdm_rx_path));
233 }
234}
235
236static void phydm_config_cck_rx_antenna_init(struct phy_dm_struct *dm) {}
237
238static void phydm_config_cck_rx_path(struct phy_dm_struct *dm, u8 path,
239 u8 path_div_en)
240{
241}
242
243void phydm_config_trx_path(void *dm_void, u32 *const dm_value, u32 *_used,
244 char *output, u32 *_out_len)
245{
246 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
247 u32 used = *_used;
248 u32 out_len = *_out_len;
249
250 /* CCK */
251 if (dm_value[0] == 0) {
252 if (dm_value[1] == 1) { /*TX*/
253 if (dm_value[2] == 1)
254 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8);
255 else if (dm_value[2] == 2)
256 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4);
257 else if (dm_value[2] == 3)
258 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc);
259 } else if (dm_value[1] == 2) { /*RX*/
260
261 phydm_config_cck_rx_antenna_init(dm);
262
263 if (dm_value[2] == 1)
264 phydm_config_cck_rx_path(dm, PHYDM_A,
265 CCA_PATHDIV_DISABLE);
266 else if (dm_value[2] == 2)
267 phydm_config_cck_rx_path(dm, PHYDM_B,
268 CCA_PATHDIV_DISABLE);
269 else if (dm_value[2] == 3 &&
270 dm_value[3] == 1) /*enable path diversity*/
271 phydm_config_cck_rx_path(dm, PHYDM_AB,
272 CCA_PATHDIV_ENABLE);
273 else if (dm_value[2] == 3 && dm_value[3] != 1)
274 phydm_config_cck_rx_path(dm, PHYDM_B,
275 CCA_PATHDIV_DISABLE);
276 }
277 }
278 /* OFDM */
279 else if (dm_value[0] == 1) {
280 if (dm_value[1] == 1) { /*TX*/
281 phydm_config_ofdm_tx_path(dm, dm_value[2]);
282 /**/
283 } else if (dm_value[1] == 2) { /*RX*/
284 phydm_config_ofdm_rx_path(dm, dm_value[2]);
285 /**/
286 }
287 }
288
289 PHYDM_SNPRINTF(
290 output + used, out_len - used,
291 "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
292 (dm_value[0] == 1) ? "OFDM" : "CCK",
293 (dm_value[1] == 1) ? "TX" : "RX",
294 (dm_value[2] & 0x1) ? "A" : "", (dm_value[2] & 0x2) ? "B" : "",
295 (dm_value[2] & 0x4) ? "C" : "", (dm_value[2] & 0x8) ? "D" : "");
296}
297
298static void phydm_init_cck_setting(struct phy_dm_struct *dm)
299{
300 dm->is_cck_high_power = (bool)odm_get_bb_reg(
301 dm, ODM_REG(CCK_RPT_FORMAT, dm), ODM_BIT(CCK_RPT_FORMAT, dm));
302
303 /* JJ ADD 20161014 */
304 /* JJ ADD 20161014 */
305 if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F |
306 ODM_RTL8821C | ODM_RTL8710B))
307 dm->cck_new_agc = odm_get_bb_reg(dm, 0xa9c, BIT(17)) ?
308 true :
309 false; /*1: new agc 0: old agc*/
310 else
311 dm->cck_new_agc = false;
312}
313
314static void phydm_init_soft_ml_setting(struct phy_dm_struct *dm)
315{
316 if (!dm->mp_mode) {
317 if (dm->support_ic_type & ODM_RTL8822B)
318 odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0xc10a0000);
319 }
320}
321
322static void phydm_init_hw_info_by_rfe(struct phy_dm_struct *dm)
323{
324 if (dm->support_ic_type & ODM_RTL8822B)
325 phydm_init_hw_info_by_rfe_type_8822b(dm);
326}
327
328static void odm_common_info_self_init(struct phy_dm_struct *dm)
329{
330 phydm_init_cck_setting(dm);
331 dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, ODM_REG(BB_RX_PATH, dm),
332 ODM_BIT(BB_RX_PATH, dm));
333 odm_init_mp_driver_status(dm);
334 phydm_init_trx_antenna_setting(dm);
335 phydm_init_soft_ml_setting(dm);
336
337 dm->phydm_period = PHYDM_WATCH_DOG_PERIOD;
338 dm->phydm_sys_up_time = 0;
339
340 if (dm->support_ic_type & ODM_IC_1SS)
341 dm->num_rf_path = 1;
342 else if (dm->support_ic_type & ODM_IC_2SS)
343 dm->num_rf_path = 2;
344 else if (dm->support_ic_type & ODM_IC_3SS)
345 dm->num_rf_path = 3;
346 else if (dm->support_ic_type & ODM_IC_4SS)
347 dm->num_rf_path = 4;
348
349 dm->tx_rate = 0xFF;
350
351 dm->number_linked_client = 0;
352 dm->pre_number_linked_client = 0;
353 dm->number_active_client = 0;
354 dm->pre_number_active_client = 0;
355
356 dm->last_tx_ok_cnt = 0;
357 dm->last_rx_ok_cnt = 0;
358 dm->tx_tp = 0;
359 dm->rx_tp = 0;
360 dm->total_tp = 0;
361 dm->traffic_load = TRAFFIC_LOW;
362
363 dm->nbi_set_result = 0;
364 dm->is_init_hw_info_by_rfe = false;
365 dm->pre_dbg_priority = BB_DBGPORT_RELEASE;
366}
367
368static void odm_common_info_self_update(struct phy_dm_struct *dm)
369{
370 u8 entry_cnt = 0, num_active_client = 0;
371 u32 i, one_entry_macid = 0;
372 struct rtl_sta_info *entry;
373
374 /* THis variable cannot be used because it is wrong*/
375 if (*dm->band_width == ODM_BW40M) {
376 if (*dm->sec_ch_offset == 1)
377 dm->control_channel = *dm->channel - 2;
378 else if (*dm->sec_ch_offset == 2)
379 dm->control_channel = *dm->channel + 2;
380 } else {
381 dm->control_channel = *dm->channel;
382 }
383
384 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
385 entry = dm->odm_sta_info[i];
386 if (IS_STA_VALID(entry)) {
387 entry_cnt++;
388 if (entry_cnt == 1)
389 one_entry_macid = i;
390 }
391 }
392
393 if (entry_cnt == 1) {
394 dm->is_one_entry_only = true;
395 dm->one_entry_macid = one_entry_macid;
396 } else {
397 dm->is_one_entry_only = false;
398 }
399
400 dm->pre_number_linked_client = dm->number_linked_client;
401 dm->pre_number_active_client = dm->number_active_client;
402
403 dm->number_linked_client = entry_cnt;
404 dm->number_active_client = num_active_client;
405
406 /* Update MP driver status*/
407 odm_update_mp_driver_status(dm);
408
409 /*Traffic load information update*/
410 phydm_traffic_load_decision(dm);
411
412 dm->phydm_sys_up_time += dm->phydm_period;
413}
414
415static void odm_common_info_self_reset(struct phy_dm_struct *dm)
416{
417 dm->phy_dbg_info.num_qry_beacon_pkt = 0;
418}
419
420void *phydm_get_structure(struct phy_dm_struct *dm, u8 structure_type)
421
422{
423 void *p_struct = NULL;
424
425 switch (structure_type) {
426 case PHYDM_FALSEALMCNT:
427 p_struct = &dm->false_alm_cnt;
428 break;
429
430 case PHYDM_CFOTRACK:
431 p_struct = &dm->dm_cfo_track;
432 break;
433
434 case PHYDM_ADAPTIVITY:
435 p_struct = &dm->adaptivity;
436 break;
437
438 default:
439 break;
440 }
441
442 return p_struct;
443}
444
445static void odm_hw_setting(struct phy_dm_struct *dm)
446{
447 if (dm->support_ic_type & ODM_RTL8822B)
448 phydm_hwsetting_8822b(dm);
449}
450
451static void phydm_supportability_init(void *dm_void)
452{
453 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
454 u32 support_ability = 0;
455
456 if (dm->support_ic_type != ODM_RTL8821C)
457 return;
458
459 switch (dm->support_ic_type) {
460 /*---------------AC Series-------------------*/
461
462 case ODM_RTL8822B:
463 support_ability |= ODM_BB_DIG | ODM_BB_FA_CNT | ODM_BB_CCK_PD |
464 ODM_BB_CFO_TRACKING | ODM_BB_RATE_ADAPTIVE |
465 ODM_BB_RSSI_MONITOR | ODM_BB_RA_MASK |
466 ODM_RF_TX_PWR_TRACK;
467 break;
468
469 default:
470 support_ability |= ODM_BB_DIG | ODM_BB_FA_CNT | ODM_BB_CCK_PD |
471 ODM_BB_CFO_TRACKING | ODM_BB_RATE_ADAPTIVE |
472 ODM_BB_RSSI_MONITOR | ODM_BB_RA_MASK |
473 ODM_RF_TX_PWR_TRACK;
474
475 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
476 "[Warning] Supportability Init Warning !!!\n");
477 break;
478 }
479
480 if (*dm->enable_antdiv)
481 support_ability |= ODM_BB_ANT_DIV;
482
483 if (*dm->enable_adaptivity) {
484 ODM_RT_TRACE(dm, ODM_COMP_INIT,
485 "ODM adaptivity is set to Enabled!!!\n");
486
487 support_ability |= ODM_BB_ADAPTIVITY;
488
489 } else {
490 ODM_RT_TRACE(dm, ODM_COMP_INIT,
491 "ODM adaptivity is set to disnabled!!!\n");
492 /**/
493 }
494
495 ODM_RT_TRACE(dm, ODM_COMP_INIT, "PHYDM support_ability = ((0x%x))\n",
496 support_ability);
497 odm_cmn_info_init(dm, ODM_CMNINFO_ABILITY, support_ability);
498}
499
500/*
501 * 2011/09/21 MH Add to describe different team necessary resource allocate??
502 */
503void odm_dm_init(struct phy_dm_struct *dm)
504{
505 phydm_supportability_init(dm);
506 odm_common_info_self_init(dm);
507 odm_dig_init(dm);
508 phydm_nhm_counter_statistics_init(dm);
509 phydm_adaptivity_init(dm);
510 phydm_ra_info_init(dm);
511 odm_rate_adaptive_mask_init(dm);
512 odm_cfo_tracking_init(dm);
513 odm_edca_turbo_init(dm);
514 odm_rssi_monitor_init(dm);
515 phydm_rf_init(dm);
516 odm_txpowertracking_init(dm);
517
518 if (dm->support_ic_type & ODM_RTL8822B)
519 phydm_txcurrentcalibration(dm);
520
521 odm_antenna_diversity_init(dm);
522 odm_auto_channel_select_init(dm);
523 odm_dynamic_tx_power_init(dm);
524 phydm_init_ra_info(dm);
525 adc_smp_init(dm);
526
527 phydm_beamforming_init(dm);
528
529 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
530 /* 11n series */
531 odm_dynamic_bb_power_saving_init(dm);
532 }
533
534 phydm_psd_init(dm);
535}
536
537void odm_dm_reset(struct phy_dm_struct *dm)
538{
539 struct dig_thres *dig_tab = &dm->dm_dig_table;
540
541 odm_ant_div_reset(dm);
542 phydm_set_edcca_threshold_api(dm, dig_tab->cur_ig_value);
543}
544
545void phydm_support_ability_debug(void *dm_void, u32 *const dm_value, u32 *_used,
546 char *output, u32 *_out_len)
547{
548 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
549 u32 pre_support_ability;
550 u32 used = *_used;
551 u32 out_len = *_out_len;
552
553 pre_support_ability = dm->support_ability;
554 PHYDM_SNPRINTF(output + used, out_len - used, "\n%s\n",
555 "================================");
556 if (dm_value[0] == 100) {
557 PHYDM_SNPRINTF(output + used, out_len - used,
558 "[Supportability] PhyDM Selection\n");
559 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
560 "================================");
561 PHYDM_SNPRINTF(
562 output + used, out_len - used, "00. (( %s ))DIG\n",
563 ((dm->support_ability & ODM_BB_DIG) ? ("V") : (".")));
564 PHYDM_SNPRINTF(
565 output + used, out_len - used, "01. (( %s ))RA_MASK\n",
566 ((dm->support_ability & ODM_BB_RA_MASK) ? ("V") :
567 (".")));
568 PHYDM_SNPRINTF(output + used, out_len - used,
569 "02. (( %s ))DYNAMIC_TXPWR\n",
570 ((dm->support_ability & ODM_BB_DYNAMIC_TXPWR) ?
571 ("V") :
572 (".")));
573 PHYDM_SNPRINTF(output + used, out_len - used,
574 "03. (( %s ))FA_CNT\n",
575 ((dm->support_ability & ODM_BB_FA_CNT) ? ("V") :
576 (".")));
577 PHYDM_SNPRINTF(output + used, out_len - used,
578 "04. (( %s ))RSSI_MONITOR\n",
579 ((dm->support_ability & ODM_BB_RSSI_MONITOR) ?
580 ("V") :
581 (".")));
582 PHYDM_SNPRINTF(output + used, out_len - used,
583 "05. (( %s ))CCK_PD\n",
584 ((dm->support_ability & ODM_BB_CCK_PD) ? ("V") :
585 (".")));
586 PHYDM_SNPRINTF(
587 output + used, out_len - used, "06. (( %s ))ANT_DIV\n",
588 ((dm->support_ability & ODM_BB_ANT_DIV) ? ("V") :
589 (".")));
590 PHYDM_SNPRINTF(output + used, out_len - used,
591 "08. (( %s ))PWR_TRAIN\n",
592 ((dm->support_ability & ODM_BB_PWR_TRAIN) ?
593 ("V") :
594 (".")));
595 PHYDM_SNPRINTF(output + used, out_len - used,
596 "09. (( %s ))RATE_ADAPTIVE\n",
597 ((dm->support_ability & ODM_BB_RATE_ADAPTIVE) ?
598 ("V") :
599 (".")));
600 PHYDM_SNPRINTF(
601 output + used, out_len - used, "10. (( %s ))PATH_DIV\n",
602 ((dm->support_ability & ODM_BB_PATH_DIV) ? ("V") :
603 (".")));
604 PHYDM_SNPRINTF(output + used, out_len - used,
605 "13. (( %s ))ADAPTIVITY\n",
606 ((dm->support_ability & ODM_BB_ADAPTIVITY) ?
607 ("V") :
608 (".")));
609 PHYDM_SNPRINTF(output + used, out_len - used,
610 "14. (( %s ))struct cfo_tracking\n",
611 ((dm->support_ability & ODM_BB_CFO_TRACKING) ?
612 ("V") :
613 (".")));
614 PHYDM_SNPRINTF(
615 output + used, out_len - used, "15. (( %s ))NHM_CNT\n",
616 ((dm->support_ability & ODM_BB_NHM_CNT) ? ("V") :
617 (".")));
618 PHYDM_SNPRINTF(output + used, out_len - used,
619 "16. (( %s ))PRIMARY_CCA\n",
620 ((dm->support_ability & ODM_BB_PRIMARY_CCA) ?
621 ("V") :
622 (".")));
623 PHYDM_SNPRINTF(
624 output + used, out_len - used, "17. (( %s ))TXBF\n",
625 ((dm->support_ability & ODM_BB_TXBF) ? ("V") : (".")));
626 PHYDM_SNPRINTF(output + used, out_len - used,
627 "18. (( %s ))DYNAMIC_ARFR\n",
628 ((dm->support_ability & ODM_BB_DYNAMIC_ARFR) ?
629 ("V") :
630 (".")));
631 PHYDM_SNPRINTF(output + used, out_len - used,
632 "20. (( %s ))EDCA_TURBO\n",
633 ((dm->support_ability & ODM_MAC_EDCA_TURBO) ?
634 ("V") :
635 (".")));
636 PHYDM_SNPRINTF(output + used, out_len - used,
637 "21. (( %s ))DYNAMIC_RX_PATH\n",
638 ((dm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ?
639 ("V") :
640 (".")));
641 PHYDM_SNPRINTF(output + used, out_len - used,
642 "24. (( %s ))TX_PWR_TRACK\n",
643 ((dm->support_ability & ODM_RF_TX_PWR_TRACK) ?
644 ("V") :
645 (".")));
646 PHYDM_SNPRINTF(output + used, out_len - used,
647 "25. (( %s ))RX_GAIN_TRACK\n",
648 ((dm->support_ability & ODM_RF_RX_GAIN_TRACK) ?
649 ("V") :
650 (".")));
651 PHYDM_SNPRINTF(output + used, out_len - used,
652 "26. (( %s ))RF_CALIBRATION\n",
653 ((dm->support_ability & ODM_RF_CALIBRATION) ?
654 ("V") :
655 (".")));
656 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
657 "================================");
658 } else {
659 if (dm_value[1] == 1) { /* enable */
660 dm->support_ability |= BIT(dm_value[0]);
661 } else if (dm_value[1] == 2) /* disable */
662 dm->support_ability &= ~(BIT(dm_value[0]));
663 else {
664 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
665 "[Warning!!!] 1:enable, 2:disable");
666 }
667 }
668 PHYDM_SNPRINTF(output + used, out_len - used,
669 "pre-support_ability = 0x%x\n", pre_support_ability);
670 PHYDM_SNPRINTF(output + used, out_len - used,
671 "Curr-support_ability = 0x%x\n", dm->support_ability);
672 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
673 "================================");
674}
675
676void phydm_watchdog_mp(struct phy_dm_struct *dm) {}
677/*
678 * 2011/09/20 MH This is the entry pointer for all team to execute HW outsrc DM.
679 * You can not add any dummy function here, be care, you can only use DM struct
680 * to perform any new ODM_DM.
681 */
682void odm_dm_watchdog(struct phy_dm_struct *dm)
683{
684 odm_common_info_self_update(dm);
685 phydm_basic_dbg_message(dm);
686 odm_hw_setting(dm);
687
688 odm_false_alarm_counter_statistics(dm);
689 phydm_noisy_detection(dm);
690
691 odm_rssi_monitor_check(dm);
692
693 if (*dm->is_power_saving) {
694 odm_dig_by_rssi_lps(dm);
695 phydm_adaptivity(dm);
696 odm_antenna_diversity(
697 dm); /*enable AntDiv in PS mode, request from SD4 Jeff*/
698 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
699 "DMWatchdog in power saving mode\n");
700 return;
701 }
702
703 phydm_check_adaptivity(dm);
704 odm_update_power_training_state(dm);
705 odm_DIG(dm);
706 phydm_adaptivity(dm);
707 odm_cck_packet_detection_thresh(dm);
708
709 phydm_ra_info_watchdog(dm);
710 odm_edca_turbo_check(dm);
711 odm_cfo_tracking(dm);
712 odm_dynamic_tx_power(dm);
713 odm_antenna_diversity(dm);
714
715 phydm_beamforming_watchdog(dm);
716
717 phydm_rf_watchdog(dm);
718
719 odm_dtc(dm);
720
721 odm_common_info_self_reset(dm);
722}
723
724/*
725 * Init /.. Fixed HW value. Only init time.
726 */
727void odm_cmn_info_init(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
728 u32 value)
729{
730 /* This section is used for init value */
731 switch (cmn_info) {
732 /* Fixed ODM value. */
733 case ODM_CMNINFO_ABILITY:
734 dm->support_ability = (u32)value;
735 break;
736
737 case ODM_CMNINFO_RF_TYPE:
738 dm->rf_type = (u8)value;
739 break;
740
741 case ODM_CMNINFO_PLATFORM:
742 dm->support_platform = (u8)value;
743 break;
744
745 case ODM_CMNINFO_INTERFACE:
746 dm->support_interface = (u8)value;
747 break;
748
749 case ODM_CMNINFO_MP_TEST_CHIP:
750 dm->is_mp_chip = (u8)value;
751 break;
752
753 case ODM_CMNINFO_IC_TYPE:
754 dm->support_ic_type = value;
755 break;
756
757 case ODM_CMNINFO_CUT_VER:
758 dm->cut_version = (u8)value;
759 break;
760
761 case ODM_CMNINFO_FAB_VER:
762 dm->fab_version = (u8)value;
763 break;
764
765 case ODM_CMNINFO_RFE_TYPE:
766 dm->rfe_type = (u8)value;
767 phydm_init_hw_info_by_rfe(dm);
768 break;
769
770 case ODM_CMNINFO_RF_ANTENNA_TYPE:
771 dm->ant_div_type = (u8)value;
772 break;
773
774 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
775 dm->with_extenal_ant_switch = (u8)value;
776 break;
777
778 case ODM_CMNINFO_BE_FIX_TX_ANT:
779 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
780 break;
781
782 case ODM_CMNINFO_BOARD_TYPE:
783 if (!dm->is_init_hw_info_by_rfe)
784 dm->board_type = (u8)value;
785 break;
786
787 case ODM_CMNINFO_PACKAGE_TYPE:
788 if (!dm->is_init_hw_info_by_rfe)
789 dm->package_type = (u8)value;
790 break;
791
792 case ODM_CMNINFO_EXT_LNA:
793 if (!dm->is_init_hw_info_by_rfe)
794 dm->ext_lna = (u8)value;
795 break;
796
797 case ODM_CMNINFO_5G_EXT_LNA:
798 if (!dm->is_init_hw_info_by_rfe)
799 dm->ext_lna_5g = (u8)value;
800 break;
801
802 case ODM_CMNINFO_EXT_PA:
803 if (!dm->is_init_hw_info_by_rfe)
804 dm->ext_pa = (u8)value;
805 break;
806
807 case ODM_CMNINFO_5G_EXT_PA:
808 if (!dm->is_init_hw_info_by_rfe)
809 dm->ext_pa_5g = (u8)value;
810 break;
811
812 case ODM_CMNINFO_GPA:
813 if (!dm->is_init_hw_info_by_rfe)
814 dm->type_gpa = (u16)value;
815 break;
816
817 case ODM_CMNINFO_APA:
818 if (!dm->is_init_hw_info_by_rfe)
819 dm->type_apa = (u16)value;
820 break;
821
822 case ODM_CMNINFO_GLNA:
823 if (!dm->is_init_hw_info_by_rfe)
824 dm->type_glna = (u16)value;
825 break;
826
827 case ODM_CMNINFO_ALNA:
828 if (!dm->is_init_hw_info_by_rfe)
829 dm->type_alna = (u16)value;
830 break;
831
832 case ODM_CMNINFO_EXT_TRSW:
833 if (!dm->is_init_hw_info_by_rfe)
834 dm->ext_trsw = (u8)value;
835 break;
836 case ODM_CMNINFO_EXT_LNA_GAIN:
837 dm->ext_lna_gain = (u8)value;
838 break;
839 case ODM_CMNINFO_PATCH_ID:
840 dm->patch_id = (u8)value;
841 break;
842 case ODM_CMNINFO_BINHCT_TEST:
843 dm->is_in_hct_test = (bool)value;
844 break;
845 case ODM_CMNINFO_BWIFI_TEST:
846 dm->wifi_test = (u8)value;
847 break;
848 case ODM_CMNINFO_SMART_CONCURRENT:
849 dm->is_dual_mac_smart_concurrent = (bool)value;
850 break;
851 case ODM_CMNINFO_DOMAIN_CODE_2G:
852 dm->odm_regulation_2_4g = (u8)value;
853 break;
854 case ODM_CMNINFO_DOMAIN_CODE_5G:
855 dm->odm_regulation_5g = (u8)value;
856 break;
857 case ODM_CMNINFO_CONFIG_BB_RF:
858 dm->config_bbrf = (bool)value;
859 break;
860 case ODM_CMNINFO_IQKFWOFFLOAD:
861 dm->iqk_fw_offload = (u8)value;
862 break;
863 case ODM_CMNINFO_IQKPAOFF:
864 dm->rf_calibrate_info.is_iqk_pa_off = (bool)value;
865 break;
866 case ODM_CMNINFO_REGRFKFREEENABLE:
867 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
868 break;
869 case ODM_CMNINFO_RFKFREEENABLE:
870 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
871 break;
872 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
873 dm->normal_rx_path = (u8)value;
874 break;
875 case ODM_CMNINFO_EFUSE0X3D8:
876 dm->efuse0x3d8 = (u8)value;
877 break;
878 case ODM_CMNINFO_EFUSE0X3D7:
879 dm->efuse0x3d7 = (u8)value;
880 break;
881 /* To remove the compiler warning, must add an empty default statement
882 * to handle the other values.
883 */
884 default:
885 /* do nothing */
886 break;
887 }
888}
889
890void odm_cmn_info_hook(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
891 void *value)
892{
893 /* */
894 /* Hook call by reference pointer. */
895 /* */
896 switch (cmn_info) {
897 /* */
898 /* Dynamic call by reference pointer. */
899 /* */
900 case ODM_CMNINFO_MAC_PHY_MODE:
901 dm->mac_phy_mode = (u8 *)value;
902 break;
903
904 case ODM_CMNINFO_TX_UNI:
905 dm->num_tx_bytes_unicast = (u64 *)value;
906 break;
907
908 case ODM_CMNINFO_RX_UNI:
909 dm->num_rx_bytes_unicast = (u64 *)value;
910 break;
911
912 case ODM_CMNINFO_WM_MODE:
913 dm->wireless_mode = (u8 *)value;
914 break;
915
916 case ODM_CMNINFO_BAND:
917 dm->band_type = (u8 *)value;
918 break;
919
920 case ODM_CMNINFO_SEC_CHNL_OFFSET:
921 dm->sec_ch_offset = (u8 *)value;
922 break;
923
924 case ODM_CMNINFO_SEC_MODE:
925 dm->security = (u8 *)value;
926 break;
927
928 case ODM_CMNINFO_BW:
929 dm->band_width = (u8 *)value;
930 break;
931
932 case ODM_CMNINFO_CHNL:
933 dm->channel = (u8 *)value;
934 break;
935
936 case ODM_CMNINFO_DMSP_GET_VALUE:
937 dm->is_get_value_from_other_mac = (bool *)value;
938 break;
939
940 case ODM_CMNINFO_BUDDY_ADAPTOR:
941 dm->buddy_adapter = (void **)value;
942 break;
943
944 case ODM_CMNINFO_DMSP_IS_MASTER:
945 dm->is_master_of_dmsp = (bool *)value;
946 break;
947
948 case ODM_CMNINFO_SCAN:
949 dm->is_scan_in_process = (bool *)value;
950 break;
951
952 case ODM_CMNINFO_POWER_SAVING:
953 dm->is_power_saving = (bool *)value;
954 break;
955
956 case ODM_CMNINFO_ONE_PATH_CCA:
957 dm->one_path_cca = (u8 *)value;
958 break;
959
960 case ODM_CMNINFO_DRV_STOP:
961 dm->is_driver_stopped = (bool *)value;
962 break;
963
964 case ODM_CMNINFO_PNP_IN:
965 dm->is_driver_is_going_to_pnp_set_power_sleep = (bool *)value;
966 break;
967
968 case ODM_CMNINFO_INIT_ON:
969 dm->pinit_adpt_in_progress = (bool *)value;
970 break;
971
972 case ODM_CMNINFO_ANT_TEST:
973 dm->antenna_test = (u8 *)value;
974 break;
975
976 case ODM_CMNINFO_NET_CLOSED:
977 dm->is_net_closed = (bool *)value;
978 break;
979
980 case ODM_CMNINFO_FORCED_RATE:
981 dm->forced_data_rate = (u16 *)value;
982 break;
983 case ODM_CMNINFO_ANT_DIV:
984 dm->enable_antdiv = (u8 *)value;
985 break;
986 case ODM_CMNINFO_ADAPTIVITY:
987 dm->enable_adaptivity = (u8 *)value;
988 break;
989 case ODM_CMNINFO_FORCED_IGI_LB:
990 dm->pu1_forced_igi_lb = (u8 *)value;
991 break;
992
993 case ODM_CMNINFO_P2P_LINK:
994 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
995 break;
996
997 case ODM_CMNINFO_IS1ANTENNA:
998 dm->is_1_antenna = (bool *)value;
999 break;
1000
1001 case ODM_CMNINFO_RFDEFAULTPATH:
1002 dm->rf_default_path = (u8 *)value;
1003 break;
1004
1005 case ODM_CMNINFO_FCS_MODE:
1006 dm->is_fcs_mode_enable = (bool *)value;
1007 break;
1008 /*add by YuChen for beamforming PhyDM*/
1009 case ODM_CMNINFO_HUBUSBMODE:
1010 dm->hub_usb_mode = (u8 *)value;
1011 break;
1012 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
1013 dm->is_fw_dw_rsvd_page_in_progress = (bool *)value;
1014 break;
1015 case ODM_CMNINFO_TX_TP:
1016 dm->current_tx_tp = (u32 *)value;
1017 break;
1018 case ODM_CMNINFO_RX_TP:
1019 dm->current_rx_tp = (u32 *)value;
1020 break;
1021 case ODM_CMNINFO_SOUNDING_SEQ:
1022 dm->sounding_seq = (u8 *)value;
1023 break;
1024 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
1025 dm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)value;
1026 break;
1027 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
1028 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
1029 break;
1030
1031 default:
1032 /*do nothing*/
1033 break;
1034 }
1035}
1036
1037void odm_cmn_info_ptr_array_hook(struct phy_dm_struct *dm,
1038 enum odm_cmninfo cmn_info, u16 index,
1039 void *value)
1040{
1041 /*Hook call by reference pointer.*/
1042 switch (cmn_info) {
1043 /*Dynamic call by reference pointer. */
1044 case ODM_CMNINFO_STA_STATUS:
1045 dm->odm_sta_info[index] = (struct rtl_sta_info *)value;
1046
1047 if (IS_STA_VALID(dm->odm_sta_info[index]))
1048 dm->platform2phydm_macid_table[index] = index;
1049
1050 break;
1051 /* To remove the compiler warning, must add an empty default statement
1052 * to handle the other values.
1053 */
1054 default:
1055 /* do nothing */
1056 break;
1057 }
1058}
1059
1060/*
1061 * Update band/CHannel/.. The values are dynamic but non-per-packet.
1062 */
1063void odm_cmn_info_update(struct phy_dm_struct *dm, u32 cmn_info, u64 value)
1064{
1065 /* This init variable may be changed in run time. */
1066 switch (cmn_info) {
1067 case ODM_CMNINFO_LINK_IN_PROGRESS:
1068 dm->is_link_in_process = (bool)value;
1069 break;
1070
1071 case ODM_CMNINFO_ABILITY:
1072 dm->support_ability = (u32)value;
1073 break;
1074
1075 case ODM_CMNINFO_RF_TYPE:
1076 dm->rf_type = (u8)value;
1077 break;
1078
1079 case ODM_CMNINFO_WIFI_DIRECT:
1080 dm->is_wifi_direct = (bool)value;
1081 break;
1082
1083 case ODM_CMNINFO_WIFI_DISPLAY:
1084 dm->is_wifi_display = (bool)value;
1085 break;
1086
1087 case ODM_CMNINFO_LINK:
1088 dm->is_linked = (bool)value;
1089 break;
1090
1091 case ODM_CMNINFO_CMW500LINK:
1092 dm->is_linkedcmw500 = (bool)value;
1093 break;
1094
1095 case ODM_CMNINFO_LPSPG:
1096 dm->is_in_lps_pg = (bool)value;
1097 break;
1098
1099 case ODM_CMNINFO_STATION_STATE:
1100 dm->bsta_state = (bool)value;
1101 break;
1102
1103 case ODM_CMNINFO_RSSI_MIN:
1104 dm->rssi_min = (u8)value;
1105 break;
1106
1107 case ODM_CMNINFO_DBG_COMP:
1108 dm->debug_components = (u32)value;
1109 break;
1110
1111 case ODM_CMNINFO_DBG_LEVEL:
1112 dm->debug_level = (u32)value;
1113 break;
1114 case ODM_CMNINFO_RA_THRESHOLD_HIGH:
1115 dm->rate_adaptive.high_rssi_thresh = (u8)value;
1116 break;
1117
1118 case ODM_CMNINFO_RA_THRESHOLD_LOW:
1119 dm->rate_adaptive.low_rssi_thresh = (u8)value;
1120 break;
1121 /* The following is for BT HS mode and BT coexist mechanism. */
1122 case ODM_CMNINFO_BT_ENABLED:
1123 dm->is_bt_enabled = (bool)value;
1124 break;
1125
1126 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
1127 dm->is_bt_connect_process = (bool)value;
1128 break;
1129
1130 case ODM_CMNINFO_BT_HS_RSSI:
1131 dm->bt_hs_rssi = (u8)value;
1132 break;
1133
1134 case ODM_CMNINFO_BT_OPERATION:
1135 dm->is_bt_hs_operation = (bool)value;
1136 break;
1137
1138 case ODM_CMNINFO_BT_LIMITED_DIG:
1139 dm->is_bt_limited_dig = (bool)value;
1140 break;
1141
1142 case ODM_CMNINFO_BT_DIG:
1143 dm->bt_hs_dig_val = (u8)value;
1144 break;
1145
1146 case ODM_CMNINFO_BT_BUSY:
1147 dm->is_bt_busy = (bool)value;
1148 break;
1149
1150 case ODM_CMNINFO_BT_DISABLE_EDCA:
1151 dm->is_bt_disable_edca_turbo = (bool)value;
1152 break;
1153
1154 case ODM_CMNINFO_AP_TOTAL_NUM:
1155 dm->ap_total_num = (u8)value;
1156 break;
1157
1158 case ODM_CMNINFO_POWER_TRAINING:
1159 dm->is_disable_power_training = (bool)value;
1160 break;
1161
1162 default:
1163 /* do nothing */
1164 break;
1165 }
1166}
1167
1168u32 phydm_cmn_info_query(struct phy_dm_struct *dm,
1169 enum phydm_info_query info_type)
1170{
1171 struct false_alarm_stat *false_alm_cnt =
1172 (struct false_alarm_stat *)phydm_get_structure(
1173 dm, PHYDM_FALSEALMCNT);
1174
1175 switch (info_type) {
1176 case PHYDM_INFO_FA_OFDM:
1177 return false_alm_cnt->cnt_ofdm_fail;
1178
1179 case PHYDM_INFO_FA_CCK:
1180 return false_alm_cnt->cnt_cck_fail;
1181
1182 case PHYDM_INFO_FA_TOTAL:
1183 return false_alm_cnt->cnt_all;
1184
1185 case PHYDM_INFO_CCA_OFDM:
1186 return false_alm_cnt->cnt_ofdm_cca;
1187
1188 case PHYDM_INFO_CCA_CCK:
1189 return false_alm_cnt->cnt_cck_cca;
1190
1191 case PHYDM_INFO_CCA_ALL:
1192 return false_alm_cnt->cnt_cca_all;
1193
1194 case PHYDM_INFO_CRC32_OK_VHT:
1195 return false_alm_cnt->cnt_vht_crc32_ok;
1196
1197 case PHYDM_INFO_CRC32_OK_HT:
1198 return false_alm_cnt->cnt_ht_crc32_ok;
1199
1200 case PHYDM_INFO_CRC32_OK_LEGACY:
1201 return false_alm_cnt->cnt_ofdm_crc32_ok;
1202
1203 case PHYDM_INFO_CRC32_OK_CCK:
1204 return false_alm_cnt->cnt_cck_crc32_ok;
1205
1206 case PHYDM_INFO_CRC32_ERROR_VHT:
1207 return false_alm_cnt->cnt_vht_crc32_error;
1208
1209 case PHYDM_INFO_CRC32_ERROR_HT:
1210 return false_alm_cnt->cnt_ht_crc32_error;
1211
1212 case PHYDM_INFO_CRC32_ERROR_LEGACY:
1213 return false_alm_cnt->cnt_ofdm_crc32_error;
1214
1215 case PHYDM_INFO_CRC32_ERROR_CCK:
1216 return false_alm_cnt->cnt_cck_crc32_error;
1217
1218 case PHYDM_INFO_EDCCA_FLAG:
1219 return false_alm_cnt->edcca_flag;
1220
1221 case PHYDM_INFO_OFDM_ENABLE:
1222 return false_alm_cnt->ofdm_block_enable;
1223
1224 case PHYDM_INFO_CCK_ENABLE:
1225 return false_alm_cnt->cck_block_enable;
1226
1227 case PHYDM_INFO_DBG_PORT_0:
1228 return false_alm_cnt->dbg_port0;
1229
1230 default:
1231 return 0xffffffff;
1232 }
1233}
1234
1235void odm_init_all_timers(struct phy_dm_struct *dm) {}
1236
1237void odm_cancel_all_timers(struct phy_dm_struct *dm) {}
1238
1239void odm_release_all_timers(struct phy_dm_struct *dm) {}
1240
1241/* 3============================================================
1242 * 3 Tx Power Tracking
1243 * 3============================================================
1244 */
1245
1246/* need to ODM CE Platform
1247 * move to here for ANT detection mechanism using
1248 */
1249
1250u32 odm_convert_to_db(u32 value)
1251{
1252 u8 i;
1253 u8 j;
1254 u32 dB;
1255
1256 value = value & 0xFFFF;
1257
1258 for (i = 0; i < 12; i++) {
1259 if (value <= db_invert_table[i][7])
1260 break;
1261 }
1262
1263 if (i >= 12)
1264 return 96; /* maximum 96 dB */
1265
1266 for (j = 0; j < 8; j++) {
1267 if (value <= db_invert_table[i][j])
1268 break;
1269 }
1270
1271 dB = (i << 3) + j + 1;
1272
1273 return dB;
1274}
1275
1276u32 odm_convert_to_linear(u32 value)
1277{
1278 u8 i;
1279 u8 j;
1280 u32 linear;
1281
1282 /* 1dB~96dB */
1283
1284 value = value & 0xFF;
1285
1286 i = (u8)((value - 1) >> 3);
1287 j = (u8)(value - 1) - (i << 3);
1288
1289 linear = db_invert_table[i][j];
1290
1291 return linear;
1292}
1293
1294/*
1295 * ODM multi-port consideration, added by Roger, 2013.10.01.
1296 */
1297void odm_asoc_entry_init(struct phy_dm_struct *dm) {}
1298
1299/* Justin: According to the current RRSI to adjust Response Frame TX power */
1300void odm_dtc(struct phy_dm_struct *dm) {}
1301
1302static void odm_update_power_training_state(struct phy_dm_struct *dm)
1303{
1304 struct false_alarm_stat *false_alm_cnt =
1305 (struct false_alarm_stat *)phydm_get_structure(
1306 dm, PHYDM_FALSEALMCNT);
1307 struct dig_thres *dig_tab = &dm->dm_dig_table;
1308 u32 score = 0;
1309
1310 if (!(dm->support_ability & ODM_BB_PWR_TRAIN))
1311 return;
1312
1313 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "%s()============>\n", __func__);
1314 dm->is_change_state = false;
1315
1316 /* Debug command */
1317 if (dm->force_power_training_state) {
1318 if (dm->force_power_training_state == 1 &&
1319 !dm->is_disable_power_training) {
1320 dm->is_change_state = true;
1321 dm->is_disable_power_training = true;
1322 } else if (dm->force_power_training_state == 2 &&
1323 dm->is_disable_power_training) {
1324 dm->is_change_state = true;
1325 dm->is_disable_power_training = false;
1326 }
1327
1328 dm->PT_score = 0;
1329 dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
1330 dm->phy_dbg_info.num_qry_phy_status_cck = 0;
1331 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1332 "%s(): force_power_training_state = %d\n",
1333 __func__, dm->force_power_training_state);
1334 return;
1335 }
1336
1337 if (!dm->is_linked)
1338 return;
1339
1340 /* First connect */
1341 if ((dm->is_linked) && !dig_tab->is_media_connect_0) {
1342 dm->PT_score = 0;
1343 dm->is_change_state = true;
1344 dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
1345 dm->phy_dbg_info.num_qry_phy_status_cck = 0;
1346 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "%s(): First Connect\n",
1347 __func__);
1348 return;
1349 }
1350
1351 /* Compute score */
1352 if (dm->nhm_cnt_0 >= 215) {
1353 score = 2;
1354 } else if (dm->nhm_cnt_0 >= 190) {
1355 score = 1; /* unknown state */
1356 } else {
1357 u32 rx_pkt_cnt;
1358
1359 rx_pkt_cnt = (u32)(dm->phy_dbg_info.num_qry_phy_status_ofdm) +
1360 (u32)(dm->phy_dbg_info.num_qry_phy_status_cck);
1361
1362 if ((false_alm_cnt->cnt_cca_all > 31 && rx_pkt_cnt > 31) &&
1363 (false_alm_cnt->cnt_cca_all >= rx_pkt_cnt)) {
1364 if ((rx_pkt_cnt + (rx_pkt_cnt >> 1)) <=
1365 false_alm_cnt->cnt_cca_all)
1366 score = 0;
1367 else if ((rx_pkt_cnt + (rx_pkt_cnt >> 2)) <=
1368 false_alm_cnt->cnt_cca_all)
1369 score = 1;
1370 else
1371 score = 2;
1372 }
1373 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1374 "%s(): rx_pkt_cnt = %d, cnt_cca_all = %d\n",
1375 __func__, rx_pkt_cnt, false_alm_cnt->cnt_cca_all);
1376 }
1377 ODM_RT_TRACE(
1378 dm, ODM_COMP_RA_MASK,
1379 "%s(): num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n",
1380 __func__, (u32)(dm->phy_dbg_info.num_qry_phy_status_ofdm),
1381 (u32)(dm->phy_dbg_info.num_qry_phy_status_cck));
1382 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "%s(): nhm_cnt_0 = %d, score = %d\n",
1383 __func__, dm->nhm_cnt_0, score);
1384
1385 /* smoothing */
1386 dm->PT_score = (score << 4) + (dm->PT_score >> 1) + (dm->PT_score >> 2);
1387 score = (dm->PT_score + 32) >> 6;
1388 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1389 "%s(): PT_score = %d, score after smoothing = %d\n",
1390 __func__, dm->PT_score, score);
1391
1392 /* mode decision */
1393 if (score == 2) {
1394 if (dm->is_disable_power_training) {
1395 dm->is_change_state = true;
1396 dm->is_disable_power_training = false;
1397 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1398 "%s(): Change state\n", __func__);
1399 }
1400 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1401 "%s(): Enable Power Training\n", __func__);
1402 } else if (score == 0) {
1403 if (!dm->is_disable_power_training) {
1404 dm->is_change_state = true;
1405 dm->is_disable_power_training = true;
1406 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1407 "%s(): Change state\n", __func__);
1408 }
1409 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1410 "%s(): Disable Power Training\n", __func__);
1411 }
1412
1413 dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
1414 dm->phy_dbg_info.num_qry_phy_status_cck = 0;
1415}
1416
1417/*===========================================================*/
1418/* The following is for compile only*/
1419/*===========================================================*/
1420/*#define TARGET_CHNL_NUM_2G_5G 59*/
1421/*===========================================================*/
1422
1423void phydm_noisy_detection(struct phy_dm_struct *dm)
1424{
1425 u32 total_fa_cnt, total_cca_cnt;
1426 u32 score = 0, i, score_smooth;
1427
1428 total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
1429 total_fa_cnt = dm->false_alm_cnt.cnt_all;
1430
1431 for (i = 0; i <= 16; i++) {
1432 if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
1433 score = 16 - i;
1434 break;
1435 }
1436 }
1437
1438 /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
1439 dm->noisy_decision_smooth =
1440 (dm->noisy_decision_smooth >> 1) + (score << 2);
1441
1442 /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
1443 score_smooth = (total_cca_cnt >= 300) ?
1444 ((dm->noisy_decision_smooth + 3) >> 3) :
1445 0;
1446
1447 dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
1448 ODM_RT_TRACE(
1449 dm, ODM_COMP_NOISY_DETECT,
1450 "[NoisyDetection] total_cca_cnt=%d, total_fa_cnt=%d, noisy_decision_smooth=%d, score=%d, score_smooth=%d, dm->noisy_decision=%d\n",
1451 total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
1452 score_smooth, dm->noisy_decision);
1453}
1454
1455void phydm_set_ext_switch(void *dm_void, u32 *const dm_value, u32 *_used,
1456 char *output, u32 *_out_len)
1457{
1458 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1459 u32 ext_ant_switch = dm_value[0];
1460
1461 if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
1462 /*Output Pin Settings*/
1463 odm_set_mac_reg(dm, 0x4C, BIT(23),
1464 0); /*select DPDT_P and DPDT_N as output pin*/
1465 odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /*by WLAN control*/
1466
1467 odm_set_bb_reg(dm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/
1468 odm_set_bb_reg(dm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/
1469
1470 if (ext_ant_switch == MAIN_ANT) {
1471 odm_set_bb_reg(dm, 0xCB4, (BIT(29) | BIT(28)), 1);
1472 ODM_RT_TRACE(
1473 dm, ODM_COMP_API,
1474 "***8821A set ant switch = 2b'01 (Main)\n");
1475 } else if (ext_ant_switch == AUX_ANT) {
1476 odm_set_bb_reg(dm, 0xCB4, BIT(29) | BIT(28), 2);
1477 ODM_RT_TRACE(dm, ODM_COMP_API,
1478 "***8821A set ant switch = 2b'10 (Aux)\n");
1479 }
1480 }
1481}
1482
1483static void phydm_csi_mask_enable(void *dm_void, u32 enable)
1484{
1485 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1486 u32 reg_value = 0;
1487
1488 reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0;
1489
1490 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1491 odm_set_bb_reg(dm, 0xD2C, BIT(28), reg_value);
1492 ODM_RT_TRACE(dm, ODM_COMP_API,
1493 "Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n",
1494 reg_value);
1495
1496 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1497 odm_set_bb_reg(dm, 0x874, BIT(0), reg_value);
1498 ODM_RT_TRACE(dm, ODM_COMP_API,
1499 "Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n",
1500 reg_value);
1501 }
1502}
1503
1504static void phydm_clean_all_csi_mask(void *dm_void)
1505{
1506 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1507
1508 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1509 odm_set_bb_reg(dm, 0xD40, MASKDWORD, 0);
1510 odm_set_bb_reg(dm, 0xD44, MASKDWORD, 0);
1511 odm_set_bb_reg(dm, 0xD48, MASKDWORD, 0);
1512 odm_set_bb_reg(dm, 0xD4c, MASKDWORD, 0);
1513
1514 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1515 odm_set_bb_reg(dm, 0x880, MASKDWORD, 0);
1516 odm_set_bb_reg(dm, 0x884, MASKDWORD, 0);
1517 odm_set_bb_reg(dm, 0x888, MASKDWORD, 0);
1518 odm_set_bb_reg(dm, 0x88c, MASKDWORD, 0);
1519 odm_set_bb_reg(dm, 0x890, MASKDWORD, 0);
1520 odm_set_bb_reg(dm, 0x894, MASKDWORD, 0);
1521 odm_set_bb_reg(dm, 0x898, MASKDWORD, 0);
1522 odm_set_bb_reg(dm, 0x89c, MASKDWORD, 0);
1523 }
1524}
1525
1526static void phydm_set_csi_mask_reg(void *dm_void, u32 tone_idx_tmp,
1527 u8 tone_direction)
1528{
1529 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1530 u8 byte_offset, bit_offset;
1531 u32 target_reg;
1532 u8 reg_tmp_value;
1533 u32 tone_num = 64;
1534 u32 tone_num_shift = 0;
1535 u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
1536
1537 /* calculate real tone idx*/
1538 if ((tone_idx_tmp % 10) >= 5)
1539 tone_idx_tmp += 10;
1540
1541 tone_idx_tmp = (tone_idx_tmp / 10);
1542
1543 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1544 tone_num = 64;
1545 csi_mask_reg_p = 0xD40;
1546 csi_mask_reg_n = 0xD48;
1547
1548 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1549 tone_num = 128;
1550 csi_mask_reg_p = 0x880;
1551 csi_mask_reg_n = 0x890;
1552 }
1553
1554 if (tone_direction == FREQ_POSITIVE) {
1555 if (tone_idx_tmp >= (tone_num - 1))
1556 tone_idx_tmp = (tone_num - 1);
1557
1558 byte_offset = (u8)(tone_idx_tmp >> 3);
1559 bit_offset = (u8)(tone_idx_tmp & 0x7);
1560 target_reg = csi_mask_reg_p + byte_offset;
1561
1562 } else {
1563 tone_num_shift = tone_num;
1564
1565 if (tone_idx_tmp >= tone_num)
1566 tone_idx_tmp = tone_num;
1567
1568 tone_idx_tmp = tone_num - tone_idx_tmp;
1569
1570 byte_offset = (u8)(tone_idx_tmp >> 3);
1571 bit_offset = (u8)(tone_idx_tmp & 0x7);
1572 target_reg = csi_mask_reg_n + byte_offset;
1573 }
1574
1575 reg_tmp_value = odm_read_1byte(dm, target_reg);
1576 ODM_RT_TRACE(dm, ODM_COMP_API,
1577 "Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
1578 (tone_idx_tmp + tone_num_shift), target_reg,
1579 reg_tmp_value);
1580 reg_tmp_value |= BIT(bit_offset);
1581 odm_write_1byte(dm, target_reg, reg_tmp_value);
1582 ODM_RT_TRACE(dm, ODM_COMP_API,
1583 "New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
1584 (tone_idx_tmp + tone_num_shift), target_reg,
1585 reg_tmp_value);
1586}
1587
1588static void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)
1589{
1590 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1591 u32 nbi_table_128[NBI_TABLE_SIZE_128] = {
1592 25, 55, 85, 115, 135, 155, 185, 205, 225, 245,
1593 /*1~10*/ /*tone_idx X 10*/
1594 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/
1595 485, 505, 525, 555, 585, 615, 635}; /*21~27*/
1596
1597 u32 nbi_table_256[NBI_TABLE_SIZE_256] = {
1598 25, 55, 85, 115, 135, 155, 175, 195, 225,
1599 245, /*1~10*/
1600 265, 285, 305, 325, 345, 365, 385, 405, 425,
1601 445, /*11~20*/
1602 465, 485, 505, 525, 545, 565, 585, 605, 625,
1603 645, /*21~30*/
1604 665, 695, 715, 735, 755, 775, 795, 815, 835,
1605 855, /*31~40*/
1606 875, 895, 915, 935, 955, 975, 995, 1015, 1035,
1607 1055, /*41~50*/
1608 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275}; /*51~59*/
1609
1610 u32 reg_idx = 0;
1611 u32 i;
1612 u8 nbi_table_idx = FFT_128_TYPE;
1613
1614 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1615 nbi_table_idx = FFT_128_TYPE;
1616 } else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {
1617 nbi_table_idx = FFT_256_TYPE;
1618 } else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
1619 if (bw == 80)
1620 nbi_table_idx = FFT_256_TYPE;
1621 else /*20M, 40M*/
1622 nbi_table_idx = FFT_128_TYPE;
1623 }
1624
1625 if (nbi_table_idx == FFT_128_TYPE) {
1626 for (i = 0; i < NBI_TABLE_SIZE_128; i++) {
1627 if (tone_idx_tmp < nbi_table_128[i]) {
1628 reg_idx = i + 1;
1629 break;
1630 }
1631 }
1632
1633 } else if (nbi_table_idx == FFT_256_TYPE) {
1634 for (i = 0; i < NBI_TABLE_SIZE_256; i++) {
1635 if (tone_idx_tmp < nbi_table_256[i]) {
1636 reg_idx = i + 1;
1637 break;
1638 }
1639 }
1640 }
1641
1642 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1643 odm_set_bb_reg(dm, 0xc40, 0x1f000000, reg_idx);
1644 ODM_RT_TRACE(dm, ODM_COMP_API,
1645 "Set tone idx: Reg0xC40[28:24] = ((0x%x))\n",
1646 reg_idx);
1647 /**/
1648 } else {
1649 odm_set_bb_reg(dm, 0x87c, 0xfc000, reg_idx);
1650 ODM_RT_TRACE(dm, ODM_COMP_API,
1651 "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n",
1652 reg_idx);
1653 /**/
1654 }
1655}
1656
1657static void phydm_nbi_enable(void *dm_void, u32 enable)
1658{
1659 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1660 u32 reg_value = 0;
1661
1662 reg_value = (enable == NBI_ENABLE) ? 1 : 0;
1663
1664 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1665 odm_set_bb_reg(dm, 0xc40, BIT(9), reg_value);
1666 ODM_RT_TRACE(dm, ODM_COMP_API,
1667 "Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value);
1668
1669 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1670 odm_set_bb_reg(dm, 0x87c, BIT(13), reg_value);
1671 ODM_RT_TRACE(dm, ODM_COMP_API,
1672 "Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value);
1673 }
1674}
1675
1676static u8 phydm_calculate_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch,
1677 u32 *fc_in)
1678{
1679 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1680 u32 fc = *fc_in;
1681 u32 start_ch_per_40m[NUM_START_CH_40M + 1] = {
1682 36, 44, 52, 60, 100, 108, 116, 124,
1683 132, 140, 149, 157, 165, 173, 173 + 8,
1684 };
1685 u32 start_ch_per_80m[NUM_START_CH_80M + 1] = {
1686 36, 52, 100, 116, 132, 149, 165, 165 + 16,
1687 };
1688 u32 *start_ch = &start_ch_per_40m[0];
1689 u32 num_start_channel = NUM_START_CH_40M;
1690 u32 channel_offset = 0;
1691 u32 i;
1692
1693 /*2.4G*/
1694 if (channel <= 14 && channel > 0) {
1695 if (bw == 80)
1696 return SET_ERROR;
1697
1698 fc = 2412 + (channel - 1) * 5;
1699
1700 if (bw == 40 && (second_ch == PHYDM_ABOVE)) {
1701 if (channel >= 10) {
1702 ODM_RT_TRACE(
1703 dm, ODM_COMP_API,
1704 "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1705 channel, second_ch);
1706 return SET_ERROR;
1707 }
1708 fc += 10;
1709 } else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
1710 if (channel <= 2) {
1711 ODM_RT_TRACE(
1712 dm, ODM_COMP_API,
1713 "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1714 channel, second_ch);
1715 return SET_ERROR;
1716 }
1717 fc -= 10;
1718 }
1719 }
1720 /*5G*/
1721 else if (channel >= 36 && channel <= 177) {
1722 if (bw == 20) {
1723 fc = 5180 + (channel - 36) * 5;
1724 *fc_in = fc;
1725 return SET_SUCCESS;
1726 }
1727
1728 if (bw == 40) {
1729 num_start_channel = NUM_START_CH_40M;
1730 start_ch = &start_ch_per_40m[0];
1731 channel_offset = CH_OFFSET_40M;
1732 } else if (bw == 80) {
1733 num_start_channel = NUM_START_CH_80M;
1734 start_ch = &start_ch_per_80m[0];
1735 channel_offset = CH_OFFSET_80M;
1736 }
1737
1738 for (i = 0; i < num_start_channel; i++) {
1739 if (channel < start_ch[i + 1]) {
1740 channel = start_ch[i] + channel_offset;
1741 break;
1742 }
1743 }
1744
1745 ODM_RT_TRACE(dm, ODM_COMP_API, "Mod_CH = ((%d))\n", channel);
1746
1747 fc = 5180 + (channel - 36) * 5;
1748
1749 } else {
1750 ODM_RT_TRACE(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n",
1751 channel);
1752 return SET_ERROR;
1753 }
1754
1755 *fc_in = fc;
1756
1757 return SET_SUCCESS;
1758}
1759
1760static u8 phydm_calculate_intf_distance(void *dm_void, u32 bw, u32 fc,
1761 u32 f_interference,
1762 u32 *tone_idx_tmp_in)
1763{
1764 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1765 u32 bw_up, bw_low;
1766 u32 int_distance;
1767 u32 tone_idx_tmp;
1768 u8 set_result = SET_NO_NEED;
1769
1770 bw_up = fc + bw / 2;
1771 bw_low = fc - bw / 2;
1772
1773 ODM_RT_TRACE(dm, ODM_COMP_API,
1774 "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
1775 fc, bw_up, f_interference);
1776
1777 if ((f_interference >= bw_low) && (f_interference <= bw_up)) {
1778 int_distance = (fc >= f_interference) ? (fc - f_interference) :
1779 (f_interference - fc);
1780 tone_idx_tmp =
1781 (int_distance << 5); /* =10*(int_distance /0.3125) */
1782 ODM_RT_TRACE(
1783 dm, ODM_COMP_API,
1784 "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n",
1785 int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10));
1786 *tone_idx_tmp_in = tone_idx_tmp;
1787 set_result = SET_SUCCESS;
1788 }
1789
1790 return set_result;
1791}
1792
1793static u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
1794 u32 f_interference, u32 second_ch)
1795{
1796 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1797 u32 fc;
1798 u8 tone_direction;
1799 u32 tone_idx_tmp;
1800 u8 set_result = SET_SUCCESS;
1801
1802 if (enable == CSI_MASK_DISABLE) {
1803 set_result = SET_SUCCESS;
1804 phydm_clean_all_csi_mask(dm);
1805
1806 } else {
1807 ODM_RT_TRACE(
1808 dm, ODM_COMP_API,
1809 "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1810 channel, bw, f_interference,
1811 (((bw == 20) || (channel > 14)) ?
1812 "Don't care" :
1813 (second_ch == PHYDM_ABOVE) ? "H" : "L"));
1814
1815 /*calculate fc*/
1816 if (phydm_calculate_fc(dm, channel, bw, second_ch, &fc) ==
1817 SET_ERROR) {
1818 set_result = SET_ERROR;
1819 } else {
1820 /*calculate interference distance*/
1821 if (phydm_calculate_intf_distance(
1822 dm, bw, fc, f_interference,
1823 &tone_idx_tmp) == SET_SUCCESS) {
1824 tone_direction = (f_interference >= fc) ?
1825 FREQ_POSITIVE :
1826 FREQ_NEGATIVE;
1827 phydm_set_csi_mask_reg(dm, tone_idx_tmp,
1828 tone_direction);
1829 set_result = SET_SUCCESS;
1830 } else {
1831 set_result = SET_NO_NEED;
1832 }
1833 }
1834 }
1835
1836 if (set_result == SET_SUCCESS)
1837 phydm_csi_mask_enable(dm, enable);
1838 else
1839 phydm_csi_mask_enable(dm, CSI_MASK_DISABLE);
1840
1841 return set_result;
1842}
1843
1844u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
1845 u32 f_interference, u32 second_ch)
1846{
1847 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1848 u32 fc;
1849 u32 tone_idx_tmp;
1850 u8 set_result = SET_SUCCESS;
1851
1852 if (enable == NBI_DISABLE) {
1853 set_result = SET_SUCCESS;
1854 } else {
1855 ODM_RT_TRACE(
1856 dm, ODM_COMP_API,
1857 "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1858 channel, bw, f_interference,
1859 (((second_ch == PHYDM_DONT_CARE) || (bw == 20) ||
1860 (channel > 14)) ?
1861 "Don't care" :
1862 (second_ch == PHYDM_ABOVE) ? "H" : "L"));
1863
1864 /*calculate fc*/
1865 if (phydm_calculate_fc(dm, channel, bw, second_ch, &fc) ==
1866 SET_ERROR) {
1867 set_result = SET_ERROR;
1868 } else {
1869 /*calculate interference distance*/
1870 if (phydm_calculate_intf_distance(
1871 dm, bw, fc, f_interference,
1872 &tone_idx_tmp) == SET_SUCCESS) {
1873 phydm_set_nbi_reg(dm, tone_idx_tmp, bw);
1874 set_result = SET_SUCCESS;
1875 } else {
1876 set_result = SET_NO_NEED;
1877 }
1878 }
1879 }
1880
1881 if (set_result == SET_SUCCESS)
1882 phydm_nbi_enable(dm, enable);
1883 else
1884 phydm_nbi_enable(dm, NBI_DISABLE);
1885
1886 return set_result;
1887}
1888
1889void phydm_api_debug(void *dm_void, u32 function_map, u32 *const dm_value,
1890 u32 *_used, char *output, u32 *_out_len)
1891{
1892 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1893 u32 used = *_used;
1894 u32 out_len = *_out_len;
1895 u32 channel = dm_value[1];
1896 u32 bw = dm_value[2];
1897 u32 f_interference = dm_value[3];
1898 u32 second_ch = dm_value[4];
1899 u8 set_result = 0;
1900
1901 /*PHYDM_API_NBI*/
1902 /*--------------------------------------------------------------------*/
1903 if (function_map == PHYDM_API_NBI) {
1904 if (dm_value[0] == 100) {
1905 PHYDM_SNPRINTF(
1906 output + used, out_len - used,
1907 "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n");
1908 return;
1909
1910 } else if (dm_value[0] == NBI_ENABLE) {
1911 PHYDM_SNPRINTF(
1912 output + used, out_len - used,
1913 "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1914 channel, bw, f_interference,
1915 ((second_ch == PHYDM_DONT_CARE) || (bw == 20) ||
1916 (channel > 14)) ?
1917 "Don't care" :
1918 ((second_ch == PHYDM_ABOVE) ? "H" :
1919 "L"));
1920 set_result =
1921 phydm_nbi_setting(dm, NBI_ENABLE, channel, bw,
1922 f_interference, second_ch);
1923
1924 } else if (dm_value[0] == NBI_DISABLE) {
1925 PHYDM_SNPRINTF(output + used, out_len - used,
1926 "[Disable NBI]\n");
1927 set_result =
1928 phydm_nbi_setting(dm, NBI_DISABLE, channel, bw,
1929 f_interference, second_ch);
1930
1931 } else {
1932 set_result = SET_ERROR;
1933 }
1934
1935 PHYDM_SNPRINTF(
1936 output + used, out_len - used, "[NBI set result: %s]\n",
1937 (set_result == SET_SUCCESS) ?
1938 "Success" :
1939 ((set_result == SET_NO_NEED) ? "No need" :
1940 "Error"));
1941 }
1942
1943 /*PHYDM_CSI_MASK*/
1944 /*--------------------------------------------------------------------*/
1945 else if (function_map == PHYDM_API_CSI_MASK) {
1946 if (dm_value[0] == 100) {
1947 PHYDM_SNPRINTF(
1948 output + used, out_len - used,
1949 "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n");
1950 return;
1951
1952 } else if (dm_value[0] == CSI_MASK_ENABLE) {
1953 PHYDM_SNPRINTF(
1954 output + used, out_len - used,
1955 "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1956 channel, bw, f_interference,
1957 (channel > 14) ?
1958 "Don't care" :
1959 (((second_ch == PHYDM_DONT_CARE) ||
1960 (bw == 20) || (channel > 14)) ?
1961 "H" :
1962 "L"));
1963 set_result = phydm_csi_mask_setting(
1964 dm, CSI_MASK_ENABLE, channel, bw,
1965 f_interference, second_ch);
1966
1967 } else if (dm_value[0] == CSI_MASK_DISABLE) {
1968 PHYDM_SNPRINTF(output + used, out_len - used,
1969 "[Disable CSI MASK]\n");
1970 set_result = phydm_csi_mask_setting(
1971 dm, CSI_MASK_DISABLE, channel, bw,
1972 f_interference, second_ch);
1973
1974 } else {
1975 set_result = SET_ERROR;
1976 }
1977
1978 PHYDM_SNPRINTF(output + used, out_len - used,
1979 "[CSI MASK set result: %s]\n",
1980 (set_result == SET_SUCCESS) ?
1981 "Success" :
1982 ((set_result == SET_NO_NEED) ?
1983 "No need" :
1984 "Error"));
1985 }
1986}
diff --git a/drivers/staging/rtlwifi/phydm/phydm.h b/drivers/staging/rtlwifi/phydm/phydm.h
new file mode 100644
index 000000000000..5812ff427ead
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm.h
@@ -0,0 +1,946 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __HALDMOUTSRC_H__
27#define __HALDMOUTSRC_H__
28
29/*============================================================*/
30/*include files*/
31/*============================================================*/
32#include "phydm_pre_define.h"
33#include "phydm_dig.h"
34#include "phydm_edcaturbocheck.h"
35#include "phydm_antdiv.h"
36#include "phydm_dynamicbbpowersaving.h"
37#include "phydm_rainfo.h"
38#include "phydm_dynamictxpower.h"
39#include "phydm_cfotracking.h"
40#include "phydm_acs.h"
41#include "phydm_adaptivity.h"
42#include "phydm_iqk.h"
43#include "phydm_dfs.h"
44#include "phydm_ccx.h"
45#include "txbf/phydm_hal_txbf_api.h"
46
47#include "phydm_adc_sampling.h"
48#include "phydm_dynamic_rx_path.h"
49#include "phydm_psd.h"
50
51#include "phydm_beamforming.h"
52
53#include "phydm_noisemonitor.h"
54#include "halphyrf_ce.h"
55
56/*============================================================*/
57/*Definition */
58/*============================================================*/
59
60/* Traffic load decision */
61#define TRAFFIC_ULTRA_LOW 1
62#define TRAFFIC_LOW 2
63#define TRAFFIC_MID 3
64#define TRAFFIC_HIGH 4
65
66#define NONE 0
67
68/*NBI API------------------------------------*/
69#define NBI_ENABLE 1
70#define NBI_DISABLE 2
71
72#define NBI_TABLE_SIZE_128 27
73#define NBI_TABLE_SIZE_256 59
74
75#define NUM_START_CH_80M 7
76#define NUM_START_CH_40M 14
77
78#define CH_OFFSET_40M 2
79#define CH_OFFSET_80M 6
80
81/*CSI MASK API------------------------------------*/
82#define CSI_MASK_ENABLE 1
83#define CSI_MASK_DISABLE 2
84
85/*------------------------------------------------*/
86
87#define FFT_128_TYPE 1
88#define FFT_256_TYPE 2
89
90#define SET_SUCCESS 1
91#define SET_ERROR 2
92#define SET_NO_NEED 3
93
94#define FREQ_POSITIVE 1
95#define FREQ_NEGATIVE 2
96
97#define PHYDM_WATCH_DOG_PERIOD 2
98
99/*============================================================*/
100/*structure and define*/
101/*============================================================*/
102
103/*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/
104/*We need to remove to other position???*/
105
106struct rtl8192cd_priv {
107 u8 temp;
108};
109
110struct dyn_primary_cca {
111 u8 pri_cca_flag;
112 u8 intf_flag;
113 u8 intf_type;
114 u8 dup_rts_flag;
115 u8 monitor_flag;
116 u8 ch_offset;
117 u8 mf_state;
118};
119
120#define dm_type_by_fw 0
121#define dm_type_by_driver 1
122
123/*Declare for common info*/
124
125#define IQK_THRESHOLD 8
126#define DPK_THRESHOLD 4
127
128struct dm_phy_status_info {
129 /* */
130 /* Be care, if you want to add any element please insert between */
131 /* rx_pwdb_all & signal_strength. */
132 /* */
133 u8 rx_pwdb_all;
134 u8 signal_quality; /* in 0-100 index. */
135 s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */
136 u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */
137 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
138 s16 cfo_short[4]; /* per-path's cfo_short */
139 s16 cfo_tail[4]; /* per-path's cfo_tail */
140 s8 rx_power; /* in dBm Translate from PWdB */
141 s8 recv_signal_power; /* Real power in dBm for this packet,
142 * no beautification and aggregation.
143 * Keep this raw info to be used for the other
144 * procedures.
145 */
146 u8 bt_rx_rssi_percentage;
147 u8 signal_strength; /* in 0-100 index. */
148 s8 rx_pwr[4]; /* per-path's pwdb */
149 s8 rx_snr[4]; /* per-path's SNR */
150 /* s8 BB_Backup[13]; backup reg. */
151 u8 rx_count : 2; /* RX path counter---*/
152 u8 band_width : 2;
153 u8 rxsc : 4; /* sub-channel---*/
154 u8 bt_coex_pwr_adjust;
155 u8 channel; /* channel number---*/
156 bool is_mu_packet; /* is MU packet or not---*/
157 bool is_beamformed; /* BF packet---*/
158};
159
160struct dm_per_pkt_info {
161 u8 data_rate;
162 u8 station_id;
163 bool is_packet_match_bssid;
164 bool is_packet_to_self;
165 bool is_packet_beacon;
166 bool is_to_self;
167 u8 ppdu_cnt;
168};
169
170struct odm_phy_dbg_info {
171 /*ODM Write,debug info*/
172 s8 rx_snr_db[4];
173 u32 num_qry_phy_status;
174 u32 num_qry_phy_status_cck;
175 u32 num_qry_phy_status_ofdm;
176 u32 num_qry_mu_pkt;
177 u32 num_qry_bf_pkt;
178 u32 num_qry_mu_vht_pkt[40];
179 u32 num_qry_vht_pkt[40];
180 bool is_ldpc_pkt;
181 bool is_stbc_pkt;
182 u8 num_of_ppdu[4];
183 u8 gid_num[4];
184 u8 num_qry_beacon_pkt;
185 /* Others */
186 s32 rx_evm[4];
187};
188
189/*2011/20/20 MH For MP driver RT_WLAN_STA = struct rtl_sta_info*/
190/*Please declare below ODM relative info in your STA info structure.*/
191
192struct odm_sta_info {
193 /*Driver Write*/
194 bool is_used; /*record the sta status link or not?*/
195 u8 iot_peer; /*Enum value. HT_IOT_PEER_E*/
196
197 /*ODM Write*/
198 /*PHY_STATUS_INFO*/
199 u8 rssi_path[4];
200 u8 rssi_ave;
201 u8 RXEVM[4];
202 u8 RXSNR[4];
203};
204
205enum odm_cmninfo {
206 /*Fixed value*/
207 /*-----------HOOK BEFORE REG INIT-----------*/
208 ODM_CMNINFO_PLATFORM = 0,
209 ODM_CMNINFO_ABILITY,
210 ODM_CMNINFO_INTERFACE,
211 ODM_CMNINFO_MP_TEST_CHIP,
212 ODM_CMNINFO_IC_TYPE,
213 ODM_CMNINFO_CUT_VER,
214 ODM_CMNINFO_FAB_VER,
215 ODM_CMNINFO_RF_TYPE,
216 ODM_CMNINFO_RFE_TYPE,
217 ODM_CMNINFO_BOARD_TYPE,
218 ODM_CMNINFO_PACKAGE_TYPE,
219 ODM_CMNINFO_EXT_LNA,
220 ODM_CMNINFO_5G_EXT_LNA,
221 ODM_CMNINFO_EXT_PA,
222 ODM_CMNINFO_5G_EXT_PA,
223 ODM_CMNINFO_GPA,
224 ODM_CMNINFO_APA,
225 ODM_CMNINFO_GLNA,
226 ODM_CMNINFO_ALNA,
227 ODM_CMNINFO_EXT_TRSW,
228 ODM_CMNINFO_DPK_EN,
229 ODM_CMNINFO_EXT_LNA_GAIN,
230 ODM_CMNINFO_PATCH_ID,
231 ODM_CMNINFO_BINHCT_TEST,
232 ODM_CMNINFO_BWIFI_TEST,
233 ODM_CMNINFO_SMART_CONCURRENT,
234 ODM_CMNINFO_CONFIG_BB_RF,
235 ODM_CMNINFO_DOMAIN_CODE_2G,
236 ODM_CMNINFO_DOMAIN_CODE_5G,
237 ODM_CMNINFO_IQKFWOFFLOAD,
238 ODM_CMNINFO_IQKPAOFF,
239 ODM_CMNINFO_HUBUSBMODE,
240 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
241 ODM_CMNINFO_TX_TP,
242 ODM_CMNINFO_RX_TP,
243 ODM_CMNINFO_SOUNDING_SEQ,
244 ODM_CMNINFO_REGRFKFREEENABLE,
245 ODM_CMNINFO_RFKFREEENABLE,
246 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
247 ODM_CMNINFO_EFUSE0X3D8,
248 ODM_CMNINFO_EFUSE0X3D7,
249 /*-----------HOOK BEFORE REG INIT-----------*/
250
251 /*Dynamic value:*/
252
253 /*--------- POINTER REFERENCE-----------*/
254 ODM_CMNINFO_MAC_PHY_MODE,
255 ODM_CMNINFO_TX_UNI,
256 ODM_CMNINFO_RX_UNI,
257 ODM_CMNINFO_WM_MODE,
258 ODM_CMNINFO_BAND,
259 ODM_CMNINFO_SEC_CHNL_OFFSET,
260 ODM_CMNINFO_SEC_MODE,
261 ODM_CMNINFO_BW,
262 ODM_CMNINFO_CHNL,
263 ODM_CMNINFO_FORCED_RATE,
264 ODM_CMNINFO_ANT_DIV,
265 ODM_CMNINFO_ADAPTIVITY,
266 ODM_CMNINFO_DMSP_GET_VALUE,
267 ODM_CMNINFO_BUDDY_ADAPTOR,
268 ODM_CMNINFO_DMSP_IS_MASTER,
269 ODM_CMNINFO_SCAN,
270 ODM_CMNINFO_POWER_SAVING,
271 ODM_CMNINFO_ONE_PATH_CCA,
272 ODM_CMNINFO_DRV_STOP,
273 ODM_CMNINFO_PNP_IN,
274 ODM_CMNINFO_INIT_ON,
275 ODM_CMNINFO_ANT_TEST,
276 ODM_CMNINFO_NET_CLOSED,
277 ODM_CMNINFO_FORCED_IGI_LB,
278 ODM_CMNINFO_P2P_LINK,
279 ODM_CMNINFO_FCS_MODE,
280 ODM_CMNINFO_IS1ANTENNA,
281 ODM_CMNINFO_RFDEFAULTPATH,
282 ODM_CMNINFO_DFS_MASTER_ENABLE,
283 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
284 ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
285 /*--------- POINTER REFERENCE-----------*/
286
287 /*------------CALL BY VALUE-------------*/
288 ODM_CMNINFO_WIFI_DIRECT,
289 ODM_CMNINFO_WIFI_DISPLAY,
290 ODM_CMNINFO_LINK_IN_PROGRESS,
291 ODM_CMNINFO_LINK,
292 ODM_CMNINFO_CMW500LINK,
293 ODM_CMNINFO_LPSPG,
294 ODM_CMNINFO_STATION_STATE,
295 ODM_CMNINFO_RSSI_MIN,
296 ODM_CMNINFO_DBG_COMP,
297 ODM_CMNINFO_DBG_LEVEL,
298 ODM_CMNINFO_RA_THRESHOLD_HIGH,
299 ODM_CMNINFO_RA_THRESHOLD_LOW,
300 ODM_CMNINFO_RF_ANTENNA_TYPE,
301 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
302 ODM_CMNINFO_BE_FIX_TX_ANT,
303 ODM_CMNINFO_BT_ENABLED,
304 ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
305 ODM_CMNINFO_BT_HS_RSSI,
306 ODM_CMNINFO_BT_OPERATION,
307 ODM_CMNINFO_BT_LIMITED_DIG,
308 ODM_CMNINFO_BT_DIG,
309 ODM_CMNINFO_BT_BUSY,
310 ODM_CMNINFO_BT_DISABLE_EDCA,
311 ODM_CMNINFO_AP_TOTAL_NUM,
312 ODM_CMNINFO_POWER_TRAINING,
313 ODM_CMNINFO_DFS_REGION_DOMAIN,
314 /*------------CALL BY VALUE-------------*/
315
316 /*Dynamic ptr array hook itms.*/
317 ODM_CMNINFO_STA_STATUS,
318 ODM_CMNINFO_MAX,
319
320};
321
322enum phydm_info_query {
323 PHYDM_INFO_FA_OFDM,
324 PHYDM_INFO_FA_CCK,
325 PHYDM_INFO_FA_TOTAL,
326 PHYDM_INFO_CCA_OFDM,
327 PHYDM_INFO_CCA_CCK,
328 PHYDM_INFO_CCA_ALL,
329 PHYDM_INFO_CRC32_OK_VHT,
330 PHYDM_INFO_CRC32_OK_HT,
331 PHYDM_INFO_CRC32_OK_LEGACY,
332 PHYDM_INFO_CRC32_OK_CCK,
333 PHYDM_INFO_CRC32_ERROR_VHT,
334 PHYDM_INFO_CRC32_ERROR_HT,
335 PHYDM_INFO_CRC32_ERROR_LEGACY,
336 PHYDM_INFO_CRC32_ERROR_CCK,
337 PHYDM_INFO_EDCCA_FLAG,
338 PHYDM_INFO_OFDM_ENABLE,
339 PHYDM_INFO_CCK_ENABLE,
340 PHYDM_INFO_DBG_PORT_0
341};
342
343enum phydm_api {
344 PHYDM_API_NBI = 1,
345 PHYDM_API_CSI_MASK,
346
347};
348
349/*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/
350enum odm_ability {
351 /*BB ODM section BIT 0-19*/
352 ODM_BB_DIG = BIT(0),
353 ODM_BB_RA_MASK = BIT(1),
354 ODM_BB_DYNAMIC_TXPWR = BIT(2),
355 ODM_BB_FA_CNT = BIT(3),
356 ODM_BB_RSSI_MONITOR = BIT(4),
357 ODM_BB_CCK_PD = BIT(5),
358 ODM_BB_ANT_DIV = BIT(6),
359 ODM_BB_PWR_TRAIN = BIT(8),
360 ODM_BB_RATE_ADAPTIVE = BIT(9),
361 ODM_BB_PATH_DIV = BIT(10),
362 ODM_BB_ADAPTIVITY = BIT(13),
363 ODM_BB_CFO_TRACKING = BIT(14),
364 ODM_BB_NHM_CNT = BIT(15),
365 ODM_BB_PRIMARY_CCA = BIT(16),
366 ODM_BB_TXBF = BIT(17),
367 ODM_BB_DYNAMIC_ARFR = BIT(18),
368
369 ODM_MAC_EDCA_TURBO = BIT(20),
370 ODM_BB_DYNAMIC_RX_PATH = BIT(21),
371
372 /*RF ODM section BIT 24-31*/
373 ODM_RF_TX_PWR_TRACK = BIT(24),
374 ODM_RF_RX_GAIN_TRACK = BIT(25),
375 ODM_RF_CALIBRATION = BIT(26),
376
377};
378
379/*ODM_CMNINFO_ONE_PATH_CCA*/
380enum odm_cca_path {
381 ODM_CCA_2R = 0,
382 ODM_CCA_1R_A = 1,
383 ODM_CCA_1R_B = 2,
384};
385
386enum cca_pathdiv_en {
387 CCA_PATHDIV_DISABLE = 0,
388 CCA_PATHDIV_ENABLE = 1,
389
390};
391
392enum phy_reg_pg_type {
393 PHY_REG_PG_RELATIVE_VALUE = 0,
394 PHY_REG_PG_EXACT_VALUE = 1
395};
396
397/*2011/09/22 MH Copy from SD4 defined structure.
398 *We use to support PHY DM integration.
399 */
400
401struct phy_dm_struct {
402 /*Add for different team use temporarily*/
403 void *adapter; /*For CE/NIC team*/
404 struct rtl8192cd_priv *priv; /*For AP/ADSL team*/
405 /*When you use adapter or priv pointer,
406 *you must make sure the pointer is ready.
407 */
408 bool odm_ready;
409
410 struct rtl8192cd_priv fake_priv;
411
412 enum phy_reg_pg_type phy_reg_pg_value_type;
413 u8 phy_reg_pg_version;
414
415 u32 debug_components;
416 u32 fw_debug_components;
417 u32 debug_level;
418
419 u32 num_qry_phy_status_all; /*CCK + OFDM*/
420 u32 last_num_qry_phy_status_all;
421 u32 rx_pwdb_ave;
422 bool MPDIG_2G; /*off MPDIG*/
423 u8 times_2g;
424 bool is_init_hw_info_by_rfe;
425
426 /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
427 bool is_cck_high_power;
428 u8 rf_path_rx_enable;
429 u8 control_channel;
430 /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
431
432 /* 1 COMMON INFORMATION */
433
434 /*Init value*/
435 /*-----------HOOK BEFORE REG INIT-----------*/
436 /*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/
437 u8 support_platform;
438 /* ODM Platform info WIN/AP/CE = 1/2/3 */
439 u8 normal_rx_path;
440 /*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ... = 1/2/3/...*/
441 u32 support_ability;
442 /*ODM PCIE/USB/SDIO = 1/2/3*/
443 u8 support_interface;
444 /*ODM composite or independent. Bit oriented/ 92C+92D+ .... or
445 *any other type = 1/2/3/...
446 */
447 u32 support_ic_type;
448 /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
449 u8 cut_version;
450 /*Fab version TSMC/UMC = 0/1*/
451 u8 fab_version;
452 /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
453 u8 rf_type;
454 u8 rfe_type;
455 /*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/
456 /*Enable Function DPK OFF/ON = 0/1*/
457 u8 dpk_en;
458 u8 board_type;
459 u8 package_type;
460 u16 type_glna;
461 u16 type_gpa;
462 u16 type_alna;
463 u16 type_apa;
464 /*with external LNA NO/Yes = 0/1*/
465 u8 ext_lna; /*2G*/
466 u8 ext_lna_5g; /*5G*/
467 /*with external PA NO/Yes = 0/1*/
468 u8 ext_pa; /*2G*/
469 u8 ext_pa_5g; /*5G*/
470 /*with Efuse number*/
471 u8 efuse0x3d7;
472 u8 efuse0x3d8;
473 /*with external TRSW NO/Yes = 0/1*/
474 u8 ext_trsw;
475 u8 ext_lna_gain; /*2G*/
476 u8 patch_id; /*Customer ID*/
477 bool is_in_hct_test;
478 u8 wifi_test;
479
480 bool is_dual_mac_smart_concurrent;
481 u32 bk_support_ability;
482 u8 ant_div_type;
483 u8 with_extenal_ant_switch;
484 bool config_bbrf;
485 u8 odm_regulation_2_4g;
486 u8 odm_regulation_5g;
487 u8 iqk_fw_offload;
488 bool cck_new_agc;
489 u8 phydm_period;
490 u32 phydm_sys_up_time;
491 u8 num_rf_path;
492 /*-----------HOOK BEFORE REG INIT-----------*/
493
494 /*Dynamic value*/
495
496 /*--------- POINTER REFERENCE-----------*/
497
498 u8 u1_byte_temp;
499 bool BOOLEAN_temp;
500 void *PADAPTER_temp;
501
502 /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/
503 u8 *mac_phy_mode;
504 /*TX Unicast byte count*/
505 u64 *num_tx_bytes_unicast;
506 /*RX Unicast byte count*/
507 u64 *num_rx_bytes_unicast;
508 /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/
509 u8 *wireless_mode;
510 /*Frequence band 2.4G/5G = 0/1*/
511 u8 *band_type;
512 /*Secondary channel offset don't_care/below/above = 0/1/2*/
513 u8 *sec_ch_offset;
514 /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/
515 u8 *security;
516 /*BW info 20M/40M/80M = 0/1/2*/
517 u8 *band_width;
518 /*Central channel location Ch1/Ch2/....*/
519 u8 *channel; /*central channel number*/
520 bool dpk_done;
521 /*Common info for 92D DMSP*/
522
523 bool *is_get_value_from_other_mac;
524 void **buddy_adapter;
525 bool *is_master_of_dmsp; /* MAC0: master, MAC1: slave */
526 /*Common info for status*/
527 bool *is_scan_in_process;
528 bool *is_power_saving;
529 /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
530 u8 *one_path_cca;
531 u8 *antenna_test;
532 bool *is_net_closed;
533 u8 *pu1_forced_igi_lb;
534 bool *is_fcs_mode_enable;
535 /*--------- For 8723B IQK-----------*/
536 bool *is_1_antenna;
537 u8 *rf_default_path;
538 /* 0:S1, 1:S0 */
539
540 /*--------- POINTER REFERENCE-----------*/
541 u16 *forced_data_rate;
542 u8 *enable_antdiv;
543 u8 *enable_adaptivity;
544 u8 *hub_usb_mode;
545 bool *is_fw_dw_rsvd_page_in_progress;
546 u32 *current_tx_tp;
547 u32 *current_rx_tp;
548 u8 *sounding_seq;
549 /*------------CALL BY VALUE-------------*/
550 bool is_link_in_process;
551 bool is_wifi_direct;
552 bool is_wifi_display;
553 bool is_linked;
554 bool is_linkedcmw500;
555 bool is_in_lps_pg;
556 bool bsta_state;
557 u8 rssi_min;
558 u8 interface_index; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/
559 bool is_mp_chip;
560 bool is_one_entry_only;
561 bool mp_mode;
562 u32 one_entry_macid;
563 u8 pre_number_linked_client;
564 u8 number_linked_client;
565 u8 pre_number_active_client;
566 u8 number_active_client;
567 /*Common info for BTDM*/
568 bool is_bt_enabled; /*BT is enabled*/
569 bool is_bt_connect_process; /*BT HS is under connection progress.*/
570 u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/
571 bool is_bt_hs_operation; /*BT HS mode is under progress*/
572 u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/
573 bool is_bt_disable_edca_turbo; /*Under some condition, don't enable*/
574 bool is_bt_busy; /*BT is busy.*/
575 bool is_bt_limited_dig; /*BT is busy.*/
576 bool is_disable_phy_api;
577 /*------------CALL BY VALUE-------------*/
578 u8 rssi_a;
579 u8 rssi_b;
580 u8 rssi_c;
581 u8 rssi_d;
582 u64 rssi_trsw;
583 u64 rssi_trsw_h;
584 u64 rssi_trsw_l;
585 u64 rssi_trsw_iso;
586 u8 tx_ant_status;
587 u8 rx_ant_status;
588 u8 cck_lna_idx;
589 u8 cck_vga_idx;
590 u8 curr_station_id;
591 u8 ofdm_agc_idx[4];
592
593 u8 rx_rate;
594 bool is_noisy_state;
595 u8 tx_rate;
596 u8 linked_interval;
597 u8 pre_channel;
598 u32 txagc_offset_value_a;
599 bool is_txagc_offset_positive_a;
600 u32 txagc_offset_value_b;
601 bool is_txagc_offset_positive_b;
602 u32 tx_tp;
603 u32 rx_tp;
604 u32 total_tp;
605 u64 cur_tx_ok_cnt;
606 u64 cur_rx_ok_cnt;
607 u64 last_tx_ok_cnt;
608 u64 last_rx_ok_cnt;
609 u32 bb_swing_offset_a;
610 bool is_bb_swing_offset_positive_a;
611 u32 bb_swing_offset_b;
612 bool is_bb_swing_offset_positive_b;
613 u8 igi_lower_bound;
614 u8 igi_upper_bound;
615 u8 antdiv_rssi;
616 u8 fat_comb_a;
617 u8 fat_comb_b;
618 u8 antdiv_intvl;
619 u8 ant_type;
620 u8 pre_ant_type;
621 u8 antdiv_period;
622 u8 evm_antdiv_period;
623 u8 antdiv_select;
624 u8 path_select;
625 u8 antdiv_evm_en;
626 u8 bdc_holdstate;
627 u8 ndpa_period;
628 bool h2c_rarpt_connect;
629 bool cck_agc_report_type;
630
631 u8 dm_dig_max_TH;
632 u8 dm_dig_min_TH;
633 u8 print_agc;
634 u8 traffic_load;
635 u8 pre_traffic_load;
636 /*8821C Antenna BTG/WLG/WLA Select*/
637 u8 current_rf_set_8821c;
638 u8 default_rf_set_8821c;
639 /*For Adaptivtiy*/
640 u16 nhm_cnt_0;
641 u16 nhm_cnt_1;
642 s8 TH_L2H_default;
643 s8 th_edcca_hl_diff_default;
644 s8 th_l2h_ini;
645 s8 th_edcca_hl_diff;
646 s8 th_l2h_ini_mode2;
647 s8 th_edcca_hl_diff_mode2;
648 bool carrier_sense_enable;
649 u8 adaptivity_igi_upper;
650 bool adaptivity_flag;
651 u8 dc_backoff;
652 bool adaptivity_enable;
653 u8 ap_total_num;
654 bool edcca_enable;
655 u8 pre_dbg_priority;
656 struct adaptivity_statistics adaptivity;
657 /*For Adaptivtiy*/
658 u8 last_usb_hub;
659 u8 tx_bf_data_rate;
660
661 u8 nbi_set_result;
662
663 u8 c2h_cmd_start;
664 u8 fw_debug_trace[60];
665 u8 pre_c2h_seq;
666 bool fw_buff_is_enpty;
667 u32 data_frame_num;
668
669 /*for noise detection*/
670 bool noisy_decision; /*b_noisy*/
671 bool pre_b_noisy;
672 u32 noisy_decision_smooth;
673 bool is_disable_dym_ecs;
674
675 struct odm_noise_monitor noise_level;
676 /*Define STA info.*/
677 /*odm_sta_info*/
678 /*2012/01/12 MH For MP,
679 *we need to reduce one array pointer for default port.??
680 */
681 struct rtl_sta_info *odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
682 u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];
683 /* platform_macid_table[platform_macid] = phydm_macid */
684 s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM];
685
686 /*2012/02/14 MH Add to share 88E ra with other SW team.*/
687 /*We need to colelct all support abilit to a proper area.*/
688
689 bool ra_support88e;
690
691 struct odm_phy_dbg_info phy_dbg_info;
692
693 /*ODM Structure*/
694 struct fast_antenna_training dm_fat_table;
695 struct dig_thres dm_dig_table;
696 struct dyn_pwr_saving dm_ps_table;
697 struct dyn_primary_cca dm_pri_cca;
698 struct ra_table dm_ra_table;
699 struct false_alarm_stat false_alm_cnt;
700 struct false_alarm_stat flase_alm_cnt_buddy_adapter;
701 struct sw_antenna_switch dm_swat_table;
702 struct cfo_tracking dm_cfo_track;
703 struct acs_info dm_acs;
704 struct ccx_info dm_ccx_info;
705 struct psd_info dm_psd_table;
706
707 struct rt_adcsmp adcsmp;
708
709 struct dm_iqk_info IQK_info;
710
711 struct edca_turbo dm_edca_table;
712 u32 WMMEDCA_BE;
713
714 bool *is_driver_stopped;
715 bool *is_driver_is_going_to_pnp_set_power_sleep;
716 bool *pinit_adpt_in_progress;
717
718 /*PSD*/
719 bool is_user_assign_level;
720 u8 RSSI_BT; /*come from BT*/
721 bool is_psd_in_process;
722 bool is_psd_active;
723 bool is_dm_initial_gain_enable;
724
725 /*MPT DIG*/
726 struct timer_list mpt_dig_timer;
727
728 /*for rate adaptive, in fact, 88c/92c fw will handle this*/
729 u8 is_use_ra_mask;
730
731 /* for dynamic SoML control */
732 bool bsomlenabled;
733
734 struct odm_rate_adaptive rate_adaptive;
735 struct dm_rf_calibration_struct rf_calibrate_info;
736 u32 n_iqk_cnt;
737 u32 n_iqk_ok_cnt;
738 u32 n_iqk_fail_cnt;
739
740 /*Power Training*/
741 u8 force_power_training_state;
742 bool is_change_state;
743 u32 PT_score;
744 u64 ofdm_rx_cnt;
745 u64 cck_rx_cnt;
746 bool is_disable_power_training;
747 u8 dynamic_tx_high_power_lvl;
748 u8 last_dtp_lvl;
749 u32 tx_agc_ofdm_18_6;
750 u8 rx_pkt_type;
751
752 /*ODM relative time.*/
753 struct timer_list path_div_switch_timer;
754 /*2011.09.27 add for path Diversity*/
755 struct timer_list cck_path_diversity_timer;
756 struct timer_list fast_ant_training_timer;
757 struct timer_list sbdcnt_timer;
758
759 /*ODM relative workitem.*/
760};
761
762enum phydm_structure_type {
763 PHYDM_FALSEALMCNT,
764 PHYDM_CFOTRACK,
765 PHYDM_ADAPTIVITY,
766 PHYDM_ROMINFO,
767
768};
769
770enum odm_rf_content {
771 odm_radioa_txt = 0x1000,
772 odm_radiob_txt = 0x1001,
773 odm_radioc_txt = 0x1002,
774 odm_radiod_txt = 0x1003
775};
776
777enum odm_bb_config_type {
778 CONFIG_BB_PHY_REG,
779 CONFIG_BB_AGC_TAB,
780 CONFIG_BB_AGC_TAB_2G,
781 CONFIG_BB_AGC_TAB_5G,
782 CONFIG_BB_PHY_REG_PG,
783 CONFIG_BB_PHY_REG_MP,
784 CONFIG_BB_AGC_TAB_DIFF,
785};
786
787enum odm_rf_config_type {
788 CONFIG_RF_RADIO,
789 CONFIG_RF_TXPWR_LMT,
790};
791
792enum odm_fw_config_type {
793 CONFIG_FW_NIC,
794 CONFIG_FW_NIC_2,
795 CONFIG_FW_AP,
796 CONFIG_FW_AP_2,
797 CONFIG_FW_MP,
798 CONFIG_FW_WOWLAN,
799 CONFIG_FW_WOWLAN_2,
800 CONFIG_FW_AP_WOWLAN,
801 CONFIG_FW_BT,
802};
803
804/*status code*/
805enum rt_status {
806 RT_STATUS_SUCCESS,
807 RT_STATUS_FAILURE,
808 RT_STATUS_PENDING,
809 RT_STATUS_RESOURCE,
810 RT_STATUS_INVALID_CONTEXT,
811 RT_STATUS_INVALID_PARAMETER,
812 RT_STATUS_NOT_SUPPORT,
813 RT_STATUS_OS_API_FAILED,
814};
815
816/*===========================================================*/
817/*AGC RX High Power mode*/
818/*===========================================================*/
819#define lna_low_gain_1 0x64
820#define lna_low_gain_2 0x5A
821#define lna_low_gain_3 0x58
822
823#define FA_RXHP_TH1 5000
824#define FA_RXHP_TH2 1500
825#define FA_RXHP_TH3 800
826#define FA_RXHP_TH4 600
827#define FA_RXHP_TH5 500
828
829enum dm_1r_cca {
830 CCA_1R = 0,
831 CCA_2R = 1,
832 CCA_MAX = 2,
833};
834
835enum dm_rf {
836 rf_save = 0,
837 rf_normal = 1,
838 RF_MAX = 2,
839};
840
841/*check Sta pointer valid or not*/
842
843#define IS_STA_VALID(sta) (sta)
844
845u32 odm_convert_to_db(u32 value);
846
847u32 odm_convert_to_linear(u32 value);
848
849s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
850
851s32 odm_sign_conversion(s32 value, u32 total_bit);
852
853void odm_init_mp_driver_status(struct phy_dm_struct *dm);
854
855void phydm_txcurrentcalibration(struct phy_dm_struct *dm);
856
857void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
858 u8 seq_length);
859
860void odm_dm_init(struct phy_dm_struct *dm);
861
862void odm_dm_reset(struct phy_dm_struct *dm);
863
864void phydm_support_ability_debug(void *dm_void, u32 *const dm_value, u32 *_used,
865 char *output, u32 *_out_len);
866
867void phydm_config_ofdm_rx_path(struct phy_dm_struct *dm, u32 path);
868
869void phydm_config_trx_path(void *dm_void, u32 *const dm_value, u32 *_used,
870 char *output, u32 *_out_len);
871
872void odm_dm_watchdog(struct phy_dm_struct *dm);
873
874void phydm_watchdog_mp(struct phy_dm_struct *dm);
875
876void odm_cmn_info_init(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
877 u32 value);
878
879void odm_cmn_info_hook(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
880 void *value);
881
882void odm_cmn_info_ptr_array_hook(struct phy_dm_struct *dm,
883 enum odm_cmninfo cmn_info, u16 index,
884 void *value);
885
886void odm_cmn_info_update(struct phy_dm_struct *dm, u32 cmn_info, u64 value);
887
888u32 phydm_cmn_info_query(struct phy_dm_struct *dm,
889 enum phydm_info_query info_type);
890
891void odm_init_all_timers(struct phy_dm_struct *dm);
892
893void odm_cancel_all_timers(struct phy_dm_struct *dm);
894
895void odm_release_all_timers(struct phy_dm_struct *dm);
896
897void odm_asoc_entry_init(struct phy_dm_struct *dm);
898
899void *phydm_get_structure(struct phy_dm_struct *dm, u8 structure_type);
900
901/*===========================================================*/
902/* The following is for compile only*/
903/*===========================================================*/
904
905#define IS_HARDWARE_TYPE_8188E(_adapter) false
906#define IS_HARDWARE_TYPE_8188F(_adapter) false
907#define IS_HARDWARE_TYPE_8703B(_adapter) false
908#define IS_HARDWARE_TYPE_8723D(_adapter) false
909#define IS_HARDWARE_TYPE_8821C(_adapter) false
910#define IS_HARDWARE_TYPE_8812AU(_adapter) false
911#define IS_HARDWARE_TYPE_8814A(_adapter) false
912#define IS_HARDWARE_TYPE_8814AU(_adapter) false
913#define IS_HARDWARE_TYPE_8814AE(_adapter) false
914#define IS_HARDWARE_TYPE_8814AS(_adapter) false
915#define IS_HARDWARE_TYPE_8723BU(_adapter) false
916#define IS_HARDWARE_TYPE_8822BU(_adapter) false
917#define IS_HARDWARE_TYPE_8822BS(_adapter) false
918#define IS_HARDWARE_TYPE_JAGUAR(_adapter) \
919 (IS_HARDWARE_TYPE_8812(_adapter) || IS_HARDWARE_TYPE_8821(_adapter))
920#define IS_HARDWARE_TYPE_8723AE(_adapter) false
921#define IS_HARDWARE_TYPE_8192C(_adapter) false
922#define IS_HARDWARE_TYPE_8192D(_adapter) false
923#define RF_T_METER_92D 0x42
924
925#define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) \
926 LE_BITS_TO_1BYTE(__prx_status_desc + 12, 0, 6)
927
928#define REG_CONFIG_RAM64X16 0xb2c
929
930#define TARGET_CHNL_NUM_2G_5G 59
931
932/* *********************************************************** */
933
934void odm_dtc(struct phy_dm_struct *dm);
935
936void phydm_noisy_detection(struct phy_dm_struct *dm);
937
938void phydm_set_ext_switch(void *dm_void, u32 *const dm_value, u32 *_used,
939 char *output, u32 *_out_len);
940
941void phydm_api_debug(void *dm_void, u32 function_map, u32 *const dm_value,
942 u32 *_used, char *output, u32 *_out_len);
943
944u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
945 u32 f_interference, u32 second_ch);
946#endif /* __HALDMOUTSRC_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/phydm_acs.c b/drivers/staging/rtlwifi/phydm/phydm_acs.c
new file mode 100644
index 000000000000..eae5a0a24b9b
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_acs.c
@@ -0,0 +1,200 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31
32u8 odm_get_auto_channel_select_result(void *dm_void, u8 band)
33{
34 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
35 struct acs_info *acs = &dm->dm_acs;
36 u8 result;
37
38 if (band == ODM_BAND_2_4G) {
39 ODM_RT_TRACE(
40 dm, ODM_COMP_ACS,
41 "[struct acs_info] %s(): clean_channel_2g(%d)\n",
42 __func__, acs->clean_channel_2g);
43 result = (u8)acs->clean_channel_2g;
44 } else {
45 ODM_RT_TRACE(
46 dm, ODM_COMP_ACS,
47 "[struct acs_info] %s(): clean_channel_5g(%d)\n",
48 __func__, acs->clean_channel_5g);
49 result = (u8)acs->clean_channel_5g;
50 }
51
52 return result;
53}
54
55static void odm_auto_channel_select_setting(void *dm_void, bool is_enable)
56{
57 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
58 u16 period = 0x2710; /* 40ms in default */
59 u16 nhm_type = 0x7;
60
61 ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
62
63 if (is_enable) {
64 /* 20 ms */
65 period = 0x1388;
66 nhm_type = 0x1;
67 }
68
69 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
70 /* PHY parameters initialize for ac series */
71
72 /* 0x990[31:16]=0x2710
73 * Time duration for NHM unit: 4us, 0x2710=40ms
74 */
75 odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, period);
76 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
77 /* PHY parameters initialize for n series */
78
79 /* 0x894[31:16]=0x2710
80 * Time duration for NHM unit: 4us, 0x2710=40ms
81 */
82 odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11N + 2, period);
83 }
84}
85
86void odm_auto_channel_select_init(void *dm_void)
87{
88 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
89 struct acs_info *acs = &dm->dm_acs;
90 u8 i;
91
92 if (!(dm->support_ability & ODM_BB_NHM_CNT))
93 return;
94
95 if (acs->is_force_acs_result)
96 return;
97
98 ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
99
100 acs->clean_channel_2g = 1;
101 acs->clean_channel_5g = 36;
102
103 for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) {
104 acs->channel_info_2g[0][i] = 0;
105 acs->channel_info_2g[1][i] = 0;
106 }
107
108 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
109 for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) {
110 acs->channel_info_5g[0][i] = 0;
111 acs->channel_info_5g[1][i] = 0;
112 }
113 }
114}
115
116void odm_auto_channel_select_reset(void *dm_void)
117{
118 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
119 struct acs_info *acs = &dm->dm_acs;
120
121 if (!(dm->support_ability & ODM_BB_NHM_CNT))
122 return;
123
124 if (acs->is_force_acs_result)
125 return;
126
127 ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
128
129 odm_auto_channel_select_setting(dm, true); /* for 20ms measurement */
130 phydm_nhm_counter_statistics_reset(dm);
131}
132
133void odm_auto_channel_select(void *dm_void, u8 channel)
134{
135 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
136 struct acs_info *acs = &dm->dm_acs;
137 u8 channel_idx = 0, search_idx = 0;
138 u16 max_score = 0;
139
140 if (!(dm->support_ability & ODM_BB_NHM_CNT)) {
141 ODM_RT_TRACE(
142 dm, ODM_COMP_DIG,
143 "%s(): Return: support_ability ODM_BB_NHM_CNT is disabled\n",
144 __func__);
145 return;
146 }
147
148 if (acs->is_force_acs_result) {
149 ODM_RT_TRACE(
150 dm, ODM_COMP_DIG,
151 "%s(): Force 2G clean channel = %d, 5G clean channel = %d\n",
152 __func__, acs->clean_channel_2g, acs->clean_channel_5g);
153 return;
154 }
155
156 ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s(): channel = %d=========>\n",
157 __func__, channel);
158
159 phydm_get_nhm_counter_statistics(dm);
160 odm_auto_channel_select_setting(dm, false);
161
162 if (channel >= 1 && channel <= 14) {
163 channel_idx = channel - 1;
164 acs->channel_info_2g[1][channel_idx]++;
165
166 if (acs->channel_info_2g[1][channel_idx] >= 2)
167 acs->channel_info_2g[0][channel_idx] =
168 (acs->channel_info_2g[0][channel_idx] >> 1) +
169 (acs->channel_info_2g[0][channel_idx] >> 2) +
170 (dm->nhm_cnt_0 >> 2);
171 else
172 acs->channel_info_2g[0][channel_idx] = dm->nhm_cnt_0;
173
174 ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s(): nhm_cnt_0 = %d\n",
175 __func__, dm->nhm_cnt_0);
176 ODM_RT_TRACE(
177 dm, ODM_COMP_ACS,
178 "%s(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n",
179 __func__, channel_idx,
180 acs->channel_info_2g[0][channel_idx], channel_idx,
181 acs->channel_info_2g[1][channel_idx]);
182
183 for (search_idx = 0; search_idx < ODM_MAX_CHANNEL_2G;
184 search_idx++) {
185 if (acs->channel_info_2g[1][search_idx] != 0 &&
186 acs->channel_info_2g[0][search_idx] >= max_score) {
187 max_score = acs->channel_info_2g[0][search_idx];
188 acs->clean_channel_2g = search_idx + 1;
189 }
190 }
191 ODM_RT_TRACE(
192 dm, ODM_COMP_ACS,
193 "(1)%s(): 2G: clean_channel_2g = %d, max_score = %d\n",
194 __func__, acs->clean_channel_2g, max_score);
195
196 } else if (channel >= 36) {
197 /* Need to do */
198 acs->clean_channel_5g = channel;
199 }
200}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_acs.h b/drivers/staging/rtlwifi/phydm/phydm_acs.h
new file mode 100644
index 000000000000..51d72b72bd6f
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_acs.h
@@ -0,0 +1,57 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMACS_H__
27#define __PHYDMACS_H__
28
29#define ACS_VERSION "1.1" /*20150729 by YuChen*/
30#define CLM_VERSION "1.0"
31
32#define ODM_MAX_CHANNEL_2G 14
33#define ODM_MAX_CHANNEL_5G 24
34
35/* For phydm_auto_channel_select_setting_ap() */
36#define STORE_DEFAULT_NHM_SETTING 0
37#define RESTORE_DEFAULT_NHM_SETTING 1
38#define ACS_NHM_SETTING 2
39
40struct acs_info {
41 bool is_force_acs_result;
42 u8 clean_channel_2g;
43 u8 clean_channel_5g;
44 /* channel_info[1]: channel score, channel_info[2]:channel_scan_times */
45 u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G];
46 u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G];
47};
48
49void odm_auto_channel_select_init(void *dm_void);
50
51void odm_auto_channel_select_reset(void *dm_void);
52
53void odm_auto_channel_select(void *dm_void, u8 channel);
54
55u8 odm_get_auto_channel_select_result(void *dm_void, u8 band);
56
57#endif /* #ifndef __PHYDMACS_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/phydm_adaptivity.c b/drivers/staging/rtlwifi/phydm/phydm_adaptivity.c
new file mode 100644
index 000000000000..4f9e267409f6
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_adaptivity.c
@@ -0,0 +1,941 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31
32void phydm_check_adaptivity(void *dm_void)
33{
34 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
35 struct adaptivity_statistics *adaptivity =
36 (struct adaptivity_statistics *)phydm_get_structure(
37 dm, PHYDM_ADAPTIVITY);
38
39 if (dm->support_ability & ODM_BB_ADAPTIVITY) {
40 if (adaptivity->dynamic_link_adaptivity ||
41 adaptivity->acs_for_adaptivity) {
42 if (dm->is_linked && !adaptivity->is_check) {
43 phydm_nhm_counter_statistics(dm);
44 phydm_check_environment(dm);
45 } else if (!dm->is_linked) {
46 adaptivity->is_check = false;
47 }
48 } else {
49 dm->adaptivity_enable = true;
50
51 if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA |
52 ODM_IC_11N_GAIN_IDX_EDCCA))
53 dm->adaptivity_flag = false;
54 else
55 dm->adaptivity_flag = true;
56 }
57 } else {
58 dm->adaptivity_enable = false;
59 dm->adaptivity_flag = false;
60 }
61}
62
63void phydm_nhm_counter_statistics_init(void *dm_void)
64{
65 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
66
67 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
68 /*PHY parameters initialize for n series*/
69
70 /*0x894[31:16]=0x0xC350
71 *Time duration for NHM unit: us, 0xc350=200ms
72 */
73 odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11N + 2, 0xC350);
74 /*0x890[31:16]=0xffff th_9, th_10*/
75 odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff);
76 /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/
77 odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50);
78 /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/
79 odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff);
80 /*0xe28[7:0]=0xff th_8*/
81 odm_set_bb_reg(dm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff);
82 /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
83 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N,
84 BIT(10) | BIT(9) | BIT(8), 0x1);
85 /*0xc0c[7]=1 max power among all RX ants*/
86 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1);
87 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
88 /*PHY parameters initialize for ac series*/
89
90 odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, 0xC350);
91 /*0x994[31:16]=0xffff th_9, th_10*/
92 odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff);
93 /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/
94 odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50);
95 /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/
96 odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff);
97 /*0x9a0[7:0]=0xff th_8*/
98 odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff);
99 /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
100 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC,
101 BIT(8) | BIT(9) | BIT(10), 0x1);
102 /*0x9e8[7]=1 max power among all RX ants*/
103 odm_set_bb_reg(dm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1);
104 }
105}
106
107void phydm_nhm_counter_statistics(void *dm_void)
108{
109 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
110
111 if (!(dm->support_ability & ODM_BB_NHM_CNT))
112 return;
113
114 /*Get NHM report*/
115 phydm_get_nhm_counter_statistics(dm);
116
117 /*Reset NHM counter*/
118 phydm_nhm_counter_statistics_reset(dm);
119}
120
121void phydm_get_nhm_counter_statistics(void *dm_void)
122{
123 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
124 u32 value32 = 0;
125
126 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
127 value32 = odm_get_bb_reg(dm, ODM_REG_NHM_CNT_11AC, MASKDWORD);
128 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
129 value32 = odm_get_bb_reg(dm, ODM_REG_NHM_CNT_11N, MASKDWORD);
130
131 dm->nhm_cnt_0 = (u8)(value32 & MASKBYTE0);
132 dm->nhm_cnt_1 = (u8)((value32 & MASKBYTE1) >> 8);
133}
134
135void phydm_nhm_counter_statistics_reset(void *dm_void)
136{
137 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
138
139 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
140 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
141 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
142 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
143 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
144 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
145 }
146}
147
148void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
149{
150 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
151
152 if (dm->support_ic_type & ODM_IC_11N_SERIES)
153 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
154 MASKBYTE2 | MASKBYTE0,
155 (u32)((u8)L2H | (u8)H2L << 16));
156 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
157 odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
158 (u16)((u8)L2H | (u8)H2L << 8));
159}
160
161static void phydm_set_lna(void *dm_void, enum phydm_set_lna type)
162{
163 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
164
165 if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) {
166 if (type == phydm_disable_lna) {
167 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
168 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
169 0x18000); /*select Rx mode*/
170 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
171 0x0000f);
172 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
173 0x37f82); /*disable LNA*/
174 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
175 if (dm->rf_type > ODM_1T1R) {
176 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
177 0x1);
178 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
179 0x18000);
180 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
181 0x0000f);
182 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
183 0x37f82);
184 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
185 0x0);
186 }
187 } else if (type == phydm_enable_lna) {
188 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
189 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
190 0x18000); /*select Rx mode*/
191 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
192 0x0000f);
193 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
194 0x77f82); /*back to normal*/
195 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
196 if (dm->rf_type > ODM_1T1R) {
197 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
198 0x1);
199 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
200 0x18000);
201 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
202 0x0000f);
203 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
204 0x77f82);
205 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
206 0x0);
207 }
208 }
209 } else if (dm->support_ic_type & ODM_RTL8723B) {
210 if (type == phydm_disable_lna) {
211 /*S0*/
212 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
213 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
214 0x18000); /*select Rx mode*/
215 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
216 0x0001f);
217 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
218 0xe6137); /*disable LNA*/
219 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
220 /*S1*/
221 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
222 odm_set_rf_reg(
223 dm, ODM_RF_PATH_A, 0x43, 0xfffff,
224 0x3008d); /*select Rx mode and disable LNA*/
225 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
226 } else if (type == phydm_enable_lna) {
227 /*S0*/
228 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
229 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
230 0x18000); /*select Rx mode*/
231 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
232 0x0001f);
233 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
234 0xe6177); /*disable LNA*/
235 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
236 /*S1*/
237 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
238 odm_set_rf_reg(
239 dm, ODM_RF_PATH_A, 0x43, 0xfffff,
240 0x300bd); /*select Rx mode and disable LNA*/
241 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
242 }
243
244 } else if (dm->support_ic_type & ODM_RTL8812) {
245 if (type == phydm_disable_lna) {
246 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
247 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
248 0x18000); /*select Rx mode*/
249 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
250 0x3f7ff);
251 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
252 0xc22bf); /*disable LNA*/
253 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
254 if (dm->rf_type > ODM_1T1R) {
255 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
256 0x1);
257 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
258 0x18000); /*select Rx mode*/
259 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
260 0x3f7ff);
261 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
262 0xc22bf); /*disable LNA*/
263 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
264 0x0);
265 }
266 } else if (type == phydm_enable_lna) {
267 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
268 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
269 0x18000); /*select Rx mode*/
270 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
271 0x3f7ff);
272 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
273 0xc26bf); /*disable LNA*/
274 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
275 if (dm->rf_type > ODM_1T1R) {
276 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
277 0x1);
278 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
279 0x18000); /*select Rx mode*/
280 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
281 0x3f7ff);
282 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
283 0xc26bf); /*disable LNA*/
284 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
285 0x0);
286 }
287 }
288 } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
289 if (type == phydm_disable_lna) {
290 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
291 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
292 0x18000); /*select Rx mode*/
293 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
294 0x0002f);
295 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
296 0xfb09b); /*disable LNA*/
297 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
298 } else if (type == phydm_enable_lna) {
299 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
300 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
301 0x18000); /*select Rx mode*/
302 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
303 0x0002f);
304 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
305 0xfb0bb); /*disable LNA*/
306 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
307 }
308 }
309}
310
311void phydm_set_trx_mux(void *dm_void, enum phydm_trx_mux_type tx_mode,
312 enum phydm_trx_mux_type rx_mode)
313{
314 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
315
316 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
317 /*set TXmod to standby mode to remove outside noise affect*/
318 odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N,
319 BIT(3) | BIT(2) | BIT(1), tx_mode);
320 /*set RXmod to standby mode to remove outside noise affect*/
321 odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N,
322 BIT(22) | BIT(21) | BIT(20), rx_mode);
323 if (dm->rf_type > ODM_1T1R) {
324 /*set TXmod to standby mode to rm outside noise affect*/
325 odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B,
326 BIT(3) | BIT(2) | BIT(1), tx_mode);
327 /*set RXmod to standby mode to rm outside noise affect*/
328 odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B,
329 BIT(22) | BIT(21) | BIT(20), rx_mode);
330 }
331 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
332 /*set TXmod to standby mode to remove outside noise affect*/
333 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC,
334 BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode);
335 /*set RXmod to standby mode to remove outside noise affect*/
336 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC,
337 BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode);
338 if (dm->rf_type > ODM_1T1R) {
339 /*set TXmod to standby mode to rm outside noise affect*/
340 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B,
341 BIT(11) | BIT(10) | BIT(9) | BIT(8),
342 tx_mode);
343 /*set RXmod to standby mode to rm outside noise affect*/
344 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B,
345 BIT(7) | BIT(6) | BIT(5) | BIT(4),
346 rx_mode);
347 }
348 }
349}
350
351void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
352{
353 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
354
355 if (state == phydm_ignore_edcca) {
356 /*ignore EDCCA reg520[15]=1*/
357 odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 1);
358 } else { /*don't set MAC ignore EDCCA signal*/
359 /*don't ignore EDCCA reg520[15]=0*/
360 odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 0);
361 }
362 ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "EDCCA enable state = %d\n",
363 state);
364}
365
366bool phydm_cal_nhm_cnt(void *dm_void)
367{
368 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
369 u16 base = 0;
370
371 base = dm->nhm_cnt_0 + dm->nhm_cnt_1;
372
373 if (base != 0) {
374 dm->nhm_cnt_0 = ((dm->nhm_cnt_0) << 8) / base;
375 dm->nhm_cnt_1 = ((dm->nhm_cnt_1) << 8) / base;
376 }
377 if ((dm->nhm_cnt_0 - dm->nhm_cnt_1) >= 100)
378 return true; /*clean environment*/
379 else
380 return false; /*noisy environment*/
381}
382
383void phydm_check_environment(void *dm_void)
384{
385 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
386 struct adaptivity_statistics *adaptivity =
387 (struct adaptivity_statistics *)phydm_get_structure(
388 dm, PHYDM_ADAPTIVITY);
389 bool is_clean_environment = false;
390
391 if (adaptivity->is_first_link) {
392 if (dm->support_ic_type &
393 (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
394 dm->adaptivity_flag = false;
395 else
396 dm->adaptivity_flag = true;
397
398 adaptivity->is_first_link = false;
399 return;
400 }
401
402 if (adaptivity->nhm_wait < 3) { /*Start enter NHM after 4 nhm_wait*/
403 adaptivity->nhm_wait++;
404 phydm_nhm_counter_statistics(dm);
405 return;
406 }
407
408 phydm_nhm_counter_statistics(dm);
409 is_clean_environment = phydm_cal_nhm_cnt(dm);
410
411 if (is_clean_environment) {
412 dm->th_l2h_ini =
413 adaptivity->th_l2h_ini_backup; /*adaptivity mode*/
414 dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
415
416 dm->adaptivity_enable = true;
417
418 if (dm->support_ic_type &
419 (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
420 dm->adaptivity_flag = false;
421 else
422 dm->adaptivity_flag = true;
423 } else {
424 if (!adaptivity->acs_for_adaptivity) {
425 dm->th_l2h_ini = dm->th_l2h_ini_mode2; /*mode2*/
426 dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
427
428 dm->adaptivity_flag = false;
429 dm->adaptivity_enable = false;
430 }
431 }
432
433 adaptivity->nhm_wait = 0;
434 adaptivity->is_first_link = true;
435 adaptivity->is_check = true;
436}
437
438void phydm_search_pwdb_lower_bound(void *dm_void)
439{
440 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
441 struct adaptivity_statistics *adaptivity =
442 (struct adaptivity_statistics *)phydm_get_structure(
443 dm, PHYDM_ADAPTIVITY);
444 u32 value32 = 0, reg_value32 = 0;
445 u8 cnt, try_count = 0;
446 u8 tx_edcca1 = 0, tx_edcca0 = 0;
447 bool is_adjust = true;
448 s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;
449 s8 diff;
450 u8 IGI = adaptivity->igi_base + 30 + (u8)dm->th_l2h_ini -
451 (u8)dm->th_edcca_hl_diff;
452
453 if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
454 ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) {
455 phydm_set_lna(dm, phydm_disable_lna);
456 } else {
457 phydm_set_trx_mux(dm, phydm_standby_mode, phydm_standby_mode);
458 odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);
459 }
460
461 diff = igi_target - (s8)IGI;
462 th_l2h_dmc = dm->th_l2h_ini + diff;
463 if (th_l2h_dmc > 10)
464 th_l2h_dmc = 10;
465 th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
466
467 phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
468 ODM_delay_ms(30);
469
470 while (is_adjust) {
471 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
472 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x0);
473 reg_value32 =
474 odm_get_bb_reg(dm, ODM_REG_RPT_11N, MASKDWORD);
475 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
476 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD,
477 0x0);
478 reg_value32 =
479 odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
480 }
481 while (reg_value32 & BIT(3) && try_count < 3) {
482 ODM_delay_ms(3);
483 try_count = try_count + 1;
484 if (dm->support_ic_type & ODM_IC_11N_SERIES)
485 reg_value32 = odm_get_bb_reg(
486 dm, ODM_REG_RPT_11N, MASKDWORD);
487 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
488 reg_value32 = odm_get_bb_reg(
489 dm, ODM_REG_RPT_11AC, MASKDWORD);
490 }
491 try_count = 0;
492
493 for (cnt = 0; cnt < 20; cnt++) {
494 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
495 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N,
496 MASKDWORD, 0x208);
497 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11N,
498 MASKDWORD);
499 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
500 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC,
501 MASKDWORD, 0x209);
502 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC,
503 MASKDWORD);
504 }
505 if (value32 & BIT(30) &&
506 (dm->support_ic_type &
507 (ODM_RTL8723B | ODM_RTL8188E)))
508 tx_edcca1 = tx_edcca1 + 1;
509 else if (value32 & BIT(29))
510 tx_edcca1 = tx_edcca1 + 1;
511 else
512 tx_edcca0 = tx_edcca0 + 1;
513 }
514
515 if (tx_edcca1 > 1) {
516 IGI = IGI - 1;
517 th_l2h_dmc = th_l2h_dmc + 1;
518 if (th_l2h_dmc > 10)
519 th_l2h_dmc = 10;
520 th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
521
522 phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
523 if (th_l2h_dmc == 10) {
524 is_adjust = false;
525 adaptivity->h2l_lb = th_h2l_dmc;
526 adaptivity->l2h_lb = th_l2h_dmc;
527 dm->adaptivity_igi_upper = IGI;
528 }
529
530 tx_edcca1 = 0;
531 tx_edcca0 = 0;
532
533 } else {
534 is_adjust = false;
535 adaptivity->h2l_lb = th_h2l_dmc;
536 adaptivity->l2h_lb = th_l2h_dmc;
537 dm->adaptivity_igi_upper = IGI;
538 tx_edcca1 = 0;
539 tx_edcca0 = 0;
540 }
541 }
542
543 dm->adaptivity_igi_upper = dm->adaptivity_igi_upper - dm->dc_backoff;
544 adaptivity->h2l_lb = adaptivity->h2l_lb + dm->dc_backoff;
545 adaptivity->l2h_lb = adaptivity->l2h_lb + dm->dc_backoff;
546
547 if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
548 ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) {
549 phydm_set_lna(dm, phydm_enable_lna);
550 } else {
551 phydm_set_trx_mux(dm, phydm_tx_mode, phydm_rx_mode);
552 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);
553 }
554
555 phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
556}
557
558static bool phydm_re_search_condition(void *dm_void)
559{
560 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
561 u8 adaptivity_igi_upper;
562 u8 count = 0;
563
564 adaptivity_igi_upper = dm->adaptivity_igi_upper + dm->dc_backoff;
565
566 if (adaptivity_igi_upper <= 0x26 && count < 3) {
567 count = count + 1;
568 return true;
569 }
570
571 return false;
572}
573
574void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
575 u32 value)
576{
577 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
578 struct adaptivity_statistics *adaptivity =
579 (struct adaptivity_statistics *)phydm_get_structure(
580 dm, PHYDM_ADAPTIVITY);
581
582 switch (cmn_info) {
583 case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
584 dm->carrier_sense_enable = (bool)value;
585 break;
586
587 case PHYDM_ADAPINFO_DCBACKOFF:
588 dm->dc_backoff = (u8)value;
589 break;
590
591 case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
592 adaptivity->dynamic_link_adaptivity = (bool)value;
593 break;
594
595 case PHYDM_ADAPINFO_TH_L2H_INI:
596 dm->th_l2h_ini = (s8)value;
597 break;
598
599 case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
600 dm->th_edcca_hl_diff = (s8)value;
601 break;
602
603 case PHYDM_ADAPINFO_AP_NUM_TH:
604 adaptivity->ap_num_th = (u8)value;
605 break;
606
607 default:
608 break;
609 }
610}
611
612void phydm_adaptivity_init(void *dm_void)
613{
614 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
615 struct adaptivity_statistics *adaptivity =
616 (struct adaptivity_statistics *)phydm_get_structure(
617 dm, PHYDM_ADAPTIVITY);
618 s8 igi_target = 0x32;
619
620 if (!dm->carrier_sense_enable) {
621 if (dm->th_l2h_ini == 0)
622 dm->th_l2h_ini = 0xf5;
623 } else {
624 dm->th_l2h_ini = 0xa;
625 }
626
627 if (dm->th_edcca_hl_diff == 0)
628 dm->th_edcca_hl_diff = 7;
629 if (dm->wifi_test || dm->mp_mode) {
630 /*even no adaptivity, we still enable EDCCA, AP use mib ctrl*/
631 dm->edcca_enable = false;
632 } else {
633 dm->edcca_enable = true;
634 }
635
636 dm->adaptivity_igi_upper = 0;
637 dm->adaptivity_enable =
638 false; /*use this flag to decide enable or disable*/
639
640 dm->th_l2h_ini_mode2 = 20;
641 dm->th_edcca_hl_diff_mode2 = 8;
642 adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
643 adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
644
645 adaptivity->igi_base = 0x32;
646 adaptivity->igi_target = 0x1c;
647 adaptivity->h2l_lb = 0;
648 adaptivity->l2h_lb = 0;
649 adaptivity->nhm_wait = 0;
650 adaptivity->is_check = false;
651 adaptivity->is_first_link = true;
652 adaptivity->adajust_igi_level = 0;
653 adaptivity->is_stop_edcca = false;
654 adaptivity->backup_h2l = 0;
655 adaptivity->backup_l2h = 0;
656
657 phydm_mac_edcca_state(dm, phydm_dont_ignore_edcca);
658
659 /*Search pwdB lower bound*/
660 if (dm->support_ic_type & ODM_IC_11N_SERIES)
661 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x208);
662 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
663 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x209);
664
665 if (dm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) {
666 if (dm->support_ic_type & ODM_RTL8197F) {
667 /*set to page B1*/
668 odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1);
669 /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
670 odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_97F,
671 BIT(27) | BIT(26), 0x1);
672 odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0);
673 } else {
674 /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
675 odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_11N,
676 BIT(21) | BIT(20), 0x1);
677 }
678 }
679 /*8814a no need to find pwdB lower bound, maybe*/
680 if (dm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) {
681 /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
682 odm_set_bb_reg(dm, ODM_REG_ACBB_EDCCA_ENHANCE,
683 BIT(29) | BIT(28), 0x1);
684 }
685
686 if (!(dm->support_ic_type &
687 (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
688 phydm_search_pwdb_lower_bound(dm);
689 if (phydm_re_search_condition(dm))
690 phydm_search_pwdb_lower_bound(dm);
691 }
692
693 /*we need to consider PwdB upper bound for 8814 later IC*/
694 adaptivity->adajust_igi_level =
695 (u8)((dm->th_l2h_ini + igi_target) - pwdb_upper_bound +
696 dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/
697
698 ODM_RT_TRACE(
699 dm, PHYDM_COMP_ADAPTIVITY,
700 "th_l2h_ini = 0x%x, th_edcca_hl_diff = 0x%x, adaptivity->adajust_igi_level = 0x%x\n",
701 dm->th_l2h_ini, dm->th_edcca_hl_diff,
702 adaptivity->adajust_igi_level);
703
704 /*Check this later on Windows*/
705 /*phydm_set_edcca_threshold_api(dm, dig_tab->cur_ig_value);*/
706}
707
708void phydm_adaptivity(void *dm_void)
709{
710 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
711 struct dig_thres *dig_tab = &dm->dm_dig_table;
712 u8 IGI = dig_tab->cur_ig_value;
713 s8 th_l2h_dmc, th_h2l_dmc;
714 s8 diff = 0, igi_target;
715 struct adaptivity_statistics *adaptivity =
716 (struct adaptivity_statistics *)phydm_get_structure(
717 dm, PHYDM_ADAPTIVITY);
718
719 if (!dm->edcca_enable || adaptivity->is_stop_edcca) {
720 ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "Disable EDCCA!!!\n");
721 return;
722 }
723
724 if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
725 ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
726 "adaptivity disable, enable EDCCA mode!!!\n");
727 dm->th_l2h_ini = dm->th_l2h_ini_mode2;
728 dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
729 }
730
731 ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "%s() =====>\n", __func__);
732 ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
733 "igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
734 adaptivity->igi_base, dm->th_l2h_ini,
735 dm->th_edcca_hl_diff);
736 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
737 /*fix AC series when enable EDCCA hang issue*/
738 odm_set_bb_reg(dm, 0x800, BIT(10), 1); /*ADC_mask disable*/
739 odm_set_bb_reg(dm, 0x800, BIT(10), 0); /*ADC_mask enable*/
740 }
741 if (*dm->band_width == ODM_BW20M) /*CHANNEL_WIDTH_20*/
742 igi_target = adaptivity->igi_base;
743 else if (*dm->band_width == ODM_BW40M)
744 igi_target = adaptivity->igi_base + 2;
745 else if (*dm->band_width == ODM_BW80M)
746 igi_target = adaptivity->igi_base + 2;
747 else
748 igi_target = adaptivity->igi_base;
749 adaptivity->igi_target = (u8)igi_target;
750
751 ODM_RT_TRACE(
752 dm, PHYDM_COMP_ADAPTIVITY,
753 "band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d, acs_for_adaptivity = %d\n",
754 (*dm->band_width == ODM_BW80M) ?
755 "80M" :
756 ((*dm->band_width == ODM_BW40M) ? "40M" : "20M"),
757 igi_target, adaptivity->dynamic_link_adaptivity,
758 adaptivity->acs_for_adaptivity);
759 ODM_RT_TRACE(
760 dm, PHYDM_COMP_ADAPTIVITY,
761 "rssi_min = %d, adaptivity->adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n",
762 dm->rssi_min, adaptivity->adajust_igi_level,
763 dm->adaptivity_flag, dm->adaptivity_enable);
764
765 if (adaptivity->dynamic_link_adaptivity && (!dm->is_linked) &&
766 !dm->adaptivity_enable) {
767 phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
768 ODM_RT_TRACE(
769 dm, PHYDM_COMP_ADAPTIVITY,
770 "In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n");
771 return;
772 }
773
774 if (dm->support_ic_type &
775 (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
776 if ((adaptivity->adajust_igi_level > IGI) &&
777 dm->adaptivity_enable)
778 diff = adaptivity->adajust_igi_level - IGI;
779
780 th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
781 th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
782 } else {
783 diff = igi_target - (s8)IGI;
784 th_l2h_dmc = dm->th_l2h_ini + diff;
785 if (th_l2h_dmc > 10 && dm->adaptivity_enable)
786 th_l2h_dmc = 10;
787
788 th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
789
790 /*replace lower bound to prevent EDCCA always equal 1*/
791 if (th_h2l_dmc < adaptivity->h2l_lb)
792 th_h2l_dmc = adaptivity->h2l_lb;
793 if (th_l2h_dmc < adaptivity->l2h_lb)
794 th_l2h_dmc = adaptivity->l2h_lb;
795 }
796 ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
797 "IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI,
798 th_l2h_dmc, th_h2l_dmc);
799 ODM_RT_TRACE(
800 dm, PHYDM_COMP_ADAPTIVITY,
801 "adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
802 dm->adaptivity_igi_upper, adaptivity->h2l_lb,
803 adaptivity->l2h_lb);
804
805 phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
806
807 if (dm->adaptivity_enable)
808 odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);
809}
810
811/*This is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
812void phydm_pause_edcca(void *dm_void, bool is_pasue_edcca)
813{
814 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
815 struct adaptivity_statistics *adaptivity =
816 (struct adaptivity_statistics *)phydm_get_structure(
817 dm, PHYDM_ADAPTIVITY);
818 struct dig_thres *dig_tab = &dm->dm_dig_table;
819 u8 IGI = dig_tab->cur_ig_value;
820 s8 diff = 0;
821
822 if (is_pasue_edcca) {
823 adaptivity->is_stop_edcca = true;
824
825 if (dm->support_ic_type &
826 (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
827 if (adaptivity->adajust_igi_level > IGI)
828 diff = adaptivity->adajust_igi_level - IGI;
829
830 adaptivity->backup_l2h =
831 dm->th_l2h_ini - diff + adaptivity->igi_target;
832 adaptivity->backup_h2l =
833 adaptivity->backup_l2h - dm->th_edcca_hl_diff;
834 } else {
835 diff = adaptivity->igi_target - (s8)IGI;
836 adaptivity->backup_l2h = dm->th_l2h_ini + diff;
837 if (adaptivity->backup_l2h > 10)
838 adaptivity->backup_l2h = 10;
839
840 adaptivity->backup_h2l =
841 adaptivity->backup_l2h - dm->th_edcca_hl_diff;
842
843 /*replace lower bound to prevent EDCCA always equal 1*/
844 if (adaptivity->backup_h2l < adaptivity->h2l_lb)
845 adaptivity->backup_h2l = adaptivity->h2l_lb;
846 if (adaptivity->backup_l2h < adaptivity->l2h_lb)
847 adaptivity->backup_l2h = adaptivity->l2h_lb;
848 }
849 ODM_RT_TRACE(
850 dm, PHYDM_COMP_ADAPTIVITY,
851 "pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n",
852 adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
853
854 /*Disable EDCCA*/
855 phydm_pause_edcca_work_item_callback(dm);
856
857 } else {
858 adaptivity->is_stop_edcca = false;
859 ODM_RT_TRACE(
860 dm, PHYDM_COMP_ADAPTIVITY,
861 "resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n",
862 adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
863 /*Resume EDCCA*/
864 phydm_resume_edcca_work_item_callback(dm);
865 }
866}
867
868void phydm_pause_edcca_work_item_callback(void *dm_void)
869{
870 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
871
872 if (dm->support_ic_type & ODM_IC_11N_SERIES)
873 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
874 MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16));
875 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
876 odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
877 (u16)(0x7f | 0x7f << 8));
878}
879
880void phydm_resume_edcca_work_item_callback(void *dm_void)
881{
882 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
883 struct adaptivity_statistics *adaptivity =
884 (struct adaptivity_statistics *)phydm_get_structure(
885 dm, PHYDM_ADAPTIVITY);
886
887 if (dm->support_ic_type & ODM_IC_11N_SERIES)
888 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
889 MASKBYTE2 | MASKBYTE0,
890 (u32)((u8)adaptivity->backup_l2h |
891 (u8)adaptivity->backup_h2l << 16));
892 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
893 odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
894 (u16)((u8)adaptivity->backup_l2h |
895 (u8)adaptivity->backup_h2l << 8));
896}
897
898void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI)
899{
900 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
901 struct adaptivity_statistics *adaptivity =
902 (struct adaptivity_statistics *)phydm_get_structure(
903 dm, PHYDM_ADAPTIVITY);
904 s8 th_l2h_dmc, th_h2l_dmc;
905 s8 diff = 0, igi_target = 0x32;
906
907 if (dm->support_ability & ODM_BB_ADAPTIVITY) {
908 if (dm->support_ic_type &
909 (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
910 if (adaptivity->adajust_igi_level > IGI)
911 diff = adaptivity->adajust_igi_level - IGI;
912
913 th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
914 th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
915 } else {
916 diff = igi_target - (s8)IGI;
917 th_l2h_dmc = dm->th_l2h_ini + diff;
918 if (th_l2h_dmc > 10)
919 th_l2h_dmc = 10;
920
921 th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
922
923 /*replace lower bound to prevent EDCCA always equal 1*/
924 if (th_h2l_dmc < adaptivity->h2l_lb)
925 th_h2l_dmc = adaptivity->h2l_lb;
926 if (th_l2h_dmc < adaptivity->l2h_lb)
927 th_l2h_dmc = adaptivity->l2h_lb;
928 }
929 ODM_RT_TRACE(
930 dm, PHYDM_COMP_ADAPTIVITY,
931 "API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n",
932 IGI, th_l2h_dmc, th_h2l_dmc);
933 ODM_RT_TRACE(
934 dm, PHYDM_COMP_ADAPTIVITY,
935 "API :adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
936 dm->adaptivity_igi_upper, adaptivity->h2l_lb,
937 adaptivity->l2h_lb);
938
939 phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
940 }
941}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_adaptivity.h b/drivers/staging/rtlwifi/phydm/phydm_adaptivity.h
new file mode 100644
index 000000000000..fdb39b4f9df2
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_adaptivity.h
@@ -0,0 +1,119 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMADAPTIVITY_H__
27#define __PHYDMADAPTIVITY_H__
28
29/*20160902 changed by Kevin, refine method for searching pwdb lower bound*/
30#define ADAPTIVITY_VERSION "9.3.5"
31
32#define pwdb_upper_bound 7
33#define dfir_loss 5
34
35enum phydm_adapinfo {
36 PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
37 PHYDM_ADAPINFO_DCBACKOFF,
38 PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
39 PHYDM_ADAPINFO_TH_L2H_INI,
40 PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
41 PHYDM_ADAPINFO_AP_NUM_TH
42
43};
44
45enum phydm_set_lna {
46 phydm_disable_lna = 0,
47 phydm_enable_lna = 1,
48};
49
50enum phydm_trx_mux_type {
51 phydm_shutdown = 0,
52 phydm_standby_mode = 1,
53 phydm_tx_mode = 2,
54 phydm_rx_mode = 3
55};
56
57enum phydm_mac_edcca_type {
58 phydm_ignore_edcca = 0,
59 phydm_dont_ignore_edcca = 1
60};
61
62struct adaptivity_statistics {
63 s8 th_l2h_ini_backup;
64 s8 th_edcca_hl_diff_backup;
65 s8 igi_base;
66 u8 igi_target;
67 u8 nhm_wait;
68 s8 h2l_lb;
69 s8 l2h_lb;
70 bool is_first_link;
71 bool is_check;
72 bool dynamic_link_adaptivity;
73 u8 ap_num_th;
74 u8 adajust_igi_level;
75 bool acs_for_adaptivity;
76 s8 backup_l2h;
77 s8 backup_h2l;
78 bool is_stop_edcca;
79};
80
81void phydm_pause_edcca(void *dm_void, bool is_pasue_edcca);
82
83void phydm_check_adaptivity(void *dm_void);
84
85void phydm_check_environment(void *dm_void);
86
87void phydm_nhm_counter_statistics_init(void *dm_void);
88
89void phydm_nhm_counter_statistics(void *dm_void);
90
91void phydm_nhm_counter_statistics_reset(void *dm_void);
92
93void phydm_get_nhm_counter_statistics(void *dm_void);
94
95void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state);
96
97void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H);
98
99void phydm_set_trx_mux(void *dm_void, enum phydm_trx_mux_type tx_mode,
100 enum phydm_trx_mux_type rx_mode);
101
102bool phydm_cal_nhm_cnt(void *dm_void);
103
104void phydm_search_pwdb_lower_bound(void *dm_void);
105
106void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
107 u32 value);
108
109void phydm_adaptivity_init(void *dm_void);
110
111void phydm_adaptivity(void *dm_void);
112
113void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI);
114
115void phydm_pause_edcca_work_item_callback(void *dm_void);
116
117void phydm_resume_edcca_work_item_callback(void *dm_void);
118
119#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_adc_sampling.c b/drivers/staging/rtlwifi/phydm/phydm_adc_sampling.c
new file mode 100644
index 000000000000..158dd5d05de4
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_adc_sampling.c
@@ -0,0 +1,628 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#include "mp_precomp.h"
26#include "phydm_precomp.h"
27
28static bool phydm_la_buffer_allocate(void *dm_void)
29{
30 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
31 struct rt_adcsmp *adc_smp = &dm->adcsmp;
32 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
33 bool ret = false;
34
35 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA mode BufferAllocate]\n");
36
37 if (adc_smp_buf->length == 0) {
38 odm_allocate_memory(dm, (void **)&adc_smp_buf->octet,
39 adc_smp_buf->buffer_size);
40 if (!adc_smp_buf->octet) {
41 ret = false;
42 } else {
43 adc_smp_buf->length = adc_smp_buf->buffer_size;
44 ret = true;
45 }
46 }
47
48 return ret;
49}
50
51static void phydm_la_get_tx_pkt_buf(void *dm_void)
52{
53 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
54 struct rt_adcsmp *adc_smp = &dm->adcsmp;
55 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
56 u32 i = 0, value32, data_l = 0, data_h = 0;
57 u32 addr, finish_addr;
58 u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) -
59 1; /*end_addr = 0x3ffff;*/
60 bool is_round_up;
61 static u32 page = 0xFF;
62 u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0;
63
64 odm_memory_set(dm, adc_smp_buf->octet, 0, adc_smp_buf->length);
65 odm_write_1byte(dm, 0x0106, 0x69);
66
67 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "GetTxPktBuf\n");
68
69 value32 = odm_read_4byte(dm, 0x7c0);
70 is_round_up = (bool)((value32 & BIT(31)) >> 31);
71 /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
72 finish_addr = (value32 & 0x7FFF0000) >> 16;
73
74 if (is_round_up) {
75 addr = (finish_addr + 1) << 3;
76 ODM_RT_TRACE(
77 dm, ODM_COMP_UNCOND,
78 "is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n",
79 is_round_up, finish_addr, value32);
80 /*Byte to 64Byte*/
81 smp_number = ((adc_smp_buf->buffer_size) >> 3);
82 } else {
83 addr = adc_smp_buf->start_pos;
84
85 addr_8byte = addr >> 3;
86 if (addr_8byte > finish_addr)
87 smp_number = addr_8byte - finish_addr;
88 else
89 smp_number = finish_addr - addr_8byte;
90
91 ODM_RT_TRACE(
92 dm, ODM_COMP_UNCOND,
93 "is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n",
94 is_round_up, finish_addr, addr_8byte, smp_number);
95 }
96
97 if (dm->support_ic_type & ODM_RTL8197F) {
98 /*64K byte*/
99 for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) {
100 if ((addr & 0xfff) == 0)
101 odm_set_bb_reg(dm, 0x0140, MASKLWORD,
102 0x780 + (addr >> 12));
103 data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
104 MASKDWORD);
105 data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
106 MASKDWORD);
107
108 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
109 data_l);
110 }
111 } else {
112 while (addr != (finish_addr << 3)) {
113 if (page != (addr >> 12)) {
114 /*Reg140=0x780+(addr>>12),
115 *addr=0x30~0x3F, total 16 pages
116 */
117 page = (addr >> 12);
118 }
119 odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + page);
120
121 /*pDataL = 0x8000+(addr&0xfff);*/
122 data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
123 MASKDWORD);
124 data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
125 MASKDWORD);
126
127 adc_smp_buf->octet[i] = data_h;
128 adc_smp_buf->octet[i + 1] = data_l;
129
130 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
131 data_l);
132
133 i = i + 2;
134
135 if ((addr + 8) >= end_addr)
136 addr = adc_smp_buf->start_pos;
137 else
138 addr = addr + 8;
139
140 smp_cnt++;
141 if (smp_cnt >= (smp_number - 1))
142 break;
143 }
144 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "smp_cnt = ((%d))\n",
145 smp_cnt);
146 }
147}
148
149static void phydm_la_mode_set_mac_iq_dump(void *dm_void)
150{
151 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
152 struct rt_adcsmp *adc_smp = &dm->adcsmp;
153 u32 reg_value;
154
155 odm_write_1byte(dm, 0x7c0, 0); /*clear all 0x7c0*/
156 odm_set_mac_reg(dm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/
157
158 if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) {
159 adc_smp->is_bb_trigger = 0;
160 odm_set_mac_reg(dm, 0x7c0, BIT(2),
161 1); /*polling bit for MAC mode*/
162 odm_set_mac_reg(
163 dm, 0x7c0, BIT(4) | BIT(3),
164 adc_smp->la_trigger_edge); /*trigger mode for MAC*/
165
166 ODM_RT_TRACE(
167 dm, ODM_COMP_UNCOND,
168 "[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n",
169 adc_smp->la_mac_ref_mask, adc_smp->la_trig_sig_sel,
170 adc_smp->la_dbg_port);
171 /*[Set MAC Debug Port]*/
172 odm_set_mac_reg(dm, 0xF4, BIT(16), 1);
173 odm_set_mac_reg(dm, 0x38, 0xff0000, adc_smp->la_dbg_port);
174 odm_set_mac_reg(dm, 0x7c4, MASKDWORD, adc_smp->la_mac_ref_mask);
175 odm_set_mac_reg(dm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel);
176
177 } else {
178 adc_smp->is_bb_trigger = 1;
179 odm_set_mac_reg(dm, 0x7c0, BIT(1),
180 1); /*polling bit for BB ADC mode*/
181
182 if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
183 odm_set_mac_reg(
184 dm, 0x7c0, BIT(3),
185 1); /*polling bit for MAC trigger event*/
186 odm_set_mac_reg(dm, 0x7c0, BIT(7) | BIT(6),
187 adc_smp->la_trig_sig_sel);
188
189 if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
190 odm_set_mac_reg(
191 dm, 0x7c0, BIT(5),
192 1); /* manual trigger 0x7C0[5] = 0->1*/
193 }
194 }
195
196 reg_value = odm_get_bb_reg(dm, 0x7c0, 0xff);
197 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
198 "4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
199}
200
201static void phydm_la_mode_set_dma_type(void *dm_void, u8 la_dma_type)
202{
203 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
204
205 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
206 "2. [LA mode DMA setting] Dma_type = ((%d))\n",
207 la_dma_type);
208
209 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
210 odm_set_bb_reg(dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
211 else
212 odm_set_bb_reg(dm, odm_adc_trigger_jaguar2, 0xf00,
213 la_dma_type); /*0x95C[11:8]*/
214}
215
216static void phydm_adc_smp_start(void *dm_void)
217{
218 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
219 struct rt_adcsmp *adc_smp = &dm->adcsmp;
220 u8 tmp_u1b;
221 u8 while_cnt = 0;
222 u8 polling_ok = false, target_polling_bit;
223
224 phydm_la_mode_bb_setting(dm);
225 phydm_la_mode_set_dma_type(dm, adc_smp->la_dma_type);
226 phydm_la_mode_set_trigger_time(dm, adc_smp->la_trigger_time);
227
228 if (dm->support_ic_type & ODM_RTL8197F) {
229 odm_set_bb_reg(dm, 0xd00, BIT(26), 0x1);
230 } else { /*for 8814A and 8822B?*/
231 odm_write_1byte(dm, 0x198c, 0x7);
232 odm_write_1byte(dm, 0x8b4, 0x80);
233 /* odm_set_bb_reg(dm, 0x8b4, BIT(7), 1); */
234 }
235
236 phydm_la_mode_set_mac_iq_dump(dm);
237 /* return; */
238
239 target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
240 do { /*Poll time always use 100ms, when it exceed 2s, break while loop*/
241 tmp_u1b = odm_read_1byte(dm, 0x7c0);
242
243 if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) {
244 ODM_RT_TRACE(
245 dm, ODM_COMP_UNCOND,
246 "[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
247 break;
248
249 } else if (tmp_u1b & target_polling_bit) {
250 ODM_delay_ms(100);
251 while_cnt = while_cnt + 1;
252 continue;
253 } else {
254 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
255 "[LA Query OK] polling_bit=((0x%x))\n",
256 target_polling_bit);
257 polling_ok = true;
258 if (dm->support_ic_type & ODM_RTL8197F)
259 odm_set_bb_reg(dm, 0x7c0, BIT(0), 0x0);
260 break;
261 }
262 } while (while_cnt < 20);
263
264 if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
265 if (polling_ok)
266 phydm_la_get_tx_pkt_buf(dm);
267 else
268 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
269 "[Polling timeout]\n");
270 }
271
272 if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
273 adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
274
275 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
276 "[LA mode] LA_pattern_count = ((%d))\n",
277 adc_smp->la_count);
278
279 adc_smp_stop(dm);
280
281 if (adc_smp->la_count == 0) {
282 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
283 "LA Dump finished ---------->\n\n\n");
284 /**/
285 } else {
286 adc_smp->la_count--;
287 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
288 "LA Dump more ---------->\n\n\n");
289 adc_smp_set(dm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel,
290 adc_smp->la_dma_type, adc_smp->la_trigger_time, 0);
291 }
292}
293
294void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
295 u8 dma_data_sig_sel, u32 trigger_time, u16 polling_time)
296{
297 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
298 bool is_set_success = true;
299 struct rt_adcsmp *adc_smp = &dm->adcsmp;
300
301 adc_smp->la_trig_mode = trig_mode;
302 adc_smp->la_trig_sig_sel = trig_sig_sel;
303 adc_smp->la_dma_type = dma_data_sig_sel;
304 adc_smp->la_trigger_time = trigger_time;
305
306 if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
307 is_set_success = false;
308 else if (adc_smp->adc_smp_buf.length == 0)
309 is_set_success = phydm_la_buffer_allocate(dm);
310
311 if (is_set_success) {
312 adc_smp->adc_smp_state = ADCSMP_STATE_SET;
313
314 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
315 "[LA Set Success] LA_State=((%d))\n",
316 adc_smp->adc_smp_state);
317
318 phydm_adc_smp_start(dm);
319 } else {
320 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
321 "[LA Set Fail] LA_State=((%d))\n",
322 adc_smp->adc_smp_state);
323 }
324}
325
326void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused)
327{
328 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
329 struct rt_adcsmp *adc_smp = &dm->adcsmp;
330 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
331 u32 used = *pused;
332 u32 i;
333
334 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%s adc_smp_state %d", __func__,
335 adc_smp->adc_smp_state);
336
337 for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) {
338 PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
339 adc_smp_buf->octet[i],
340 adc_smp_buf->octet[i + 1]);
341 }
342
343 PHYDM_SNPRINTF(output + used, out_len - used, "\n");
344 *pused = used;
345}
346
347s32 adc_smp_get_sample_counts(void *dm_void)
348{
349 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
350 struct rt_adcsmp *adc_smp = &dm->adcsmp;
351 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
352
353 return (adc_smp_buf->length >> 2) - 2;
354}
355
356s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
357 u32 index)
358{
359 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
360 struct rt_adcsmp *adc_smp = &dm->adcsmp;
361 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
362 u32 used = 0;
363
364 if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
365 PHYDM_SNPRINTF(output + used, out_len - used,
366 "Error: la data is not ready yet ...\n");
367 return -1;
368 }
369
370 if (index < ((adc_smp_buf->length >> 2) - 2)) {
371 PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
372 adc_smp_buf->octet[index],
373 adc_smp_buf->octet[index + 1]);
374 }
375 return 0;
376}
377
378void adc_smp_stop(void *dm_void)
379{
380 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
381 struct rt_adcsmp *adc_smp = &dm->adcsmp;
382
383 adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
384 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA_Stop] LA_state = ((%d))\n",
385 adc_smp->adc_smp_state);
386}
387
388void adc_smp_init(void *dm_void)
389{
390 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
391 struct rt_adcsmp *adc_smp = &dm->adcsmp;
392 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
393
394 adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
395
396 if (dm->support_ic_type & ODM_RTL8814A) {
397 adc_smp_buf->start_pos = 0x30000;
398 adc_smp_buf->buffer_size = 0x10000;
399 } else if (dm->support_ic_type & ODM_RTL8822B) {
400 adc_smp_buf->start_pos = 0x20000;
401 adc_smp_buf->buffer_size = 0x20000;
402 } else if (dm->support_ic_type & ODM_RTL8197F) {
403 adc_smp_buf->start_pos = 0x00000;
404 adc_smp_buf->buffer_size = 0x10000;
405 } else if (dm->support_ic_type & ODM_RTL8821C) {
406 adc_smp_buf->start_pos = 0x8000;
407 adc_smp_buf->buffer_size = 0x8000;
408 }
409}
410
411void adc_smp_de_init(void *dm_void)
412{
413 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
414 struct rt_adcsmp *adc_smp = &dm->adcsmp;
415 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
416
417 adc_smp_stop(dm);
418
419 if (adc_smp_buf->length != 0x0) {
420 odm_free_memory(dm, adc_smp_buf->octet, adc_smp_buf->length);
421 adc_smp_buf->length = 0x0;
422 }
423}
424
425void phydm_la_mode_bb_setting(void *dm_void)
426{
427 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
428 struct rt_adcsmp *adc_smp = &dm->adcsmp;
429
430 u8 trig_mode = adc_smp->la_trig_mode;
431 u32 trig_sig_sel = adc_smp->la_trig_sig_sel;
432 u32 dbg_port = adc_smp->la_dbg_port;
433 u8 is_trigger_edge = adc_smp->la_trigger_edge;
434 u8 sampling_rate = adc_smp->la_smp_rate;
435
436 ODM_RT_TRACE(
437 dm, ODM_COMP_UNCOND,
438 "1. [LA mode bb_setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n",
439 trig_mode, dbg_port, is_trigger_edge, sampling_rate,
440 trig_sig_sel);
441
442 if (trig_mode == PHYDM_MAC_TRIG)
443 trig_sig_sel = 0; /*ignore this setting*/
444
445 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
446 if (trig_mode == PHYDM_ADC_RF0_TRIG) {
447 /*DBGOUT_RFC_a[31:0]*/
448 odm_set_bb_reg(dm, 0x8f8,
449 BIT(25) | BIT(24) | BIT(23) | BIT(22),
450 9);
451 } else if (trig_mode == PHYDM_ADC_RF1_TRIG) {
452 /*DBGOUT_RFC_b[31:0]*/
453 odm_set_bb_reg(dm, 0x8f8,
454 BIT(25) | BIT(24) | BIT(23) | BIT(22),
455 8);
456 } else {
457 odm_set_bb_reg(dm, 0x8f8,
458 BIT(25) | BIT(24) | BIT(23) | BIT(22),
459 0);
460 }
461 /*
462 * (0:) '{ofdm_dbg[31:0]}'
463 * (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'
464 * (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'
465 * (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'
466 * (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'
467 * (5:) '{dbg_iqk_anta}'
468 * (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'
469 * (7:) '{dbg_iqk_antb}'
470 * (8:) '{DBGOUT_RFC_b[31:0]}'
471 * (9:) '{DBGOUT_RFC_a[31:0]}'
472 * (a:) '{dbg_ofdm}'
473 * (b:) '{dbg_cck}'
474 */
475
476 /*disable dbg clk gating*/
477 odm_set_bb_reg(dm, 0x198C, BIT(2) | BIT(1) | BIT(0), 7);
478
479 /*0x95C[4:0], BB debug port bit*/
480 odm_set_bb_reg(dm, 0x95C, 0x1f, trig_sig_sel);
481 odm_set_bb_reg(dm, 0x8FC, MASKDWORD, dbg_port);
482 /*0: posedge, 1: negedge*/
483 odm_set_bb_reg(dm, 0x95C, BIT(31), is_trigger_edge);
484 odm_set_bb_reg(dm, 0x95c, 0xe0, sampling_rate);
485 /* (0:) '80MHz'
486 * (1:) '40MHz'
487 * (2:) '20MHz'
488 * (3:) '10MHz'
489 * (4:) '5MHz'
490 * (5:) '2.5MHz'
491 * (6:) '1.25MHz'
492 * (7:) '160MHz (for BW160 ic)'
493 */
494 } else {
495 /*0x9A0[4:0], BB debug port bit*/
496 odm_set_bb_reg(dm, 0x9a0, 0x1f, trig_sig_sel);
497 odm_set_bb_reg(dm, 0x908, MASKDWORD, dbg_port);
498 /*0: posedge, 1: negedge*/
499 odm_set_bb_reg(dm, 0x9A0, BIT(31), is_trigger_edge);
500 odm_set_bb_reg(dm, 0x9A0, 0xe0, sampling_rate);
501 /* (0:) '80MHz'
502 * (1:) '40MHz'
503 * (2:) '20MHz'
504 * (3:) '10MHz'
505 * (4:) '5MHz'
506 * (5:) '2.5MHz'
507 * (6:) '1.25MHz'
508 * (7:) '160MHz (for BW160 ic)'
509 */
510 }
511}
512
513void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
514{
515 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
516 u8 trigger_time_unit_num;
517 u32 time_unit = 0;
518
519 if (trigger_time_mu_sec < 128)
520 time_unit = 0; /*unit: 1mu sec*/
521 else if (trigger_time_mu_sec < 256)
522 time_unit = 1; /*unit: 2mu sec*/
523 else if (trigger_time_mu_sec < 512)
524 time_unit = 2; /*unit: 4mu sec*/
525 else if (trigger_time_mu_sec < 1024)
526 time_unit = 3; /*unit: 8mu sec*/
527 else if (trigger_time_mu_sec < 2048)
528 time_unit = 4; /*unit: 16mu sec*/
529 else if (trigger_time_mu_sec < 4096)
530 time_unit = 5; /*unit: 32mu sec*/
531 else if (trigger_time_mu_sec < 8192)
532 time_unit = 6; /*unit: 64mu sec*/
533
534 trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
535
536 ODM_RT_TRACE(
537 dm, ODM_COMP_UNCOND,
538 "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
539 trigger_time_unit_num, time_unit);
540
541 odm_set_mac_reg(dm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
542 odm_set_mac_reg(dm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
543}
544
545void phydm_lamode_trigger_setting(void *dm_void, char input[][16], u32 *_used,
546 char *output, u32 *_out_len, u32 input_num)
547{
548 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
549 struct rt_adcsmp *adc_smp = &dm->adcsmp;
550 u8 trig_mode, dma_data_sig_sel;
551 u32 trig_sig_sel;
552 bool is_enable_la_mode;
553 u32 trigger_time_mu_sec;
554 char help[] = "-h";
555 u32 var1[10] = {0};
556 u32 used = *_used;
557 u32 out_len = *_out_len;
558
559 if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
560 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
561 is_enable_la_mode = (bool)var1[0];
562 /*dbg_print("echo cmd input_num = %d\n", input_num);*/
563
564 if ((strcmp(input[1], help) == 0)) {
565 PHYDM_SNPRINTF(
566 output + used, out_len - used,
567 "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC}\n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime}\n {polling_time/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n");
568 /**/
569 } else if ((is_enable_la_mode == 1)) {
570 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
571
572 trig_mode = (u8)var1[1];
573
574 if (trig_mode == PHYDM_MAC_TRIG)
575 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
576 else
577 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
578 trig_sig_sel = var1[2];
579
580 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
581 PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
582 PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
583 PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
584 PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
585 PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
586 PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
587
588 dma_data_sig_sel = (u8)var1[3];
589 trigger_time_mu_sec = var1[4]; /*unit: us*/
590
591 adc_smp->la_mac_ref_mask = var1[5];
592 adc_smp->la_dbg_port = var1[6];
593 adc_smp->la_trigger_edge = (u8)var1[7];
594 adc_smp->la_smp_rate = (u8)(var1[8] & 0x7);
595 adc_smp->la_count = var1[9];
596
597 ODM_RT_TRACE(
598 dm, ODM_COMP_UNCOND,
599 "echo lamode %d %d %d %d %d %d %x %d %d %d\n",
600 var1[0], var1[1], var1[2], var1[3], var1[4],
601 var1[5], var1[6], var1[7], var1[8], var1[9]);
602
603 PHYDM_SNPRINTF(
604 output + used, out_len - used,
605 "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
606 trig_mode, trig_sig_sel, dma_data_sig_sel);
607 PHYDM_SNPRINTF(
608 output + used, out_len - used,
609 "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
610 trigger_time_mu_sec, adc_smp->la_mac_ref_mask,
611 adc_smp->la_dbg_port);
612 PHYDM_SNPRINTF(
613 output + used, out_len - used,
614 "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
615 adc_smp->la_trigger_edge,
616 (80 >> adc_smp->la_smp_rate),
617 adc_smp->la_count);
618
619 adc_smp_set(dm, trig_mode, trig_sig_sel,
620 dma_data_sig_sel, trigger_time_mu_sec, 0);
621
622 } else {
623 adc_smp_stop(dm);
624 PHYDM_SNPRINTF(output + used, out_len - used,
625 "Disable LA mode\n");
626 }
627 }
628}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_adc_sampling.h b/drivers/staging/rtlwifi/phydm/phydm_adc_sampling.h
new file mode 100644
index 000000000000..460931489be3
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_adc_sampling.h
@@ -0,0 +1,96 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __INC_ADCSMP_H
26#define __INC_ADCSMP_H
27
28#define DYNAMIC_LA_MODE "1.0" /*2016.07.15 Dino */
29
30struct rt_adcsmp_string {
31 u32 *octet;
32 u32 length;
33 u32 buffer_size;
34 u32 start_pos;
35};
36
37enum rt_adcsmp_trig_sel {
38 PHYDM_ADC_BB_TRIG = 0,
39 PHYDM_ADC_MAC_TRIG = 1,
40 PHYDM_ADC_RF0_TRIG = 2,
41 PHYDM_ADC_RF1_TRIG = 3,
42 PHYDM_MAC_TRIG = 4
43};
44
45enum rt_adcsmp_trig_sig_sel {
46 ADCSMP_TRIG_CRCOK = 0,
47 ADCSMP_TRIG_CRCFAIL = 1,
48 ADCSMP_TRIG_CCA = 2,
49 ADCSMP_TRIG_REG = 3
50};
51
52enum rt_adcsmp_state {
53 ADCSMP_STATE_IDLE = 0,
54 ADCSMP_STATE_SET = 1,
55 ADCSMP_STATE_QUERY = 2
56};
57
58struct rt_adcsmp {
59 struct rt_adcsmp_string adc_smp_buf;
60 enum rt_adcsmp_state adc_smp_state;
61 u8 la_trig_mode;
62 u32 la_trig_sig_sel;
63 u8 la_dma_type;
64 u32 la_trigger_time;
65 u32 la_mac_ref_mask;
66 u32 la_dbg_port;
67 u8 la_trigger_edge;
68 u8 la_smp_rate;
69 u32 la_count;
70 u8 is_bb_trigger;
71 u8 la_work_item_index;
72};
73
74void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
75 u8 dma_data_sig_sel, u32 trigger_time, u16 polling_time);
76
77void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused);
78
79s32 adc_smp_get_sample_counts(void *dm_void);
80
81s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
82 u32 index);
83
84void adc_smp_stop(void *dm_void);
85
86void adc_smp_init(void *dm_void);
87
88void adc_smp_de_init(void *dm_void);
89
90void phydm_la_mode_bb_setting(void *dm_void);
91
92void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec);
93
94void phydm_lamode_trigger_setting(void *dm_void, char input[][16], u32 *_used,
95 char *output, u32 *_out_len, u32 input_num);
96#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_antdiv.c b/drivers/staging/rtlwifi/phydm/phydm_antdiv.c
new file mode 100644
index 000000000000..39d3c6947556
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_antdiv.c
@@ -0,0 +1,83 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29
30#include "mp_precomp.h"
31#include "phydm_precomp.h"
32
33/* ******************************************************
34 * when antenna test utility is on or some testing need to disable antenna
35 * diversity, call this function to disable all ODM related mechanisms which
36 * will switch antenna.
37 * *******************************************************/
38void odm_stop_antenna_switch_dm(void *dm_void)
39{
40 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
41
42 /* disable ODM antenna diversity */
43 dm->support_ability &= ~ODM_BB_ANT_DIV;
44 ODM_RT_TRACE(dm, ODM_COMP_ANT_DIV, "STOP Antenna Diversity\n");
45}
46
47void phydm_enable_antenna_diversity(void *dm_void)
48{
49 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
50
51 dm->support_ability |= ODM_BB_ANT_DIV;
52 ODM_RT_TRACE(dm, ODM_COMP_ANT_DIV,
53 "AntDiv is enabled & Re-Init AntDiv\n");
54 odm_antenna_diversity_init(dm);
55}
56
57void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
58 )
59{
60 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
61
62 if (dm->support_ic_type == ODM_RTL8723B) {
63 if (ant_setting == 0) /* ant A*/
64 odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000000);
65 else if (ant_setting == 1)
66 odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000280);
67 } else if (dm->support_ic_type == ODM_RTL8723D) {
68 if (ant_setting == 0) /* ant A*/
69 odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0000);
70 else if (ant_setting == 1)
71 odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0280);
72 }
73}
74
75/* ****************************************************** */
76
77void odm_sw_ant_div_rest_after_link(void *dm_void) {}
78
79void odm_ant_div_reset(void *dm_void) {}
80
81void odm_antenna_diversity_init(void *dm_void) {}
82
83void odm_antenna_diversity(void *dm_void) {}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_antdiv.h b/drivers/staging/rtlwifi/phydm/phydm_antdiv.h
new file mode 100644
index 000000000000..ebbff2f56c5e
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_antdiv.h
@@ -0,0 +1,301 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMANTDIV_H__
27#define __PHYDMANTDIV_H__
28
29/* 2.0 2014.11.04
30 * 2.1 2015.01.13 Dino
31 * 2.2 2015.01.16 Dino
32 * 3.1 2015.07.29 YuChen, remove 92c 92d 8723a
33 * 3.2 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B
34 * 3.3 2015.08.12 Stanley. 8723B does not need to check the antenna is control
35 * by BT, because antenna diversity only works when BT is disable
36 * or radio off
37 * 3.4 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna
38 * Diversity
39 * 3.5 2015.10.07 Stanley Always check antenna detection result from BT-coex.
40 * for 8723B, not from PHYDM
41 * 3.6 2015.11.16 Stanley
42 * 3.7 2015.11.20 Dino Add SmartAnt FAT Patch
43 * 3.8 2015.12.21 Dino, Add SmartAnt dynamic training packet num
44 * 3.9 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and
45 * add cmd for adjust truth table
46 */
47#define ANTDIV_VERSION "3.9"
48
49/* 1 ============================================================
50 * 1 Definition
51 * 1 ============================================================
52 */
53
54#define ANTDIV_INIT 0xff
55#define MAIN_ANT 1 /*ant A or ant Main or S1*/
56#define AUX_ANT 2 /*AntB or ant Aux or S0*/
57#define MAX_ANT 3 /* 3 for AP using*/
58
59#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D,
60 * TX fixed at S1
61 */
62#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D,
63 * TX fixed at S1
64 */
65/*smart antenna*/
66#define SUPPORT_RF_PATH_NUM 4
67#define SUPPORT_BEAM_PATTERN_NUM 4
68#define NUM_ANTENNA_8821A 2
69
70#define SUPPORT_BEAM_SET_PATTERN_NUM 8
71
72#define NO_FIX_TX_ANT 0
73#define FIX_TX_AT_MAIN 1
74#define FIX_AUX_AT_MAIN 2
75
76/* Antenna Diversty Control type */
77#define ODM_AUTO_ANT 0
78#define ODM_FIX_MAIN_ANT 1
79#define ODM_FIX_AUX_ANT 2
80
81#define ODM_N_ANTDIV_SUPPORT \
82 (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | \
83 ODM_RTL8723D | ODM_RTL8195A)
84#define ODM_AC_ANTDIV_SUPPORT \
85 (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | \
86 ODM_RTL8822B | ODM_RTL8814B)
87#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
88#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
89#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
90
91#define ODM_ANTDIV_2G_SUPPORT_IC \
92 (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | \
93 ODM_RTL8188F | ODM_RTL8723D)
94#define ODM_ANTDIV_5G_SUPPORT_IC \
95 (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
96
97#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
98
99#define ODM_ANTDIV_2G BIT(0)
100#define ODM_ANTDIV_5G BIT(1)
101
102#define ANTDIV_ON 1
103#define ANTDIV_OFF 0
104
105#define FAT_ON 1
106#define FAT_OFF 0
107
108#define TX_BY_DESC 1
109#define TX_BY_REG 0
110
111#define RSSI_METHOD 0
112#define EVM_METHOD 1
113#define CRC32_METHOD 2
114
115#define INIT_ANTDIV_TIMMER 0
116#define CANCEL_ANTDIV_TIMMER 1
117#define RELEASE_ANTDIV_TIMMER 2
118
119#define CRC32_FAIL 1
120#define CRC32_OK 0
121
122#define evm_rssi_th_high 25
123#define evm_rssi_th_low 20
124
125#define NORMAL_STATE_MIAN 1
126#define NORMAL_STATE_AUX 2
127#define TRAINING_STATE 3
128
129#define FORCE_RSSI_DIFF 10
130
131#define CSI_ON 1
132#define CSI_OFF 0
133
134#define DIVON_CSIOFF 1
135#define DIVOFF_CSION 2
136
137#define BDC_DIV_TRAIN_STATE 0
138#define bdc_bfer_train_state 1
139#define BDC_DECISION_STATE 2
140#define BDC_BF_HOLD_STATE 3
141#define BDC_DIV_HOLD_STATE 4
142
143#define BDC_MODE_1 1
144#define BDC_MODE_2 2
145#define BDC_MODE_3 3
146#define BDC_MODE_4 4
147#define BDC_MODE_NULL 0xff
148
149/*SW S0S1 antenna diversity*/
150#define SWAW_STEP_INIT 0xff
151#define SWAW_STEP_PEEK 0
152#define SWAW_STEP_DETERMINE 1
153
154#define RSSI_CHECK_RESET_PERIOD 10
155#define RSSI_CHECK_THRESHOLD 50
156
157/*Hong Lin Smart antenna*/
158#define HL_SMTANT_2WIRE_DATA_LEN 24
159
160/* 1 ============================================================
161 * 1 structure
162 * 1 ============================================================
163 */
164
165struct sw_antenna_switch {
166 u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD",
167 *than check this antenna again
168 */
169 u8 try_flag;
170 s32 pre_rssi;
171 u8 cur_antenna;
172 u8 pre_antenna;
173 u8 rssi_trying;
174 u8 reset_idx;
175 u8 train_time;
176 u8 train_time_flag; /*base on RSSI difference between two antennas*/
177 struct timer_list phydm_sw_antenna_switch_timer;
178 u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
179 bool is_sw_ant_div_by_ctrl_frame;
180
181 /* AntDect (Before link Antenna Switch check) need to be moved*/
182 u16 single_ant_counter;
183 u16 dual_ant_counter;
184 u16 aux_fail_detec_counter;
185 u16 retry_counter;
186 u8 swas_no_link_state;
187 u32 swas_no_link_bk_reg948;
188 bool ANTA_ON; /*To indicate ant A is or not*/
189 bool ANTB_ON; /*To indicate ant B is on or not*/
190 bool pre_aux_fail_detec;
191 bool rssi_ant_dect_result;
192 u8 ant_5g;
193 u8 ant_2g;
194};
195
196struct fast_antenna_training {
197 u8 bssid[6];
198 u8 antsel_rx_keep_0;
199 u8 antsel_rx_keep_1;
200 u8 antsel_rx_keep_2;
201 u8 antsel_rx_keep_3;
202 u32 ant_sum_rssi[7];
203 u32 ant_rssi_cnt[7];
204 u32 ant_ave_rssi[7];
205 u8 fat_state;
206 u32 train_idx;
207 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
208 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
209 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
210 u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
211 u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
212 u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
213 u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
214 u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
215 u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
216 u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
217 u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
218 u8 rx_idle_ant;
219 u8 ant_div_on_off;
220 bool is_become_linked;
221 u32 min_max_rssi;
222 u8 idx_ant_div_counter_2g;
223 u8 idx_ant_div_counter_5g;
224 u8 ant_div_2g_5g;
225
226 u32 cck_ctrl_frame_cnt_main;
227 u32 cck_ctrl_frame_cnt_aux;
228 u32 ofdm_ctrl_frame_cnt_main;
229 u32 ofdm_ctrl_frame_cnt_aux;
230 u32 main_ant_ctrl_frame_sum;
231 u32 aux_ant_ctrl_frame_sum;
232 u32 main_ant_ctrl_frame_cnt;
233 u32 aux_ant_ctrl_frame_cnt;
234 u8 b_fix_tx_ant;
235 bool fix_ant_bfee;
236 bool enable_ctrl_frame_antdiv;
237 bool use_ctrl_frame_antdiv;
238 u8 hw_antsw_occur;
239 u8 *p_force_tx_ant_by_desc;
240 u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's
241 *outer parameter later
242 */
243 u8 *p_default_s0_s1;
244 u8 default_s0_s1;
245};
246
247/* 1 ============================================================
248 * 1 enumeration
249 * 1 ============================================================
250 */
251
252/*Fast antenna training*/
253enum fat_state {
254 FAT_BEFORE_LINK_STATE = 0,
255 FAT_PREPARE_STATE = 1,
256 FAT_TRAINING_STATE = 2,
257 FAT_DECISION_STATE = 3
258};
259
260enum ant_div_type {
261 NO_ANTDIV = 0xFF,
262 CG_TRX_HW_ANTDIV = 0x01,
263 CGCS_RX_HW_ANTDIV = 0x02,
264 FIXED_HW_ANTDIV = 0x03,
265 CG_TRX_SMART_ANTDIV = 0x04,
266 CGCS_RX_SW_ANTDIV = 0x05,
267 /*8723B intrnal switch S0 S1*/
268 S0S1_SW_ANTDIV = 0x06,
269 /*TRX S0S1 diversity for 8723D*/
270 S0S1_TRX_HW_ANTDIV = 0x07,
271 /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and
272 *each ant. is equipped with 4 antenna patterns
273 */
274 HL_SW_SMART_ANT_TYPE1 = 0x10,
275 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
276 HL_SW_SMART_ANT_TYPE2 = 0x11,
277};
278
279/* 1 ============================================================
280 * 1 function prototype
281 * 1 ============================================================
282 */
283
284void odm_stop_antenna_switch_dm(void *dm_void);
285
286void phydm_enable_antenna_diversity(void *dm_void);
287
288void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
289 );
290
291#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
292
293void odm_sw_ant_div_rest_after_link(void *dm_void);
294
295void odm_ant_div_reset(void *dm_void);
296
297void odm_antenna_diversity_init(void *dm_void);
298
299void odm_antenna_diversity(void *dm_void);
300
301#endif /*#ifndef __ODMANTDIV_H__*/
diff --git a/drivers/staging/rtlwifi/phydm/phydm_beamforming.h b/drivers/staging/rtlwifi/phydm/phydm_beamforming.h
new file mode 100644
index 000000000000..adc04ba4e218
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_beamforming.h
@@ -0,0 +1,48 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __INC_PHYDM_BEAMFORMING_H
26#define __INC_PHYDM_BEAMFORMING_H
27
28/*Beamforming Related*/
29#include "txbf/halcomtxbf.h"
30#include "txbf/haltxbfjaguar.h"
31#include "txbf/haltxbf8822b.h"
32#include "txbf/haltxbfinterface.h"
33
34#define beamforming_gid_paid(adapter, tcb)
35#define phydm_acting_determine(dm, type) false
36#define beamforming_enter(dm, sta_idx)
37#define beamforming_leave(dm, RA)
38#define beamforming_end_fw(dm)
39#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
40#define beamforming_control_v2(dm, idx, mode, BW, period) true
41#define phydm_beamforming_end_sw(dm, _status)
42#define beamforming_timer_callback(dm)
43#define phydm_beamforming_init(dm)
44#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
45#define beamforming_watchdog(dm)
46#define phydm_beamforming_watchdog(dm)
47
48#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_ccx.c b/drivers/staging/rtlwifi/phydm/phydm_ccx.c
new file mode 100644
index 000000000000..2e0dc68757dc
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_ccx.c
@@ -0,0 +1,457 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#include "mp_precomp.h"
26#include "phydm_precomp.h"
27
28/*Set NHM period, threshold, disable ignore cca or not,
29 *disable ignore txon or not
30 */
31void phydm_nhm_setting(void *dm_void, u8 nhm_setting)
32{
33 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
34 struct ccx_info *ccx_info = &dm->dm_ccx_info;
35
36 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
37 if (nhm_setting == SET_NHM_SETTING) {
38 /*Set inexclude_cca, inexclude_txon*/
39 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
40 ccx_info->nhm_inexclude_cca);
41 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
42 ccx_info->nhm_inexclude_txon);
43
44 /*Set NHM period*/
45 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
46 ccx_info->NHM_period);
47
48 /*Set NHM threshold*/
49 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
50 MASKBYTE0, ccx_info->NHM_th[0]);
51 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
52 MASKBYTE1, ccx_info->NHM_th[1]);
53 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
54 MASKBYTE2, ccx_info->NHM_th[2]);
55 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
56 MASKBYTE3, ccx_info->NHM_th[3]);
57 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
58 MASKBYTE0, ccx_info->NHM_th[4]);
59 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
60 MASKBYTE1, ccx_info->NHM_th[5]);
61 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
62 MASKBYTE2, ccx_info->NHM_th[6]);
63 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
64 MASKBYTE3, ccx_info->NHM_th[7]);
65 odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
66 ccx_info->NHM_th[8]);
67 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
68 ccx_info->NHM_th[9]);
69 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
70 ccx_info->NHM_th[10]);
71
72 /*CCX EN*/
73 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8),
74 CCX_EN);
75 } else if (nhm_setting == STORE_NHM_SETTING) {
76 /*Store prev. disable_ignore_cca, disable_ignore_txon*/
77 ccx_info->NHM_inexclude_cca_restore =
78 (enum nhm_inexclude_cca)odm_get_bb_reg(
79 dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9));
80 ccx_info->NHM_inexclude_txon_restore =
81 (enum nhm_inexclude_txon)odm_get_bb_reg(
82 dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10));
83
84 /*Store pervious NHM period*/
85 ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
86 dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD);
87
88 /*Store NHM threshold*/
89 ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
90 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0);
91 ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
92 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1);
93 ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
94 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2);
95 ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
96 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3);
97 ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
98 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0);
99 ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
100 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1);
101 ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
102 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2);
103 ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
104 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3);
105 ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
106 dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0);
107 ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
108 dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2);
109 ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
110 dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3);
111 } else if (nhm_setting == RESTORE_NHM_SETTING) {
112 /*Set disable_ignore_cca, disable_ignore_txon*/
113 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
114 ccx_info->NHM_inexclude_cca_restore);
115 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
116 ccx_info->NHM_inexclude_txon_restore);
117
118 /*Set NHM period*/
119 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
120 ccx_info->NHM_period);
121
122 /*Set NHM threshold*/
123 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
124 MASKBYTE0, ccx_info->NHM_th_restore[0]);
125 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
126 MASKBYTE1, ccx_info->NHM_th_restore[1]);
127 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
128 MASKBYTE2, ccx_info->NHM_th_restore[2]);
129 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
130 MASKBYTE3, ccx_info->NHM_th_restore[3]);
131 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
132 MASKBYTE0, ccx_info->NHM_th_restore[4]);
133 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
134 MASKBYTE1, ccx_info->NHM_th_restore[5]);
135 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
136 MASKBYTE2, ccx_info->NHM_th_restore[6]);
137 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
138 MASKBYTE3, ccx_info->NHM_th_restore[7]);
139 odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
140 ccx_info->NHM_th_restore[8]);
141 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
142 ccx_info->NHM_th_restore[9]);
143 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
144 ccx_info->NHM_th_restore[10]);
145 } else {
146 return;
147 }
148 }
149
150 else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
151 if (nhm_setting == SET_NHM_SETTING) {
152 /*Set disable_ignore_cca, disable_ignore_txon*/
153 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
154 ccx_info->nhm_inexclude_cca);
155 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
156 ccx_info->nhm_inexclude_txon);
157
158 /*Set NHM period*/
159 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
160 ccx_info->NHM_period);
161
162 /*Set NHM threshold*/
163 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
164 MASKBYTE0, ccx_info->NHM_th[0]);
165 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
166 MASKBYTE1, ccx_info->NHM_th[1]);
167 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
168 MASKBYTE2, ccx_info->NHM_th[2]);
169 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
170 MASKBYTE3, ccx_info->NHM_th[3]);
171 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
172 MASKBYTE0, ccx_info->NHM_th[4]);
173 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
174 MASKBYTE1, ccx_info->NHM_th[5]);
175 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
176 MASKBYTE2, ccx_info->NHM_th[6]);
177 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
178 MASKBYTE3, ccx_info->NHM_th[7]);
179 odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
180 ccx_info->NHM_th[8]);
181 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
182 ccx_info->NHM_th[9]);
183 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
184 ccx_info->NHM_th[10]);
185
186 /*CCX EN*/
187 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(8),
188 CCX_EN);
189 } else if (nhm_setting == STORE_NHM_SETTING) {
190 /*Store prev. disable_ignore_cca, disable_ignore_txon*/
191 ccx_info->NHM_inexclude_cca_restore =
192 (enum nhm_inexclude_cca)odm_get_bb_reg(
193 dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9));
194 ccx_info->NHM_inexclude_txon_restore =
195 (enum nhm_inexclude_txon)odm_get_bb_reg(
196 dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10));
197
198 /*Store pervious NHM period*/
199 ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
200 dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD);
201
202 /*Store NHM threshold*/
203 ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
204 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0);
205 ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
206 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1);
207 ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
208 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2);
209 ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
210 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3);
211 ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
212 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0);
213 ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
214 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1);
215 ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
216 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2);
217 ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
218 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3);
219 ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
220 dm, ODM_REG_NHM_TH8_11N, MASKBYTE0);
221 ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
222 dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2);
223 ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
224 dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3);
225 } else if (nhm_setting == RESTORE_NHM_SETTING) {
226 /*Set disable_ignore_cca, disable_ignore_txon*/
227 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
228 ccx_info->NHM_inexclude_cca_restore);
229 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
230 ccx_info->NHM_inexclude_txon_restore);
231
232 /*Set NHM period*/
233 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
234 ccx_info->NHM_period_restore);
235
236 /*Set NHM threshold*/
237 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
238 MASKBYTE0, ccx_info->NHM_th_restore[0]);
239 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
240 MASKBYTE1, ccx_info->NHM_th_restore[1]);
241 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
242 MASKBYTE2, ccx_info->NHM_th_restore[2]);
243 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
244 MASKBYTE3, ccx_info->NHM_th_restore[3]);
245 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
246 MASKBYTE0, ccx_info->NHM_th_restore[4]);
247 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
248 MASKBYTE1, ccx_info->NHM_th_restore[5]);
249 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
250 MASKBYTE2, ccx_info->NHM_th_restore[6]);
251 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
252 MASKBYTE3, ccx_info->NHM_th_restore[7]);
253 odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
254 ccx_info->NHM_th_restore[8]);
255 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
256 ccx_info->NHM_th_restore[9]);
257 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
258 ccx_info->NHM_th_restore[10]);
259 } else {
260 return;
261 }
262 }
263}
264
265void phydm_nhm_trigger(void *dm_void)
266{
267 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
268
269 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
270 /*Trigger NHM*/
271 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
272 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
273 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
274 /*Trigger NHM*/
275 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
276 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
277 }
278}
279
280void phydm_get_nhm_result(void *dm_void)
281{
282 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
283 u32 value32;
284 struct ccx_info *ccx_info = &dm->dm_ccx_info;
285
286 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
287 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC);
288 ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
289 ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
290 ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
291 ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
292
293 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
294 ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
295 ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
296 ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
297 ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
298
299 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT11_TO_CNT8_11AC);
300 ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0);
301 ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8);
302 ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
303 ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
304
305 /*Get NHM duration*/
306 value32 = odm_read_4byte(dm, ODM_REG_NHM_DUR_READY_11AC);
307 ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
308 }
309
310 else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
311 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N);
312 ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
313 ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
314 ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
315 ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
316
317 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
318 ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
319 ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
320 ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
321 ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
322
323 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT9_TO_CNT8_11N);
324 ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16);
325 ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24);
326
327 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
328 ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
329 ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
330
331 /*Get NHM duration*/
332 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
333 ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
334 }
335}
336
337bool phydm_check_nhm_ready(void *dm_void)
338{
339 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
340 u32 value32 = 0;
341 u8 i;
342 bool ret = false;
343
344 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
345 value32 =
346 odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC, MASKDWORD);
347
348 for (i = 0; i < 200; i++) {
349 ODM_delay_ms(1);
350 if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
351 BIT(17))) {
352 ret = 1;
353 break;
354 }
355 }
356 }
357
358 else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
359 value32 = odm_get_bb_reg(dm, ODM_REG_CLM_READY_11N, MASKDWORD);
360
361 for (i = 0; i < 200; i++) {
362 ODM_delay_ms(1);
363 if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
364 BIT(17))) {
365 ret = 1;
366 break;
367 }
368 }
369 }
370 return ret;
371}
372
373void phydm_clm_setting(void *dm_void)
374{
375 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
376 struct ccx_info *ccx_info = &dm->dm_ccx_info;
377
378 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
379 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD,
380 ccx_info->CLM_period); /*4us sample 1 time*/
381 odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(8),
382 0x1); /*Enable CCX for CLM*/
383
384 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
385 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKLWORD,
386 ccx_info->CLM_period); /*4us sample 1 time*/
387 odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(8),
388 0x1); /*Enable CCX for CLM*/
389 }
390
391 ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM period = %dus\n", __func__,
392 ccx_info->CLM_period * 4);
393}
394
395void phydm_clm_trigger(void *dm_void)
396{
397 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
398
399 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
400 odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0),
401 0x0); /*Trigger CLM*/
402 odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0), 0x1);
403 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
404 odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0),
405 0x0); /*Trigger CLM*/
406 odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0), 0x1);
407 }
408}
409
410bool phydm_check_cl_mready(void *dm_void)
411{
412 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
413 u32 value32 = 0;
414 bool ret = false;
415
416 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
417 value32 = odm_get_bb_reg(
418 dm, ODM_REG_CLM_RESULT_11AC,
419 MASKDWORD); /*make sure CLM calc is ready*/
420 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
421 value32 = odm_get_bb_reg(
422 dm, ODM_REG_CLM_READY_11N,
423 MASKDWORD); /*make sure CLM calc is ready*/
424
425 if ((dm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16)))
426 ret = true;
427 else if ((dm->support_ic_type & ODM_IC_11N_SERIES) &&
428 (value32 & BIT(16)))
429 ret = true;
430 else
431 ret = false;
432
433 ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM ready = %d\n", __func__,
434 ret);
435
436 return ret;
437}
438
439void phydm_get_cl_mresult(void *dm_void)
440{
441 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
442 struct ccx_info *ccx_info = &dm->dm_ccx_info;
443
444 u32 value32 = 0;
445
446 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
447 value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC,
448 MASKDWORD); /*read CLM calc result*/
449 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
450 value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11N,
451 MASKDWORD); /*read CLM calc result*/
452
453 ccx_info->CLM_result = (u16)(value32 & MASKLWORD);
454
455 ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM result = %dus\n", __func__,
456 ccx_info->CLM_result * 4);
457}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_ccx.h b/drivers/staging/rtlwifi/phydm/phydm_ccx.h
new file mode 100644
index 000000000000..a3517f4642f9
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_ccx.h
@@ -0,0 +1,83 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __PHYDMCCX_H__
26#define __PHYDMCCX_H__
27
28#define CCX_EN 1
29
30#define SET_NHM_SETTING 0
31#define STORE_NHM_SETTING 1
32#define RESTORE_NHM_SETTING 2
33
34enum nhm_inexclude_cca { NHM_EXCLUDE_CCA, NHM_INCLUDE_CCA };
35
36enum nhm_inexclude_txon { NHM_EXCLUDE_TXON, NHM_INCLUDE_TXON };
37
38struct ccx_info {
39 /*Settings*/
40 u8 NHM_th[11];
41 u16 NHM_period; /* 4us per unit */
42 u16 CLM_period; /* 4us per unit */
43 enum nhm_inexclude_txon nhm_inexclude_txon;
44 enum nhm_inexclude_cca nhm_inexclude_cca;
45
46 /*Previous Settings*/
47 u8 NHM_th_restore[11];
48 u16 NHM_period_restore; /* 4us per unit */
49 u16 CLM_period_restore; /* 4us per unit */
50 enum nhm_inexclude_txon NHM_inexclude_txon_restore;
51 enum nhm_inexclude_cca NHM_inexclude_cca_restore;
52
53 /*Report*/
54 u8 NHM_result[12];
55 u16 NHM_duration;
56 u16 CLM_result;
57
58 bool echo_NHM_en;
59 bool echo_CLM_en;
60 u8 echo_IGI;
61};
62
63/*NHM*/
64
65void phydm_nhm_setting(void *dm_void, u8 nhm_setting);
66
67void phydm_nhm_trigger(void *dm_void);
68
69void phydm_get_nhm_result(void *dm_void);
70
71bool phydm_check_nhm_ready(void *dm_void);
72
73/*CLM*/
74
75void phydm_clm_setting(void *dm_void);
76
77void phydm_clm_trigger(void *dm_void);
78
79bool phydm_check_cl_mready(void *dm_void);
80
81void phydm_get_cl_mresult(void *dm_void);
82
83#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_cfotracking.c b/drivers/staging/rtlwifi/phydm/phydm_cfotracking.c
new file mode 100644
index 000000000000..2ec8444f31a7
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_cfotracking.c
@@ -0,0 +1,343 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#include "mp_precomp.h"
26#include "phydm_precomp.h"
27
28static void odm_set_crystal_cap(void *dm_void, u8 crystal_cap)
29{
30 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
31 struct cfo_tracking *cfo_track =
32 (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
33
34 if (cfo_track->crystal_cap == crystal_cap)
35 return;
36
37 cfo_track->crystal_cap = crystal_cap;
38
39 if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
40 /* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
41 crystal_cap = crystal_cap & 0x3F;
42 odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x007ff800,
43 (crystal_cap | (crystal_cap << 6)));
44 } else if (dm->support_ic_type & ODM_RTL8812) {
45 /* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
46 crystal_cap = crystal_cap & 0x3F;
47 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x7FF80000,
48 (crystal_cap | (crystal_cap << 6)));
49 } else if ((dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B |
50 ODM_RTL8192E | ODM_RTL8821))) {
51 /* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */
52 crystal_cap = crystal_cap & 0x3F;
53 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x00FFF000,
54 (crystal_cap | (crystal_cap << 6)));
55 } else if (dm->support_ic_type & ODM_RTL8814A) {
56 /* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
57 crystal_cap = crystal_cap & 0x3F;
58 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x07FF8000,
59 (crystal_cap | (crystal_cap << 6)));
60 } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
61 /* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
62 crystal_cap = crystal_cap & 0x3F;
63 odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
64 odm_set_bb_reg(dm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
65 } else {
66 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
67 "%s(): Use default setting.\n", __func__);
68 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000,
69 (crystal_cap | (crystal_cap << 6)));
70 }
71
72 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING, "%s(): crystal_cap = 0x%x\n",
73 __func__, crystal_cap);
74
75 /* JJ modified 20161115 */
76}
77
78static u8 odm_get_default_crytaltal_cap(void *dm_void)
79{
80 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
81 u8 crystal_cap = 0x20;
82
83 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
84 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
85
86 crystal_cap = rtlefuse->crystalcap;
87
88 crystal_cap = crystal_cap & 0x3f;
89
90 return crystal_cap;
91}
92
93static void odm_set_atc_status(void *dm_void, bool atc_status)
94{
95 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
96 struct cfo_tracking *cfo_track =
97 (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
98
99 if (cfo_track->is_atc_status == atc_status)
100 return;
101
102 odm_set_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm),
103 atc_status);
104 cfo_track->is_atc_status = atc_status;
105}
106
107static bool odm_get_atc_status(void *dm_void)
108{
109 bool atc_status;
110 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
111
112 atc_status = (bool)odm_get_bb_reg(dm, ODM_REG(BB_ATC, dm),
113 ODM_BIT(BB_ATC, dm));
114 return atc_status;
115}
116
117void odm_cfo_tracking_reset(void *dm_void)
118{
119 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
120 struct cfo_tracking *cfo_track =
121 (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
122
123 cfo_track->def_x_cap = odm_get_default_crytaltal_cap(dm);
124 cfo_track->is_adjust = true;
125
126 if (cfo_track->crystal_cap > cfo_track->def_x_cap) {
127 odm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);
128 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
129 "%s(): approch default value (0x%x)\n", __func__,
130 cfo_track->crystal_cap);
131 } else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {
132 odm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);
133 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
134 "%s(): approch default value (0x%x)\n", __func__,
135 cfo_track->crystal_cap);
136 }
137
138 odm_set_atc_status(dm, true);
139}
140
141void odm_cfo_tracking_init(void *dm_void)
142{
143 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
144 struct cfo_tracking *cfo_track =
145 (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
146
147 cfo_track->crystal_cap = odm_get_default_crytaltal_cap(dm);
148 cfo_track->def_x_cap = cfo_track->crystal_cap;
149 cfo_track->is_atc_status = odm_get_atc_status(dm);
150 cfo_track->is_adjust = true;
151 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING, "%s()=========>\n", __func__);
152 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
153 "%s(): is_atc_status = %d, crystal_cap = 0x%x\n", __func__,
154 cfo_track->is_atc_status, cfo_track->def_x_cap);
155
156 /* Crystal cap. control by WiFi */
157 if (dm->support_ic_type & ODM_RTL8822B)
158 odm_set_bb_reg(dm, 0x10, 0x40, 0x1);
159}
160
161void odm_cfo_tracking(void *dm_void)
162{
163 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
164 struct cfo_tracking *cfo_track =
165 (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
166 s32 cfo_ave = 0;
167 u32 cfo_rpt_sum, cfo_khz_avg[4] = {0};
168 s32 cfo_ave_diff;
169 s8 crystal_cap = cfo_track->crystal_cap;
170 u8 adjust_xtal = 1, i, valid_path_cnt = 0;
171
172 /* 4 Support ability */
173 if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) {
174 ODM_RT_TRACE(
175 dm, ODM_COMP_CFO_TRACKING,
176 "%s(): Return: support_ability ODM_BB_CFO_TRACKING is disabled\n",
177 __func__);
178 return;
179 }
180
181 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING, "%s()=========>\n", __func__);
182
183 if (!dm->is_linked || !dm->is_one_entry_only) {
184 /* 4 No link or more than one entry */
185 odm_cfo_tracking_reset(dm);
186 ODM_RT_TRACE(
187 dm, ODM_COMP_CFO_TRACKING,
188 "%s(): Reset: is_linked = %d, is_one_entry_only = %d\n",
189 __func__, dm->is_linked, dm->is_one_entry_only);
190 } else {
191 /* 3 1. CFO Tracking */
192 /* 4 1.1 No new packet */
193 if (cfo_track->packet_count == cfo_track->packet_count_pre) {
194 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
195 "%s(): packet counter doesn't change\n",
196 __func__);
197 return;
198 }
199 cfo_track->packet_count_pre = cfo_track->packet_count;
200
201 /* 4 1.2 Calculate CFO */
202 for (i = 0; i < dm->num_rf_path; i++) {
203 if (cfo_track->CFO_cnt[i] == 0)
204 continue;
205
206 valid_path_cnt++;
207 cfo_rpt_sum =
208 (u32)((cfo_track->CFO_tail[i] < 0) ?
209 (0 - cfo_track->CFO_tail[i]) :
210 cfo_track->CFO_tail[i]);
211 cfo_khz_avg[i] = CFO_HW_RPT_2_MHZ(cfo_rpt_sum) /
212 cfo_track->CFO_cnt[i];
213
214 ODM_RT_TRACE(
215 dm, ODM_COMP_CFO_TRACKING,
216 "[path %d] cfo_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n",
217 i, cfo_rpt_sum, cfo_track->CFO_cnt[i],
218 ((cfo_track->CFO_tail[i] < 0) ? "-" : " "),
219 cfo_khz_avg[i]);
220 }
221
222 for (i = 0; i < valid_path_cnt; i++) {
223 if (cfo_track->CFO_tail[i] < 0) {
224 /* */
225 cfo_ave += (0 - (s32)cfo_khz_avg[i]);
226 } else {
227 cfo_ave += (s32)cfo_khz_avg[i];
228 }
229 }
230
231 if (valid_path_cnt >= 2)
232 cfo_ave = cfo_ave / valid_path_cnt;
233
234 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
235 "valid_path_cnt = ((%d)), cfo_ave = ((%d kHz))\n",
236 valid_path_cnt, cfo_ave);
237
238 /*reset counter*/
239 for (i = 0; i < dm->num_rf_path; i++) {
240 cfo_track->CFO_tail[i] = 0;
241 cfo_track->CFO_cnt[i] = 0;
242 }
243
244 /* 4 1.3 Avoid abnormal large CFO */
245 cfo_ave_diff = (cfo_track->CFO_ave_pre >= cfo_ave) ?
246 (cfo_track->CFO_ave_pre - cfo_ave) :
247 (cfo_ave - cfo_track->CFO_ave_pre);
248 if (cfo_ave_diff > 20 && cfo_track->large_cfo_hit == 0 &&
249 !cfo_track->is_adjust) {
250 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
251 "%s(): first large CFO hit\n", __func__);
252 cfo_track->large_cfo_hit = 1;
253 return;
254 }
255
256 cfo_track->large_cfo_hit = 0;
257 cfo_track->CFO_ave_pre = cfo_ave;
258
259 /* 4 1.4 Dynamic Xtal threshold */
260 if (!cfo_track->is_adjust) {
261 if (cfo_ave > CFO_TH_XTAL_HIGH ||
262 cfo_ave < (-CFO_TH_XTAL_HIGH))
263 cfo_track->is_adjust = true;
264 } else {
265 if (cfo_ave < CFO_TH_XTAL_LOW &&
266 cfo_ave > (-CFO_TH_XTAL_LOW))
267 cfo_track->is_adjust = false;
268 }
269
270 /* 4 1.5 BT case: Disable CFO tracking */
271 if (dm->is_bt_enabled) {
272 cfo_track->is_adjust = false;
273 odm_set_crystal_cap(dm, cfo_track->def_x_cap);
274 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
275 "%s(): Disable CFO tracking for BT!!\n",
276 __func__);
277 }
278
279 /* 4 1.7 Adjust Crystal Cap. */
280 if (cfo_track->is_adjust) {
281 if (cfo_ave > CFO_TH_XTAL_LOW)
282 crystal_cap = crystal_cap + adjust_xtal;
283 else if (cfo_ave < (-CFO_TH_XTAL_LOW))
284 crystal_cap = crystal_cap - adjust_xtal;
285
286 if (crystal_cap > 0x3f)
287 crystal_cap = 0x3f;
288 else if (crystal_cap < 0)
289 crystal_cap = 0;
290
291 odm_set_crystal_cap(dm, (u8)crystal_cap);
292 }
293 ODM_RT_TRACE(
294 dm, ODM_COMP_CFO_TRACKING,
295 "%s(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
296 __func__, cfo_track->crystal_cap, cfo_track->def_x_cap);
297
298 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
299 return;
300
301 /* 3 2. Dynamic ATC switch */
302 if (cfo_ave < CFO_TH_ATC && cfo_ave > -CFO_TH_ATC) {
303 odm_set_atc_status(dm, false);
304 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
305 "%s(): Disable ATC!!\n", __func__);
306 } else {
307 odm_set_atc_status(dm, true);
308 ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
309 "%s(): Enable ATC!!\n", __func__);
310 }
311 }
312}
313
314void odm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail, u8 num_ss)
315{
316 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
317 struct dm_per_pkt_info *pktinfo =
318 (struct dm_per_pkt_info *)pktinfo_void;
319 struct cfo_tracking *cfo_track =
320 (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
321 u8 i;
322
323 if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
324 return;
325
326 if (pktinfo->is_packet_match_bssid) {
327 if (num_ss > dm->num_rf_path) /*For fool proof*/
328 num_ss = dm->num_rf_path;
329
330 /* 3 Update CFO report for path-A & path-B */
331 /* Only paht-A and path-B have CFO tail and short CFO */
332 for (i = 0; i < num_ss; i++) {
333 cfo_track->CFO_tail[i] += pcfotail[i];
334 cfo_track->CFO_cnt[i]++;
335 }
336
337 /* 3 Update packet counter */
338 if (cfo_track->packet_count == 0xffffffff)
339 cfo_track->packet_count = 0;
340 else
341 cfo_track->packet_count++;
342 }
343}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_cfotracking.h b/drivers/staging/rtlwifi/phydm/phydm_cfotracking.h
new file mode 100644
index 000000000000..e8436a31019d
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_cfotracking.h
@@ -0,0 +1,60 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMCFOTRACK_H__
27#define __PHYDMCFOTRACK_H__
28
29#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/
30
31#define CFO_TH_XTAL_HIGH 20 /* kHz */
32#define CFO_TH_XTAL_LOW 10 /* kHz */
33#define CFO_TH_ATC 80 /* kHz */
34
35struct cfo_tracking {
36 bool is_atc_status;
37 bool large_cfo_hit;
38 bool is_adjust;
39 u8 crystal_cap;
40 u8 def_x_cap;
41 s32 CFO_tail[4];
42 u32 CFO_cnt[4];
43 s32 CFO_ave_pre;
44 u32 packet_count;
45 u32 packet_count_pre;
46
47 bool is_force_xtal_cap;
48 bool is_reset;
49};
50
51void odm_cfo_tracking_reset(void *dm_void);
52
53void odm_cfo_tracking_init(void *dm_void);
54
55void odm_cfo_tracking(void *dm_void);
56
57void odm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
58 u8 num_ss);
59
60#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_debug.c b/drivers/staging/rtlwifi/phydm/phydm_debug.c
new file mode 100644
index 000000000000..a5f90afdae9b
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_debug.c
@@ -0,0 +1,2910 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29
30#include "mp_precomp.h"
31#include "phydm_precomp.h"
32
33bool phydm_api_set_txagc(struct phy_dm_struct *, u32, enum odm_rf_radio_path,
34 u8, bool);
35static inline void phydm_check_dmval_txagc(struct phy_dm_struct *dm, u32 used,
36 u32 out_len, u32 *const dm_value,
37 char *output)
38{
39 if ((u8)dm_value[2] != 0xff) {
40 if (phydm_api_set_txagc(dm, dm_value[3],
41 (enum odm_rf_radio_path)dm_value[1],
42 (u8)dm_value[2], true))
43 PHYDM_SNPRINTF(output + used, out_len - used,
44 " %s%d %s%x%s%x\n", "Write path-",
45 dm_value[1], "rate index-0x",
46 dm_value[2], " = 0x", dm_value[3]);
47 else
48 PHYDM_SNPRINTF(output + used, out_len - used,
49 " %s%d %s%x%s\n", "Write path-",
50 (dm_value[1] & 0x1), "rate index-0x",
51 (dm_value[2] & 0x7f), " fail");
52 } else {
53 u8 i;
54 u32 power_index;
55 bool status = true;
56
57 power_index = (dm_value[3] & 0x3f);
58
59 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
60 power_index = (power_index << 24) |
61 (power_index << 16) | (power_index << 8) |
62 (power_index);
63 for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4)
64 status = (status &
65 phydm_api_set_txagc(
66 dm, power_index,
67 (enum odm_rf_radio_path)
68 dm_value[1],
69 i, false));
70 } else if (dm->support_ic_type & ODM_RTL8197F) {
71 for (i = 0; i <= ODM_RATEMCS15; i++)
72 status = (status &
73 phydm_api_set_txagc(
74 dm, power_index,
75 (enum odm_rf_radio_path)
76 dm_value[1],
77 i, false));
78 }
79
80 if (status)
81 PHYDM_SNPRINTF(output + used, out_len - used,
82 " %s%d %s%x\n",
83 "Write all TXAGC of path-", dm_value[1],
84 " = 0x", dm_value[3]);
85 else
86 PHYDM_SNPRINTF(output + used, out_len - used,
87 " %s%d %s\n",
88 "Write all TXAGC of path-", dm_value[1],
89 " fail");
90 }
91}
92
93static inline void phydm_print_nhm_trigger(char *output, u32 used, u32 out_len,
94 struct ccx_info *ccx_info)
95{
96 int i;
97
98 for (i = 0; i <= 10; i++) {
99 if (i == 5)
100 PHYDM_SNPRINTF(
101 output + used, out_len - used,
102 "\r\n NHM_th[%d] = 0x%x, echo_IGI = 0x%x", i,
103 ccx_info->NHM_th[i], ccx_info->echo_IGI);
104 else if (i == 10)
105 PHYDM_SNPRINTF(output + used, out_len - used,
106 "\r\n NHM_th[%d] = 0x%x\n", i,
107 ccx_info->NHM_th[i]);
108 else
109 PHYDM_SNPRINTF(output + used, out_len - used,
110 "\r\n NHM_th[%d] = 0x%x", i,
111 ccx_info->NHM_th[i]);
112 }
113}
114
115static inline void phydm_print_nhm_result(char *output, u32 used, u32 out_len,
116 struct ccx_info *ccx_info)
117{
118 int i;
119
120 for (i = 0; i <= 11; i++) {
121 if (i == 5)
122 PHYDM_SNPRINTF(
123 output + used, out_len - used,
124 "\r\n nhm_result[%d] = %d, echo_IGI = 0x%x", i,
125 ccx_info->NHM_result[i], ccx_info->echo_IGI);
126 else if (i == 11)
127 PHYDM_SNPRINTF(output + used, out_len - used,
128 "\r\n nhm_result[%d] = %d\n", i,
129 ccx_info->NHM_result[i]);
130 else
131 PHYDM_SNPRINTF(output + used, out_len - used,
132 "\r\n nhm_result[%d] = %d", i,
133 ccx_info->NHM_result[i]);
134 }
135}
136
137static inline void phydm_print_csi(struct phy_dm_struct *dm, u32 used,
138 u32 out_len, char *output)
139{
140 int index, ptr;
141 u32 dword_h, dword_l;
142
143 for (index = 0; index < 80; index++) {
144 ptr = index + 256;
145
146 if (ptr > 311)
147 ptr -= 312;
148
149 odm_set_bb_reg(dm, 0x1910, 0x03FF0000, ptr); /*Select Address*/
150 dword_h = odm_get_bb_reg(dm, 0xF74, MASKDWORD);
151 dword_l = odm_get_bb_reg(dm, 0xF5C, MASKDWORD);
152
153 if (index % 2 == 0)
154 PHYDM_SNPRINTF(
155 output + used, out_len - used,
156 "%02x %02x %02x %02x %02x %02x %02x %02x\n",
157 dword_l & MASKBYTE0, (dword_l & MASKBYTE1) >> 8,
158 (dword_l & MASKBYTE2) >> 16,
159 (dword_l & MASKBYTE3) >> 24,
160 dword_h & MASKBYTE0, (dword_h & MASKBYTE1) >> 8,
161 (dword_h & MASKBYTE2) >> 16,
162 (dword_h & MASKBYTE3) >> 24);
163 else
164 PHYDM_SNPRINTF(
165 output + used, out_len - used,
166 "%02x %02x %02x %02x %02x %02x %02x %02x\n",
167 dword_l & MASKBYTE0, (dword_l & MASKBYTE1) >> 8,
168 (dword_l & MASKBYTE2) >> 16,
169 (dword_l & MASKBYTE3) >> 24,
170 dword_h & MASKBYTE0, (dword_h & MASKBYTE1) >> 8,
171 (dword_h & MASKBYTE2) >> 16,
172 (dword_h & MASKBYTE3) >> 24);
173 }
174}
175
176void phydm_init_debug_setting(struct phy_dm_struct *dm)
177{
178 dm->debug_level = ODM_DBG_TRACE;
179
180 dm->fw_debug_components = 0;
181 dm->debug_components =
182
183 0;
184
185 dm->fw_buff_is_enpty = true;
186 dm->pre_c2h_seq = 0;
187}
188
189u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port)
190{
191 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
192 u8 dbg_port_result = false;
193
194 if (curr_dbg_priority > dm->pre_dbg_priority) {
195 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
196 odm_set_bb_reg(dm, 0x8fc, MASKDWORD, debug_port);
197 /**/
198 } else /*if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ {
199 odm_set_bb_reg(dm, 0x908, MASKDWORD, debug_port);
200 /**/
201 }
202 ODM_RT_TRACE(
203 dm, ODM_COMP_API,
204 "DbgPort set success, Reg((0x%x)), Cur_priority=((%d)), Pre_priority=((%d))\n",
205 debug_port, curr_dbg_priority, dm->pre_dbg_priority);
206 dm->pre_dbg_priority = curr_dbg_priority;
207 dbg_port_result = true;
208 }
209
210 return dbg_port_result;
211}
212
213void phydm_release_bb_dbg_port(void *dm_void)
214{
215 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
216
217 dm->pre_dbg_priority = BB_DBGPORT_RELEASE;
218 ODM_RT_TRACE(dm, ODM_COMP_API, "Release BB dbg_port\n");
219}
220
221u32 phydm_get_bb_dbg_port_value(void *dm_void)
222{
223 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
224 u32 dbg_port_value = 0;
225
226 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
227 dbg_port_value = odm_get_bb_reg(dm, 0xfa0, MASKDWORD);
228 /**/
229 } else /*if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ {
230 dbg_port_value = odm_get_bb_reg(dm, 0xdf4, MASKDWORD);
231 /**/
232 }
233 ODM_RT_TRACE(dm, ODM_COMP_API, "dbg_port_value = 0x%x\n",
234 dbg_port_value);
235 return dbg_port_value;
236}
237
238static void phydm_bb_rx_hang_info(void *dm_void, u32 *_used, char *output,
239 u32 *_out_len)
240{
241 u32 value32 = 0;
242 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
243 u32 used = *_used;
244 u32 out_len = *_out_len;
245
246 if (dm->support_ic_type & ODM_IC_11N_SERIES)
247 return;
248
249 value32 = odm_get_bb_reg(dm, 0xF80, MASKDWORD);
250 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = 0x%x",
251 "rptreg of sc/bw/ht/...", value32);
252
253 if (dm->support_ic_type & ODM_RTL8822B)
254 odm_set_bb_reg(dm, 0x198c, BIT(2) | BIT(1) | BIT(0), 7);
255
256 /* dbg_port = basic state machine */
257 {
258 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);
259 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
260 PHYDM_SNPRINTF(output + used, out_len - used,
261 "\r\n %-35s = 0x%x", "0x8fc", value32);
262
263 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
264 PHYDM_SNPRINTF(output + used, out_len - used,
265 "\r\n %-35s = 0x%x", "basic state machine",
266 value32);
267 }
268
269 /* dbg_port = state machine */
270 {
271 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);
272 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
273 PHYDM_SNPRINTF(output + used, out_len - used,
274 "\r\n %-35s = 0x%x", "0x8fc", value32);
275
276 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
277 PHYDM_SNPRINTF(output + used, out_len - used,
278 "\r\n %-35s = 0x%x", "state machine", value32);
279 }
280
281 /* dbg_port = CCA-related*/
282 {
283 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);
284 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
285 PHYDM_SNPRINTF(output + used, out_len - used,
286 "\r\n %-35s = 0x%x", "0x8fc", value32);
287
288 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
289 PHYDM_SNPRINTF(output + used, out_len - used,
290 "\r\n %-35s = 0x%x", "CCA-related", value32);
291 }
292
293 /* dbg_port = edcca/rxd*/
294 {
295 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);
296 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
297 PHYDM_SNPRINTF(output + used, out_len - used,
298 "\r\n %-35s = 0x%x", "0x8fc", value32);
299
300 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
301 PHYDM_SNPRINTF(output + used, out_len - used,
302 "\r\n %-35s = 0x%x", "edcca/rxd", value32);
303 }
304
305 /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/
306 {
307 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);
308 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
309 PHYDM_SNPRINTF(output + used, out_len - used,
310 "\r\n %-35s = 0x%x", "0x8fc", value32);
311
312 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
313 PHYDM_SNPRINTF(output + used, out_len - used,
314 "\r\n %-35s = 0x%x",
315 "rx_state/mux_state/ADC_MASK_OFDM", value32);
316 }
317
318 /* dbg_port = bf-related*/
319 {
320 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);
321 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
322 PHYDM_SNPRINTF(output + used, out_len - used,
323 "\r\n %-35s = 0x%x", "0x8fc", value32);
324
325 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
326 PHYDM_SNPRINTF(output + used, out_len - used,
327 "\r\n %-35s = 0x%x", "bf-related", value32);
328 }
329
330 /* dbg_port = bf-related*/
331 {
332 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);
333 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
334 PHYDM_SNPRINTF(output + used, out_len - used,
335 "\r\n %-35s = 0x%x", "0x8fc", value32);
336
337 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
338 PHYDM_SNPRINTF(output + used, out_len - used,
339 "\r\n %-35s = 0x%x", "bf-related", value32);
340 }
341
342 /* dbg_port = txon/rxd*/
343 {
344 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);
345 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
346 PHYDM_SNPRINTF(output + used, out_len - used,
347 "\r\n %-35s = 0x%x", "0x8fc", value32);
348
349 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
350 PHYDM_SNPRINTF(output + used, out_len - used,
351 "\r\n %-35s = 0x%x", "txon/rxd", value32);
352 }
353
354 /* dbg_port = l_rate/l_length*/
355 {
356 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);
357 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
358 PHYDM_SNPRINTF(output + used, out_len - used,
359 "\r\n %-35s = 0x%x", "0x8fc", value32);
360
361 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
362 PHYDM_SNPRINTF(output + used, out_len - used,
363 "\r\n %-35s = 0x%x", "l_rate/l_length", value32);
364 }
365
366 /* dbg_port = rxd/rxd_hit*/
367 {
368 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);
369 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
370 PHYDM_SNPRINTF(output + used, out_len - used,
371 "\r\n %-35s = 0x%x", "0x8fc", value32);
372
373 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
374 PHYDM_SNPRINTF(output + used, out_len - used,
375 "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
376 }
377
378 /* dbg_port = dis_cca*/
379 {
380 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);
381 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
382 PHYDM_SNPRINTF(output + used, out_len - used,
383 "\r\n %-35s = 0x%x", "0x8fc", value32);
384
385 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
386 PHYDM_SNPRINTF(output + used, out_len - used,
387 "\r\n %-35s = 0x%x", "dis_cca", value32);
388 }
389
390 /* dbg_port = tx*/
391 {
392 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);
393 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
394 PHYDM_SNPRINTF(output + used, out_len - used,
395 "\r\n %-35s = 0x%x", "0x8fc", value32);
396
397 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
398 PHYDM_SNPRINTF(output + used, out_len - used,
399 "\r\n %-35s = 0x%x", "tx", value32);
400 }
401
402 /* dbg_port = rx plcp*/
403 {
404 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);
405 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
406 PHYDM_SNPRINTF(output + used, out_len - used,
407 "\r\n %-35s = 0x%x", "0x8fc", value32);
408
409 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
410 PHYDM_SNPRINTF(output + used, out_len - used,
411 "\r\n %-35s = 0x%x", "rx plcp", value32);
412
413 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);
414 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
415 PHYDM_SNPRINTF(output + used, out_len - used,
416 "\r\n %-35s = 0x%x", "0x8fc", value32);
417
418 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
419 PHYDM_SNPRINTF(output + used, out_len - used,
420 "\r\n %-35s = 0x%x", "rx plcp", value32);
421
422 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);
423 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
424 PHYDM_SNPRINTF(output + used, out_len - used,
425 "\r\n %-35s = 0x%x", "0x8fc", value32);
426
427 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
428 PHYDM_SNPRINTF(output + used, out_len - used,
429 "\r\n %-35s = 0x%x", "rx plcp", value32);
430
431 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);
432 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
433 PHYDM_SNPRINTF(output + used, out_len - used,
434 "\r\n %-35s = 0x%x", "0x8fc", value32);
435
436 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
437 PHYDM_SNPRINTF(output + used, out_len - used,
438 "\r\n %-35s = 0x%x", "rx plcp", value32);
439 }
440}
441
442static void phydm_bb_debug_info_n_series(void *dm_void, u32 *_used,
443 char *output, u32 *_out_len)
444{
445 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
446 u32 used = *_used;
447 u32 out_len = *_out_len;
448
449 u32 value32 = 0, value32_1 = 0;
450 u8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0;
451 u8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0;
452
453 s8 rxevm_0 = 0, rxevm_1 = 0;
454 s32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0;
455 s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0;
456 s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0;
457
458 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s\n",
459 "BB Report Info");
460
461 /*AGC result*/
462 value32 = odm_get_bb_reg(dm, 0xdd0, MASKDWORD);
463 rf_gain_a = (u8)(value32 & 0x3f);
464 rf_gain_a = rf_gain_a << 1;
465
466 rf_gain_b = (u8)((value32 >> 8) & 0x3f);
467 rf_gain_b = rf_gain_b << 1;
468
469 rf_gain_c = (u8)((value32 >> 16) & 0x3f);
470 rf_gain_c = rf_gain_c << 1;
471
472 rf_gain_d = (u8)((value32 >> 24) & 0x3f);
473 rf_gain_d = rf_gain_d << 1;
474
475 PHYDM_SNPRINTF(output + used, out_len - used,
476 "\r\n %-35s = %d / %d / %d / %d",
477 "OFDM RX RF Gain(A/B/C/D)", rf_gain_a, rf_gain_b,
478 rf_gain_c, rf_gain_d);
479
480 /*SNR report*/
481 value32 = odm_get_bb_reg(dm, 0xdd4, MASKDWORD);
482 rx_snr_a = (u8)(value32 & 0xff);
483 rx_snr_a = rx_snr_a >> 1;
484
485 rx_snr_b = (u8)((value32 >> 8) & 0xff);
486 rx_snr_b = rx_snr_b >> 1;
487
488 rx_snr_c = (u8)((value32 >> 16) & 0xff);
489 rx_snr_c = rx_snr_c >> 1;
490
491 rx_snr_d = (u8)((value32 >> 24) & 0xff);
492 rx_snr_d = rx_snr_d >> 1;
493
494 PHYDM_SNPRINTF(output + used, out_len - used,
495 "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)",
496 rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d);
497
498 /* PostFFT related info*/
499 value32 = odm_get_bb_reg(dm, 0xdd8, MASKDWORD);
500
501 rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
502 rxevm_0 /= 2;
503 if (rxevm_0 < -63)
504 rxevm_0 = 0;
505
506 rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
507 rxevm_1 /= 2;
508 if (rxevm_1 < -63)
509 rxevm_1 = 0;
510
511 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
512 "RXEVM (1ss/2ss)", rxevm_0, rxevm_1);
513
514 /*CFO Report Info*/
515 odm_set_bb_reg(dm, 0xd00, BIT(26), 1);
516
517 /*Short CFO*/
518 value32 = odm_get_bb_reg(dm, 0xdac, MASKDWORD);
519 value32_1 = odm_get_bb_reg(dm, 0xdb0, MASKDWORD);
520
521 short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/
522 short_cfo_a = (s32)((value32 & 0x0fff0000) >> 16);
523
524 long_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
525 long_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
526
527 /*SFO 2's to dec*/
528 if (short_cfo_a > 2047)
529 short_cfo_a = short_cfo_a - 4096;
530 if (short_cfo_b > 2047)
531 short_cfo_b = short_cfo_b - 4096;
532
533 short_cfo_a = (short_cfo_a * 312500) / 2048;
534 short_cfo_b = (short_cfo_b * 312500) / 2048;
535
536 /*LFO 2's to dec*/
537
538 if (long_cfo_a > 4095)
539 long_cfo_a = long_cfo_a - 8192;
540
541 if (long_cfo_b > 4095)
542 long_cfo_b = long_cfo_b - 8192;
543
544 long_cfo_a = long_cfo_a * 312500 / 4096;
545 long_cfo_b = long_cfo_b * 312500 / 4096;
546
547 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
548 "CFO Report Info");
549 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
550 "Short CFO(Hz) <A/B>", short_cfo_a, short_cfo_b);
551 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
552 "Long CFO(Hz) <A/B>", long_cfo_a, long_cfo_b);
553
554 /*SCFO*/
555 value32 = odm_get_bb_reg(dm, 0xdb8, MASKDWORD);
556 value32_1 = odm_get_bb_reg(dm, 0xdb4, MASKDWORD);
557
558 scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/
559 scfo_a = (s32)((value32 & 0x07ff0000) >> 16);
560
561 if (scfo_a > 1023)
562 scfo_a = scfo_a - 2048;
563
564 if (scfo_b > 1023)
565 scfo_b = scfo_b - 2048;
566
567 scfo_a = scfo_a * 312500 / 1024;
568 scfo_b = scfo_b * 312500 / 1024;
569
570 avg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
571 avg_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
572
573 if (avg_cfo_a > 4095)
574 avg_cfo_a = avg_cfo_a - 8192;
575
576 if (avg_cfo_b > 4095)
577 avg_cfo_b = avg_cfo_b - 8192;
578
579 avg_cfo_a = avg_cfo_a * 312500 / 4096;
580 avg_cfo_b = avg_cfo_b * 312500 / 4096;
581
582 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
583 "value SCFO(Hz) <A/B>", scfo_a, scfo_b);
584 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
585 "Avg CFO(Hz) <A/B>", avg_cfo_a, avg_cfo_b);
586
587 value32 = odm_get_bb_reg(dm, 0xdbc, MASKDWORD);
588 value32_1 = odm_get_bb_reg(dm, 0xde0, MASKDWORD);
589
590 cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/
591 cfo_end_a = (s32)((value32 & 0x1fff0000) >> 16);
592
593 if (cfo_end_a > 4095)
594 cfo_end_a = cfo_end_a - 8192;
595
596 if (cfo_end_b > 4095)
597 cfo_end_b = cfo_end_b - 8192;
598
599 cfo_end_a = cfo_end_a * 312500 / 4096;
600 cfo_end_b = cfo_end_b * 312500 / 4096;
601
602 acq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
603 acq_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
604
605 if (acq_cfo_a > 4095)
606 acq_cfo_a = acq_cfo_a - 8192;
607
608 if (acq_cfo_b > 4095)
609 acq_cfo_b = acq_cfo_b - 8192;
610
611 acq_cfo_a = acq_cfo_a * 312500 / 4096;
612 acq_cfo_b = acq_cfo_b * 312500 / 4096;
613
614 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
615 "End CFO(Hz) <A/B>", cfo_end_a, cfo_end_b);
616 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
617 "ACQ CFO(Hz) <A/B>", acq_cfo_a, acq_cfo_b);
618}
619
620static void phydm_bb_debug_info(void *dm_void, u32 *_used, char *output,
621 u32 *_out_len)
622{
623 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
624 u32 used = *_used;
625 u32 out_len = *_out_len;
626
627 char *tmp_string = NULL;
628
629 u8 rx_ht_bw, rx_vht_bw, rxsc, rx_ht, rx_bw;
630 static u8 v_rx_bw;
631 u32 value32, value32_1, value32_2, value32_3;
632 s32 sfo_a, sfo_b, sfo_c, sfo_d;
633 s32 lfo_a, lfo_b, lfo_c, lfo_d;
634 static u8 MCSS, tail, parity, rsv, vrsv, idx, smooth, htsound, agg,
635 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts,
636 vtxops, vrsv2, vbrsv, bf, vbcrc;
637 static u16 h_length, htcrc8, length;
638 static u16 vpaid;
639 static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;
640 static u8 hmcss, hrx_bw;
641
642 u8 pwdb;
643 s8 rxevm_0, rxevm_1, rxevm_2;
644 u8 rf_gain_path_a, rf_gain_path_b, rf_gain_path_c, rf_gain_path_d;
645 u8 rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, rx_snr_path_d;
646 s32 sig_power;
647
648 const char *L_rate[8] = {"6M", "9M", "12M", "18M",
649 "24M", "36M", "48M", "54M"};
650
651 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
652 phydm_bb_debug_info_n_series(dm, &used, output, &out_len);
653 return;
654 }
655
656 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s\n",
657 "BB Report Info");
658
659 /*BW & mode Detection*/
660
661 value32 = odm_get_bb_reg(dm, 0xf80, MASKDWORD);
662 value32_2 = value32;
663 rx_ht_bw = (u8)(value32 & 0x1);
664 rx_vht_bw = (u8)((value32 >> 1) & 0x3);
665 rxsc = (u8)(value32 & 0x78);
666 value32_1 = (value32 & 0x180) >> 7;
667 rx_ht = (u8)(value32_1);
668
669 rx_bw = 0;
670
671 if (rx_ht == 2) {
672 if (rx_vht_bw == 0)
673 tmp_string = "20M";
674 else if (rx_vht_bw == 1)
675 tmp_string = "40M";
676 else
677 tmp_string = "80M";
678 PHYDM_SNPRINTF(output + used, out_len - used,
679 "\r\n %-35s %s %s", "mode", "VHT", tmp_string);
680 rx_bw = rx_vht_bw;
681 } else if (rx_ht == 1) {
682 if (rx_ht_bw == 0)
683 tmp_string = "20M";
684 else if (rx_ht_bw == 1)
685 tmp_string = "40M";
686 PHYDM_SNPRINTF(output + used, out_len - used,
687 "\r\n %-35s %s %s", "mode", "HT", tmp_string);
688 rx_bw = rx_ht_bw;
689 } else {
690 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s %s",
691 "mode", "Legacy");
692 }
693 if (rx_ht != 0) {
694 if (rxsc == 0)
695 tmp_string = "duplicate/full bw";
696 else if (rxsc == 1)
697 tmp_string = "usc20-1";
698 else if (rxsc == 2)
699 tmp_string = "lsc20-1";
700 else if (rxsc == 3)
701 tmp_string = "usc20-2";
702 else if (rxsc == 4)
703 tmp_string = "lsc20-2";
704 else if (rxsc == 9)
705 tmp_string = "usc40";
706 else if (rxsc == 10)
707 tmp_string = "lsc40";
708 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s",
709 tmp_string);
710 }
711
712 /* RX signal power and AGC related info*/
713
714 value32 = odm_get_bb_reg(dm, 0xF90, MASKDWORD);
715 pwdb = (u8)((value32 & MASKBYTE1) >> 8);
716 pwdb = pwdb >> 1;
717 sig_power = -110 + pwdb;
718 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d",
719 "OFDM RX Signal Power(dB)", sig_power);
720
721 value32 = odm_get_bb_reg(dm, 0xd14, MASKDWORD);
722 rx_snr_path_a = (u8)(value32 & 0xFF) >> 1;
723 rf_gain_path_a = (s8)((value32 & MASKBYTE1) >> 8);
724 rf_gain_path_a *= 2;
725 value32 = odm_get_bb_reg(dm, 0xd54, MASKDWORD);
726 rx_snr_path_b = (u8)(value32 & 0xFF) >> 1;
727 rf_gain_path_b = (s8)((value32 & MASKBYTE1) >> 8);
728 rf_gain_path_b *= 2;
729 value32 = odm_get_bb_reg(dm, 0xd94, MASKDWORD);
730 rx_snr_path_c = (u8)(value32 & 0xFF) >> 1;
731 rf_gain_path_c = (s8)((value32 & MASKBYTE1) >> 8);
732 rf_gain_path_c *= 2;
733 value32 = odm_get_bb_reg(dm, 0xdd4, MASKDWORD);
734 rx_snr_path_d = (u8)(value32 & 0xFF) >> 1;
735 rf_gain_path_d = (s8)((value32 & MASKBYTE1) >> 8);
736 rf_gain_path_d *= 2;
737
738 PHYDM_SNPRINTF(output + used, out_len - used,
739 "\r\n %-35s = %d / %d / %d / %d",
740 "OFDM RX RF Gain(A/B/C/D)", rf_gain_path_a,
741 rf_gain_path_b, rf_gain_path_c, rf_gain_path_d);
742
743 /* RX counter related info*/
744
745 value32 = odm_get_bb_reg(dm, 0xF08, MASKDWORD);
746 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d",
747 "OFDM CCA counter", ((value32 & 0xFFFF0000) >> 16));
748
749 value32 = odm_get_bb_reg(dm, 0xFD0, MASKDWORD);
750 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d",
751 "OFDM SBD Fail counter", value32 & 0xFFFF);
752
753 value32 = odm_get_bb_reg(dm, 0xFC4, MASKDWORD);
754 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
755 "VHT SIGA/SIGB CRC8 Fail counter", value32 & 0xFFFF,
756 ((value32 & 0xFFFF0000) >> 16));
757
758 value32 = odm_get_bb_reg(dm, 0xFCC, MASKDWORD);
759 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d",
760 "CCK CCA counter", value32 & 0xFFFF);
761
762 value32 = odm_get_bb_reg(dm, 0xFBC, MASKDWORD);
763 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
764 "LSIG (parity Fail/rate Illegal) counter",
765 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
766
767 value32_1 = odm_get_bb_reg(dm, 0xFC8, MASKDWORD);
768 value32_2 = odm_get_bb_reg(dm, 0xFC0, MASKDWORD);
769 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
770 "HT/VHT MCS NOT SUPPORT counter",
771 ((value32_2 & 0xFFFF0000) >> 16), value32_1 & 0xFFFF);
772
773 /* PostFFT related info*/
774 value32 = odm_get_bb_reg(dm, 0xF8c, MASKDWORD);
775 rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
776 rxevm_0 /= 2;
777 if (rxevm_0 < -63)
778 rxevm_0 = 0;
779
780 rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
781 rxevm_1 /= 2;
782 value32 = odm_get_bb_reg(dm, 0xF88, MASKDWORD);
783 rxevm_2 = (s8)((value32 & MASKBYTE2) >> 16);
784 rxevm_2 /= 2;
785
786 if (rxevm_1 < -63)
787 rxevm_1 = 0;
788 if (rxevm_2 < -63)
789 rxevm_2 = 0;
790
791 PHYDM_SNPRINTF(output + used, out_len - used,
792 "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)",
793 rxevm_0, rxevm_1, rxevm_2);
794 PHYDM_SNPRINTF(output + used, out_len - used,
795 "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)",
796 rx_snr_path_a, rx_snr_path_b, rx_snr_path_c,
797 rx_snr_path_d);
798
799 value32 = odm_get_bb_reg(dm, 0xF8C, MASKDWORD);
800 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
801 "CSI_1st /CSI_2nd", value32 & 0xFFFF,
802 ((value32 & 0xFFFF0000) >> 16));
803
804 /*BW & mode Detection*/
805
806 /*Reset Page F counter*/
807 odm_set_bb_reg(dm, 0xB58, BIT(0), 1);
808 odm_set_bb_reg(dm, 0xB58, BIT(0), 0);
809
810 /*CFO Report Info*/
811 /*Short CFO*/
812 value32 = odm_get_bb_reg(dm, 0xd0c, MASKDWORD);
813 value32_1 = odm_get_bb_reg(dm, 0xd4c, MASKDWORD);
814 value32_2 = odm_get_bb_reg(dm, 0xd8c, MASKDWORD);
815 value32_3 = odm_get_bb_reg(dm, 0xdcc, MASKDWORD);
816
817 sfo_a = (s32)(value32 & 0xfff);
818 sfo_b = (s32)(value32_1 & 0xfff);
819 sfo_c = (s32)(value32_2 & 0xfff);
820 sfo_d = (s32)(value32_3 & 0xfff);
821
822 lfo_a = (s32)(value32 >> 16);
823 lfo_b = (s32)(value32_1 >> 16);
824 lfo_c = (s32)(value32_2 >> 16);
825 lfo_d = (s32)(value32_3 >> 16);
826
827 /*SFO 2's to dec*/
828 if (sfo_a > 2047)
829 sfo_a = sfo_a - 4096;
830 sfo_a = (sfo_a * 312500) / 2048;
831 if (sfo_b > 2047)
832 sfo_b = sfo_b - 4096;
833 sfo_b = (sfo_b * 312500) / 2048;
834 if (sfo_c > 2047)
835 sfo_c = sfo_c - 4096;
836 sfo_c = (sfo_c * 312500) / 2048;
837 if (sfo_d > 2047)
838 sfo_d = sfo_d - 4096;
839 sfo_d = (sfo_d * 312500) / 2048;
840
841 /*LFO 2's to dec*/
842
843 if (lfo_a > 4095)
844 lfo_a = lfo_a - 8192;
845
846 if (lfo_b > 4095)
847 lfo_b = lfo_b - 8192;
848
849 if (lfo_c > 4095)
850 lfo_c = lfo_c - 8192;
851
852 if (lfo_d > 4095)
853 lfo_d = lfo_d - 8192;
854 lfo_a = lfo_a * 312500 / 4096;
855 lfo_b = lfo_b * 312500 / 4096;
856 lfo_c = lfo_c * 312500 / 4096;
857 lfo_d = lfo_d * 312500 / 4096;
858 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
859 "CFO Report Info");
860 PHYDM_SNPRINTF(output + used, out_len - used,
861 "\r\n %-35s = %d / %d / %d /%d",
862 "Short CFO(Hz) <A/B/C/D>", sfo_a, sfo_b, sfo_c, sfo_d);
863 PHYDM_SNPRINTF(output + used, out_len - used,
864 "\r\n %-35s = %d / %d / %d /%d",
865 "Long CFO(Hz) <A/B/C/D>", lfo_a, lfo_b, lfo_c, lfo_d);
866
867 /*SCFO*/
868 value32 = odm_get_bb_reg(dm, 0xd10, MASKDWORD);
869 value32_1 = odm_get_bb_reg(dm, 0xd50, MASKDWORD);
870 value32_2 = odm_get_bb_reg(dm, 0xd90, MASKDWORD);
871 value32_3 = odm_get_bb_reg(dm, 0xdd0, MASKDWORD);
872
873 sfo_a = (s32)(value32 & 0x7ff);
874 sfo_b = (s32)(value32_1 & 0x7ff);
875 sfo_c = (s32)(value32_2 & 0x7ff);
876 sfo_d = (s32)(value32_3 & 0x7ff);
877
878 if (sfo_a > 1023)
879 sfo_a = sfo_a - 2048;
880
881 if (sfo_b > 2047)
882 sfo_b = sfo_b - 4096;
883
884 if (sfo_c > 2047)
885 sfo_c = sfo_c - 4096;
886
887 if (sfo_d > 2047)
888 sfo_d = sfo_d - 4096;
889
890 sfo_a = sfo_a * 312500 / 1024;
891 sfo_b = sfo_b * 312500 / 1024;
892 sfo_c = sfo_c * 312500 / 1024;
893 sfo_d = sfo_d * 312500 / 1024;
894
895 lfo_a = (s32)(value32 >> 16);
896 lfo_b = (s32)(value32_1 >> 16);
897 lfo_c = (s32)(value32_2 >> 16);
898 lfo_d = (s32)(value32_3 >> 16);
899
900 if (lfo_a > 4095)
901 lfo_a = lfo_a - 8192;
902
903 if (lfo_b > 4095)
904 lfo_b = lfo_b - 8192;
905
906 if (lfo_c > 4095)
907 lfo_c = lfo_c - 8192;
908
909 if (lfo_d > 4095)
910 lfo_d = lfo_d - 8192;
911 lfo_a = lfo_a * 312500 / 4096;
912 lfo_b = lfo_b * 312500 / 4096;
913 lfo_c = lfo_c * 312500 / 4096;
914 lfo_d = lfo_d * 312500 / 4096;
915
916 PHYDM_SNPRINTF(output + used, out_len - used,
917 "\r\n %-35s = %d / %d / %d /%d",
918 "value SCFO(Hz) <A/B/C/D>", sfo_a, sfo_b, sfo_c, sfo_d);
919 PHYDM_SNPRINTF(output + used, out_len - used,
920 "\r\n %-35s = %d / %d / %d /%d", "ACQ CFO(Hz) <A/B/C/D>",
921 lfo_a, lfo_b, lfo_c, lfo_d);
922
923 value32 = odm_get_bb_reg(dm, 0xd14, MASKDWORD);
924 value32_1 = odm_get_bb_reg(dm, 0xd54, MASKDWORD);
925 value32_2 = odm_get_bb_reg(dm, 0xd94, MASKDWORD);
926 value32_3 = odm_get_bb_reg(dm, 0xdd4, MASKDWORD);
927
928 lfo_a = (s32)(value32 >> 16);
929 lfo_b = (s32)(value32_1 >> 16);
930 lfo_c = (s32)(value32_2 >> 16);
931 lfo_d = (s32)(value32_3 >> 16);
932
933 if (lfo_a > 4095)
934 lfo_a = lfo_a - 8192;
935
936 if (lfo_b > 4095)
937 lfo_b = lfo_b - 8192;
938
939 if (lfo_c > 4095)
940 lfo_c = lfo_c - 8192;
941
942 if (lfo_d > 4095)
943 lfo_d = lfo_d - 8192;
944
945 lfo_a = lfo_a * 312500 / 4096;
946 lfo_b = lfo_b * 312500 / 4096;
947 lfo_c = lfo_c * 312500 / 4096;
948 lfo_d = lfo_d * 312500 / 4096;
949
950 PHYDM_SNPRINTF(output + used, out_len - used,
951 "\r\n %-35s = %d / %d / %d /%d", "End CFO(Hz) <A/B/C/D>",
952 lfo_a, lfo_b, lfo_c, lfo_d);
953
954 value32 = odm_get_bb_reg(dm, 0xf20, MASKDWORD); /*L SIG*/
955
956 tail = (u8)((value32 & 0xfc0000) >> 16);
957 parity = (u8)((value32 & 0x20000) >> 16);
958 length = (u16)((value32 & 0x1ffe00) >> 8);
959 rsv = (u8)(value32 & 0x10);
960 MCSS = (u8)(value32 & 0x0f);
961
962 switch (MCSS) {
963 case 0x0b:
964 idx = 0;
965 break;
966 case 0x0f:
967 idx = 1;
968 break;
969 case 0x0a:
970 idx = 2;
971 break;
972 case 0x0e:
973 idx = 3;
974 break;
975 case 0x09:
976 idx = 4;
977 break;
978 case 0x08:
979 idx = 5;
980 break;
981 case 0x0c:
982 idx = 6;
983 break;
984 default:
985 idx = 6;
986 break;
987 }
988
989 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s", "L-SIG");
990 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s : %s", "rate",
991 L_rate[idx]);
992 PHYDM_SNPRINTF(output + used, out_len - used,
993 "\r\n %-35s = %x / %x / %x", "Rsv/length/parity", rsv,
994 rx_bw, length);
995
996 value32 = odm_get_bb_reg(dm, 0xf2c, MASKDWORD); /*HT SIG*/
997 if (rx_ht == 1) {
998 hmcss = (u8)(value32 & 0x7F);
999 hrx_bw = (u8)(value32 & 0x80);
1000 h_length = (u16)((value32 >> 8) & 0xffff);
1001 }
1002 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s", "HT-SIG1");
1003 PHYDM_SNPRINTF(output + used, out_len - used,
1004 "\r\n %-35s = %x / %x / %x", "MCS/BW/length", hmcss,
1005 hrx_bw, h_length);
1006
1007 value32 = odm_get_bb_reg(dm, 0xf30, MASKDWORD); /*HT SIG*/
1008
1009 if (rx_ht == 1) {
1010 smooth = (u8)(value32 & 0x01);
1011 htsound = (u8)(value32 & 0x02);
1012 rsv = (u8)(value32 & 0x04);
1013 agg = (u8)(value32 & 0x08);
1014 stbc = (u8)(value32 & 0x30);
1015 fec = (u8)(value32 & 0x40);
1016 sgi = (u8)(value32 & 0x80);
1017 htltf = (u8)((value32 & 0x300) >> 8);
1018 htcrc8 = (u16)((value32 & 0x3fc00) >> 8);
1019 tail = (u8)((value32 & 0xfc0000) >> 16);
1020 }
1021 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s", "HT-SIG2");
1022 PHYDM_SNPRINTF(output + used, out_len - used,
1023 "\r\n %-35s = %x / %x / %x / %x / %x / %x",
1024 "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", smooth,
1025 htsound, rsv, agg, stbc, fec);
1026 PHYDM_SNPRINTF(output + used, out_len - used,
1027 "\r\n %-35s = %x / %x / %x / %x",
1028 "SGI/E-HT-LTFs/CRC/tail", sgi, htltf, htcrc8, tail);
1029
1030 value32 = odm_get_bb_reg(dm, 0xf2c, MASKDWORD); /*VHT SIG A1*/
1031 if (rx_ht == 2) {
1032 /* value32 = odm_get_bb_reg(dm, 0xf2c,MASKDWORD);*/
1033 v_rx_bw = (u8)(value32 & 0x03);
1034 vrsv = (u8)(value32 & 0x04);
1035 vstbc = (u8)(value32 & 0x08);
1036 vgid = (u8)((value32 & 0x3f0) >> 4);
1037 v_nsts = (u8)(((value32 & 0x1c00) >> 8) + 1);
1038 vpaid = (u16)(value32 & 0x3fe);
1039 vtxops = (u8)((value32 & 0x400000) >> 20);
1040 vrsv2 = (u8)((value32 & 0x800000) >> 20);
1041 }
1042 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
1043 "VHT-SIG-A1");
1044 PHYDM_SNPRINTF(output + used, out_len - used,
1045 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x",
1046 "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, vrsv,
1047 vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);
1048
1049 value32 = odm_get_bb_reg(dm, 0xf30, MASKDWORD); /*VHT SIG*/
1050
1051 if (rx_ht == 2) {
1052 /*value32 = odm_get_bb_reg(dm, 0xf30,MASKDWORD); */ /*VHT SIG*/
1053
1054 /* sgi=(u8)(value32&0x01); */
1055 sgiext = (u8)(value32 & 0x03);
1056 /* fec = (u8)(value32&0x04); */
1057 fecext = (u8)(value32 & 0x0C);
1058
1059 v_mcss = (u8)(value32 & 0xf0);
1060 bf = (u8)((value32 & 0x100) >> 8);
1061 vrsv = (u8)((value32 & 0x200) >> 8);
1062 vhtcrc8 = (u16)((value32 & 0x3fc00) >> 8);
1063 v_tail = (u8)((value32 & 0xfc0000) >> 16);
1064 }
1065 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
1066 "VHT-SIG-A2");
1067 PHYDM_SNPRINTF(output + used, out_len - used,
1068 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x",
1069 "SGI/FEC/MCS/BF/Rsv/CRC/tail", sgiext, fecext, v_mcss,
1070 bf, vrsv, vhtcrc8, v_tail);
1071
1072 value32 = odm_get_bb_reg(dm, 0xf34, MASKDWORD); /*VHT SIG*/
1073 {
1074 v_length = (u16)(value32 & 0x1fffff);
1075 vbrsv = (u8)((value32 & 0x600000) >> 20);
1076 vb_tail = (u16)((value32 & 0x1f800000) >> 20);
1077 vbcrc = (u8)((value32 & 0x80000000) >> 28);
1078 }
1079 PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
1080 "VHT-SIG-B");
1081 PHYDM_SNPRINTF(output + used, out_len - used,
1082 "\r\n %-35s = %x / %x / %x / %x", "length/Rsv/tail/CRC",
1083 v_length, vbrsv, vb_tail, vbcrc);
1084
1085 /*for Condition number*/
1086 if (dm->support_ic_type & ODM_RTL8822B) {
1087 s32 condition_num = 0;
1088 char *factor = NULL;
1089
1090 /*enable report condition number*/
1091 odm_set_bb_reg(dm, 0x1988, BIT(22), 0x1);
1092
1093 condition_num = odm_get_bb_reg(dm, 0xf84, MASKDWORD);
1094 condition_num = (condition_num & 0x3ffff) >> 4;
1095
1096 if (*dm->band_width == ODM_BW80M) {
1097 factor = "256/234";
1098 } else if (*dm->band_width == ODM_BW40M) {
1099 factor = "128/108";
1100 } else if (*dm->band_width == ODM_BW20M) {
1101 if (rx_ht == 2 || rx_ht == 1)
1102 factor = "64/52"; /*HT or VHT*/
1103 else
1104 factor = "64/48"; /*legacy*/
1105 }
1106
1107 PHYDM_SNPRINTF(output + used, out_len - used,
1108 "\r\n %-35s = %d (factor = %s)",
1109 "Condition number", condition_num, factor);
1110 }
1111}
1112
1113void phydm_basic_dbg_message(void *dm_void)
1114{
1115 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1116 struct false_alarm_stat *false_alm_cnt =
1117 (struct false_alarm_stat *)phydm_get_structure(
1118 dm, PHYDM_FALSEALMCNT);
1119 struct cfo_tracking *cfo_track =
1120 (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
1121 struct dig_thres *dig_tab = &dm->dm_dig_table;
1122 struct ra_table *ra_tab = &dm->dm_ra_table;
1123 u16 macid, phydm_macid, client_cnt = 0;
1124 struct rtl_sta_info *entry;
1125 s32 tmp_val = 0;
1126 u8 tmp_val_u1 = 0;
1127
1128 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
1129 "[PHYDM Common MSG] System up time: ((%d sec))----->\n",
1130 dm->phydm_sys_up_time);
1131
1132 if (dm->is_linked) {
1133 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
1134 "ID=%d, BW=((%d)), CH=((%d))\n",
1135 dm->curr_station_id, 20 << *dm->band_width,
1136 *dm->channel);
1137
1138 /*Print RX rate*/
1139 if (dm->rx_rate <= ODM_RATE11M)
1140 ODM_RT_TRACE(
1141 dm, ODM_COMP_COMMON,
1142 "[CCK AGC Report] LNA_idx = 0x%x, VGA_idx = 0x%x\n",
1143 dm->cck_lna_idx, dm->cck_vga_idx);
1144 else
1145 ODM_RT_TRACE(
1146 dm, ODM_COMP_COMMON,
1147 "[OFDM AGC Report] { 0x%x, 0x%x, 0x%x, 0x%x }\n",
1148 dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],
1149 dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);
1150
1151 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
1152 "RSSI: { %d, %d, %d, %d }, rx_rate:",
1153 (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,
1154 (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,
1155 (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,
1156 (dm->rssi_d == 0xff) ? 0 : dm->rssi_d);
1157
1158 phydm_print_rate(dm, dm->rx_rate, ODM_COMP_COMMON);
1159
1160 /*Print TX rate*/
1161 for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
1162 entry = dm->odm_sta_info[macid];
1163 if (!IS_STA_VALID(entry))
1164 continue;
1165
1166 phydm_macid = (dm->platform2phydm_macid_table[macid]);
1167 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "TXRate [%d]:",
1168 macid);
1169 phydm_print_rate(dm, ra_tab->link_tx_rate[macid],
1170 ODM_COMP_COMMON);
1171
1172 client_cnt++;
1173
1174 if (client_cnt == dm->number_linked_client)
1175 break;
1176 }
1177
1178 ODM_RT_TRACE(
1179 dm, ODM_COMP_COMMON,
1180 "TP { TX, RX, total} = {%d, %d, %d }Mbps, traffic_load = (%d))\n",
1181 dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);
1182
1183 tmp_val_u1 =
1184 (cfo_track->crystal_cap > cfo_track->def_x_cap) ?
1185 (cfo_track->crystal_cap -
1186 cfo_track->def_x_cap) :
1187 (cfo_track->def_x_cap - cfo_track->crystal_cap);
1188 ODM_RT_TRACE(
1189 dm, ODM_COMP_COMMON,
1190 "CFO_avg = ((%d kHz)) , CrystalCap_tracking = ((%s%d))\n",
1191 cfo_track->CFO_ave_pre,
1192 ((cfo_track->crystal_cap > cfo_track->def_x_cap) ? "+" :
1193 "-"),
1194 tmp_val_u1);
1195
1196 /* Condition number */
1197 if (dm->support_ic_type == ODM_RTL8822B) {
1198 tmp_val = phydm_get_condition_number_8822B(dm);
1199 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
1200 "Condition number = ((%d))\n", tmp_val);
1201 }
1202
1203 /*STBC or LDPC pkt*/
1204 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "LDPC = %s, STBC = %s\n",
1205 (dm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N",
1206 (dm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N");
1207 } else {
1208 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "No Link !!!\n");
1209 }
1210
1211 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
1212 "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1213 false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca,
1214 false_alm_cnt->cnt_cca_all);
1215
1216 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
1217 "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1218 false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail,
1219 false_alm_cnt->cnt_all);
1220
1221 if (dm->support_ic_type & ODM_IC_11N_SERIES)
1222 ODM_RT_TRACE(
1223 dm, ODM_COMP_COMMON,
1224 "[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n",
1225 false_alm_cnt->cnt_parity_fail,
1226 false_alm_cnt->cnt_rate_illegal,
1227 false_alm_cnt->cnt_crc8_fail,
1228 false_alm_cnt->cnt_mcs_fail,
1229 false_alm_cnt->cnt_fast_fsync,
1230 false_alm_cnt->cnt_sb_search_fail);
1231
1232 ODM_RT_TRACE(
1233 dm, ODM_COMP_COMMON,
1234 "is_linked = %d, Num_client = %d, rssi_min = %d, current_igi = 0x%x, bNoisy=%d\n\n",
1235 dm->is_linked, dm->number_linked_client, dm->rssi_min,
1236 dig_tab->cur_ig_value, dm->noisy_decision);
1237}
1238
1239void phydm_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
1240{
1241 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1242 char *cut = NULL;
1243 char *ic_type = NULL;
1244 u32 used = *_used;
1245 u32 out_len = *_out_len;
1246 u32 date = 0;
1247 char *commit_by = NULL;
1248 u32 release_ver = 0;
1249
1250 PHYDM_SNPRINTF(output + used, out_len - used, "%-35s\n",
1251 "% Basic Profile %");
1252
1253 if (dm->support_ic_type == ODM_RTL8188E) {
1254 } else if (dm->support_ic_type == ODM_RTL8822B) {
1255 ic_type = "RTL8822B";
1256 date = RELEASE_DATE_8822B;
1257 commit_by = COMMIT_BY_8822B;
1258 release_ver = RELEASE_VERSION_8822B;
1259 }
1260
1261 /* JJ ADD 20161014 */
1262
1263 PHYDM_SNPRINTF(output + used, out_len - used,
1264 " %-35s: %s (MP Chip: %s)\n", "IC type", ic_type,
1265 dm->is_mp_chip ? "Yes" : "No");
1266
1267 if (dm->cut_version == ODM_CUT_A)
1268 cut = "A";
1269 else if (dm->cut_version == ODM_CUT_B)
1270 cut = "B";
1271 else if (dm->cut_version == ODM_CUT_C)
1272 cut = "C";
1273 else if (dm->cut_version == ODM_CUT_D)
1274 cut = "D";
1275 else if (dm->cut_version == ODM_CUT_E)
1276 cut = "E";
1277 else if (dm->cut_version == ODM_CUT_F)
1278 cut = "F";
1279 else if (dm->cut_version == ODM_CUT_I)
1280 cut = "I";
1281 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1282 "cut version", cut);
1283 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %d\n",
1284 "PHY Parameter version", odm_get_hw_img_version(dm));
1285 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %d\n",
1286 "PHY Parameter Commit date", date);
1287 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1288 "PHY Parameter Commit by", commit_by);
1289 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %d\n",
1290 "PHY Parameter Release version", release_ver);
1291
1292 {
1293 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
1294 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1295
1296 PHYDM_SNPRINTF(output + used, out_len - used,
1297 " %-35s: %d (Subversion: %d)\n", "FW version",
1298 rtlhal->fw_version, rtlhal->fw_subversion);
1299 }
1300 /* 1 PHY DM version List */
1301 PHYDM_SNPRINTF(output + used, out_len - used, "%-35s\n",
1302 "% PHYDM version %");
1303 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1304 "Code base", PHYDM_CODE_BASE);
1305 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1306 "Release Date", PHYDM_RELEASE_DATE);
1307 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1308 "adaptivity", ADAPTIVITY_VERSION);
1309 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n", "DIG",
1310 DIG_VERSION);
1311 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1312 "Dynamic BB PowerSaving", DYNAMIC_BBPWRSAV_VERSION);
1313 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1314 "CFO Tracking", CFO_TRACKING_VERSION);
1315 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1316 "Antenna Diversity", ANTDIV_VERSION);
1317 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1318 "Power Tracking", POWRTRACKING_VERSION);
1319 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1320 "Dynamic TxPower", DYNAMIC_TXPWR_VERSION);
1321 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1322 "RA Info", RAINFO_VERSION);
1323 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1324 "Auto channel Selection", ACS_VERSION);
1325 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1326 "EDCA Turbo", EDCATURBO_VERSION);
1327 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1328 "LA mode", DYNAMIC_LA_MODE);
1329 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1330 "Dynamic RX path", DYNAMIC_RX_PATH_VERSION);
1331
1332 if (dm->support_ic_type & ODM_RTL8822B)
1333 PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
1334 "PHY config 8822B", PHY_CONFIG_VERSION_8822B);
1335
1336 *_used = used;
1337 *_out_len = out_len;
1338}
1339
1340void phydm_fw_trace_en_h2c(void *dm_void, bool enable, u32 fw_debug_component,
1341 u32 monitor_mode, u32 macid)
1342{
1343 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1344 u8 h2c_parameter[7] = {0};
1345 u8 cmd_length;
1346
1347 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
1348 h2c_parameter[0] = enable;
1349 h2c_parameter[1] = (u8)(fw_debug_component & MASKBYTE0);
1350 h2c_parameter[2] = (u8)((fw_debug_component & MASKBYTE1) >> 8);
1351 h2c_parameter[3] = (u8)((fw_debug_component & MASKBYTE2) >> 16);
1352 h2c_parameter[4] = (u8)((fw_debug_component & MASKBYTE3) >> 24);
1353 h2c_parameter[5] = (u8)monitor_mode;
1354 h2c_parameter[6] = (u8)macid;
1355 cmd_length = 7;
1356
1357 } else {
1358 h2c_parameter[0] = enable;
1359 h2c_parameter[1] = (u8)monitor_mode;
1360 h2c_parameter[2] = (u8)macid;
1361 cmd_length = 3;
1362 }
1363
1364 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "---->\n");
1365 if (monitor_mode == 0)
1366 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
1367 "[H2C] FW_debug_en: (( %d ))\n", enable);
1368 else
1369 ODM_RT_TRACE(
1370 dm, ODM_FW_DEBUG_TRACE,
1371 "[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n",
1372 enable, monitor_mode, macid);
1373 odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter);
1374}
1375
1376bool phydm_api_set_txagc(struct phy_dm_struct *dm, u32 power_index,
1377 enum odm_rf_radio_path path, u8 hw_rate,
1378 bool is_single_rate)
1379{
1380 bool ret = false;
1381
1382 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
1383 if (is_single_rate) {
1384 if (dm->support_ic_type == ODM_RTL8822B)
1385 ret = phydm_write_txagc_1byte_8822b(
1386 dm, power_index, path, hw_rate);
1387
1388 } else {
1389 if (dm->support_ic_type == ODM_RTL8822B)
1390 ret = config_phydm_write_txagc_8822b(
1391 dm, power_index, path, hw_rate);
1392 }
1393 }
1394
1395 return ret;
1396}
1397
1398static u8 phydm_api_get_txagc(struct phy_dm_struct *dm,
1399 enum odm_rf_radio_path path, u8 hw_rate)
1400{
1401 u8 ret = 0;
1402
1403 if (dm->support_ic_type & ODM_RTL8822B)
1404 ret = config_phydm_read_txagc_8822b(dm, path, hw_rate);
1405
1406 return ret;
1407}
1408
1409static bool phydm_api_switch_bw_channel(struct phy_dm_struct *dm, u8 central_ch,
1410 u8 primary_ch_idx,
1411 enum odm_bw bandwidth)
1412{
1413 bool ret = false;
1414
1415 if (dm->support_ic_type & ODM_RTL8822B)
1416 ret = config_phydm_switch_channel_bw_8822b(
1417 dm, central_ch, primary_ch_idx, bandwidth);
1418
1419 return ret;
1420}
1421
1422bool phydm_api_trx_mode(struct phy_dm_struct *dm, enum odm_rf_path tx_path,
1423 enum odm_rf_path rx_path, bool is_tx2_path)
1424{
1425 bool ret = false;
1426
1427 if (dm->support_ic_type & ODM_RTL8822B)
1428 ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path,
1429 is_tx2_path);
1430
1431 return ret;
1432}
1433
1434static void phydm_get_per_path_txagc(void *dm_void, u8 path, u32 *_used,
1435 char *output, u32 *_out_len)
1436{
1437 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1438 u8 rate_idx;
1439 u8 txagc;
1440 u32 used = *_used;
1441 u32 out_len = *_out_len;
1442
1443 if (((dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) &&
1444 (path <= ODM_RF_PATH_B)) ||
1445 ((dm->support_ic_type & (ODM_RTL8821C)) &&
1446 (path <= ODM_RF_PATH_A))) {
1447 for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) {
1448 if (rate_idx == ODM_RATE1M)
1449 PHYDM_SNPRINTF(output + used, out_len - used,
1450 " %-35s\n", "CCK====>");
1451 else if (rate_idx == ODM_RATE6M)
1452 PHYDM_SNPRINTF(output + used, out_len - used,
1453 "\n %-35s\n", "OFDM====>");
1454 else if (rate_idx == ODM_RATEMCS0)
1455 PHYDM_SNPRINTF(output + used, out_len - used,
1456 "\n %-35s\n", "HT 1ss====>");
1457 else if (rate_idx == ODM_RATEMCS8)
1458 PHYDM_SNPRINTF(output + used, out_len - used,
1459 "\n %-35s\n", "HT 2ss====>");
1460 else if (rate_idx == ODM_RATEMCS16)
1461 PHYDM_SNPRINTF(output + used, out_len - used,
1462 "\n %-35s\n", "HT 3ss====>");
1463 else if (rate_idx == ODM_RATEMCS24)
1464 PHYDM_SNPRINTF(output + used, out_len - used,
1465 "\n %-35s\n", "HT 4ss====>");
1466 else if (rate_idx == ODM_RATEVHTSS1MCS0)
1467 PHYDM_SNPRINTF(output + used, out_len - used,
1468 "\n %-35s\n", "VHT 1ss====>");
1469 else if (rate_idx == ODM_RATEVHTSS2MCS0)
1470 PHYDM_SNPRINTF(output + used, out_len - used,
1471 "\n %-35s\n", "VHT 2ss====>");
1472 else if (rate_idx == ODM_RATEVHTSS3MCS0)
1473 PHYDM_SNPRINTF(output + used, out_len - used,
1474 "\n %-35s\n", "VHT 3ss====>");
1475 else if (rate_idx == ODM_RATEVHTSS4MCS0)
1476 PHYDM_SNPRINTF(output + used, out_len - used,
1477 "\n %-35s\n", "VHT 4ss====>");
1478
1479 txagc = phydm_api_get_txagc(
1480 dm, (enum odm_rf_radio_path)path, rate_idx);
1481 if (config_phydm_read_txagc_check(txagc))
1482 PHYDM_SNPRINTF(output + used, out_len - used,
1483 " 0x%02x ", txagc);
1484 else
1485 PHYDM_SNPRINTF(output + used, out_len - used,
1486 " 0x%s ", "xx");
1487 }
1488 }
1489}
1490
1491static void phydm_get_txagc(void *dm_void, u32 *_used, char *output,
1492 u32 *_out_len)
1493{
1494 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1495 u32 used = *_used;
1496 u32 out_len = *_out_len;
1497
1498 /* path-A */
1499 PHYDM_SNPRINTF(output + used, out_len - used, "%-35s\n",
1500 "path-A====================");
1501 phydm_get_per_path_txagc(dm, ODM_RF_PATH_A, _used, output, _out_len);
1502
1503 /* path-B */
1504 PHYDM_SNPRINTF(output + used, out_len - used, "\n%-35s\n",
1505 "path-B====================");
1506 phydm_get_per_path_txagc(dm, ODM_RF_PATH_B, _used, output, _out_len);
1507
1508 /* path-C */
1509 PHYDM_SNPRINTF(output + used, out_len - used, "\n%-35s\n",
1510 "path-C====================");
1511 phydm_get_per_path_txagc(dm, ODM_RF_PATH_C, _used, output, _out_len);
1512
1513 /* path-D */
1514 PHYDM_SNPRINTF(output + used, out_len - used, "\n%-35s\n",
1515 "path-D====================");
1516 phydm_get_per_path_txagc(dm, ODM_RF_PATH_D, _used, output, _out_len);
1517}
1518
1519static void phydm_set_txagc(void *dm_void, u32 *const dm_value, u32 *_used,
1520 char *output, u32 *_out_len)
1521{
1522 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1523 u32 used = *_used;
1524 u32 out_len = *_out_len;
1525
1526 /*dm_value[1] = path*/
1527 /*dm_value[2] = hw_rate*/
1528 /*dm_value[3] = power_index*/
1529
1530 if (dm->support_ic_type &
1531 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) {
1532 if (dm_value[1] <= 1) {
1533 phydm_check_dmval_txagc(dm, used, out_len, dm_value,
1534 output);
1535 } else {
1536 PHYDM_SNPRINTF(output + used, out_len - used,
1537 " %s%d %s%x%s\n", "Write path-",
1538 (dm_value[1] & 0x1), "rate index-0x",
1539 (dm_value[2] & 0x7f), " fail");
1540 }
1541 }
1542}
1543
1544static void phydm_debug_trace(void *dm_void, u32 *const dm_value, u32 *_used,
1545 char *output, u32 *_out_len)
1546{
1547 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1548 u32 pre_debug_components, one = 1;
1549 u32 used = *_used;
1550 u32 out_len = *_out_len;
1551
1552 pre_debug_components = dm->debug_components;
1553
1554 PHYDM_SNPRINTF(output + used, out_len - used, "\n%s\n",
1555 "================================");
1556 if (dm_value[0] == 100) {
1557 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1558 "[Debug Message] PhyDM Selection");
1559 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1560 "================================");
1561 PHYDM_SNPRINTF(output + used, out_len - used,
1562 "00. (( %s ))DIG\n",
1563 ((dm->debug_components & ODM_COMP_DIG) ? ("V") :
1564 (".")));
1565 PHYDM_SNPRINTF(
1566 output + used, out_len - used, "01. (( %s ))RA_MASK\n",
1567 ((dm->debug_components & ODM_COMP_RA_MASK) ? ("V") :
1568 (".")));
1569 PHYDM_SNPRINTF(
1570 output + used, out_len - used,
1571 "02. (( %s ))DYNAMIC_TXPWR\n",
1572 ((dm->debug_components & ODM_COMP_DYNAMIC_TXPWR) ?
1573 ("V") :
1574 (".")));
1575 PHYDM_SNPRINTF(
1576 output + used, out_len - used, "03. (( %s ))FA_CNT\n",
1577 ((dm->debug_components & ODM_COMP_FA_CNT) ? ("V") :
1578 (".")));
1579 PHYDM_SNPRINTF(output + used, out_len - used,
1580 "04. (( %s ))RSSI_MONITOR\n",
1581 ((dm->debug_components & ODM_COMP_RSSI_MONITOR) ?
1582 ("V") :
1583 (".")));
1584 PHYDM_SNPRINTF(
1585 output + used, out_len - used, "05. (( %s ))SNIFFER\n",
1586 ((dm->debug_components & ODM_COMP_SNIFFER) ? ("V") :
1587 (".")));
1588 PHYDM_SNPRINTF(
1589 output + used, out_len - used, "06. (( %s ))ANT_DIV\n",
1590 ((dm->debug_components & ODM_COMP_ANT_DIV) ? ("V") :
1591 (".")));
1592 PHYDM_SNPRINTF(output + used, out_len - used,
1593 "07. (( %s ))DFS\n",
1594 ((dm->debug_components & ODM_COMP_DFS) ? ("V") :
1595 (".")));
1596 PHYDM_SNPRINTF(output + used, out_len - used,
1597 "08. (( %s ))NOISY_DETECT\n",
1598 ((dm->debug_components & ODM_COMP_NOISY_DETECT) ?
1599 ("V") :
1600 (".")));
1601 PHYDM_SNPRINTF(
1602 output + used, out_len - used,
1603 "09. (( %s ))RATE_ADAPTIVE\n",
1604 ((dm->debug_components & ODM_COMP_RATE_ADAPTIVE) ?
1605 ("V") :
1606 (".")));
1607 PHYDM_SNPRINTF(
1608 output + used, out_len - used, "10. (( %s ))PATH_DIV\n",
1609 ((dm->debug_components & ODM_COMP_PATH_DIV) ? ("V") :
1610 (".")));
1611 PHYDM_SNPRINTF(
1612 output + used, out_len - used,
1613 "12. (( %s ))DYNAMIC_PRICCA\n",
1614 ((dm->debug_components & ODM_COMP_DYNAMIC_PRICCA) ?
1615 ("V") :
1616 (".")));
1617 PHYDM_SNPRINTF(
1618 output + used, out_len - used, "14. (( %s ))MP\n",
1619 ((dm->debug_components & ODM_COMP_MP) ? ("V") : (".")));
1620 PHYDM_SNPRINTF(output + used, out_len - used,
1621 "15. (( %s ))struct cfo_tracking\n",
1622 ((dm->debug_components & ODM_COMP_CFO_TRACKING) ?
1623 ("V") :
1624 (".")));
1625 PHYDM_SNPRINTF(output + used, out_len - used,
1626 "16. (( %s ))struct acs_info\n",
1627 ((dm->debug_components & ODM_COMP_ACS) ? ("V") :
1628 (".")));
1629 PHYDM_SNPRINTF(output + used, out_len - used,
1630 "17. (( %s ))ADAPTIVITY\n",
1631 ((dm->debug_components & PHYDM_COMP_ADAPTIVITY) ?
1632 ("V") :
1633 (".")));
1634 PHYDM_SNPRINTF(
1635 output + used, out_len - used, "18. (( %s ))RA_DBG\n",
1636 ((dm->debug_components & PHYDM_COMP_RA_DBG) ? ("V") :
1637 (".")));
1638 PHYDM_SNPRINTF(
1639 output + used, out_len - used, "19. (( %s ))TXBF\n",
1640 ((dm->debug_components & PHYDM_COMP_TXBF) ? ("V") :
1641 (".")));
1642 PHYDM_SNPRINTF(output + used, out_len - used,
1643 "20. (( %s ))EDCA_TURBO\n",
1644 ((dm->debug_components & ODM_COMP_EDCA_TURBO) ?
1645 ("V") :
1646 (".")));
1647 PHYDM_SNPRINTF(output + used, out_len - used,
1648 "22. (( %s ))FW_DEBUG_TRACE\n",
1649 ((dm->debug_components & ODM_FW_DEBUG_TRACE) ?
1650 ("V") :
1651 (".")));
1652
1653 PHYDM_SNPRINTF(output + used, out_len - used,
1654 "24. (( %s ))TX_PWR_TRACK\n",
1655 ((dm->debug_components & ODM_COMP_TX_PWR_TRACK) ?
1656 ("V") :
1657 (".")));
1658 PHYDM_SNPRINTF(output + used, out_len - used,
1659 "26. (( %s ))CALIBRATION\n",
1660 ((dm->debug_components & ODM_COMP_CALIBRATION) ?
1661 ("V") :
1662 (".")));
1663 PHYDM_SNPRINTF(output + used, out_len - used,
1664 "28. (( %s ))PHY_CONFIG\n",
1665 ((dm->debug_components & ODM_PHY_CONFIG) ?
1666 ("V") :
1667 (".")));
1668 PHYDM_SNPRINTF(
1669 output + used, out_len - used, "29. (( %s ))INIT\n",
1670 ((dm->debug_components & ODM_COMP_INIT) ? ("V") :
1671 (".")));
1672 PHYDM_SNPRINTF(
1673 output + used, out_len - used, "30. (( %s ))COMMON\n",
1674 ((dm->debug_components & ODM_COMP_COMMON) ? ("V") :
1675 (".")));
1676 PHYDM_SNPRINTF(output + used, out_len - used,
1677 "31. (( %s ))API\n",
1678 ((dm->debug_components & ODM_COMP_API) ? ("V") :
1679 (".")));
1680 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1681 "================================");
1682
1683 } else if (dm_value[0] == 101) {
1684 dm->debug_components = 0;
1685 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1686 "Disable all debug components");
1687 } else {
1688 if (dm_value[1] == 1) /*enable*/
1689 dm->debug_components |= (one << dm_value[0]);
1690 else if (dm_value[1] == 2) /*disable*/
1691 dm->debug_components &= ~(one << dm_value[0]);
1692 else
1693 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1694 "[Warning!!!] 1:enable, 2:disable");
1695 }
1696 PHYDM_SNPRINTF(output + used, out_len - used,
1697 "pre-DbgComponents = 0x%x\n", pre_debug_components);
1698 PHYDM_SNPRINTF(output + used, out_len - used,
1699 "Curr-DbgComponents = 0x%x\n", dm->debug_components);
1700 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1701 "================================");
1702}
1703
1704static void phydm_fw_debug_trace(void *dm_void, u32 *const dm_value, u32 *_used,
1705 char *output, u32 *_out_len)
1706{
1707 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1708 u32 pre_fw_debug_components, one = 1;
1709 u32 used = *_used;
1710 u32 out_len = *_out_len;
1711
1712 pre_fw_debug_components = dm->fw_debug_components;
1713
1714 PHYDM_SNPRINTF(output + used, out_len - used, "\n%s\n",
1715 "================================");
1716 if (dm_value[0] == 100) {
1717 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1718 "[FW Debug Component]");
1719 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1720 "================================");
1721 PHYDM_SNPRINTF(
1722 output + used, out_len - used, "00. (( %s ))RA\n",
1723 ((dm->fw_debug_components & PHYDM_FW_COMP_RA) ? ("V") :
1724 (".")));
1725
1726 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
1727 PHYDM_SNPRINTF(
1728 output + used, out_len - used,
1729 "01. (( %s ))MU\n",
1730 ((dm->fw_debug_components & PHYDM_FW_COMP_MU) ?
1731 ("V") :
1732 (".")));
1733 PHYDM_SNPRINTF(output + used, out_len - used,
1734 "02. (( %s ))path Div\n",
1735 ((dm->fw_debug_components &
1736 PHYDM_FW_COMP_PHY_CONFIG) ?
1737 ("V") :
1738 (".")));
1739 PHYDM_SNPRINTF(output + used, out_len - used,
1740 "03. (( %s ))Phy Config\n",
1741 ((dm->fw_debug_components &
1742 PHYDM_FW_COMP_PHY_CONFIG) ?
1743 ("V") :
1744 (".")));
1745 }
1746 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1747 "================================");
1748
1749 } else {
1750 if (dm_value[0] == 101) {
1751 dm->fw_debug_components = 0;
1752 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
1753 "Clear all fw debug components");
1754 } else {
1755 if (dm_value[1] == 1) /*enable*/
1756 dm->fw_debug_components |= (one << dm_value[0]);
1757 else if (dm_value[1] == 2) /*disable*/
1758 dm->fw_debug_components &=
1759 ~(one << dm_value[0]);
1760 else
1761 PHYDM_SNPRINTF(
1762 output + used, out_len - used, "%s\n",
1763 "[Warning!!!] 1:enable, 2:disable");
1764 }
1765
1766 if (dm->fw_debug_components == 0) {
1767 dm->debug_components &= ~ODM_FW_DEBUG_TRACE;
1768 phydm_fw_trace_en_h2c(
1769 dm, false, dm->fw_debug_components, dm_value[2],
1770 dm_value[3]); /*H2C to enable C2H Msg*/
1771 } else {
1772 dm->debug_components |= ODM_FW_DEBUG_TRACE;
1773 phydm_fw_trace_en_h2c(
1774 dm, true, dm->fw_debug_components, dm_value[2],
1775 dm_value[3]); /*H2C to enable C2H Msg*/
1776 }
1777 }
1778}
1779
1780static void phydm_dump_bb_reg(void *dm_void, u32 *_used, char *output,
1781 u32 *_out_len)
1782{
1783 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1784 u32 addr = 0;
1785 u32 used = *_used;
1786 u32 out_len = *_out_len;
1787
1788 /* For Nseries IC we only need to dump page8 to pageF using 3 digits*/
1789 for (addr = 0x800; addr < 0xfff; addr += 4) {
1790 if (dm->support_ic_type & ODM_IC_11N_SERIES)
1791 PHYDM_VAST_INFO_SNPRINTF(
1792 output + used, out_len - used,
1793 "0x%03x 0x%08x\n", addr,
1794 odm_get_bb_reg(dm, addr, MASKDWORD));
1795 else
1796 PHYDM_VAST_INFO_SNPRINTF(
1797 output + used, out_len - used,
1798 "0x%04x 0x%08x\n", addr,
1799 odm_get_bb_reg(dm, addr, MASKDWORD));
1800 }
1801
1802 if (dm->support_ic_type &
1803 (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)) {
1804 if (dm->rf_type > ODM_2T2R) {
1805 for (addr = 0x1800; addr < 0x18ff; addr += 4)
1806 PHYDM_VAST_INFO_SNPRINTF(
1807 output + used, out_len - used,
1808 "0x%04x 0x%08x\n", addr,
1809 odm_get_bb_reg(dm, addr, MASKDWORD));
1810 }
1811
1812 if (dm->rf_type > ODM_3T3R) {
1813 for (addr = 0x1a00; addr < 0x1aff; addr += 4)
1814 PHYDM_VAST_INFO_SNPRINTF(
1815 output + used, out_len - used,
1816 "0x%04x 0x%08x\n", addr,
1817 odm_get_bb_reg(dm, addr, MASKDWORD));
1818 }
1819
1820 for (addr = 0x1900; addr < 0x19ff; addr += 4)
1821 PHYDM_VAST_INFO_SNPRINTF(
1822 output + used, out_len - used,
1823 "0x%04x 0x%08x\n", addr,
1824 odm_get_bb_reg(dm, addr, MASKDWORD));
1825
1826 for (addr = 0x1c00; addr < 0x1cff; addr += 4)
1827 PHYDM_VAST_INFO_SNPRINTF(
1828 output + used, out_len - used,
1829 "0x%04x 0x%08x\n", addr,
1830 odm_get_bb_reg(dm, addr, MASKDWORD));
1831
1832 for (addr = 0x1f00; addr < 0x1fff; addr += 4)
1833 PHYDM_VAST_INFO_SNPRINTF(
1834 output + used, out_len - used,
1835 "0x%04x 0x%08x\n", addr,
1836 odm_get_bb_reg(dm, addr, MASKDWORD));
1837 }
1838}
1839
1840static void phydm_dump_all_reg(void *dm_void, u32 *_used, char *output,
1841 u32 *_out_len)
1842{
1843 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1844 u32 addr = 0;
1845 u32 used = *_used;
1846 u32 out_len = *_out_len;
1847
1848 /* dump MAC register */
1849 PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
1850 "MAC==========\n");
1851 for (addr = 0; addr < 0x7ff; addr += 4)
1852 PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
1853 "0x%04x 0x%08x\n", addr,
1854 odm_get_bb_reg(dm, addr, MASKDWORD));
1855
1856 for (addr = 0x1000; addr < 0x17ff; addr += 4)
1857 PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
1858 "0x%04x 0x%08x\n", addr,
1859 odm_get_bb_reg(dm, addr, MASKDWORD));
1860
1861 /* dump BB register */
1862 PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
1863 "BB==========\n");
1864 phydm_dump_bb_reg(dm, &used, output, &out_len);
1865
1866 /* dump RF register */
1867 PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
1868 "RF-A==========\n");
1869 for (addr = 0; addr < 0xFF; addr++)
1870 PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
1871 "0x%02x 0x%05x\n", addr,
1872 odm_get_rf_reg(dm, ODM_RF_PATH_A, addr,
1873 RFREGOFFSETMASK));
1874
1875 if (dm->rf_type > ODM_1T1R) {
1876 PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
1877 "RF-B==========\n");
1878 for (addr = 0; addr < 0xFF; addr++)
1879 PHYDM_VAST_INFO_SNPRINTF(
1880 output + used, out_len - used,
1881 "0x%02x 0x%05x\n", addr,
1882 odm_get_rf_reg(dm, ODM_RF_PATH_B, addr,
1883 RFREGOFFSETMASK));
1884 }
1885
1886 if (dm->rf_type > ODM_2T2R) {
1887 PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
1888 "RF-C==========\n");
1889 for (addr = 0; addr < 0xFF; addr++)
1890 PHYDM_VAST_INFO_SNPRINTF(
1891 output + used, out_len - used,
1892 "0x%02x 0x%05x\n", addr,
1893 odm_get_rf_reg(dm, ODM_RF_PATH_C, addr,
1894 RFREGOFFSETMASK));
1895 }
1896
1897 if (dm->rf_type > ODM_3T3R) {
1898 PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
1899 "RF-D==========\n");
1900 for (addr = 0; addr < 0xFF; addr++)
1901 PHYDM_VAST_INFO_SNPRINTF(
1902 output + used, out_len - used,
1903 "0x%02x 0x%05x\n", addr,
1904 odm_get_rf_reg(dm, ODM_RF_PATH_D, addr,
1905 RFREGOFFSETMASK));
1906 }
1907}
1908
1909static void phydm_enable_big_jump(struct phy_dm_struct *dm, bool state)
1910{
1911 struct dig_thres *dig_tab = &dm->dm_dig_table;
1912
1913 if (!state) {
1914 dm->dm_dig_table.enable_adjust_big_jump = false;
1915 odm_set_bb_reg(dm, 0x8c8, 0xfe,
1916 ((dig_tab->big_jump_step3 << 5) |
1917 (dig_tab->big_jump_step2 << 3) |
1918 dig_tab->big_jump_step1));
1919 } else {
1920 dm->dm_dig_table.enable_adjust_big_jump = true;
1921 }
1922}
1923
1924static void phydm_show_rx_rate(struct phy_dm_struct *dm, u32 *_used,
1925 char *output, u32 *_out_len)
1926{
1927 u32 used = *_used;
1928 u32 out_len = *_out_len;
1929
1930 PHYDM_SNPRINTF(output + used, out_len - used,
1931 "=====Rx SU rate Statistics=====\n");
1932 PHYDM_SNPRINTF(
1933 output + used, out_len - used,
1934 "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n",
1935 dm->phy_dbg_info.num_qry_vht_pkt[0],
1936 dm->phy_dbg_info.num_qry_vht_pkt[1],
1937 dm->phy_dbg_info.num_qry_vht_pkt[2],
1938 dm->phy_dbg_info.num_qry_vht_pkt[3]);
1939 PHYDM_SNPRINTF(
1940 output + used, out_len - used,
1941 "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n",
1942 dm->phy_dbg_info.num_qry_vht_pkt[4],
1943 dm->phy_dbg_info.num_qry_vht_pkt[5],
1944 dm->phy_dbg_info.num_qry_vht_pkt[6],
1945 dm->phy_dbg_info.num_qry_vht_pkt[7]);
1946 PHYDM_SNPRINTF(output + used, out_len - used,
1947 "1SS MCS8 = %d, 1SS MCS9 = %d\n",
1948 dm->phy_dbg_info.num_qry_vht_pkt[8],
1949 dm->phy_dbg_info.num_qry_vht_pkt[9]);
1950 PHYDM_SNPRINTF(
1951 output + used, out_len - used,
1952 "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n",
1953 dm->phy_dbg_info.num_qry_vht_pkt[10],
1954 dm->phy_dbg_info.num_qry_vht_pkt[11],
1955 dm->phy_dbg_info.num_qry_vht_pkt[12],
1956 dm->phy_dbg_info.num_qry_vht_pkt[13]);
1957 PHYDM_SNPRINTF(
1958 output + used, out_len - used,
1959 "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n",
1960 dm->phy_dbg_info.num_qry_vht_pkt[14],
1961 dm->phy_dbg_info.num_qry_vht_pkt[15],
1962 dm->phy_dbg_info.num_qry_vht_pkt[16],
1963 dm->phy_dbg_info.num_qry_vht_pkt[17]);
1964 PHYDM_SNPRINTF(output + used, out_len - used,
1965 "2SS MCS8 = %d, 2SS MCS9 = %d\n",
1966 dm->phy_dbg_info.num_qry_vht_pkt[18],
1967 dm->phy_dbg_info.num_qry_vht_pkt[19]);
1968
1969 PHYDM_SNPRINTF(output + used, out_len - used,
1970 "=====Rx MU rate Statistics=====\n");
1971 PHYDM_SNPRINTF(
1972 output + used, out_len - used,
1973 "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n",
1974 dm->phy_dbg_info.num_qry_mu_vht_pkt[0],
1975 dm->phy_dbg_info.num_qry_mu_vht_pkt[1],
1976 dm->phy_dbg_info.num_qry_mu_vht_pkt[2],
1977 dm->phy_dbg_info.num_qry_mu_vht_pkt[3]);
1978 PHYDM_SNPRINTF(
1979 output + used, out_len - used,
1980 "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n",
1981 dm->phy_dbg_info.num_qry_mu_vht_pkt[4],
1982 dm->phy_dbg_info.num_qry_mu_vht_pkt[5],
1983 dm->phy_dbg_info.num_qry_mu_vht_pkt[6],
1984 dm->phy_dbg_info.num_qry_mu_vht_pkt[7]);
1985 PHYDM_SNPRINTF(output + used, out_len - used,
1986 "1SS MCS8 = %d, 1SS MCS9 = %d\n",
1987 dm->phy_dbg_info.num_qry_mu_vht_pkt[8],
1988 dm->phy_dbg_info.num_qry_mu_vht_pkt[9]);
1989 PHYDM_SNPRINTF(
1990 output + used, out_len - used,
1991 "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n",
1992 dm->phy_dbg_info.num_qry_mu_vht_pkt[10],
1993 dm->phy_dbg_info.num_qry_mu_vht_pkt[11],
1994 dm->phy_dbg_info.num_qry_mu_vht_pkt[12],
1995 dm->phy_dbg_info.num_qry_mu_vht_pkt[13]);
1996 PHYDM_SNPRINTF(
1997 output + used, out_len - used,
1998 "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n",
1999 dm->phy_dbg_info.num_qry_mu_vht_pkt[14],
2000 dm->phy_dbg_info.num_qry_mu_vht_pkt[15],
2001 dm->phy_dbg_info.num_qry_mu_vht_pkt[16],
2002 dm->phy_dbg_info.num_qry_mu_vht_pkt[17]);
2003 PHYDM_SNPRINTF(output + used, out_len - used,
2004 "2SS MCS8 = %d, 2SS MCS9 = %d\n",
2005 dm->phy_dbg_info.num_qry_mu_vht_pkt[18],
2006 dm->phy_dbg_info.num_qry_mu_vht_pkt[19]);
2007}
2008
2009struct phydm_command {
2010 char name[16];
2011 u8 id;
2012};
2013
2014enum PHYDM_CMD_ID {
2015 PHYDM_HELP,
2016 PHYDM_DEMO,
2017 PHYDM_RA,
2018 PHYDM_PROFILE,
2019 PHYDM_ANTDIV,
2020 PHYDM_PATHDIV,
2021 PHYDM_DEBUG,
2022 PHYDM_FW_DEBUG,
2023 PHYDM_SUPPORT_ABILITY,
2024 PHYDM_GET_TXAGC,
2025 PHYDM_SET_TXAGC,
2026 PHYDM_SMART_ANT,
2027 PHYDM_API,
2028 PHYDM_TRX_PATH,
2029 PHYDM_LA_MODE,
2030 PHYDM_DUMP_REG,
2031 PHYDM_MU_MIMO,
2032 PHYDM_HANG,
2033 PHYDM_BIG_JUMP,
2034 PHYDM_SHOW_RXRATE,
2035 PHYDM_NBI_EN,
2036 PHYDM_CSI_MASK_EN,
2037 PHYDM_DFS,
2038 PHYDM_IQK,
2039 PHYDM_NHM,
2040 PHYDM_CLM,
2041 PHYDM_BB_INFO,
2042 PHYDM_TXBF,
2043 PHYDM_PAUSE_DIG_EN,
2044 PHYDM_H2C,
2045 PHYDM_ANT_SWITCH,
2046 PHYDM_DYNAMIC_RA_PATH,
2047 PHYDM_PSD,
2048 PHYDM_DEBUG_PORT
2049};
2050
2051static struct phydm_command phy_dm_ary[] = {
2052 {"-h", PHYDM_HELP}, /*do not move this element to other position*/
2053 {"demo", PHYDM_DEMO}, /*do not move this element to other position*/
2054 {"ra", PHYDM_RA},
2055 {"profile", PHYDM_PROFILE},
2056 {"antdiv", PHYDM_ANTDIV},
2057 {"pathdiv", PHYDM_PATHDIV},
2058 {"dbg", PHYDM_DEBUG},
2059 {"fw_dbg", PHYDM_FW_DEBUG},
2060 {"ability", PHYDM_SUPPORT_ABILITY},
2061 {"get_txagc", PHYDM_GET_TXAGC},
2062 {"set_txagc", PHYDM_SET_TXAGC},
2063 {"smtant", PHYDM_SMART_ANT},
2064 {"api", PHYDM_API},
2065 {"trxpath", PHYDM_TRX_PATH},
2066 {"lamode", PHYDM_LA_MODE},
2067 {"dumpreg", PHYDM_DUMP_REG},
2068 {"mu", PHYDM_MU_MIMO},
2069 {"hang", PHYDM_HANG},
2070 {"bigjump", PHYDM_BIG_JUMP},
2071 {"rxrate", PHYDM_SHOW_RXRATE},
2072 {"nbi", PHYDM_NBI_EN},
2073 {"csi_mask", PHYDM_CSI_MASK_EN},
2074 {"dfs", PHYDM_DFS},
2075 {"iqk", PHYDM_IQK},
2076 {"nhm", PHYDM_NHM},
2077 {"clm", PHYDM_CLM},
2078 {"bbinfo", PHYDM_BB_INFO},
2079 {"txbf", PHYDM_TXBF},
2080 {"pause_dig", PHYDM_PAUSE_DIG_EN},
2081 {"h2c", PHYDM_H2C},
2082 {"ant_switch", PHYDM_ANT_SWITCH},
2083 {"drp", PHYDM_DYNAMIC_RA_PATH},
2084 {"psd", PHYDM_PSD},
2085 {"dbgport", PHYDM_DEBUG_PORT},
2086};
2087
2088void phydm_cmd_parser(struct phy_dm_struct *dm, char input[][MAX_ARGV],
2089 u32 input_num, u8 flag, char *output, u32 out_len)
2090{
2091 u32 used = 0;
2092 u8 id = 0;
2093 int var1[10] = {0};
2094 int i, input_idx = 0, phydm_ary_size;
2095 char help[] = "-h";
2096
2097 bool is_enable_dbg_mode;
2098 u8 central_ch, primary_ch_idx, bandwidth;
2099
2100 if (flag == 0) {
2101 PHYDM_SNPRINTF(output + used, out_len - used,
2102 "GET, nothing to print\n");
2103 return;
2104 }
2105
2106 PHYDM_SNPRINTF(output + used, out_len - used, "\n");
2107
2108 /* Parsing Cmd ID */
2109 if (input_num) {
2110 phydm_ary_size =
2111 sizeof(phy_dm_ary) / sizeof(struct phydm_command);
2112 for (i = 0; i < phydm_ary_size; i++) {
2113 if (strcmp(phy_dm_ary[i].name, input[0]) == 0) {
2114 id = phy_dm_ary[i].id;
2115 break;
2116 }
2117 }
2118 if (i == phydm_ary_size) {
2119 PHYDM_SNPRINTF(output + used, out_len - used,
2120 "SET, command not found!\n");
2121 return;
2122 }
2123 }
2124
2125 switch (id) {
2126 case PHYDM_HELP: {
2127 PHYDM_SNPRINTF(output + used, out_len - used, "BB cmd ==>\n");
2128 for (i = 0; i < phydm_ary_size - 2; i++) {
2129 PHYDM_SNPRINTF(output + used, out_len - used,
2130 " %-5d: %s\n", i,
2131 phy_dm_ary[i + 2].name);
2132 /**/
2133 }
2134 } break;
2135
2136 case PHYDM_DEMO: { /*echo demo 10 0x3a z abcde >cmd*/
2137 u32 directory = 0;
2138
2139 char char_temp;
2140
2141 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory);
2142 PHYDM_SNPRINTF(output + used, out_len - used,
2143 "Decimal value = %d\n", directory);
2144 PHYDM_SSCANF(input[2], DCMD_HEX, &directory);
2145 PHYDM_SNPRINTF(output + used, out_len - used,
2146 "Hex value = 0x%x\n", directory);
2147 PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp);
2148 PHYDM_SNPRINTF(output + used, out_len - used, "Char = %c\n",
2149 char_temp);
2150 PHYDM_SNPRINTF(output + used, out_len - used, "String = %s\n",
2151 input[4]);
2152 } break;
2153
2154 case PHYDM_RA:
2155
2156 for (i = 0; i < 5; i++) {
2157 if (input[i + 1]) {
2158 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2159 &var1[i]);
2160
2161 input_idx++;
2162 }
2163 }
2164
2165 if (input_idx >= 1) {
2166 phydm_RA_debug_PCR(dm, (u32 *)var1, &used, output,
2167 &out_len);
2168 }
2169
2170 break;
2171
2172 case PHYDM_ANTDIV:
2173
2174 for (i = 0; i < 5; i++) {
2175 if (input[i + 1]) {
2176 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2177
2178 input_idx++;
2179 }
2180 }
2181
2182 break;
2183
2184 case PHYDM_PATHDIV:
2185
2186 for (i = 0; i < 5; i++) {
2187 if (input[i + 1]) {
2188 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2189
2190 input_idx++;
2191 }
2192 }
2193
2194 break;
2195
2196 case PHYDM_DEBUG:
2197
2198 for (i = 0; i < 5; i++) {
2199 if (input[i + 1]) {
2200 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2201 &var1[i]);
2202
2203 input_idx++;
2204 }
2205 }
2206
2207 if (input_idx >= 1) {
2208 phydm_debug_trace(dm, (u32 *)var1, &used, output,
2209 &out_len);
2210 }
2211
2212 break;
2213
2214 case PHYDM_FW_DEBUG:
2215
2216 for (i = 0; i < 5; i++) {
2217 if (input[i + 1]) {
2218 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2219 &var1[i]);
2220 input_idx++;
2221 }
2222 }
2223
2224 if (input_idx >= 1)
2225 phydm_fw_debug_trace(dm, (u32 *)var1, &used, output,
2226 &out_len);
2227
2228 break;
2229
2230 case PHYDM_SUPPORT_ABILITY:
2231
2232 for (i = 0; i < 5; i++) {
2233 if (input[i + 1]) {
2234 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2235 &var1[i]);
2236
2237 input_idx++;
2238 }
2239 }
2240
2241 if (input_idx >= 1) {
2242 phydm_support_ability_debug(dm, (u32 *)var1, &used,
2243 output, &out_len);
2244 }
2245
2246 break;
2247
2248 case PHYDM_SMART_ANT:
2249
2250 for (i = 0; i < 5; i++) {
2251 if (input[i + 1]) {
2252 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2253 input_idx++;
2254 }
2255 }
2256
2257 break;
2258
2259 case PHYDM_API:
2260 if (!(dm->support_ic_type &
2261 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C))) {
2262 PHYDM_SNPRINTF(
2263 output + used, out_len - used,
2264 "This IC doesn't support PHYDM API function\n");
2265 }
2266
2267 for (i = 0; i < 4; i++) {
2268 if (input[i + 1])
2269 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2270 &var1[i]);
2271 }
2272
2273 is_enable_dbg_mode = (bool)var1[0];
2274 central_ch = (u8)var1[1];
2275 primary_ch_idx = (u8)var1[2];
2276 bandwidth = (enum odm_bw)var1[3];
2277
2278 if (is_enable_dbg_mode) {
2279 dm->is_disable_phy_api = false;
2280 phydm_api_switch_bw_channel(dm, central_ch,
2281 primary_ch_idx,
2282 (enum odm_bw)bandwidth);
2283 dm->is_disable_phy_api = true;
2284 PHYDM_SNPRINTF(
2285 output + used, out_len - used,
2286 "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n",
2287 central_ch, primary_ch_idx, bandwidth);
2288 } else {
2289 dm->is_disable_phy_api = false;
2290 PHYDM_SNPRINTF(output + used, out_len - used,
2291 "Disable API debug mode\n");
2292 }
2293 break;
2294
2295 case PHYDM_PROFILE: /*echo profile, >cmd*/
2296 phydm_basic_profile(dm, &used, output, &out_len);
2297 break;
2298
2299 case PHYDM_GET_TXAGC:
2300 phydm_get_txagc(dm, &used, output, &out_len);
2301 break;
2302
2303 case PHYDM_SET_TXAGC: {
2304 bool is_enable_dbg_mode;
2305
2306 for (i = 0; i < 5; i++) {
2307 if (input[i + 1]) {
2308 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2309 input_idx++;
2310 }
2311 }
2312
2313 if ((strcmp(input[1], help) == 0)) {
2314 PHYDM_SNPRINTF(
2315 output + used, out_len - used,
2316 "{En} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n");
2317 /**/
2318
2319 } else {
2320 is_enable_dbg_mode = (bool)var1[0];
2321 if (is_enable_dbg_mode) {
2322 dm->is_disable_phy_api = false;
2323 phydm_set_txagc(dm, (u32 *)var1, &used, output,
2324 &out_len);
2325 dm->is_disable_phy_api = true;
2326 } else {
2327 dm->is_disable_phy_api = false;
2328 PHYDM_SNPRINTF(output + used, out_len - used,
2329 "Disable API debug mode\n");
2330 }
2331 }
2332 } break;
2333
2334 case PHYDM_TRX_PATH:
2335
2336 for (i = 0; i < 4; i++) {
2337 if (input[i + 1])
2338 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2339 &var1[i]);
2340 }
2341 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) {
2342 u8 tx_path, rx_path;
2343 bool is_enable_dbg_mode, is_tx2_path;
2344
2345 is_enable_dbg_mode = (bool)var1[0];
2346 tx_path = (u8)var1[1];
2347 rx_path = (u8)var1[2];
2348 is_tx2_path = (bool)var1[3];
2349
2350 if (is_enable_dbg_mode) {
2351 dm->is_disable_phy_api = false;
2352 phydm_api_trx_mode(
2353 dm, (enum odm_rf_path)tx_path,
2354 (enum odm_rf_path)rx_path, is_tx2_path);
2355 dm->is_disable_phy_api = true;
2356 PHYDM_SNPRINTF(
2357 output + used, out_len - used,
2358 "tx_path = 0x%x, rx_path = 0x%x, is_tx2_path = %d\n",
2359 tx_path, rx_path, is_tx2_path);
2360 } else {
2361 dm->is_disable_phy_api = false;
2362 PHYDM_SNPRINTF(output + used, out_len - used,
2363 "Disable API debug mode\n");
2364 }
2365 } else {
2366 phydm_config_trx_path(dm, (u32 *)var1, &used, output,
2367 &out_len);
2368 }
2369 break;
2370
2371 case PHYDM_LA_MODE:
2372
2373 dm->support_ability &= ~(ODM_BB_FA_CNT);
2374 phydm_lamode_trigger_setting(dm, &input[0], &used, output,
2375 &out_len, input_num);
2376 dm->support_ability |= ODM_BB_FA_CNT;
2377
2378 break;
2379
2380 case PHYDM_DUMP_REG: {
2381 u8 type = 0;
2382
2383 if (input[1]) {
2384 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2385 type = (u8)var1[0];
2386 }
2387
2388 if (type == 0)
2389 phydm_dump_bb_reg(dm, &used, output, &out_len);
2390 else if (type == 1)
2391 phydm_dump_all_reg(dm, &used, output, &out_len);
2392 } break;
2393
2394 case PHYDM_MU_MIMO:
2395
2396 if (input[1])
2397 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2398 else
2399 var1[0] = 0;
2400
2401 if (var1[0] == 1) {
2402 PHYDM_SNPRINTF(output + used, out_len - used,
2403 "Get MU BFee CSI\n");
2404 odm_set_bb_reg(dm, 0x9e8, BIT(17) | BIT(16),
2405 2); /*Read BFee*/
2406 odm_set_bb_reg(dm, 0x1910, BIT(15),
2407 1); /*Select BFee's CSI report*/
2408 odm_set_bb_reg(dm, 0x19b8, BIT(6),
2409 1); /*set as CSI report*/
2410 odm_set_bb_reg(dm, 0x19a8, 0xFFFF,
2411 0xFFFF); /*disable gated_clk*/
2412 phydm_print_csi(dm, used, out_len, output);
2413
2414 } else if (var1[0] == 2) {
2415 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
2416 PHYDM_SNPRINTF(output + used, out_len - used,
2417 "Get MU BFer's STA%d CSI\n", var1[1]);
2418 odm_set_bb_reg(dm, 0x9e8, BIT(24), 0); /*Read BFer*/
2419 odm_set_bb_reg(dm, 0x9e8, BIT(25),
2420 1); /*enable Read/Write RAM*/
2421 odm_set_bb_reg(dm, 0x9e8, BIT(30) | BIT(29) | BIT(28),
2422 var1[1]); /*read which STA's CSI report*/
2423 odm_set_bb_reg(dm, 0x1910, BIT(15),
2424 0); /*select BFer's CSI*/
2425 odm_set_bb_reg(dm, 0x19e0, 0x00003FC0,
2426 0xFF); /*disable gated_clk*/
2427 phydm_print_csi(dm, used, out_len, output);
2428 }
2429 break;
2430
2431 case PHYDM_BIG_JUMP: {
2432 if (input[1]) {
2433 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2434 phydm_enable_big_jump(dm, (bool)(var1[0]));
2435 } else {
2436 PHYDM_SNPRINTF(output + used, out_len - used,
2437 "unknown command!\n");
2438 }
2439 break;
2440 }
2441
2442 case PHYDM_HANG:
2443 phydm_bb_rx_hang_info(dm, &used, output, &out_len);
2444 break;
2445
2446 case PHYDM_SHOW_RXRATE: {
2447 u8 rate_idx;
2448
2449 if (input[1])
2450 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2451
2452 if (var1[0] == 1) {
2453 phydm_show_rx_rate(dm, &used, output, &out_len);
2454 } else {
2455 PHYDM_SNPRINTF(output + used, out_len - used,
2456 "Reset Rx rate counter\n");
2457
2458 for (rate_idx = 0; rate_idx < 40; rate_idx++) {
2459 dm->phy_dbg_info.num_qry_vht_pkt[rate_idx] = 0;
2460 dm->phy_dbg_info.num_qry_mu_vht_pkt[rate_idx] =
2461 0;
2462 }
2463 }
2464 } break;
2465
2466 case PHYDM_NBI_EN:
2467
2468 for (i = 0; i < 5; i++) {
2469 if (input[i + 1]) {
2470 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2471 &var1[i]);
2472 input_idx++;
2473 }
2474 }
2475
2476 if (input_idx >= 1) {
2477 phydm_api_debug(dm, PHYDM_API_NBI, (u32 *)var1, &used,
2478 output, &out_len);
2479 /**/
2480 }
2481
2482 break;
2483
2484 case PHYDM_CSI_MASK_EN:
2485
2486 for (i = 0; i < 5; i++) {
2487 if (input[i + 1]) {
2488 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2489 &var1[i]);
2490 input_idx++;
2491 }
2492 }
2493
2494 if (input_idx >= 1) {
2495 phydm_api_debug(dm, PHYDM_API_CSI_MASK, (u32 *)var1,
2496 &used, output, &out_len);
2497 /**/
2498 }
2499
2500 break;
2501
2502 case PHYDM_DFS:
2503 break;
2504
2505 case PHYDM_IQK:
2506 break;
2507
2508 case PHYDM_NHM: {
2509 u8 target_rssi;
2510 u16 nhm_period = 0xC350; /* 200ms */
2511 u8 IGI;
2512 struct ccx_info *ccx_info = &dm->dm_ccx_info;
2513
2514 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2515
2516 if (input_num == 1) {
2517 ccx_info->echo_NHM_en = false;
2518 PHYDM_SNPRINTF(output + used, out_len - used,
2519 "\r\n Trigger NHM: echo nhm 1\n");
2520 PHYDM_SNPRINTF(output + used, out_len - used,
2521 "\r (Exclude CCA)\n");
2522 PHYDM_SNPRINTF(output + used, out_len - used,
2523 "\r Trigger NHM: echo nhm 2\n");
2524 PHYDM_SNPRINTF(output + used, out_len - used,
2525 "\r (Include CCA)\n");
2526 PHYDM_SNPRINTF(output + used, out_len - used,
2527 "\r Get NHM results: echo nhm 3\n");
2528
2529 return;
2530 }
2531
2532 /* NMH trigger */
2533 if ((var1[0] <= 2) && (var1[0] != 0)) {
2534 ccx_info->echo_NHM_en = true;
2535 ccx_info->echo_IGI =
2536 (u8)odm_get_bb_reg(dm, 0xC50, MASKBYTE0);
2537
2538 target_rssi = ccx_info->echo_IGI - 10;
2539
2540 ccx_info->NHM_th[0] = (target_rssi - 15 + 10) * 2;
2541
2542 for (i = 1; i <= 10; i++)
2543 ccx_info->NHM_th[i] =
2544 ccx_info->NHM_th[0] + 6 * i;
2545
2546 /* 4 1. store previous NHM setting */
2547 phydm_nhm_setting(dm, STORE_NHM_SETTING);
2548
2549 /* 4 2. Set NHM period, 0x990[31:16]=0xC350,
2550 * Time duration for NHM unit: 4us, 0xC350=200ms
2551 */
2552 ccx_info->NHM_period = nhm_period;
2553
2554 PHYDM_SNPRINTF(output + used, out_len - used,
2555 "\r\n Monitor NHM for %d us",
2556 nhm_period * 4);
2557
2558 /* 4 3. Set NHM inexclude_txon, inexclude_cca, ccx_en */
2559
2560 ccx_info->nhm_inexclude_cca = (var1[0] == 1) ?
2561 NHM_EXCLUDE_CCA :
2562 NHM_INCLUDE_CCA;
2563 ccx_info->nhm_inexclude_txon = NHM_EXCLUDE_TXON;
2564
2565 phydm_nhm_setting(dm, SET_NHM_SETTING);
2566 phydm_print_nhm_trigger(output, used, out_len,
2567 ccx_info);
2568
2569 /* 4 4. Trigger NHM */
2570 phydm_nhm_trigger(dm);
2571 }
2572
2573 /*Get NHM results*/
2574 else if (var1[0] == 3) {
2575 IGI = (u8)odm_get_bb_reg(dm, 0xC50, MASKBYTE0);
2576
2577 PHYDM_SNPRINTF(output + used, out_len - used,
2578 "\r\n Cur_IGI = 0x%x", IGI);
2579
2580 phydm_get_nhm_result(dm);
2581
2582 /* 4 Resotre NHM setting */
2583 phydm_nhm_setting(dm, RESTORE_NHM_SETTING);
2584 phydm_print_nhm_result(output, used, out_len, ccx_info);
2585
2586 ccx_info->echo_NHM_en = false;
2587 } else {
2588 ccx_info->echo_NHM_en = false;
2589 PHYDM_SNPRINTF(output + used, out_len - used,
2590 "\r\n Trigger NHM: echo nhm 1\n");
2591 PHYDM_SNPRINTF(output + used, out_len - used,
2592 "\r (Exclude CCA)\n");
2593 PHYDM_SNPRINTF(output + used, out_len - used,
2594 "\r Trigger NHM: echo nhm 2\n");
2595 PHYDM_SNPRINTF(output + used, out_len - used,
2596 "\r (Include CCA)\n");
2597 PHYDM_SNPRINTF(output + used, out_len - used,
2598 "\r Get NHM results: echo nhm 3\n");
2599
2600 return;
2601 }
2602 } break;
2603
2604 case PHYDM_CLM: {
2605 struct ccx_info *ccx_info = &dm->dm_ccx_info;
2606
2607 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2608
2609 if (input_num == 1) {
2610 ccx_info->echo_CLM_en = false;
2611 PHYDM_SNPRINTF(output + used, out_len - used,
2612 "\r\n Trigger CLM: echo clm 1\n");
2613 PHYDM_SNPRINTF(output + used, out_len - used,
2614 "\r Get CLM results: echo clm 2\n");
2615 return;
2616 }
2617
2618 /* Set & trigger CLM */
2619 if (var1[0] == 1) {
2620 ccx_info->echo_CLM_en = true;
2621 ccx_info->CLM_period = 0xC350; /*100ms*/
2622 phydm_clm_setting(dm);
2623 phydm_clm_trigger(dm);
2624 PHYDM_SNPRINTF(output + used, out_len - used,
2625 "\r\n Monitor CLM for 200ms\n");
2626 }
2627
2628 /* Get CLM results */
2629 else if (var1[0] == 2) {
2630 ccx_info->echo_CLM_en = false;
2631 phydm_get_cl_mresult(dm);
2632 PHYDM_SNPRINTF(output + used, out_len - used,
2633 "\r\n CLM_result = %d us\n",
2634 ccx_info->CLM_result * 4);
2635
2636 } else {
2637 ccx_info->echo_CLM_en = false;
2638 PHYDM_SNPRINTF(output + used, out_len - used,
2639 "\n\r Error command !\n");
2640 PHYDM_SNPRINTF(output + used, out_len - used,
2641 "\r Trigger CLM: echo clm 1\n");
2642 PHYDM_SNPRINTF(output + used, out_len - used,
2643 "\r Get CLM results: echo clm 2\n");
2644 }
2645 } break;
2646
2647 case PHYDM_BB_INFO: {
2648 s32 value32 = 0;
2649
2650 phydm_bb_debug_info(dm, &used, output, &out_len);
2651
2652 if (dm->support_ic_type & ODM_RTL8822B && input[1]) {
2653 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2654 odm_set_bb_reg(dm, 0x1988, 0x003fff00, var1[0]);
2655 value32 = odm_get_bb_reg(dm, 0xf84, MASKDWORD);
2656 value32 = (value32 & 0xff000000) >> 24;
2657 PHYDM_SNPRINTF(
2658 output + used, out_len - used,
2659 "\r\n %-35s = condition num = %d, subcarriers = %d\n",
2660 "Over condition num subcarrier", var1[0],
2661 value32);
2662 odm_set_bb_reg(dm, 0x1988, BIT(22),
2663 0x0); /*disable report condition number*/
2664 }
2665 } break;
2666
2667 case PHYDM_TXBF: {
2668 PHYDM_SNPRINTF(output + used, out_len - used,
2669 "\r\n no TxBF !!\n");
2670 } break;
2671
2672 case PHYDM_PAUSE_DIG_EN:
2673
2674 for (i = 0; i < 5; i++) {
2675 if (input[i + 1]) {
2676 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2677 input_idx++;
2678 }
2679 }
2680
2681 if (input_idx >= 1) {
2682 if (var1[0] == 0) {
2683 odm_pause_dig(dm, PHYDM_PAUSE,
2684 PHYDM_PAUSE_LEVEL_7, (u8)var1[1]);
2685 PHYDM_SNPRINTF(output + used, out_len - used,
2686 "Set IGI_value = ((%x))\n",
2687 var1[1]);
2688 } else if (var1[0] == 1) {
2689 odm_pause_dig(dm, PHYDM_RESUME,
2690 PHYDM_PAUSE_LEVEL_7, (u8)var1[1]);
2691 PHYDM_SNPRINTF(output + used, out_len - used,
2692 "Resume IGI_value\n");
2693 } else {
2694 PHYDM_SNPRINTF(
2695 output + used, out_len - used,
2696 "echo (1:pause, 2resume) (IGI_value)\n");
2697 }
2698 }
2699 break;
2700 case PHYDM_H2C:
2701
2702 for (i = 0; i < 8; i++) {
2703 if (input[i + 1]) {
2704 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2705 input_idx++;
2706 }
2707 }
2708
2709 if (input_idx >= 1)
2710 phydm_h2C_debug(dm, (u32 *)var1, &used, output,
2711 &out_len);
2712
2713 break;
2714
2715 case PHYDM_ANT_SWITCH:
2716
2717 for (i = 0; i < 8; i++) {
2718 if (input[i + 1]) {
2719 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2720 &var1[i]);
2721 input_idx++;
2722 }
2723 }
2724
2725 if (input_idx >= 1) {
2726 PHYDM_SNPRINTF(output + used, out_len - used,
2727 "Not Support IC");
2728 }
2729
2730 break;
2731
2732 case PHYDM_DYNAMIC_RA_PATH:
2733
2734 PHYDM_SNPRINTF(output + used, out_len - used, "Not Support IC");
2735
2736 break;
2737
2738 case PHYDM_PSD:
2739
2740 phydm_psd_debug(dm, &input[0], &used, output, &out_len,
2741 input_num);
2742
2743 break;
2744
2745 case PHYDM_DEBUG_PORT: {
2746 u32 dbg_port_value;
2747
2748 PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]);
2749
2750 if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3,
2751 var1[0])) { /*set debug port to 0x0*/
2752
2753 dbg_port_value = phydm_get_bb_dbg_port_value(dm);
2754 phydm_release_bb_dbg_port(dm);
2755
2756 PHYDM_SNPRINTF(output + used, out_len - used,
2757 "Debug Port[0x%x] = ((0x%x))\n", var1[1],
2758 dbg_port_value);
2759 }
2760 } break;
2761
2762 default:
2763 PHYDM_SNPRINTF(output + used, out_len - used,
2764 "SET, unknown command!\n");
2765 break;
2766 }
2767}
2768
2769s32 phydm_cmd(struct phy_dm_struct *dm, char *input, u32 in_len, u8 flag,
2770 char *output, u32 out_len)
2771{
2772 char *token;
2773 u32 argc = 0;
2774 char argv[MAX_ARGC][MAX_ARGV];
2775
2776 do {
2777 token = strsep(&input, ", ");
2778 if (token) {
2779 strcpy(argv[argc], token);
2780 argc++;
2781 } else {
2782 break;
2783 }
2784 } while (argc < MAX_ARGC);
2785
2786 if (argc == 1)
2787 argv[0][strlen(argv[0]) - 1] = '\0';
2788
2789 phydm_cmd_parser(dm, argv, argc, flag, output, out_len);
2790
2791 return 0;
2792}
2793
2794void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
2795{
2796 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
2797
2798 /*u8 debug_trace_11byte[60];*/
2799 u8 freg_num, c2h_seq, buf_0 = 0;
2800
2801 if (!(dm->support_ic_type & PHYDM_IC_3081_SERIES))
2802 return;
2803
2804 if (cmd_len > 12)
2805 return;
2806
2807 buf_0 = cmd_buf[0];
2808 freg_num = (buf_0 & 0xf);
2809 c2h_seq = (buf_0 & 0xf0) >> 4;
2810
2811 if ((c2h_seq != dm->pre_c2h_seq) && !dm->fw_buff_is_enpty) {
2812 dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
2813 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
2814 "[FW Dbg Queue Overflow] %s\n",
2815 dm->fw_debug_trace);
2816 dm->c2h_cmd_start = 0;
2817 }
2818
2819 if ((cmd_len - 1) > (60 - dm->c2h_cmd_start)) {
2820 dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
2821 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
2822 "[FW Dbg Queue error: wrong C2H length] %s\n",
2823 dm->fw_debug_trace);
2824 dm->c2h_cmd_start = 0;
2825 return;
2826 }
2827
2828 strncpy((char *)&dm->fw_debug_trace[dm->c2h_cmd_start],
2829 (char *)&cmd_buf[1], (cmd_len - 1));
2830 dm->c2h_cmd_start += (cmd_len - 1);
2831 dm->fw_buff_is_enpty = false;
2832
2833 if (freg_num == 0 || dm->c2h_cmd_start >= 60) {
2834 if (dm->c2h_cmd_start < 60)
2835 dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
2836 else
2837 dm->fw_debug_trace[59] = '\0';
2838
2839 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "[FW DBG Msg] %s\n",
2840 dm->fw_debug_trace);
2841 /*dbg_print("[FW DBG Msg] %s\n", dm->fw_debug_trace);*/
2842 dm->c2h_cmd_start = 0;
2843 dm->fw_buff_is_enpty = true;
2844 }
2845
2846 dm->pre_c2h_seq = c2h_seq;
2847}
2848
2849void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len)
2850{
2851 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
2852 u8 function = buffer[0];
2853 u8 dbg_num = buffer[1];
2854 u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]);
2855 u16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]);
2856 u16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]);
2857 u16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]);
2858 u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]);
2859
2860 if (cmd_len > 12)
2861 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
2862 "[FW Msg] Invalid cmd length (( %d )) >12\n",
2863 cmd_len);
2864
2865 /*--------------------------------------------*/
2866 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
2867 "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function,
2868 dbg_num, content_0, content_1, content_2, content_3,
2869 content_4);
2870 /*--------------------------------------------*/
2871}
2872
2873void phydm_fw_trace_handler_8051(void *dm_void, u8 *buffer, u8 cmd_len)
2874{
2875 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
2876
2877 int i = 0;
2878 u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0,
2879 extend_c2h_dbg_seq = 0;
2880 u8 fw_debug_trace[128];
2881 u8 *extend_c2h_dbg_content = NULL;
2882
2883 if (cmd_len > 127)
2884 return;
2885
2886 extend_c2h_sub_id = buffer[0];
2887 extend_c2h_dbg_len = buffer[1];
2888 extend_c2h_dbg_content = buffer + 2; /*DbgSeq+DbgContent for show HEX*/
2889
2890go_backfor_aggre_dbg_pkt:
2891 i = 0;
2892 extend_c2h_dbg_seq = buffer[2];
2893 extend_c2h_dbg_content = buffer + 3;
2894
2895 for (;; i++) {
2896 fw_debug_trace[i] = extend_c2h_dbg_content[i];
2897 if (extend_c2h_dbg_content[i + 1] == '\0') {
2898 fw_debug_trace[i + 1] = '\0';
2899 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "[FW DBG Msg] %s",
2900 &fw_debug_trace[0]);
2901 break;
2902 } else if (extend_c2h_dbg_content[i] == '\n') {
2903 fw_debug_trace[i + 1] = '\0';
2904 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "[FW DBG Msg] %s",
2905 &fw_debug_trace[0]);
2906 buffer = extend_c2h_dbg_content + i + 3;
2907 goto go_backfor_aggre_dbg_pkt;
2908 }
2909 }
2910}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_debug.h b/drivers/staging/rtlwifi/phydm/phydm_debug.h
new file mode 100644
index 000000000000..f442f7c19595
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_debug.h
@@ -0,0 +1,175 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __ODM_DBG_H__
27#define __ODM_DBG_H__
28
29/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
30/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
31#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/
32#define ODM_DBG_TRACE 5
33
34/*FW DBG MSG*/
35#define RATE_DECISION BIT(0)
36#define INIT_RA_TABLE BIT(1)
37#define RATE_UP BIT(2)
38#define RATE_DOWN BIT(3)
39#define TRY_DONE BIT(4)
40#define RA_H2C BIT(5)
41#define F_RATE_AP_RPT BIT(7)
42
43/* -----------------------------------------------------------------------------
44 * Define the tracing components
45 *
46 * -----------------------------------------------------------------------------
47 */
48/*BB FW Functions*/
49#define PHYDM_FW_COMP_RA BIT(0)
50#define PHYDM_FW_COMP_MU BIT(1)
51#define PHYDM_FW_COMP_PATH_DIV BIT(2)
52#define PHYDM_FW_COMP_PHY_CONFIG BIT(3)
53
54/*BB Driver Functions*/
55#define ODM_COMP_DIG BIT(0)
56#define ODM_COMP_RA_MASK BIT(1)
57#define ODM_COMP_DYNAMIC_TXPWR BIT(2)
58#define ODM_COMP_FA_CNT BIT(3)
59#define ODM_COMP_RSSI_MONITOR BIT(4)
60#define ODM_COMP_SNIFFER BIT(5)
61#define ODM_COMP_ANT_DIV BIT(6)
62#define ODM_COMP_DFS BIT(7)
63#define ODM_COMP_NOISY_DETECT BIT(8)
64#define ODM_COMP_RATE_ADAPTIVE BIT(9)
65#define ODM_COMP_PATH_DIV BIT(10)
66#define ODM_COMP_CCX BIT(11)
67
68#define ODM_COMP_DYNAMIC_PRICCA BIT(12)
69/*BIT13 TBD*/
70#define ODM_COMP_MP BIT(14)
71#define ODM_COMP_CFO_TRACKING BIT(15)
72#define ODM_COMP_ACS BIT(16)
73#define PHYDM_COMP_ADAPTIVITY BIT(17)
74#define PHYDM_COMP_RA_DBG BIT(18)
75#define PHYDM_COMP_TXBF BIT(19)
76/* MAC Functions */
77#define ODM_COMP_EDCA_TURBO BIT(20)
78#define ODM_COMP_DYNAMIC_RX_PATH BIT(21)
79#define ODM_FW_DEBUG_TRACE BIT(22)
80/* RF Functions */
81/*BIT23 TBD*/
82#define ODM_COMP_TX_PWR_TRACK BIT(24)
83/*BIT25 TBD*/
84#define ODM_COMP_CALIBRATION BIT(26)
85/* Common Functions */
86/*BIT27 TBD*/
87#define ODM_PHY_CONFIG BIT(28)
88#define ODM_COMP_INIT BIT(29)
89#define ODM_COMP_COMMON BIT(30)
90#define ODM_COMP_API BIT(31)
91
92#define ODM_COMP_UNCOND 0xFFFFFFFF
93
94/*------------------------Export Marco Definition---------------------------*/
95
96#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
97
98#define ODM_RT_TRACE(dm, comp, fmt, ...) \
99 do { \
100 if (((comp) & dm->debug_components) || \
101 ((comp) == ODM_COMP_UNCOND)) \
102 RT_TRACE(dm->adapter, COMP_PHYDM, DBG_DMESG, fmt, \
103 ##__VA_ARGS__); \
104 } while (0)
105
106#define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/
107#define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/
108#define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/
109#define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/
110
111void phydm_init_debug_setting(struct phy_dm_struct *dm);
112
113u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
114
115void phydm_release_bb_dbg_port(void *dm_void);
116
117u32 phydm_get_bb_dbg_port_value(void *dm_void);
118
119void phydm_basic_dbg_message(void *dm_void);
120
121#define PHYDM_DBGPRINT 0
122#define MAX_ARGC 20
123#define MAX_ARGV 16
124#define DCMD_DECIMAL "%d"
125#define DCMD_CHAR "%c"
126#define DCMD_HEX "%x"
127
128#define PHYDM_SSCANF(x, y, z) \
129 do { \
130 if (sscanf(x, y, z) != 1) \
131 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, \
132 "%s:%d sscanf fail!", __func__, \
133 __LINE__); \
134 } while (0)
135
136#define PHYDM_VAST_INFO_SNPRINTF(msg, ...) \
137 do { \
138 snprintf(msg, ##__VA_ARGS__); \
139 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output); \
140 } while (0)
141
142#if (PHYDM_DBGPRINT == 1)
143#define PHYDM_SNPRINTF(msg, ...) \
144 do { \
145 snprintf(msg, ##__VA_ARGS__); \
146 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output); \
147 } while (0)
148#else
149#define PHYDM_SNPRINTF(msg, ...) \
150 do { \
151 if (out_len > used) \
152 used += snprintf(msg, ##__VA_ARGS__); \
153 } while (0)
154#endif
155
156void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
157 u32 *_out_len);
158s32 phydm_cmd(struct phy_dm_struct *dm, char *input, u32 in_len, u8 flag,
159 char *output, u32 out_len);
160void phydm_cmd_parser(struct phy_dm_struct *dm, char input[][16], u32 input_num,
161 u8 flag, char *output, u32 out_len);
162
163bool phydm_api_trx_mode(struct phy_dm_struct *dm, enum odm_rf_path tx_path,
164 enum odm_rf_path rx_path, bool is_tx2_path);
165
166void phydm_fw_trace_en_h2c(void *dm_void, bool enable, u32 fw_debug_component,
167 u32 monitor_mode, u32 macid);
168
169void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
170
171void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
172
173void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
174
175#endif /* __ODM_DBG_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/phydm_dfs.h b/drivers/staging/rtlwifi/phydm/phydm_dfs.h
new file mode 100644
index 000000000000..59a1d08cf381
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_dfs.h
@@ -0,0 +1,59 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDM_DFS_H__
27#define __PHYDM_DFS_H__
28
29#define DFS_VERSION "0.0"
30
31/* ============================================================
32 * Definition
33 * ============================================================
34 */
35
36/* ============================================================
37 * 1 structure
38 * ============================================================
39 */
40
41/* ============================================================
42 * enumeration
43 * ============================================================
44 */
45
46enum phydm_dfs_region_domain {
47 PHYDM_DFS_DOMAIN_UNKNOWN = 0,
48 PHYDM_DFS_DOMAIN_FCC = 1,
49 PHYDM_DFS_DOMAIN_MKK = 2,
50 PHYDM_DFS_DOMAIN_ETSI = 3,
51};
52
53/* ============================================================
54 * function prototype
55 * ============================================================
56 */
57#define phydm_dfs_master_enabled(dm) false
58
59#endif /*#ifndef __PHYDM_DFS_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/phydm_dig.c b/drivers/staging/rtlwifi/phydm/phydm_dig.c
new file mode 100644
index 000000000000..31a4f3fcad19
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_dig.c
@@ -0,0 +1,1535 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31
32static int get_igi_for_diff(int);
33
34static inline void phydm_check_ap_write_dig(struct phy_dm_struct *dm,
35 u8 current_igi)
36{
37 switch (*dm->one_path_cca) {
38 case ODM_CCA_2R:
39 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm),
40 current_igi);
41
42 if (dm->rf_type > ODM_1T1R)
43 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm),
44 current_igi);
45 break;
46 case ODM_CCA_1R_A:
47 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm),
48 current_igi);
49 if (dm->rf_type != ODM_1T1R)
50 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm),
51 get_igi_for_diff(current_igi));
52 break;
53 case ODM_CCA_1R_B:
54 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm),
55 get_igi_for_diff(current_igi));
56 if (dm->rf_type != ODM_1T1R)
57 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm),
58 current_igi);
59 break;
60 }
61}
62
63static inline u8 phydm_get_current_igi(u8 dig_max_of_min, u8 rssi_min,
64 u8 current_igi)
65{
66 if (rssi_min < dig_max_of_min) {
67 if (current_igi < rssi_min)
68 return rssi_min;
69 } else {
70 if (current_igi < dig_max_of_min)
71 return dig_max_of_min;
72 }
73 return current_igi;
74}
75
76void odm_change_dynamic_init_gain_thresh(void *dm_void, u32 dm_type,
77 u32 dm_value)
78{
79 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
80 struct dig_thres *dig_tab = &dm->dm_dig_table;
81
82 if (dm_type == DIG_TYPE_THRESH_HIGH) {
83 dig_tab->rssi_high_thresh = dm_value;
84 } else if (dm_type == DIG_TYPE_THRESH_LOW) {
85 dig_tab->rssi_low_thresh = dm_value;
86 } else if (dm_type == DIG_TYPE_ENABLE) {
87 dig_tab->dig_enable_flag = true;
88 } else if (dm_type == DIG_TYPE_DISABLE) {
89 dig_tab->dig_enable_flag = false;
90 } else if (dm_type == DIG_TYPE_BACKOFF) {
91 if (dm_value > 30)
92 dm_value = 30;
93 dig_tab->backoff_val = (u8)dm_value;
94 } else if (dm_type == DIG_TYPE_RX_GAIN_MIN) {
95 if (dm_value == 0)
96 dm_value = 0x1;
97 dig_tab->rx_gain_range_min = (u8)dm_value;
98 } else if (dm_type == DIG_TYPE_RX_GAIN_MAX) {
99 if (dm_value > 0x50)
100 dm_value = 0x50;
101 dig_tab->rx_gain_range_max = (u8)dm_value;
102 }
103} /* dm_change_dynamic_init_gain_thresh */
104
105static int get_igi_for_diff(int value_IGI)
106{
107#define ONERCCA_LOW_TH 0x30
108#define ONERCCA_LOW_DIFF 8
109
110 if (value_IGI < ONERCCA_LOW_TH) {
111 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
112 return ONERCCA_LOW_TH;
113 else
114 return value_IGI + ONERCCA_LOW_DIFF;
115 }
116
117 return value_IGI;
118}
119
120static void odm_fa_threshold_check(void *dm_void, bool is_dfs_band,
121 bool is_performance, u32 rx_tp, u32 tx_tp,
122 u32 *dm_FA_thres)
123{
124 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
125
126 if (dm->is_linked && (is_performance || is_dfs_band)) {
127 /*For NIC*/
128 dm_FA_thres[0] = DM_DIG_FA_TH0;
129 dm_FA_thres[1] = DM_DIG_FA_TH1;
130 dm_FA_thres[2] = DM_DIG_FA_TH2;
131 } else {
132 if (is_dfs_band) {
133 /* For DFS band and no link */
134 dm_FA_thres[0] = 250;
135 dm_FA_thres[1] = 1000;
136 dm_FA_thres[2] = 2000;
137 } else {
138 dm_FA_thres[0] = 2000;
139 dm_FA_thres[1] = 4000;
140 dm_FA_thres[2] = 5000;
141 }
142 }
143}
144
145static u8 odm_forbidden_igi_check(void *dm_void, u8 dig_dynamic_min,
146 u8 current_igi)
147{
148 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
149 struct dig_thres *dig_tab = &dm->dm_dig_table;
150 struct false_alarm_stat *fa_cnt =
151 (struct false_alarm_stat *)phydm_get_structure(
152 dm, PHYDM_FALSEALMCNT);
153 u8 rx_gain_range_min = dig_tab->rx_gain_range_min;
154
155 if (dig_tab->large_fa_timeout) {
156 if (--dig_tab->large_fa_timeout == 0)
157 dig_tab->large_fa_hit = 0;
158 }
159
160 if (fa_cnt->cnt_all > 10000) {
161 ODM_RT_TRACE(dm, ODM_COMP_DIG,
162 "%s(): Abnormally false alarm case.\n", __func__);
163
164 if (dig_tab->large_fa_hit != 3)
165 dig_tab->large_fa_hit++;
166
167 if (dig_tab->forbidden_igi < current_igi) {
168 dig_tab->forbidden_igi = current_igi;
169 dig_tab->large_fa_hit = 1;
170 dig_tab->large_fa_timeout = LARGE_FA_TIMEOUT;
171 }
172
173 if (dig_tab->large_fa_hit >= 3) {
174 if ((dig_tab->forbidden_igi + 2) >
175 dig_tab->rx_gain_range_max)
176 rx_gain_range_min = dig_tab->rx_gain_range_max;
177 else
178 rx_gain_range_min =
179 (dig_tab->forbidden_igi + 2);
180 dig_tab->recover_cnt = 1800;
181 ODM_RT_TRACE(
182 dm, ODM_COMP_DIG,
183 "%s(): Abnormally false alarm case: recover_cnt = %d\n",
184 __func__, dig_tab->recover_cnt);
185 }
186 }
187
188 else if (fa_cnt->cnt_all > 2000) {
189 ODM_RT_TRACE(dm, ODM_COMP_DIG,
190 "Abnormally false alarm case.\n");
191 ODM_RT_TRACE(
192 dm, ODM_COMP_DIG,
193 "cnt_all=%d, cnt_all_pre=%d, current_igi=0x%x, pre_ig_value=0x%x\n",
194 fa_cnt->cnt_all, fa_cnt->cnt_all_pre, current_igi,
195 dig_tab->pre_ig_value);
196
197 /* fa_cnt->cnt_all = 1.1875*fa_cnt->cnt_all_pre */
198 if ((fa_cnt->cnt_all >
199 (fa_cnt->cnt_all_pre + (fa_cnt->cnt_all_pre >> 3) +
200 (fa_cnt->cnt_all_pre >> 4))) &&
201 (current_igi < dig_tab->pre_ig_value)) {
202 if (dig_tab->large_fa_hit != 3)
203 dig_tab->large_fa_hit++;
204
205 if (dig_tab->forbidden_igi < current_igi) {
206 ODM_RT_TRACE(
207 dm, ODM_COMP_DIG,
208 "Updating forbidden_igi by current_igi, forbidden_igi=0x%x, current_igi=0x%x\n",
209 dig_tab->forbidden_igi, current_igi);
210
211 dig_tab->forbidden_igi = current_igi;
212 dig_tab->large_fa_hit = 1;
213 dig_tab->large_fa_timeout = LARGE_FA_TIMEOUT;
214 }
215 }
216
217 if (dig_tab->large_fa_hit >= 3) {
218 ODM_RT_TRACE(
219 dm, ODM_COMP_DIG,
220 "FaHit is greater than 3, rx_gain_range_max=0x%x, rx_gain_range_min=0x%x, forbidden_igi=0x%x\n",
221 dig_tab->rx_gain_range_max, rx_gain_range_min,
222 dig_tab->forbidden_igi);
223
224 if ((dig_tab->forbidden_igi + 1) >
225 dig_tab->rx_gain_range_max)
226 rx_gain_range_min = dig_tab->rx_gain_range_max;
227 else
228 rx_gain_range_min =
229 (dig_tab->forbidden_igi + 1);
230
231 dig_tab->recover_cnt = 1200;
232 ODM_RT_TRACE(
233 dm, ODM_COMP_DIG,
234 "Abnormally false alarm case: recover_cnt = %d, rx_gain_range_min = 0x%x\n",
235 dig_tab->recover_cnt, rx_gain_range_min);
236 }
237 } else {
238 if (dig_tab->recover_cnt != 0) {
239 dig_tab->recover_cnt--;
240 ODM_RT_TRACE(dm, ODM_COMP_DIG,
241 "%s(): Normal Case: recover_cnt = %d\n",
242 __func__, dig_tab->recover_cnt);
243 return rx_gain_range_min;
244 }
245
246 if (dig_tab->large_fa_hit >= 3) {
247 dig_tab->large_fa_hit = 0;
248 return rx_gain_range_min;
249 }
250
251 if ((dig_tab->forbidden_igi - 2) <
252 dig_dynamic_min) { /* DM_DIG_MIN) */
253 dig_tab->forbidden_igi =
254 dig_dynamic_min; /* DM_DIG_MIN; */
255 rx_gain_range_min = dig_dynamic_min; /* DM_DIG_MIN; */
256 ODM_RT_TRACE(dm, ODM_COMP_DIG,
257 "%s(): Normal Case: At Lower Bound\n",
258 __func__);
259 } else {
260 if (dig_tab->large_fa_hit == 0) {
261 dig_tab->forbidden_igi -= 2;
262 rx_gain_range_min =
263 (dig_tab->forbidden_igi + 2);
264 ODM_RT_TRACE(
265 dm, ODM_COMP_DIG,
266 "%s(): Normal Case: Approach Lower Bound\n",
267 __func__);
268 }
269 }
270 }
271
272 return rx_gain_range_min;
273}
274
275static void phydm_set_big_jump_step(void *dm_void, u8 current_igi)
276{
277 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
278 struct dig_thres *dig_tab = &dm->dm_dig_table;
279 u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
280 u8 i;
281
282 if (dig_tab->enable_adjust_big_jump == 0)
283 return;
284
285 for (i = 0; i <= dig_tab->big_jump_step1; i++) {
286 if ((current_igi + step1[i]) >
287 dig_tab->big_jump_lmt[dig_tab->agc_table_idx]) {
288 if (i != 0)
289 i = i - 1;
290 break;
291 } else if (i == dig_tab->big_jump_step1) {
292 break;
293 }
294 }
295 if (dm->support_ic_type & ODM_RTL8822B)
296 odm_set_bb_reg(dm, 0x8c8, 0xe, i);
297 else if (dm->support_ic_type & ODM_RTL8197F)
298 odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
299
300 ODM_RT_TRACE(dm, ODM_COMP_DIG,
301 "%s(): bigjump = %d (ori = 0x%x), LMT=0x%x\n", __func__, i,
302 dig_tab->big_jump_step1,
303 dig_tab->big_jump_lmt[dig_tab->agc_table_idx]);
304}
305
306void odm_write_dig(void *dm_void, u8 current_igi)
307{
308 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
309 struct dig_thres *dig_tab = &dm->dm_dig_table;
310
311 if (dig_tab->is_stop_dig) {
312 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Stop Writing IGI\n",
313 __func__);
314 return;
315 }
316
317 ODM_RT_TRACE(dm, ODM_COMP_DIG,
318 "%s(): ODM_REG(IGI_A,dm)=0x%x, ODM_BIT(IGI,dm)=0x%x\n",
319 __func__, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
320
321 /* 1 Check initial gain by upper bound */
322 if ((!dig_tab->is_psd_in_progress) && dm->is_linked) {
323 if (current_igi > dig_tab->rx_gain_range_max) {
324 ODM_RT_TRACE(
325 dm, ODM_COMP_DIG,
326 "%s(): current_igi(0x%02x) is larger than upper bound !!\n",
327 __func__, current_igi);
328 current_igi = dig_tab->rx_gain_range_max;
329 }
330 if (dm->support_ability & ODM_BB_ADAPTIVITY &&
331 dm->adaptivity_flag) {
332 if (current_igi > dm->adaptivity_igi_upper)
333 current_igi = dm->adaptivity_igi_upper;
334
335 ODM_RT_TRACE(
336 dm, ODM_COMP_DIG,
337 "%s(): adaptivity case: Force upper bound to 0x%x !!!!!!\n",
338 __func__, current_igi);
339 }
340 }
341
342 if (dig_tab->cur_ig_value != current_igi) {
343 /* Modify big jump step for 8822B and 8197F */
344 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F))
345 phydm_set_big_jump_step(dm, current_igi);
346
347 /* Set IGI value of CCK for new CCK AGC */
348 if (dm->cck_new_agc) {
349 if (dm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE)
350 odm_set_bb_reg(dm, 0xa0c, 0x00003f00,
351 (current_igi >> 1));
352 }
353
354 /*Add by YuChen for USB IO too slow issue*/
355 if ((dm->support_ability & ODM_BB_ADAPTIVITY) &&
356 (current_igi > dig_tab->cur_ig_value)) {
357 dig_tab->cur_ig_value = current_igi;
358 phydm_adaptivity(dm);
359 }
360
361 /* 1 Set IGI value */
362 if (dm->support_platform & (ODM_WIN | ODM_CE)) {
363 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm),
364 current_igi);
365
366 if (dm->rf_type > ODM_1T1R)
367 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm),
368 ODM_BIT(IGI, dm), current_igi);
369
370 } else if (dm->support_platform & (ODM_AP)) {
371 phydm_check_ap_write_dig(dm, current_igi);
372 }
373
374 dig_tab->cur_ig_value = current_igi;
375 }
376
377 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): current_igi(0x%02x).\n", __func__,
378 current_igi);
379}
380
381void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
382 enum phydm_pause_level pause_level, u8 igi_value)
383{
384 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
385 struct dig_thres *dig_tab = &dm->dm_dig_table;
386 s8 max_level;
387
388 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s()=========> level = %d\n", __func__,
389 pause_level);
390
391 if ((dig_tab->pause_dig_level == 0) &&
392 (!(dm->support_ability & ODM_BB_DIG) ||
393 !(dm->support_ability & ODM_BB_FA_CNT))) {
394 ODM_RT_TRACE(
395 dm, ODM_COMP_DIG,
396 "%s(): Return: support_ability DIG or FA is disabled !!\n",
397 __func__);
398 return;
399 }
400
401 if (pause_level > DM_DIG_MAX_PAUSE_TYPE) {
402 ODM_RT_TRACE(dm, ODM_COMP_DIG,
403 "%s(): Return: Wrong pause level !!\n", __func__);
404 return;
405 }
406
407 ODM_RT_TRACE(dm, ODM_COMP_DIG,
408 "%s(): pause level = 0x%x, Current value = 0x%x\n",
409 __func__, dig_tab->pause_dig_level, igi_value);
410 ODM_RT_TRACE(
411 dm, ODM_COMP_DIG,
412 "%s(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
413 __func__, dig_tab->pause_dig_value[7],
414 dig_tab->pause_dig_value[6], dig_tab->pause_dig_value[5],
415 dig_tab->pause_dig_value[4], dig_tab->pause_dig_value[3],
416 dig_tab->pause_dig_value[2], dig_tab->pause_dig_value[1],
417 dig_tab->pause_dig_value[0]);
418
419 switch (pause_type) {
420 /* Pause DIG */
421 case PHYDM_PAUSE: {
422 /* Disable DIG */
423 odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY,
424 dm->support_ability & (~ODM_BB_DIG));
425 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Pause DIG !!\n",
426 __func__);
427
428 /* Backup IGI value */
429 if (dig_tab->pause_dig_level == 0) {
430 dig_tab->igi_backup = dig_tab->cur_ig_value;
431 ODM_RT_TRACE(
432 dm, ODM_COMP_DIG,
433 "%s(): Backup IGI = 0x%x, new IGI = 0x%x\n",
434 __func__, dig_tab->igi_backup, igi_value);
435 }
436
437 /* Record IGI value */
438 dig_tab->pause_dig_value[pause_level] = igi_value;
439
440 /* Update pause level */
441 dig_tab->pause_dig_level =
442 (dig_tab->pause_dig_level | BIT(pause_level));
443
444 /* Write new IGI value */
445 if (BIT(pause_level + 1) > dig_tab->pause_dig_level) {
446 odm_write_dig(dm, igi_value);
447 ODM_RT_TRACE(dm, ODM_COMP_DIG,
448 "%s(): IGI of higher level = 0x%x\n",
449 __func__, igi_value);
450 }
451 break;
452 }
453 /* Resume DIG */
454 case PHYDM_RESUME: {
455 /* check if the level is illegal or not */
456 if ((dig_tab->pause_dig_level & (BIT(pause_level))) != 0) {
457 dig_tab->pause_dig_level = dig_tab->pause_dig_level &
458 (~(BIT(pause_level)));
459 dig_tab->pause_dig_value[pause_level] = 0;
460 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Resume DIG !!\n",
461 __func__);
462 } else {
463 ODM_RT_TRACE(dm, ODM_COMP_DIG,
464 "%s(): Wrong resume level !!\n", __func__);
465 break;
466 }
467
468 /* Resume DIG */
469 if (dig_tab->pause_dig_level == 0) {
470 /* Write backup IGI value */
471 odm_write_dig(dm, dig_tab->igi_backup);
472 dig_tab->is_ignore_dig = true;
473 ODM_RT_TRACE(dm, ODM_COMP_DIG,
474 "%s(): Write original IGI = 0x%x\n",
475 __func__, dig_tab->igi_backup);
476
477 /* Enable DIG */
478 odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY,
479 dm->support_ability | ODM_BB_DIG);
480 break;
481 }
482
483 if (BIT(pause_level) <= dig_tab->pause_dig_level)
484 break;
485
486 /* Calculate the maximum level now */
487 for (max_level = (pause_level - 1); max_level >= 0;
488 max_level--) {
489 if ((dig_tab->pause_dig_level & BIT(max_level)) > 0)
490 break;
491 }
492
493 /* write IGI of lower level */
494 odm_write_dig(dm, dig_tab->pause_dig_value[max_level]);
495 ODM_RT_TRACE(dm, ODM_COMP_DIG,
496 "%s(): Write IGI (0x%x) of level (%d)\n", __func__,
497 dig_tab->pause_dig_value[max_level], max_level);
498 break;
499 }
500 default:
501 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Wrong type !!\n",
502 __func__);
503 break;
504 }
505
506 ODM_RT_TRACE(dm, ODM_COMP_DIG,
507 "%s(): pause level = 0x%x, Current value = 0x%x\n",
508 __func__, dig_tab->pause_dig_level, igi_value);
509 ODM_RT_TRACE(
510 dm, ODM_COMP_DIG,
511 "%s(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
512 __func__, dig_tab->pause_dig_value[7],
513 dig_tab->pause_dig_value[6], dig_tab->pause_dig_value[5],
514 dig_tab->pause_dig_value[4], dig_tab->pause_dig_value[3],
515 dig_tab->pause_dig_value[2], dig_tab->pause_dig_value[1],
516 dig_tab->pause_dig_value[0]);
517}
518
519static bool odm_dig_abort(void *dm_void)
520{
521 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
522 struct dig_thres *dig_tab = &dm->dm_dig_table;
523
524 /* support_ability */
525 if (!(dm->support_ability & ODM_BB_FA_CNT)) {
526 ODM_RT_TRACE(
527 dm, ODM_COMP_DIG,
528 "%s(): Return: support_ability ODM_BB_FA_CNT is disabled\n",
529 __func__);
530 return true;
531 }
532
533 /* support_ability */
534 if (!(dm->support_ability & ODM_BB_DIG)) {
535 ODM_RT_TRACE(
536 dm, ODM_COMP_DIG,
537 "%s(): Return: support_ability ODM_BB_DIG is disabled\n",
538 __func__);
539 return true;
540 }
541
542 /* ScanInProcess */
543 if (*dm->is_scan_in_process) {
544 ODM_RT_TRACE(dm, ODM_COMP_DIG,
545 "%s(): Return: In Scan Progress\n", __func__);
546 return true;
547 }
548
549 if (dig_tab->is_ignore_dig) {
550 dig_tab->is_ignore_dig = false;
551 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Return: Ignore DIG\n",
552 __func__);
553 return true;
554 }
555
556 /* add by Neil Chen to avoid PSD is processing */
557 if (!dm->is_dm_initial_gain_enable) {
558 ODM_RT_TRACE(dm, ODM_COMP_DIG,
559 "%s(): Return: PSD is Processing\n", __func__);
560 return true;
561 }
562
563 return false;
564}
565
566void odm_dig_init(void *dm_void)
567{
568 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
569 struct dig_thres *dig_tab = &dm->dm_dig_table;
570 u32 ret_value;
571 u8 i;
572
573 dig_tab->is_stop_dig = false;
574 dig_tab->is_ignore_dig = false;
575 dig_tab->is_psd_in_progress = false;
576 dig_tab->cur_ig_value =
577 (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
578 dig_tab->pre_ig_value = 0;
579 dig_tab->rssi_low_thresh = DM_DIG_THRESH_LOW;
580 dig_tab->rssi_high_thresh = DM_DIG_THRESH_HIGH;
581 dig_tab->fa_low_thresh = DM_FALSEALARM_THRESH_LOW;
582 dig_tab->fa_high_thresh = DM_FALSEALARM_THRESH_HIGH;
583 dig_tab->backoff_val = DM_DIG_BACKOFF_DEFAULT;
584 dig_tab->backoff_val_range_max = DM_DIG_BACKOFF_MAX;
585 dig_tab->backoff_val_range_min = DM_DIG_BACKOFF_MIN;
586 dig_tab->pre_cck_cca_thres = 0xFF;
587 dig_tab->cur_cck_cca_thres = 0x83;
588 dig_tab->forbidden_igi = DM_DIG_MIN_NIC;
589 dig_tab->large_fa_hit = 0;
590 dig_tab->large_fa_timeout = 0;
591 dig_tab->recover_cnt = 0;
592 dig_tab->is_media_connect_0 = false;
593 dig_tab->is_media_connect_1 = false;
594
595 /*To initialize dm->is_dm_initial_gain_enable==false to avoid DIG err*/
596 dm->is_dm_initial_gain_enable = true;
597
598 dig_tab->dig_dynamic_min_0 = DM_DIG_MIN_NIC;
599 dig_tab->dig_dynamic_min_1 = DM_DIG_MIN_NIC;
600
601 /* To Initi BT30 IGI */
602 dig_tab->bt30_cur_igi = 0x32;
603
604 odm_memory_set(dm, dig_tab->pause_dig_value, 0,
605 (DM_DIG_MAX_PAUSE_TYPE + 1));
606 dig_tab->pause_dig_level = 0;
607 odm_memory_set(dm, dig_tab->pause_cckpd_value, 0,
608 (DM_DIG_MAX_PAUSE_TYPE + 1));
609 dig_tab->pause_cckpd_level = 0;
610
611 if (dm->board_type & (ODM_BOARD_EXT_PA | ODM_BOARD_EXT_LNA)) {
612 dig_tab->rx_gain_range_max = DM_DIG_MAX_NIC;
613 dig_tab->rx_gain_range_min = DM_DIG_MIN_NIC;
614 } else {
615 dig_tab->rx_gain_range_max = DM_DIG_MAX_NIC;
616 dig_tab->rx_gain_range_min = DM_DIG_MIN_NIC;
617 }
618
619 dig_tab->enable_adjust_big_jump = 1;
620 if (dm->support_ic_type & ODM_RTL8822B) {
621 ret_value = odm_get_bb_reg(dm, 0x8c8, MASKLWORD);
622 dig_tab->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
623 dig_tab->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
624 dig_tab->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
625
626 } else if (dm->support_ic_type & ODM_RTL8197F) {
627 ret_value =
628 odm_get_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, MASKLWORD);
629 dig_tab->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
630 dig_tab->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
631 dig_tab->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
632 }
633 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) {
634 for (i = 0; i < sizeof(dig_tab->big_jump_lmt); i++) {
635 if (dig_tab->big_jump_lmt[i] == 0)
636 dig_tab->big_jump_lmt[i] =
637 0x64; /* Set -10dBm as default value */
638 }
639 }
640}
641
642void odm_DIG(void *dm_void)
643{
644 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
645
646 /* Common parameters */
647 struct dig_thres *dig_tab = &dm->dm_dig_table;
648 struct false_alarm_stat *fa_cnt =
649 (struct false_alarm_stat *)phydm_get_structure(
650 dm, PHYDM_FALSEALMCNT);
651 bool first_connect, first_dis_connect;
652 u8 dig_max_of_min, dig_dynamic_min;
653 u8 dm_dig_max, dm_dig_min;
654 u8 current_igi = dig_tab->cur_ig_value;
655 u8 offset;
656 u32 dm_FA_thres[3];
657 u32 tx_tp = 0, rx_tp = 0;
658 bool is_dfs_band = false;
659 bool is_performance = true, is_first_tp_target = false,
660 is_first_coverage = false;
661
662 if (odm_dig_abort(dm))
663 return;
664
665 ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG Start===>\n");
666
667 /* 1 Update status */
668 {
669 dig_dynamic_min = dig_tab->dig_dynamic_min_0;
670 first_connect = (dm->is_linked) && !dig_tab->is_media_connect_0;
671 first_dis_connect =
672 (!dm->is_linked) && dig_tab->is_media_connect_0;
673 }
674
675 /* 1 Boundary Decision */
676 {
677 /* 2 For WIN\CE */
678 if (dm->support_ic_type >= ODM_RTL8188E)
679 dm_dig_max = 0x5A;
680 else
681 dm_dig_max = DM_DIG_MAX_NIC;
682
683 if (dm->support_ic_type != ODM_RTL8821)
684 dm_dig_min = DM_DIG_MIN_NIC;
685 else
686 dm_dig_min = 0x1C;
687
688 dig_max_of_min = DM_DIG_MAX_AP;
689
690 /* Modify lower bound for DFS band */
691 if ((((*dm->channel >= 52) && (*dm->channel <= 64)) ||
692 ((*dm->channel >= 100) && (*dm->channel <= 140))) &&
693 phydm_dfs_master_enabled(dm)) {
694 is_dfs_band = true;
695 if (*dm->band_width == ODM_BW20M)
696 dm_dig_min = DM_DIG_MIN_AP_DFS + 2;
697 else
698 dm_dig_min = DM_DIG_MIN_AP_DFS;
699 ODM_RT_TRACE(dm, ODM_COMP_DIG,
700 "DIG: ====== In DFS band ======\n");
701 }
702 }
703 ODM_RT_TRACE(dm, ODM_COMP_DIG,
704 "DIG: Absolutly upper bound = 0x%x, lower bound = 0x%x\n",
705 dm_dig_max, dm_dig_min);
706
707 if (dm->pu1_forced_igi_lb && (*dm->pu1_forced_igi_lb > 0)) {
708 ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG: Force IGI lb to: 0x%02x\n",
709 *dm->pu1_forced_igi_lb);
710 dm_dig_min = *dm->pu1_forced_igi_lb;
711 dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) :
712 (dm_dig_min + 1);
713 }
714
715 /* 1 Adjust boundary by RSSI */
716 if (dm->is_linked && is_performance) {
717 /* 2 Modify DIG upper bound */
718 /* 4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT */
719 if ((dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8723B |
720 ODM_RTL8812 | ODM_RTL8821)) &&
721 (dm->is_bt_limited_dig == 1)) {
722 offset = 10;
723 ODM_RT_TRACE(
724 dm, ODM_COMP_DIG,
725 "DIG: Coex. case: Force upper bound to RSSI + %d\n",
726 offset);
727 } else {
728 offset = 15;
729 }
730
731 if ((dm->rssi_min + offset) > dm_dig_max)
732 dig_tab->rx_gain_range_max = dm_dig_max;
733 else if ((dm->rssi_min + offset) < dm_dig_min)
734 dig_tab->rx_gain_range_max = dm_dig_min;
735 else
736 dig_tab->rx_gain_range_max = dm->rssi_min + offset;
737
738 /* 2 Modify DIG lower bound */
739 /* if(dm->is_one_entry_only) */
740 {
741 if (dm->rssi_min < dm_dig_min)
742 dig_dynamic_min = dm_dig_min;
743 else if (dm->rssi_min > dig_max_of_min)
744 dig_dynamic_min = dig_max_of_min;
745 else
746 dig_dynamic_min = dm->rssi_min;
747
748 if (is_dfs_band) {
749 dig_dynamic_min = dm_dig_min;
750 ODM_RT_TRACE(
751 dm, ODM_COMP_DIG,
752 "DIG: DFS band: Force lower bound to 0x%x after link\n",
753 dm_dig_min);
754 }
755 }
756 } else {
757 if (is_performance && is_dfs_band) {
758 dig_tab->rx_gain_range_max = 0x28;
759 ODM_RT_TRACE(
760 dm, ODM_COMP_DIG,
761 "DIG: DFS band: Force upper bound to 0x%x before link\n",
762 dig_tab->rx_gain_range_max);
763 } else {
764 if (is_performance)
765 dig_tab->rx_gain_range_max = DM_DIG_MAX_OF_MIN;
766 else
767 dig_tab->rx_gain_range_max = dm_dig_max;
768 }
769 dig_dynamic_min = dm_dig_min;
770 }
771
772 /* 1 Force Lower Bound for AntDiv */
773 if (dm->is_linked && !dm->is_one_entry_only &&
774 (dm->support_ic_type & ODM_ANTDIV_SUPPORT) &&
775 (dm->support_ability & ODM_BB_ANT_DIV)) {
776 if (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
777 dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
778 if (dig_tab->ant_div_rssi_max > dig_max_of_min)
779 dig_dynamic_min = dig_max_of_min;
780 else
781 dig_dynamic_min = (u8)dig_tab->ant_div_rssi_max;
782 ODM_RT_TRACE(
783 dm, ODM_COMP_DIG,
784 "DIG: AntDiv case: Force lower bound to 0x%x\n",
785 dig_dynamic_min);
786 ODM_RT_TRACE(dm, ODM_COMP_DIG,
787 "DIG: AntDiv case: rssi_max = 0x%x\n",
788 dig_tab->ant_div_rssi_max);
789 }
790 }
791 ODM_RT_TRACE(
792 dm, ODM_COMP_DIG,
793 "DIG: Adjust boundary by RSSI Upper bound = 0x%x, Lower bound = 0x%x\n",
794 dig_tab->rx_gain_range_max, dig_dynamic_min);
795 ODM_RT_TRACE(
796 dm, ODM_COMP_DIG,
797 "DIG: Link status: is_linked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n",
798 dm->is_linked, dm->rssi_min, first_connect, first_dis_connect);
799
800 /* 1 Modify DIG lower bound, deal with abnormal case */
801 /* 2 Abnormal false alarm case */
802 if (is_dfs_band) {
803 dig_tab->rx_gain_range_min = dig_dynamic_min;
804 } else {
805 if (!dm->is_linked) {
806 dig_tab->rx_gain_range_min = dig_dynamic_min;
807
808 if (first_dis_connect)
809 dig_tab->forbidden_igi = dig_dynamic_min;
810 } else {
811 dig_tab->rx_gain_range_min = odm_forbidden_igi_check(
812 dm, dig_dynamic_min, current_igi);
813 }
814 }
815
816 /* 2 Abnormal # beacon case */
817 if (dm->is_linked && !first_connect) {
818 ODM_RT_TRACE(dm, ODM_COMP_DIG, "Beacon Num (%d)\n",
819 dm->phy_dbg_info.num_qry_beacon_pkt);
820 if ((dm->phy_dbg_info.num_qry_beacon_pkt < 5) &&
821 (dm->bsta_state)) {
822 dig_tab->rx_gain_range_min = 0x1c;
823 ODM_RT_TRACE(
824 dm, ODM_COMP_DIG,
825 "DIG: Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x\n",
826 dm->phy_dbg_info.num_qry_beacon_pkt,
827 dig_tab->rx_gain_range_min);
828 }
829 }
830
831 /* 2 Abnormal lower bound case */
832 if (dig_tab->rx_gain_range_min > dig_tab->rx_gain_range_max) {
833 dig_tab->rx_gain_range_min = dig_tab->rx_gain_range_max;
834 ODM_RT_TRACE(
835 dm, ODM_COMP_DIG,
836 "DIG: Abnrormal lower bound case: Force lower bound to 0x%x\n",
837 dig_tab->rx_gain_range_min);
838 }
839
840 /* 1 False alarm threshold decision */
841 odm_fa_threshold_check(dm, is_dfs_band, is_performance, rx_tp, tx_tp,
842 dm_FA_thres);
843 ODM_RT_TRACE(dm, ODM_COMP_DIG,
844 "DIG: False alarm threshold = %d, %d, %d\n",
845 dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2]);
846
847 /* 1 Adjust initial gain by false alarm */
848 if (dm->is_linked && is_performance) {
849 /* 2 After link */
850 ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG: Adjust IGI after link\n");
851
852 if (is_first_tp_target || (first_connect && is_performance)) {
853 dig_tab->large_fa_hit = 0;
854
855 if (is_dfs_band) {
856 u8 rssi = dm->rssi_min;
857
858 current_igi =
859 (dm->rssi_min > 0x28) ? 0x28 : rssi;
860 ODM_RT_TRACE(
861 dm, ODM_COMP_DIG,
862 "DIG: DFS band: One-shot to 0x28 upmost\n");
863 } else {
864 current_igi = phydm_get_current_igi(
865 dig_max_of_min, dm->rssi_min,
866 current_igi);
867 }
868
869 ODM_RT_TRACE(
870 dm, ODM_COMP_DIG,
871 "DIG: First connect case: IGI does on-shot to 0x%x\n",
872 current_igi);
873
874 } else {
875 if (fa_cnt->cnt_all > dm_FA_thres[2])
876 current_igi = current_igi + 4;
877 else if (fa_cnt->cnt_all > dm_FA_thres[1])
878 current_igi = current_igi + 2;
879 else if (fa_cnt->cnt_all < dm_FA_thres[0])
880 current_igi = current_igi - 2;
881
882 /* 4 Abnormal # beacon case */
883 if ((dm->phy_dbg_info.num_qry_beacon_pkt < 5) &&
884 (fa_cnt->cnt_all < DM_DIG_FA_TH1) &&
885 (dm->bsta_state)) {
886 current_igi = dig_tab->rx_gain_range_min;
887 ODM_RT_TRACE(
888 dm, ODM_COMP_DIG,
889 "DIG: Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n",
890 dm->phy_dbg_info.num_qry_beacon_pkt,
891 current_igi);
892 }
893 }
894 } else {
895 /* 2 Before link */
896 ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG: Adjust IGI before link\n");
897
898 if (first_dis_connect || is_first_coverage) {
899 current_igi = dm_dig_min;
900 ODM_RT_TRACE(
901 dm, ODM_COMP_DIG,
902 "DIG: First disconnect case: IGI does on-shot to lower bound\n");
903 } else {
904 if (fa_cnt->cnt_all > dm_FA_thres[2])
905 current_igi = current_igi + 4;
906 else if (fa_cnt->cnt_all > dm_FA_thres[1])
907 current_igi = current_igi + 2;
908 else if (fa_cnt->cnt_all < dm_FA_thres[0])
909 current_igi = current_igi - 2;
910 }
911 }
912
913 /* 1 Check initial gain by upper/lower bound */
914 if (current_igi < dig_tab->rx_gain_range_min)
915 current_igi = dig_tab->rx_gain_range_min;
916
917 if (current_igi > dig_tab->rx_gain_range_max)
918 current_igi = dig_tab->rx_gain_range_max;
919
920 ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG: cur_ig_value=0x%x, TotalFA = %d\n",
921 current_igi, fa_cnt->cnt_all);
922
923 /* 1 Update status */
924 if (dm->is_bt_hs_operation) {
925 if (dm->is_linked) {
926 if (dig_tab->bt30_cur_igi > (current_igi))
927 odm_write_dig(dm, current_igi);
928 else
929 odm_write_dig(dm, dig_tab->bt30_cur_igi);
930
931 dig_tab->is_media_connect_0 = dm->is_linked;
932 dig_tab->dig_dynamic_min_0 = dig_dynamic_min;
933 } else {
934 if (dm->is_link_in_process)
935 odm_write_dig(dm, 0x1c);
936 else if (dm->is_bt_connect_process)
937 odm_write_dig(dm, 0x28);
938 else
939 odm_write_dig(dm, dig_tab->bt30_cur_igi);
940 }
941 } else { /* BT is not using */
942 odm_write_dig(dm, current_igi);
943 dig_tab->is_media_connect_0 = dm->is_linked;
944 dig_tab->dig_dynamic_min_0 = dig_dynamic_min;
945 }
946 ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG end\n");
947}
948
949void odm_dig_by_rssi_lps(void *dm_void)
950{
951 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
952 struct false_alarm_stat *fa_cnt =
953 (struct false_alarm_stat *)phydm_get_structure(
954 dm, PHYDM_FALSEALMCNT);
955
956 u8 rssi_lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */
957 u8 current_igi = dm->rssi_min;
958
959 if (odm_dig_abort(dm))
960 return;
961
962 current_igi = current_igi + RSSI_OFFSET_DIG;
963
964 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s()==>\n", __func__);
965
966 /* Using FW PS mode to make IGI */
967 /* Adjust by FA in LPS MODE */
968 if (fa_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
969 current_igi = current_igi + 4;
970 else if (fa_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
971 current_igi = current_igi + 2;
972 else if (fa_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
973 current_igi = current_igi - 2;
974
975 /* Lower bound checking */
976
977 /* RSSI Lower bound check */
978 if ((dm->rssi_min - 10) > DM_DIG_MIN_NIC)
979 rssi_lower = (dm->rssi_min - 10);
980 else
981 rssi_lower = DM_DIG_MIN_NIC;
982
983 /* Upper and Lower Bound checking */
984 if (current_igi > DM_DIG_MAX_NIC)
985 current_igi = DM_DIG_MAX_NIC;
986 else if (current_igi < rssi_lower)
987 current_igi = rssi_lower;
988
989 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): fa_cnt->cnt_all = %d\n", __func__,
990 fa_cnt->cnt_all);
991 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): dm->rssi_min = %d\n", __func__,
992 dm->rssi_min);
993 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): current_igi = 0x%x\n", __func__,
994 current_igi);
995
996 odm_write_dig(
997 dm,
998 current_igi); /* odm_write_dig(dm, dig_tab->cur_ig_value); */
999}
1000
1001/* 3============================================================
1002 * 3 FASLE ALARM CHECK
1003 * 3============================================================
1004 */
1005
1006void odm_false_alarm_counter_statistics(void *dm_void)
1007{
1008 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1009 struct false_alarm_stat *false_alm_cnt =
1010 (struct false_alarm_stat *)phydm_get_structure(
1011 dm, PHYDM_FALSEALMCNT);
1012 struct rt_adcsmp *adc_smp = &dm->adcsmp;
1013 u32 ret_value;
1014
1015 if (!(dm->support_ability & ODM_BB_FA_CNT))
1016 return;
1017
1018 ODM_RT_TRACE(dm, ODM_COMP_FA_CNT, "%s()======>\n", __func__);
1019
1020 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1021 /* hold ofdm counter */
1022 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31),
1023 1); /* hold page C counter */
1024 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31),
1025 1); /* hold page D counter */
1026
1027 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N,
1028 MASKDWORD);
1029 false_alm_cnt->cnt_fast_fsync = (ret_value & 0xffff);
1030 false_alm_cnt->cnt_sb_search_fail =
1031 ((ret_value & 0xffff0000) >> 16);
1032
1033 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N,
1034 MASKDWORD);
1035 false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff);
1036 false_alm_cnt->cnt_parity_fail =
1037 ((ret_value & 0xffff0000) >> 16);
1038
1039 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N,
1040 MASKDWORD);
1041 false_alm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
1042 false_alm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
1043
1044 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N,
1045 MASKDWORD);
1046 false_alm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
1047
1048 false_alm_cnt->cnt_ofdm_fail =
1049 false_alm_cnt->cnt_parity_fail +
1050 false_alm_cnt->cnt_rate_illegal +
1051 false_alm_cnt->cnt_crc8_fail +
1052 false_alm_cnt->cnt_mcs_fail +
1053 false_alm_cnt->cnt_fast_fsync +
1054 false_alm_cnt->cnt_sb_search_fail;
1055
1056 /* read CCK CRC32 counter */
1057 false_alm_cnt->cnt_cck_crc32_error = odm_get_bb_reg(
1058 dm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, MASKDWORD);
1059 false_alm_cnt->cnt_cck_crc32_ok = odm_get_bb_reg(
1060 dm, ODM_REG_CCK_CRC32_OK_CNT_11N, MASKDWORD);
1061
1062 /* read OFDM CRC32 counter */
1063 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N,
1064 MASKDWORD);
1065 false_alm_cnt->cnt_ofdm_crc32_error =
1066 (ret_value & 0xffff0000) >> 16;
1067 false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff;
1068
1069 /* read HT CRC32 counter */
1070 ret_value =
1071 odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
1072 false_alm_cnt->cnt_ht_crc32_error =
1073 (ret_value & 0xffff0000) >> 16;
1074 false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff;
1075
1076 /* read VHT CRC32 counter */
1077 false_alm_cnt->cnt_vht_crc32_error = 0;
1078 false_alm_cnt->cnt_vht_crc32_ok = 0;
1079
1080 {
1081 /* hold cck counter */
1082 odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
1083 odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
1084
1085 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N,
1086 MASKBYTE0);
1087 false_alm_cnt->cnt_cck_fail = ret_value;
1088
1089 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N,
1090 MASKBYTE3);
1091 false_alm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
1092
1093 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N,
1094 MASKDWORD);
1095 false_alm_cnt->cnt_cck_cca =
1096 ((ret_value & 0xFF) << 8) |
1097 ((ret_value & 0xFF00) >> 8);
1098 }
1099
1100 false_alm_cnt->cnt_all_pre = false_alm_cnt->cnt_all;
1101
1102 false_alm_cnt->cnt_all = (false_alm_cnt->cnt_fast_fsync +
1103 false_alm_cnt->cnt_sb_search_fail +
1104 false_alm_cnt->cnt_parity_fail +
1105 false_alm_cnt->cnt_rate_illegal +
1106 false_alm_cnt->cnt_crc8_fail +
1107 false_alm_cnt->cnt_mcs_fail +
1108 false_alm_cnt->cnt_cck_fail);
1109
1110 false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca +
1111 false_alm_cnt->cnt_cck_cca;
1112
1113 if (dm->support_ic_type >= ODM_RTL8188E) {
1114 /*reset false alarm counter registers*/
1115 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31),
1116 1);
1117 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31),
1118 0);
1119 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27),
1120 1);
1121 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27),
1122 0);
1123
1124 /*update ofdm counter*/
1125 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31),
1126 0); /*update page C counter*/
1127 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31),
1128 0); /*update page D counter*/
1129
1130 /*reset CCK CCA counter*/
1131 odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N,
1132 BIT(13) | BIT(12), 0);
1133 odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N,
1134 BIT(13) | BIT(12), 2);
1135
1136 /*reset CCK FA counter*/
1137 odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N,
1138 BIT(15) | BIT(14), 0);
1139 odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N,
1140 BIT(15) | BIT(14), 2);
1141
1142 /*reset CRC32 counter*/
1143 odm_set_bb_reg(dm, ODM_REG_PAGE_F_RST_11N, BIT(16), 1);
1144 odm_set_bb_reg(dm, ODM_REG_PAGE_F_RST_11N, BIT(16), 0);
1145 }
1146
1147 /* Get debug port 0 */
1148 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x0);
1149 false_alm_cnt->dbg_port0 =
1150 odm_get_bb_reg(dm, ODM_REG_RPT_11N, MASKDWORD);
1151
1152 /* Get EDCCA flag */
1153 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x208);
1154 false_alm_cnt->edcca_flag =
1155 (bool)odm_get_bb_reg(dm, ODM_REG_RPT_11N, BIT(30));
1156
1157 ODM_RT_TRACE(
1158 dm, ODM_COMP_FA_CNT,
1159 "[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n",
1160 false_alm_cnt->cnt_parity_fail,
1161 false_alm_cnt->cnt_rate_illegal,
1162 false_alm_cnt->cnt_crc8_fail,
1163 false_alm_cnt->cnt_mcs_fail,
1164 false_alm_cnt->cnt_fast_fsync,
1165 false_alm_cnt->cnt_sb_search_fail);
1166 }
1167
1168 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1169 u32 cck_enable;
1170
1171 /* read OFDM FA counter */
1172 false_alm_cnt->cnt_ofdm_fail =
1173 odm_get_bb_reg(dm, ODM_REG_OFDM_FA_11AC, MASKLWORD);
1174
1175 /* Read CCK FA counter */
1176 false_alm_cnt->cnt_cck_fail =
1177 odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
1178
1179 /* read CCK/OFDM CCA counter */
1180 ret_value =
1181 odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
1182 false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
1183 false_alm_cnt->cnt_cck_cca = ret_value & 0xffff;
1184
1185 /* read CCK CRC32 counter */
1186 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC,
1187 MASKDWORD);
1188 false_alm_cnt->cnt_cck_crc32_error =
1189 (ret_value & 0xffff0000) >> 16;
1190 false_alm_cnt->cnt_cck_crc32_ok = ret_value & 0xffff;
1191
1192 /* read OFDM CRC32 counter */
1193 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC,
1194 MASKDWORD);
1195 false_alm_cnt->cnt_ofdm_crc32_error =
1196 (ret_value & 0xffff0000) >> 16;
1197 false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff;
1198
1199 /* read HT CRC32 counter */
1200 ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC,
1201 MASKDWORD);
1202 false_alm_cnt->cnt_ht_crc32_error =
1203 (ret_value & 0xffff0000) >> 16;
1204 false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff;
1205
1206 /* read VHT CRC32 counter */
1207 ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC,
1208 MASKDWORD);
1209 false_alm_cnt->cnt_vht_crc32_error =
1210 (ret_value & 0xffff0000) >> 16;
1211 false_alm_cnt->cnt_vht_crc32_ok = ret_value & 0xffff;
1212
1213 /* reset OFDM FA counter */
1214 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1);
1215 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0);
1216
1217 /* reset CCK FA counter */
1218 odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0);
1219 odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1);
1220
1221 /* reset CCA counter */
1222 odm_set_bb_reg(dm, ODM_REG_RST_RPT_11AC, BIT(0), 1);
1223 odm_set_bb_reg(dm, ODM_REG_RST_RPT_11AC, BIT(0), 0);
1224
1225 cck_enable =
1226 odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
1227 if (cck_enable) { /* if(*dm->band_type == ODM_BAND_2_4G) */
1228 false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail +
1229 false_alm_cnt->cnt_cck_fail;
1230 false_alm_cnt->cnt_cca_all =
1231 false_alm_cnt->cnt_cck_cca +
1232 false_alm_cnt->cnt_ofdm_cca;
1233 } else {
1234 false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail;
1235 false_alm_cnt->cnt_cca_all =
1236 false_alm_cnt->cnt_ofdm_cca;
1237 }
1238
1239 if (adc_smp->adc_smp_state == ADCSMP_STATE_IDLE) {
1240 if (phydm_set_bb_dbg_port(
1241 dm, BB_DBGPORT_PRIORITY_1,
1242 0x0)) { /*set debug port to 0x0*/
1243 false_alm_cnt->dbg_port0 =
1244 phydm_get_bb_dbg_port_value(dm);
1245 phydm_release_bb_dbg_port(dm);
1246 }
1247
1248 if (phydm_set_bb_dbg_port(
1249 dm, BB_DBGPORT_PRIORITY_1,
1250 0x209)) { /*set debug port to 0x0*/
1251 false_alm_cnt->edcca_flag =
1252 (bool)((phydm_get_bb_dbg_port_value(
1253 dm) &
1254 BIT(30)) >>
1255 30);
1256 phydm_release_bb_dbg_port(dm);
1257 }
1258 }
1259 }
1260
1261 false_alm_cnt->cnt_crc32_error_all =
1262 false_alm_cnt->cnt_vht_crc32_error +
1263 false_alm_cnt->cnt_ht_crc32_error +
1264 false_alm_cnt->cnt_ofdm_crc32_error +
1265 false_alm_cnt->cnt_cck_crc32_error;
1266 false_alm_cnt->cnt_crc32_ok_all = false_alm_cnt->cnt_vht_crc32_ok +
1267 false_alm_cnt->cnt_ht_crc32_ok +
1268 false_alm_cnt->cnt_ofdm_crc32_ok +
1269 false_alm_cnt->cnt_cck_crc32_ok;
1270
1271 ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
1272 "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1273 false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca,
1274 false_alm_cnt->cnt_cca_all);
1275
1276 ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
1277 "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1278 false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail,
1279 false_alm_cnt->cnt_all);
1280
1281 ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
1282 "[CCK] CRC32 {error, ok}= {%d, %d}\n",
1283 false_alm_cnt->cnt_cck_crc32_error,
1284 false_alm_cnt->cnt_cck_crc32_ok);
1285 ODM_RT_TRACE(dm, ODM_COMP_FA_CNT, "[OFDM]CRC32 {error, ok}= {%d, %d}\n",
1286 false_alm_cnt->cnt_ofdm_crc32_error,
1287 false_alm_cnt->cnt_ofdm_crc32_ok);
1288 ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
1289 "[ HT ] CRC32 {error, ok}= {%d, %d}\n",
1290 false_alm_cnt->cnt_ht_crc32_error,
1291 false_alm_cnt->cnt_ht_crc32_ok);
1292 ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
1293 "[VHT] CRC32 {error, ok}= {%d, %d}\n",
1294 false_alm_cnt->cnt_vht_crc32_error,
1295 false_alm_cnt->cnt_vht_crc32_ok);
1296 ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
1297 "[VHT] CRC32 {error, ok}= {%d, %d}\n",
1298 false_alm_cnt->cnt_crc32_error_all,
1299 false_alm_cnt->cnt_crc32_ok_all);
1300 ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
1301 "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n",
1302 false_alm_cnt->dbg_port0, false_alm_cnt->edcca_flag);
1303}
1304
1305/* 3============================================================
1306 * 3 CCK Packet Detect threshold
1307 * 3============================================================
1308 */
1309
1310void odm_pause_cck_packet_detection(void *dm_void,
1311 enum phydm_pause_type pause_type,
1312 enum phydm_pause_level pause_level,
1313 u8 cck_pd_threshold)
1314{
1315 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1316 struct dig_thres *dig_tab = &dm->dm_dig_table;
1317 s8 max_level;
1318
1319 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s()=========> level = %d\n", __func__,
1320 pause_level);
1321
1322 if ((dig_tab->pause_cckpd_level == 0) &&
1323 (!(dm->support_ability & ODM_BB_CCK_PD) ||
1324 !(dm->support_ability & ODM_BB_FA_CNT))) {
1325 ODM_RT_TRACE(
1326 dm, ODM_COMP_DIG,
1327 "Return: support_ability ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n");
1328 return;
1329 }
1330
1331 if (pause_level > DM_DIG_MAX_PAUSE_TYPE) {
1332 ODM_RT_TRACE(dm, ODM_COMP_DIG,
1333 "%s(): Return: Wrong pause level !!\n", __func__);
1334 return;
1335 }
1336
1337 ODM_RT_TRACE(dm, ODM_COMP_DIG,
1338 "%s(): pause level = 0x%x, Current value = 0x%x\n",
1339 __func__, dig_tab->pause_cckpd_level, cck_pd_threshold);
1340 ODM_RT_TRACE(
1341 dm, ODM_COMP_DIG,
1342 "%s(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1343 __func__, dig_tab->pause_cckpd_value[7],
1344 dig_tab->pause_cckpd_value[6], dig_tab->pause_cckpd_value[5],
1345 dig_tab->pause_cckpd_value[4], dig_tab->pause_cckpd_value[3],
1346 dig_tab->pause_cckpd_value[2], dig_tab->pause_cckpd_value[1],
1347 dig_tab->pause_cckpd_value[0]);
1348
1349 switch (pause_type) {
1350 /* Pause CCK Packet Detection threshold */
1351 case PHYDM_PAUSE: {
1352 /* Disable CCK PD */
1353 odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY,
1354 dm->support_ability & (~ODM_BB_CCK_PD));
1355 ODM_RT_TRACE(dm, ODM_COMP_DIG,
1356 "%s(): Pause CCK packet detection threshold !!\n",
1357 __func__);
1358
1359 /*Backup original CCK PD threshold decided by CCK PD mechanism*/
1360 if (dig_tab->pause_cckpd_level == 0) {
1361 dig_tab->cck_pd_backup = dig_tab->cur_cck_cca_thres;
1362 ODM_RT_TRACE(
1363 dm, ODM_COMP_DIG,
1364 "%s(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n",
1365 __func__, dig_tab->cck_pd_backup,
1366 cck_pd_threshold);
1367 }
1368
1369 /* Update pause level */
1370 dig_tab->pause_cckpd_level =
1371 (dig_tab->pause_cckpd_level | BIT(pause_level));
1372
1373 /* Record CCK PD threshold */
1374 dig_tab->pause_cckpd_value[pause_level] = cck_pd_threshold;
1375
1376 /* Write new CCK PD threshold */
1377 if (BIT(pause_level + 1) > dig_tab->pause_cckpd_level) {
1378 odm_write_cck_cca_thres(dm, cck_pd_threshold);
1379 ODM_RT_TRACE(dm, ODM_COMP_DIG,
1380 "%s(): CCKPD of higher level = 0x%x\n",
1381 __func__, cck_pd_threshold);
1382 }
1383 break;
1384 }
1385 /* Resume CCK Packet Detection threshold */
1386 case PHYDM_RESUME: {
1387 /* check if the level is illegal or not */
1388 if ((dig_tab->pause_cckpd_level & (BIT(pause_level))) != 0) {
1389 dig_tab->pause_cckpd_level =
1390 dig_tab->pause_cckpd_level &
1391 (~(BIT(pause_level)));
1392 dig_tab->pause_cckpd_value[pause_level] = 0;
1393 ODM_RT_TRACE(dm, ODM_COMP_DIG,
1394 "%s(): Resume CCK PD !!\n", __func__);
1395 } else {
1396 ODM_RT_TRACE(dm, ODM_COMP_DIG,
1397 "%s(): Wrong resume level !!\n", __func__);
1398 break;
1399 }
1400
1401 /* Resume DIG */
1402 if (dig_tab->pause_cckpd_level == 0) {
1403 /* Write backup IGI value */
1404 odm_write_cck_cca_thres(dm, dig_tab->cck_pd_backup);
1405 /* dig_tab->is_ignore_dig = true; */
1406 ODM_RT_TRACE(dm, ODM_COMP_DIG,
1407 "%s(): Write original CCKPD = 0x%x\n",
1408 __func__, dig_tab->cck_pd_backup);
1409
1410 /* Enable DIG */
1411 odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY,
1412 dm->support_ability |
1413 ODM_BB_CCK_PD);
1414 break;
1415 }
1416
1417 if (BIT(pause_level) <= dig_tab->pause_cckpd_level)
1418 break;
1419
1420 /* Calculate the maximum level now */
1421 for (max_level = (pause_level - 1); max_level >= 0;
1422 max_level--) {
1423 if ((dig_tab->pause_cckpd_level & BIT(max_level)) > 0)
1424 break;
1425 }
1426
1427 /* write CCKPD of lower level */
1428 odm_write_cck_cca_thres(dm,
1429 dig_tab->pause_cckpd_value[max_level]);
1430 ODM_RT_TRACE(dm, ODM_COMP_DIG,
1431 "%s(): Write CCKPD (0x%x) of level (%d)\n",
1432 __func__, dig_tab->pause_cckpd_value[max_level],
1433 max_level);
1434 break;
1435 }
1436 default:
1437 ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Wrong type !!\n",
1438 __func__);
1439 break;
1440 }
1441
1442 ODM_RT_TRACE(dm, ODM_COMP_DIG,
1443 "%s(): pause level = 0x%x, Current value = 0x%x\n",
1444 __func__, dig_tab->pause_cckpd_level, cck_pd_threshold);
1445 ODM_RT_TRACE(
1446 dm, ODM_COMP_DIG,
1447 "%s(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1448 __func__, dig_tab->pause_cckpd_value[7],
1449 dig_tab->pause_cckpd_value[6], dig_tab->pause_cckpd_value[5],
1450 dig_tab->pause_cckpd_value[4], dig_tab->pause_cckpd_value[3],
1451 dig_tab->pause_cckpd_value[2], dig_tab->pause_cckpd_value[1],
1452 dig_tab->pause_cckpd_value[0]);
1453}
1454
1455void odm_cck_packet_detection_thresh(void *dm_void)
1456{
1457 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1458 struct dig_thres *dig_tab = &dm->dm_dig_table;
1459 struct false_alarm_stat *false_alm_cnt =
1460 (struct false_alarm_stat *)phydm_get_structure(
1461 dm, PHYDM_FALSEALMCNT);
1462 u8 cur_cck_cca_thres = dig_tab->cur_cck_cca_thres, rssi_thd = 35;
1463
1464 if ((!(dm->support_ability & ODM_BB_CCK_PD)) ||
1465 (!(dm->support_ability & ODM_BB_FA_CNT))) {
1466 ODM_RT_TRACE(dm, ODM_COMP_DIG, "CCK_PD: return==========\n");
1467 return;
1468 }
1469
1470 if (dm->ext_lna)
1471 return;
1472
1473 ODM_RT_TRACE(dm, ODM_COMP_DIG, "CCK_PD: ==========>\n");
1474
1475 if (dig_tab->cck_fa_ma == 0xffffffff)
1476 dig_tab->cck_fa_ma = false_alm_cnt->cnt_cck_fail;
1477 else
1478 dig_tab->cck_fa_ma =
1479 ((dig_tab->cck_fa_ma << 1) + dig_tab->cck_fa_ma +
1480 false_alm_cnt->cnt_cck_fail) >>
1481 2;
1482
1483 ODM_RT_TRACE(dm, ODM_COMP_DIG, "CCK_PD: CCK FA moving average = %d\n",
1484 dig_tab->cck_fa_ma);
1485
1486 if (dm->is_linked) {
1487 if (dm->rssi_min > rssi_thd) {
1488 cur_cck_cca_thres = 0xcd;
1489 } else if (dm->rssi_min > 20) {
1490 if (dig_tab->cck_fa_ma >
1491 ((DM_DIG_FA_TH1 >> 1) + (DM_DIG_FA_TH1 >> 3)))
1492 cur_cck_cca_thres = 0xcd;
1493 else if (dig_tab->cck_fa_ma < (DM_DIG_FA_TH0 >> 1))
1494 cur_cck_cca_thres = 0x83;
1495 } else if (dm->rssi_min > 7) {
1496 cur_cck_cca_thres = 0x83;
1497 } else {
1498 cur_cck_cca_thres = 0x40;
1499 }
1500
1501 } else {
1502 if (dig_tab->cck_fa_ma > 0x400)
1503 cur_cck_cca_thres = 0x83;
1504 else if (dig_tab->cck_fa_ma < 0x200)
1505 cur_cck_cca_thres = 0x40;
1506 }
1507
1508 {
1509 odm_write_cck_cca_thres(dm, cur_cck_cca_thres);
1510 }
1511
1512 ODM_RT_TRACE(dm, ODM_COMP_DIG, "CCK_PD: cck_cca_th=((0x%x))\n\n",
1513 cur_cck_cca_thres);
1514}
1515
1516void odm_write_cck_cca_thres(void *dm_void, u8 cur_cck_cca_thres)
1517{
1518 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1519 struct dig_thres *dig_tab = &dm->dm_dig_table;
1520
1521 if (dig_tab->cur_cck_cca_thres !=
1522 cur_cck_cca_thres) { /* modify by Guo.Mingzhi 2012-01-03 */
1523 odm_write_1byte(dm, ODM_REG(CCK_CCA, dm), cur_cck_cca_thres);
1524 dig_tab->cck_fa_ma = 0xffffffff;
1525 }
1526 dig_tab->pre_cck_cca_thres = dig_tab->cur_cck_cca_thres;
1527 dig_tab->cur_cck_cca_thres = cur_cck_cca_thres;
1528}
1529
1530bool phydm_dig_go_up_check(void *dm_void)
1531{
1532 bool ret = true;
1533
1534 return ret;
1535}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_dig.h b/drivers/staging/rtlwifi/phydm/phydm_dig.h
new file mode 100644
index 000000000000..af70aaec3b19
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_dig.h
@@ -0,0 +1,241 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMDIG_H__
27#define __PHYDMDIG_H__
28
29#define DIG_VERSION "1.32" /* 2016.09.02 YuChen. add CCK PD for 8197F*/
30
31/* Pause DIG & CCKPD */
32#define DM_DIG_MAX_PAUSE_TYPE 0x7
33
34enum dig_goupcheck_level {
35 DIG_GOUPCHECK_LEVEL_0,
36 DIG_GOUPCHECK_LEVEL_1,
37 DIG_GOUPCHECK_LEVEL_2
38
39};
40
41struct dig_thres {
42 bool is_stop_dig; /* for debug */
43 bool is_ignore_dig;
44 bool is_psd_in_progress;
45
46 u8 dig_enable_flag;
47 u8 dig_ext_port_stage;
48
49 int rssi_low_thresh;
50 int rssi_high_thresh;
51
52 u32 fa_low_thresh;
53 u32 fa_high_thresh;
54
55 u8 cur_sta_connect_state;
56 u8 pre_sta_connect_state;
57 u8 cur_multi_sta_connect_state;
58
59 u8 pre_ig_value;
60 u8 cur_ig_value;
61 u8 backup_ig_value; /* MP DIG */
62 u8 bt30_cur_igi;
63 u8 igi_backup;
64
65 s8 backoff_val;
66 s8 backoff_val_range_max;
67 s8 backoff_val_range_min;
68 u8 rx_gain_range_max;
69 u8 rx_gain_range_min;
70 u8 rssi_val_min;
71
72 u8 pre_cck_cca_thres;
73 u8 cur_cck_cca_thres;
74 u8 pre_cck_pd_state;
75 u8 cur_cck_pd_state;
76 u8 cck_pd_backup;
77 u8 pause_cckpd_level;
78 u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
79
80 u8 large_fa_hit;
81 u8 large_fa_timeout; /*if (large_fa_hit), monitor "large_fa_timeout"
82 *sec, if timeout, large_fa_hit=0
83 */
84 u8 forbidden_igi;
85 u32 recover_cnt;
86
87 u8 dig_dynamic_min_0;
88 u8 dig_dynamic_min_1;
89 bool is_media_connect_0;
90 bool is_media_connect_1;
91
92 u32 ant_div_rssi_max;
93 u32 rssi_max;
94
95 u8 *is_p2p_in_process;
96
97 u8 pause_dig_level;
98 u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
99
100 u32 cck_fa_ma;
101 enum dig_goupcheck_level dig_go_up_check_level;
102 u8 aaa_default;
103
104 u8 rf_gain_idx;
105 u8 agc_table_idx;
106 u8 big_jump_lmt[16];
107 u8 enable_adjust_big_jump : 1;
108 u8 big_jump_step1 : 3;
109 u8 big_jump_step2 : 2;
110 u8 big_jump_step3 : 2;
111};
112
113struct false_alarm_stat {
114 u32 cnt_parity_fail;
115 u32 cnt_rate_illegal;
116 u32 cnt_crc8_fail;
117 u32 cnt_mcs_fail;
118 u32 cnt_ofdm_fail;
119 u32 cnt_ofdm_fail_pre; /* For RTL8881A */
120 u32 cnt_cck_fail;
121 u32 cnt_all;
122 u32 cnt_all_pre;
123 u32 cnt_fast_fsync;
124 u32 cnt_sb_search_fail;
125 u32 cnt_ofdm_cca;
126 u32 cnt_cck_cca;
127 u32 cnt_cca_all;
128 u32 cnt_bw_usc; /* Gary */
129 u32 cnt_bw_lsc; /* Gary */
130 u32 cnt_cck_crc32_error;
131 u32 cnt_cck_crc32_ok;
132 u32 cnt_ofdm_crc32_error;
133 u32 cnt_ofdm_crc32_ok;
134 u32 cnt_ht_crc32_error;
135 u32 cnt_ht_crc32_ok;
136 u32 cnt_vht_crc32_error;
137 u32 cnt_vht_crc32_ok;
138 u32 cnt_crc32_error_all;
139 u32 cnt_crc32_ok_all;
140 bool cck_block_enable;
141 bool ofdm_block_enable;
142 u32 dbg_port0;
143 bool edcca_flag;
144};
145
146enum dm_dig_op {
147 DIG_TYPE_THRESH_HIGH = 0,
148 DIG_TYPE_THRESH_LOW = 1,
149 DIG_TYPE_BACKOFF = 2,
150 DIG_TYPE_RX_GAIN_MIN = 3,
151 DIG_TYPE_RX_GAIN_MAX = 4,
152 DIG_TYPE_ENABLE = 5,
153 DIG_TYPE_DISABLE = 6,
154 DIG_OP_TYPE_MAX
155};
156
157enum phydm_pause_type { PHYDM_PAUSE = BIT(0), PHYDM_RESUME = BIT(1) };
158
159enum phydm_pause_level {
160 /* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
161 PHYDM_PAUSE_LEVEL_0 = 0,
162 PHYDM_PAUSE_LEVEL_1 = 1,
163 PHYDM_PAUSE_LEVEL_2 = 2,
164 PHYDM_PAUSE_LEVEL_3 = 3,
165 PHYDM_PAUSE_LEVEL_4 = 4,
166 PHYDM_PAUSE_LEVEL_5 = 5,
167 PHYDM_PAUSE_LEVEL_6 = 6,
168 PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */
169};
170
171#define DM_DIG_THRESH_HIGH 40
172#define DM_DIG_THRESH_LOW 35
173
174#define DM_FALSEALARM_THRESH_LOW 400
175#define DM_FALSEALARM_THRESH_HIGH 1000
176
177#define DM_DIG_MAX_NIC 0x3e
178#define DM_DIG_MIN_NIC 0x20
179#define DM_DIG_MAX_OF_MIN_NIC 0x3e
180
181#define DM_DIG_MAX_AP 0x3e
182#define DM_DIG_MIN_AP 0x20
183#define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */
184#define DM_DIG_MIN_AP_DFS 0x20
185
186#define DM_DIG_MAX_NIC_HP 0x46
187#define DM_DIG_MIN_NIC_HP 0x2e
188
189#define DM_DIG_MAX_AP_HP 0x42
190#define DM_DIG_MIN_AP_HP 0x30
191
192/* vivi 92c&92d has different definition, 20110504
193 * this is for 92c
194 */
195#define DM_DIG_FA_TH0 0x200 /* 0x20 */
196
197#define DM_DIG_FA_TH1 0x300
198#define DM_DIG_FA_TH2 0x400
199/* this is for 92d */
200#define DM_DIG_FA_TH0_92D 0x100
201#define DM_DIG_FA_TH1_92D 0x400
202#define DM_DIG_FA_TH2_92D 0x600
203
204#define DM_DIG_BACKOFF_MAX 12
205#define DM_DIG_BACKOFF_MIN -4
206#define DM_DIG_BACKOFF_DEFAULT 10
207
208#define DM_DIG_FA_TH0_LPS 4 /* -> 4 in lps */
209#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */
210#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */
211#define RSSI_OFFSET_DIG 0x05
212#define LARGE_FA_TIMEOUT 60
213
214void odm_change_dynamic_init_gain_thresh(void *dm_void, u32 dm_type,
215 u32 dm_value);
216
217void odm_write_dig(void *dm_void, u8 current_igi);
218
219void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
220 enum phydm_pause_level pause_level, u8 igi_value);
221
222void odm_dig_init(void *dm_void);
223
224void odm_DIG(void *dm_void);
225
226void odm_dig_by_rssi_lps(void *dm_void);
227
228void odm_false_alarm_counter_statistics(void *dm_void);
229
230void odm_pause_cck_packet_detection(void *dm_void,
231 enum phydm_pause_type pause_type,
232 enum phydm_pause_level pause_level,
233 u8 cck_pd_threshold);
234
235void odm_cck_packet_detection_thresh(void *dm_void);
236
237void odm_write_cck_cca_thres(void *dm_void, u8 cur_cck_cca_thres);
238
239bool phydm_dig_go_up_check(void *dm_void);
240
241#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_dynamic_rx_path.h b/drivers/staging/rtlwifi/phydm/phydm_dynamic_rx_path.h
new file mode 100644
index 000000000000..9f3cb2468c02
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_dynamic_rx_path.h
@@ -0,0 +1,37 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMDYMICRXPATH_H__
27#define __PHYDMDYMICRXPATH_H__
28
29#define DYNAMIC_RX_PATH_VERSION "1.0" /*2016.07.15 Dino */
30
31#define DRP_RSSI_TH 35
32
33#define INIT_DRP_TIMMER 0
34#define CANCEL_DRP_TIMMER 1
35#define RELEASE_DRP_TIMMER 2
36
37#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_dynamicbbpowersaving.c b/drivers/staging/rtlwifi/phydm/phydm_dynamicbbpowersaving.c
new file mode 100644
index 000000000000..7661c499aeb1
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_dynamicbbpowersaving.c
@@ -0,0 +1,129 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31
32static inline void phydm_update_rf_state(struct phy_dm_struct *dm,
33 struct dyn_pwr_saving *dm_ps_table,
34 int _rssi_up_bound,
35 int _rssi_low_bound,
36 int _is_force_in_normal)
37{
38 if (_is_force_in_normal) {
39 dm_ps_table->cur_rf_state = rf_normal;
40 return;
41 }
42
43 if (dm->rssi_min == 0xFF) {
44 dm_ps_table->cur_rf_state = RF_MAX;
45 return;
46 }
47
48 if (dm_ps_table->pre_rf_state == rf_normal) {
49 if (dm->rssi_min >= _rssi_up_bound)
50 dm_ps_table->cur_rf_state = rf_save;
51 else
52 dm_ps_table->cur_rf_state = rf_normal;
53 } else {
54 if (dm->rssi_min <= _rssi_low_bound)
55 dm_ps_table->cur_rf_state = rf_normal;
56 else
57 dm_ps_table->cur_rf_state = rf_save;
58 }
59}
60
61void odm_dynamic_bb_power_saving_init(void *dm_void)
62{
63 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
64 struct dyn_pwr_saving *dm_ps_table = &dm->dm_ps_table;
65
66 dm_ps_table->pre_cca_state = CCA_MAX;
67 dm_ps_table->cur_cca_state = CCA_MAX;
68 dm_ps_table->pre_rf_state = RF_MAX;
69 dm_ps_table->cur_rf_state = RF_MAX;
70 dm_ps_table->rssi_val_min = 0;
71 dm_ps_table->initialize = 0;
72}
73
74void odm_rf_saving(void *dm_void, u8 is_force_in_normal)
75{
76 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
77 struct dyn_pwr_saving *dm_ps_table = &dm->dm_ps_table;
78 u8 rssi_up_bound = 30;
79 u8 rssi_low_bound = 25;
80
81 if (dm->patch_id == 40) { /* RT_CID_819x_FUNAI_TV */
82 rssi_up_bound = 50;
83 rssi_low_bound = 45;
84 }
85 if (dm_ps_table->initialize == 0) {
86 dm_ps_table->reg874 =
87 (odm_get_bb_reg(dm, 0x874, MASKDWORD) & 0x1CC000) >> 14;
88 dm_ps_table->regc70 =
89 (odm_get_bb_reg(dm, 0xc70, MASKDWORD) & BIT(3)) >> 3;
90 dm_ps_table->reg85c =
91 (odm_get_bb_reg(dm, 0x85c, MASKDWORD) & 0xFF000000) >>
92 24;
93 dm_ps_table->rega74 =
94 (odm_get_bb_reg(dm, 0xa74, MASKDWORD) & 0xF000) >> 12;
95 /* Reg818 = phy_query_bb_reg(adapter, 0x818, MASKDWORD); */
96 dm_ps_table->initialize = 1;
97 }
98
99 phydm_update_rf_state(dm, dm_ps_table, rssi_up_bound, rssi_low_bound,
100 is_force_in_normal);
101
102 if (dm_ps_table->pre_rf_state != dm_ps_table->cur_rf_state) {
103 if (dm_ps_table->cur_rf_state == rf_save) {
104 odm_set_bb_reg(dm, 0x874, 0x1C0000,
105 0x2); /* reg874[20:18]=3'b010 */
106 odm_set_bb_reg(dm, 0xc70, BIT(3),
107 0); /* regc70[3]=1'b0 */
108 odm_set_bb_reg(dm, 0x85c, 0xFF000000,
109 0x63); /* reg85c[31:24]=0x63 */
110 odm_set_bb_reg(dm, 0x874, 0xC000,
111 0x2); /* reg874[15:14]=2'b10 */
112 odm_set_bb_reg(dm, 0xa74, 0xF000,
113 0x3); /* RegA75[7:4]=0x3 */
114 odm_set_bb_reg(dm, 0x818, BIT(28),
115 0x0); /* Reg818[28]=1'b0 */
116 odm_set_bb_reg(dm, 0x818, BIT(28),
117 0x1); /* Reg818[28]=1'b1 */
118 } else {
119 odm_set_bb_reg(dm, 0x874, 0x1CC000,
120 dm_ps_table->reg874);
121 odm_set_bb_reg(dm, 0xc70, BIT(3), dm_ps_table->regc70);
122 odm_set_bb_reg(dm, 0x85c, 0xFF000000,
123 dm_ps_table->reg85c);
124 odm_set_bb_reg(dm, 0xa74, 0xF000, dm_ps_table->rega74);
125 odm_set_bb_reg(dm, 0x818, BIT(28), 0x0);
126 }
127 dm_ps_table->pre_rf_state = dm_ps_table->cur_rf_state;
128 }
129}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_dynamicbbpowersaving.h b/drivers/staging/rtlwifi/phydm/phydm_dynamicbbpowersaving.h
new file mode 100644
index 000000000000..e7394c475395
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_dynamicbbpowersaving.h
@@ -0,0 +1,50 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__
27#define __PHYDMDYNAMICBBPOWERSAVING_H__
28
29#define DYNAMIC_BBPWRSAV_VERSION "1.1"
30
31struct dyn_pwr_saving {
32 u8 pre_cca_state;
33 u8 cur_cca_state;
34
35 u8 pre_rf_state;
36 u8 cur_rf_state;
37
38 int rssi_val_min;
39
40 u8 initialize;
41 u32 reg874, regc70, reg85c, rega74;
42};
43
44#define dm_rf_saving odm_rf_saving
45
46void odm_rf_saving(void *dm_void, u8 is_force_in_normal);
47
48void odm_dynamic_bb_power_saving_init(void *dm_void);
49
50#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_dynamictxpower.c b/drivers/staging/rtlwifi/phydm/phydm_dynamictxpower.c
new file mode 100644
index 000000000000..ebb43342b80b
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_dynamictxpower.c
@@ -0,0 +1,102 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31
32void odm_dynamic_tx_power_init(void *dm_void)
33{
34 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
35
36 dm->last_dtp_lvl = tx_high_pwr_level_normal;
37 dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
38 dm->tx_agc_ofdm_18_6 =
39 odm_get_bb_reg(dm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/
40}
41
42void odm_dynamic_tx_power_save_power_index(void *dm_void) {}
43
44void odm_dynamic_tx_power_restore_power_index(void *dm_void) {}
45
46void odm_dynamic_tx_power_write_power_index(void *dm_void, u8 value)
47{
48 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
49 u8 index;
50 u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
51
52 for (index = 0; index < 6; index++)
53 odm_write_1byte(dm, power_index_reg[index], value);
54}
55
56static void odm_dynamic_tx_power_nic_ce(void *dm_void) {}
57
58void odm_dynamic_tx_power(void *dm_void)
59{
60 /* */
61 /* For AP/ADSL use struct rtl8192cd_priv* */
62 /* For CE/NIC use struct void* */
63 /* */
64 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
65
66 if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
67 return;
68 /* 2011/09/29 MH In HW integration first stage, we provide 4 different
69 * handle to operate at the same time.
70 * In the stage2/3, we need to prive universal interface and merge all
71 * HW dynamic mechanism.
72 */
73 switch (dm->support_platform) {
74 case ODM_WIN:
75 odm_dynamic_tx_power_nic(dm);
76 break;
77 case ODM_CE:
78 odm_dynamic_tx_power_nic_ce(dm);
79 break;
80 case ODM_AP:
81 odm_dynamic_tx_power_ap(dm);
82 break;
83 default:
84 break;
85 }
86}
87
88void odm_dynamic_tx_power_nic(void *dm_void)
89{
90 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
91
92 if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
93 return;
94}
95
96void odm_dynamic_tx_power_ap(void *dm_void
97
98 )
99{
100}
101
102void odm_dynamic_tx_power_8821(void *dm_void, u8 *desc, u8 mac_id) {}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_dynamictxpower.h b/drivers/staging/rtlwifi/phydm/phydm_dynamictxpower.h
new file mode 100644
index 000000000000..10bad1209db2
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_dynamictxpower.h
@@ -0,0 +1,64 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMDYNAMICTXPOWER_H__
27#define __PHYDMDYNAMICTXPOWER_H__
28
29/*#define DYNAMIC_TXPWR_VERSION "1.0"*/
30/*#define DYNAMIC_TXPWR_VERSION "1.3" */ /*2015.08.26, Add 8814 Dynamic TX pwr*/
31#define DYNAMIC_TXPWR_VERSION "1.4" /*2015.11.06,Add CE 8821A Dynamic TX pwr*/
32
33#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
34#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
35
36#define tx_high_pwr_level_normal 0
37#define tx_high_pwr_level_level1 1
38#define tx_high_pwr_level_level2 2
39
40#define tx_high_pwr_level_bt1 3
41#define tx_high_pwr_level_bt2 4
42#define tx_high_pwr_level_15 5
43#define tx_high_pwr_level_35 6
44#define tx_high_pwr_level_50 7
45#define tx_high_pwr_level_70 8
46#define tx_high_pwr_level_100 9
47
48void odm_dynamic_tx_power_init(void *dm_void);
49
50void odm_dynamic_tx_power_restore_power_index(void *dm_void);
51
52void odm_dynamic_tx_power_nic(void *dm_void);
53
54void odm_dynamic_tx_power_save_power_index(void *dm_void);
55
56void odm_dynamic_tx_power_write_power_index(void *dm_void, u8 value);
57
58void odm_dynamic_tx_power_8821(void *dm_void, u8 *desc, u8 mac_id);
59
60void odm_dynamic_tx_power(void *dm_void);
61
62void odm_dynamic_tx_power_ap(void *dm_void);
63
64#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.c b/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.c
new file mode 100644
index 000000000000..753a9b9834e4
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.c
@@ -0,0 +1,139 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31
32void odm_edca_turbo_init(void *dm_void)
33{
34 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
35
36 dm->dm_edca_table.is_current_turbo_edca = false;
37 dm->dm_edca_table.is_cur_rdl_state = false;
38
39 ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Orginial VO PARAM: 0x%x\n",
40 odm_read_4byte(dm, ODM_EDCA_VO_PARAM));
41 ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Orginial VI PARAM: 0x%x\n",
42 odm_read_4byte(dm, ODM_EDCA_VI_PARAM));
43 ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Orginial BE PARAM: 0x%x\n",
44 odm_read_4byte(dm, ODM_EDCA_BE_PARAM));
45 ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Orginial BK PARAM: 0x%x\n",
46 odm_read_4byte(dm, ODM_EDCA_BK_PARAM));
47
48} /* ODM_InitEdcaTurbo */
49
50void odm_edca_turbo_check(void *dm_void)
51{
52 /* For AP/ADSL use struct rtl8192cd_priv* */
53 /* For CE/NIC use struct void* */
54
55 /* 2011/09/29 MH In HW integration first stage, we provide 4 different
56 * handle to operate at the same time.
57 * In the stage2/3, we need to prive universal interface and merge all
58 * HW dynamic mechanism.
59 */
60 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
61
62 ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO,
63 "%s========================>\n", __func__);
64
65 if (!(dm->support_ability & ODM_MAC_EDCA_TURBO))
66 return;
67
68 switch (dm->support_platform) {
69 case ODM_WIN:
70
71 break;
72
73 case ODM_CE:
74 odm_edca_turbo_check_ce(dm);
75 break;
76 }
77 ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO,
78 "<========================%s\n", __func__);
79
80} /* odm_CheckEdcaTurbo */
81
82void odm_edca_turbo_check_ce(void *dm_void)
83{
84 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
85 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
86 u64 cur_txok_cnt = 0;
87 u64 cur_rxok_cnt = 0;
88 u32 edca_be_ul = 0x5ea42b;
89 u32 edca_be_dl = 0x5ea42b;
90 u32 edca_be = 0x5ea42b;
91 bool is_cur_rdlstate;
92 bool edca_turbo_on = false;
93
94 if (dm->wifi_test)
95 return;
96
97 if (!dm->is_linked) {
98 rtlpriv->dm.is_any_nonbepkts = false;
99 return;
100 }
101
102 if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
103 rtlpriv->dm.is_any_nonbepkts = true;
104 rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
105
106 cur_txok_cnt = rtlpriv->stats.txbytesunicast_inperiod;
107 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast_inperiod;
108
109 /*b_bias_on_rx = false;*/
110 edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
111 (!rtlpriv->dm.disable_framebursting)) ?
112 true :
113 false;
114
115 if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
116 goto label_exit;
117
118 if (edca_turbo_on) {
119 is_cur_rdlstate =
120 (cur_rxok_cnt > cur_txok_cnt * 4) ? true : false;
121
122 edca_be = is_cur_rdlstate ? edca_be_dl : edca_be_ul;
123 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM_8822B, edca_be);
124 rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate;
125 rtlpriv->dm.current_turbo_edca = true;
126 } else {
127 if (rtlpriv->dm.current_turbo_edca) {
128 u8 tmp = AC0_BE;
129
130 rtlpriv->cfg->ops->set_hw_reg(rtlpriv->hw,
131 HW_VAR_AC_PARAM,
132 (u8 *)(&tmp));
133 rtlpriv->dm.current_turbo_edca = false;
134 }
135 }
136
137label_exit:
138 rtlpriv->dm.is_any_nonbepkts = false;
139}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.h b/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.h
new file mode 100644
index 000000000000..5845b108a001
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.h
@@ -0,0 +1,44 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMEDCATURBOCHECK_H__
27#define __PHYDMEDCATURBOCHECK_H__
28
29/*#define EDCATURBO_VERSION "2.1"*/
30#define EDCATURBO_VERSION "2.3" /*2015.07.29 by YuChen*/
31
32struct edca_turbo {
33 bool is_current_turbo_edca;
34 bool is_cur_rdl_state;
35
36 u32 prv_traffic_idx; /* edca turbo */
37};
38
39void odm_edca_turbo_check(void *dm_void);
40void odm_edca_turbo_init(void *dm_void);
41
42void odm_edca_turbo_check_ce(void *dm_void);
43
44#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_features.h b/drivers/staging/rtlwifi/phydm/phydm_features.h
new file mode 100644
index 000000000000..37f6f0cd7235
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_features.h
@@ -0,0 +1,33 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDM_FEATURES_H__
27#define __PHYDM_FEATURES
28
29/*phydm debyg report & tools*/
30
31/*Antenna Diversity*/
32
33#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_hwconfig.c b/drivers/staging/rtlwifi/phydm/phydm_hwconfig.c
new file mode 100644
index 000000000000..0a1f11a926e4
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_hwconfig.c
@@ -0,0 +1,1928 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29
30#include "mp_precomp.h"
31#include "phydm_precomp.h"
32
33#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(dm))
34#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(dm))
35
36#define READ_AND_CONFIG READ_AND_CONFIG_MP
37
38#define READ_FIRMWARE_MP(ic, txt) \
39 (odm_read_firmware_mp_##ic##txt(dm, p_firmware, size))
40#define READ_FIRMWARE_TC(ic, txt) \
41 (odm_read_firmware_tc_##ic##txt(dm, p_firmware, size))
42
43#define READ_FIRMWARE READ_FIRMWARE_MP
44
45#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt())
46#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt())
47
48#define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt)
49
50static u32 phydm_process_rssi_pwdb(struct phy_dm_struct *dm,
51 struct rtl_sta_info *entry,
52 struct dm_per_pkt_info *pktinfo,
53 u32 undecorated_smoothed_ofdm,
54 u32 undecorated_smoothed_cck)
55{
56 u32 weighting = 0, undecorated_smoothed_pwdb;
57 /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
58
59 if (entry->rssi_stat.ofdm_pkt ==
60 64) { /* speed up when all packets are OFDM*/
61 undecorated_smoothed_pwdb = undecorated_smoothed_ofdm;
62 ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
63 "PWDB_0[%d] = (( %d ))\n", pktinfo->station_id,
64 undecorated_smoothed_cck);
65 } else {
66 if (entry->rssi_stat.valid_bit < 64)
67 entry->rssi_stat.valid_bit++;
68
69 if (entry->rssi_stat.valid_bit == 64) {
70 weighting = ((entry->rssi_stat.ofdm_pkt) > 4) ?
71 64 :
72 (entry->rssi_stat.ofdm_pkt << 4);
73 undecorated_smoothed_pwdb =
74 (weighting * undecorated_smoothed_ofdm +
75 (64 - weighting) * undecorated_smoothed_cck) >>
76 6;
77 ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
78 "PWDB_1[%d] = (( %d )), W = (( %d ))\n",
79 pktinfo->station_id,
80 undecorated_smoothed_cck, weighting);
81 } else {
82 if (entry->rssi_stat.valid_bit != 0)
83 undecorated_smoothed_pwdb =
84 (entry->rssi_stat.ofdm_pkt *
85 undecorated_smoothed_ofdm +
86 (entry->rssi_stat.valid_bit -
87 entry->rssi_stat.ofdm_pkt) *
88 undecorated_smoothed_cck) /
89 entry->rssi_stat.valid_bit;
90 else
91 undecorated_smoothed_pwdb = 0;
92
93 ODM_RT_TRACE(
94 dm, ODM_COMP_RSSI_MONITOR,
95 "PWDB_2[%d] = (( %d )), ofdm_pkt = (( %d )), Valid_Bit = (( %d ))\n",
96 pktinfo->station_id, undecorated_smoothed_cck,
97 entry->rssi_stat.ofdm_pkt,
98 entry->rssi_stat.valid_bit);
99 }
100 }
101
102 return undecorated_smoothed_pwdb;
103}
104
105static u32 phydm_process_rssi_cck(struct phy_dm_struct *dm,
106 struct dm_phy_status_info *phy_info,
107 struct rtl_sta_info *entry,
108 u32 undecorated_smoothed_cck)
109{
110 u32 rssi_ave;
111 u8 i;
112
113 rssi_ave = phy_info->rx_pwdb_all;
114 dm->rssi_a = (u8)phy_info->rx_pwdb_all;
115 dm->rssi_b = 0xFF;
116 dm->rssi_c = 0xFF;
117 dm->rssi_d = 0xFF;
118
119 if (entry->rssi_stat.cck_pkt <= 63)
120 entry->rssi_stat.cck_pkt++;
121
122 /* 1 Process CCK RSSI */
123 if (undecorated_smoothed_cck <= 0) { /* initialize */
124 undecorated_smoothed_cck = phy_info->rx_pwdb_all;
125 entry->rssi_stat.cck_sum_power =
126 (u16)phy_info->rx_pwdb_all; /*reset*/
127 entry->rssi_stat.cck_pkt = 1; /*reset*/
128 ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR, "CCK_INIT: (( %d ))\n",
129 undecorated_smoothed_cck);
130 } else if (entry->rssi_stat.cck_pkt <= CCK_RSSI_INIT_COUNT) {
131 entry->rssi_stat.cck_sum_power =
132 entry->rssi_stat.cck_sum_power +
133 (u16)phy_info->rx_pwdb_all;
134 undecorated_smoothed_cck = entry->rssi_stat.cck_sum_power /
135 entry->rssi_stat.cck_pkt;
136
137 ODM_RT_TRACE(
138 dm, ODM_COMP_RSSI_MONITOR,
139 "CCK_0: (( %d )), SumPow = (( %d )), cck_pkt = (( %d ))\n",
140 undecorated_smoothed_cck,
141 entry->rssi_stat.cck_sum_power,
142 entry->rssi_stat.cck_pkt);
143 } else {
144 if (phy_info->rx_pwdb_all > (u32)undecorated_smoothed_cck) {
145 undecorated_smoothed_cck =
146 (((undecorated_smoothed_cck) *
147 (RX_SMOOTH_FACTOR - 1)) +
148 (phy_info->rx_pwdb_all)) /
149 (RX_SMOOTH_FACTOR);
150 undecorated_smoothed_cck = undecorated_smoothed_cck + 1;
151 ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
152 "CCK_1: (( %d ))\n",
153 undecorated_smoothed_cck);
154 } else {
155 undecorated_smoothed_cck =
156 (((undecorated_smoothed_cck) *
157 (RX_SMOOTH_FACTOR - 1)) +
158 (phy_info->rx_pwdb_all)) /
159 (RX_SMOOTH_FACTOR);
160 ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
161 "CCK_2: (( %d ))\n",
162 undecorated_smoothed_cck);
163 }
164 }
165
166 i = 63;
167 entry->rssi_stat.ofdm_pkt -=
168 (u8)((entry->rssi_stat.packet_map >> i) & BIT(0));
169 entry->rssi_stat.packet_map = entry->rssi_stat.packet_map << 1;
170 return undecorated_smoothed_cck;
171}
172
173static u32 phydm_process_rssi_ofdm(struct phy_dm_struct *dm,
174 struct dm_phy_status_info *phy_info,
175 struct rtl_sta_info *entry,
176 u32 undecorated_smoothed_ofdm)
177{
178 u32 rssi_ave;
179 u8 rssi_max, rssi_min, i;
180
181 if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) {
182 u8 rx_count = 0;
183 u32 rssi_linear = 0;
184
185 if (dm->rx_ant_status & ODM_RF_A) {
186 dm->rssi_a = phy_info->rx_mimo_signal_strength
187 [ODM_RF_PATH_A];
188 rx_count++;
189 rssi_linear += odm_convert_to_linear(
190 phy_info->rx_mimo_signal_strength
191 [ODM_RF_PATH_A]);
192 } else {
193 dm->rssi_a = 0;
194 }
195
196 if (dm->rx_ant_status & ODM_RF_B) {
197 dm->rssi_b = phy_info->rx_mimo_signal_strength
198 [ODM_RF_PATH_B];
199 rx_count++;
200 rssi_linear += odm_convert_to_linear(
201 phy_info->rx_mimo_signal_strength
202 [ODM_RF_PATH_B]);
203 } else {
204 dm->rssi_b = 0;
205 }
206
207 if (dm->rx_ant_status & ODM_RF_C) {
208 dm->rssi_c = phy_info->rx_mimo_signal_strength
209 [ODM_RF_PATH_C];
210 rx_count++;
211 rssi_linear += odm_convert_to_linear(
212 phy_info->rx_mimo_signal_strength
213 [ODM_RF_PATH_C]);
214 } else {
215 dm->rssi_c = 0;
216 }
217
218 if (dm->rx_ant_status & ODM_RF_D) {
219 dm->rssi_d = phy_info->rx_mimo_signal_strength
220 [ODM_RF_PATH_D];
221 rx_count++;
222 rssi_linear += odm_convert_to_linear(
223 phy_info->rx_mimo_signal_strength
224 [ODM_RF_PATH_D]);
225 } else {
226 dm->rssi_d = 0;
227 }
228
229 /* Calculate average RSSI */
230 switch (rx_count) {
231 case 2:
232 rssi_linear = (rssi_linear >> 1);
233 break;
234 case 3:
235 /* rssi_linear/3 ~ rssi_linear*11/32 */
236 rssi_linear = ((rssi_linear) + (rssi_linear << 1) +
237 (rssi_linear << 3)) >>
238 5;
239 break;
240 case 4:
241 rssi_linear = (rssi_linear >> 2);
242 break;
243 }
244
245 rssi_ave = odm_convert_to_db(rssi_linear);
246 } else {
247 if (phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B] == 0) {
248 rssi_ave = phy_info->rx_mimo_signal_strength
249 [ODM_RF_PATH_A];
250 dm->rssi_a = phy_info->rx_mimo_signal_strength
251 [ODM_RF_PATH_A];
252 dm->rssi_b = 0;
253 } else {
254 dm->rssi_a = phy_info->rx_mimo_signal_strength
255 [ODM_RF_PATH_A];
256 dm->rssi_b = phy_info->rx_mimo_signal_strength
257 [ODM_RF_PATH_B];
258
259 if (phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A] >
260 phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]) {
261 rssi_max = phy_info->rx_mimo_signal_strength
262 [ODM_RF_PATH_A];
263 rssi_min = phy_info->rx_mimo_signal_strength
264 [ODM_RF_PATH_B];
265 } else {
266 rssi_max = phy_info->rx_mimo_signal_strength
267 [ODM_RF_PATH_B];
268 rssi_min = phy_info->rx_mimo_signal_strength
269 [ODM_RF_PATH_A];
270 }
271 if ((rssi_max - rssi_min) < 3)
272 rssi_ave = rssi_max;
273 else if ((rssi_max - rssi_min) < 6)
274 rssi_ave = rssi_max - 1;
275 else if ((rssi_max - rssi_min) < 10)
276 rssi_ave = rssi_max - 2;
277 else
278 rssi_ave = rssi_max - 3;
279 }
280 }
281
282 /* 1 Process OFDM RSSI */
283 if (undecorated_smoothed_ofdm <= 0) { /* initialize */
284 undecorated_smoothed_ofdm = phy_info->rx_pwdb_all;
285 ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR, "OFDM_INIT: (( %d ))\n",
286 undecorated_smoothed_ofdm);
287 } else {
288 if (phy_info->rx_pwdb_all > (u32)undecorated_smoothed_ofdm) {
289 undecorated_smoothed_ofdm =
290 (((undecorated_smoothed_ofdm) *
291 (RX_SMOOTH_FACTOR - 1)) +
292 (rssi_ave)) /
293 (RX_SMOOTH_FACTOR);
294 undecorated_smoothed_ofdm =
295 undecorated_smoothed_ofdm + 1;
296 ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
297 "OFDM_1: (( %d ))\n",
298 undecorated_smoothed_ofdm);
299 } else {
300 undecorated_smoothed_ofdm =
301 (((undecorated_smoothed_ofdm) *
302 (RX_SMOOTH_FACTOR - 1)) +
303 (rssi_ave)) /
304 (RX_SMOOTH_FACTOR);
305 ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
306 "OFDM_2: (( %d ))\n",
307 undecorated_smoothed_ofdm);
308 }
309 }
310
311 if (entry->rssi_stat.ofdm_pkt != 64) {
312 i = 63;
313 entry->rssi_stat.ofdm_pkt -=
314 (u8)(((entry->rssi_stat.packet_map >> i) & BIT(0)) - 1);
315 }
316
317 entry->rssi_stat.packet_map =
318 (entry->rssi_stat.packet_map << 1) | BIT(0);
319 return undecorated_smoothed_ofdm;
320}
321
322static u8 odm_evm_db_to_percentage(s8);
323static u8 odm_evm_dbm_jaguar_series(s8);
324
325static inline u32 phydm_get_rssi_average(struct phy_dm_struct *dm,
326 struct dm_phy_status_info *phy_info)
327{
328 u8 rssi_max = 0, rssi_min = 0;
329
330 dm->rssi_a = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
331 dm->rssi_b = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
332
333 if (phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A] >
334 phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]) {
335 rssi_max = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
336 rssi_min = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
337 } else {
338 rssi_max = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
339 rssi_min = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
340 }
341 if ((rssi_max - rssi_min) < 3)
342 return rssi_max;
343 else if ((rssi_max - rssi_min) < 6)
344 return rssi_max - 1;
345 else if ((rssi_max - rssi_min) < 10)
346 return rssi_max - 2;
347 else
348 return rssi_max - 3;
349}
350
351static inline u8 phydm_get_evm_dbm(u8 i, u8 EVM,
352 struct phy_status_rpt_8812 *phy_sta_rpt,
353 struct dm_phy_status_info *phy_info)
354{
355 if (i < ODM_RF_PATH_C)
356 return odm_evm_dbm_jaguar_series(phy_sta_rpt->rxevm[i]);
357 else
358 return odm_evm_dbm_jaguar_series(phy_sta_rpt->rxevm_cd[i - 2]);
359 /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/
360 /*pktinfo->data_rate, phy_sta_rpt->rxevm[i], "%", EVM));*/
361}
362
363static inline u8 phydm_get_odm_evm(u8 i, struct dm_per_pkt_info *pktinfo,
364 struct phy_status_rpt_8812 *phy_sta_rpt)
365{
366 u8 evm = 0;
367
368 if (pktinfo->data_rate >= ODM_RATE6M &&
369 pktinfo->data_rate <= ODM_RATE54M) {
370 if (i == ODM_RF_PATH_A) {
371 evm = odm_evm_db_to_percentage(
372 (phy_sta_rpt->sigevm)); /*dbm*/
373 evm += 20;
374 if (evm > 100)
375 evm = 100;
376 }
377 } else {
378 if (i < ODM_RF_PATH_C) {
379 if (phy_sta_rpt->rxevm[i] == -128)
380 phy_sta_rpt->rxevm[i] = -25;
381 evm = odm_evm_db_to_percentage(
382 (phy_sta_rpt->rxevm[i])); /*dbm*/
383 } else {
384 if (phy_sta_rpt->rxevm_cd[i - 2] == -128)
385 phy_sta_rpt->rxevm_cd[i - 2] = -25;
386 evm = odm_evm_db_to_percentage(
387 (phy_sta_rpt->rxevm_cd[i - 2])); /*dbm*/
388 }
389 }
390
391 return evm;
392}
393
394static inline s8 phydm_get_rx_pwr(u8 LNA_idx, u8 VGA_idx, u8 cck_highpwr)
395{
396 switch (LNA_idx) {
397 case 7:
398 if (VGA_idx <= 27)
399 return -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/
400 else
401 return -100;
402 break;
403 case 6:
404 return -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/
405 case 5:
406 return -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/
407 case 4:
408 return -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/
409 case 3:
410 return -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/
411 case 2:
412 if (cck_highpwr)
413 return -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/
414 else
415 return -6 + 2 * (5 - VGA_idx);
416 break;
417 case 1:
418 return 8 - 2 * VGA_idx;
419 case 0:
420 return 14 - 2 * VGA_idx;
421 default:
422 break;
423 }
424 return 0;
425}
426
427static inline u8 phydm_adjust_pwdb(u8 cck_highpwr, u8 pwdb_all)
428{
429 if (!cck_highpwr) {
430 if (pwdb_all >= 80)
431 return ((pwdb_all - 80) << 1) + ((pwdb_all - 80) >> 1) +
432 80;
433 else if ((pwdb_all <= 78) && (pwdb_all >= 20))
434 return pwdb_all + 3;
435 if (pwdb_all > 100)
436 return 100;
437 }
438 return pwdb_all;
439}
440
441static inline u8
442phydm_get_signal_quality_8812(struct dm_phy_status_info *phy_info,
443 struct phy_dm_struct *dm,
444 struct phy_status_rpt_8812 *phy_sta_rpt)
445{
446 u8 sq_rpt;
447
448 if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test)
449 return 100;
450
451 sq_rpt = phy_sta_rpt->pwdb_all;
452
453 if (sq_rpt > 64)
454 return 0;
455 else if (sq_rpt < 20)
456 return 100;
457 else
458 return ((64 - sq_rpt) * 100) / 44;
459}
460
461static inline u8
462phydm_get_signal_quality_8192(struct dm_phy_status_info *phy_info,
463 struct phy_dm_struct *dm,
464 struct phy_status_rpt_8192cd *phy_sta_rpt)
465{
466 u8 sq_rpt;
467
468 if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test)
469 return 100;
470
471 sq_rpt = phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all;
472
473 if (sq_rpt > 64)
474 return 0;
475 else if (sq_rpt < 20)
476 return 100;
477 else
478 return ((64 - sq_rpt) * 100) / 44;
479}
480
481static u8 odm_query_rx_pwr_percentage(s8 ant_power)
482{
483 if ((ant_power <= -100) || (ant_power >= 20))
484 return 0;
485 else if (ant_power >= 0)
486 return 100;
487 else
488 return 100 + ant_power;
489}
490
491/*
492 * 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer.
493 * IF other SW team do not support the feature, remove this section.??
494 */
495
496s32 odm_signal_scale_mapping(struct phy_dm_struct *dm, s32 curr_sig)
497{
498 {
499 return curr_sig;
500 }
501}
502
503static u8 odm_sq_process_patch_rt_cid_819x_lenovo(struct phy_dm_struct *dm,
504 u8 is_cck_rate, u8 pwdb_all,
505 u8 path, u8 RSSI)
506{
507 u8 sq = 0;
508 return sq;
509}
510
511static u8 odm_evm_db_to_percentage(s8 value)
512{
513 /* -33dB~0dB to 0%~99% */
514 s8 ret_val;
515
516 ret_val = value;
517 ret_val /= 2;
518
519 if (ret_val >= 0)
520 ret_val = 0;
521
522 if (ret_val <= -33)
523 ret_val = -33;
524
525 ret_val = 0 - ret_val;
526 ret_val *= 3;
527
528 if (ret_val == 99)
529 ret_val = 100;
530
531 return (u8)ret_val;
532}
533
534static u8 odm_evm_dbm_jaguar_series(s8 value)
535{
536 s8 ret_val = value;
537
538 /* -33dB~0dB to 33dB ~ 0dB */
539 if (ret_val == -128)
540 ret_val = 127;
541 else if (ret_val < 0)
542 ret_val = 0 - ret_val;
543
544 ret_val = ret_val >> 1;
545 return (u8)ret_val;
546}
547
548static s16 odm_cfo(s8 value)
549{
550 s16 ret_val;
551
552 if (value < 0) {
553 ret_val = 0 - value;
554 ret_val = (ret_val << 1) + (ret_val >> 1); /* *2.5~=312.5/2^7 */
555 ret_val =
556 ret_val | BIT(12); /* set bit12 as 1 for negative cfo */
557 } else {
558 ret_val = value;
559 ret_val = (ret_val << 1) + (ret_val >> 1); /* *2.5~=312.5/2^7 */
560 }
561 return ret_val;
562}
563
564static u8 phydm_rate_to_num_ss(struct phy_dm_struct *dm, u8 data_rate)
565{
566 u8 num_ss = 1;
567
568 if (data_rate <= ODM_RATE54M)
569 num_ss = 1;
570 else if (data_rate <= ODM_RATEMCS31)
571 num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;
572 else if (data_rate <= ODM_RATEVHTSS1MCS9)
573 num_ss = 1;
574 else if (data_rate <= ODM_RATEVHTSS2MCS9)
575 num_ss = 2;
576 else if (data_rate <= ODM_RATEVHTSS3MCS9)
577 num_ss = 3;
578 else if (data_rate <= ODM_RATEVHTSS4MCS9)
579 num_ss = 4;
580
581 return num_ss;
582}
583
584static void odm_rx_phy_status92c_series_parsing(
585 struct phy_dm_struct *dm, struct dm_phy_status_info *phy_info,
586 u8 *phy_status, struct dm_per_pkt_info *pktinfo)
587{
588 u8 i, max_spatial_stream;
589 s8 rx_pwr[4], rx_pwr_all = 0;
590 u8 EVM, pwdb_all = 0, pwdb_all_bt;
591 u8 RSSI, total_rssi = 0;
592 bool is_cck_rate = false;
593 u8 rf_rx_num = 0;
594 u8 LNA_idx = 0;
595 u8 VGA_idx = 0;
596 u8 cck_agc_rpt;
597 u8 num_ss;
598 struct phy_status_rpt_8192cd *phy_sta_rpt =
599 (struct phy_status_rpt_8192cd *)phy_status;
600
601 is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false;
602
603 if (pktinfo->is_to_self)
604 dm->curr_station_id = pktinfo->station_id;
605
606 phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1;
607 phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
608
609 if (is_cck_rate) {
610 dm->phy_dbg_info.num_qry_phy_status_cck++;
611 cck_agc_rpt = phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a;
612
613 if (dm->support_ic_type & (ODM_RTL8703B)) {
614 } else { /*3 bit LNA*/
615
616 LNA_idx = ((cck_agc_rpt & 0xE0) >> 5);
617 VGA_idx = (cck_agc_rpt & 0x1F);
618 }
619
620 ODM_RT_TRACE(
621 dm, ODM_COMP_RSSI_MONITOR,
622 "ext_lna_gain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n",
623 dm->ext_lna_gain, LNA_idx, VGA_idx, rx_pwr_all);
624
625 if (dm->board_type & ODM_BOARD_EXT_LNA)
626 rx_pwr_all -= dm->ext_lna_gain;
627
628 pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
629
630 if (pktinfo->is_to_self) {
631 dm->cck_lna_idx = LNA_idx;
632 dm->cck_vga_idx = VGA_idx;
633 }
634 phy_info->rx_pwdb_all = pwdb_all;
635
636 phy_info->bt_rx_rssi_percentage = pwdb_all;
637 phy_info->recv_signal_power = rx_pwr_all;
638 /* (3) Get Signal Quality (EVM) */
639 {
640 u8 sq;
641
642 sq = phydm_get_signal_quality_8192(phy_info, dm,
643 phy_sta_rpt);
644 phy_info->signal_quality = sq;
645 phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = sq;
646 phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
647 }
648
649 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) {
650 if (i == 0)
651 phy_info->rx_mimo_signal_strength[0] = pwdb_all;
652 else
653 phy_info->rx_mimo_signal_strength[1] = 0;
654 }
655 } else { /* 2 is OFDM rate */
656 dm->phy_dbg_info.num_qry_phy_status_ofdm++;
657
658 /* */
659 /* (1)Get RSSI for HT rate */
660 /* */
661
662 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) {
663 /* 2008/01/30 MH we will judge RF RX path now. */
664 if (dm->rf_path_rx_enable & BIT(i))
665 rf_rx_num++;
666 /* else */
667 /* continue; */
668
669 rx_pwr[i] =
670 ((phy_sta_rpt->path_agc[i].gain & 0x3F) * 2) -
671 110;
672
673 if (pktinfo->is_to_self) {
674 dm->ofdm_agc_idx[i] =
675 (phy_sta_rpt->path_agc[i].gain & 0x3F);
676 /**/
677 }
678
679 phy_info->rx_pwr[i] = rx_pwr[i];
680
681 /* Translate DBM to percentage. */
682 RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]);
683 total_rssi += RSSI;
684
685 phy_info->rx_mimo_signal_strength[i] = (u8)RSSI;
686
687 /* Get Rx snr value in DB */
688 dm->phy_dbg_info.rx_snr_db[i] =
689 (s32)(phy_sta_rpt->path_rxsnr[i] / 2);
690 phy_info->rx_snr[i] = dm->phy_dbg_info.rx_snr_db[i];
691
692 /* Record Signal Strength for next packet */
693 /* if(pktinfo->is_packet_match_bssid) */
694 {
695 }
696 }
697
698 /* */
699 /* (2)PWDB, Average PWDB calcuated by hardware (for RA) */
700 /* */
701 rx_pwr_all = (((phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all) >> 1) &
702 0x7f) -
703 110;
704
705 pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
706 pwdb_all_bt = pwdb_all;
707
708 phy_info->rx_pwdb_all = pwdb_all;
709 phy_info->bt_rx_rssi_percentage = pwdb_all_bt;
710 phy_info->rx_power = rx_pwr_all;
711 phy_info->recv_signal_power = rx_pwr_all;
712
713 if ((dm->support_platform == ODM_WIN) && (dm->patch_id == 19)) {
714 /* do nothing */
715 } else if ((dm->support_platform == ODM_WIN) &&
716 (dm->patch_id == 25)) {
717 /* do nothing */
718 } else { /* mgnt_info->customer_id != RT_CID_819X_LENOVO */
719 /* */
720 /* (3)EVM of HT rate */
721 /* */
722 if (pktinfo->data_rate >= ODM_RATEMCS8 &&
723 pktinfo->data_rate <= ODM_RATEMCS15) {
724 /* both spatial stream make sense */
725 max_spatial_stream = 2;
726 } else {
727 /* only spatial stream 1 makes sense */
728 max_spatial_stream = 1;
729 }
730
731 for (i = 0; i < max_spatial_stream; i++) {
732 /*Don't use shift operation like "rx_evmX >>= 1"
733 *because the compilor of free build environment
734 *fill most significant bit to "zero" when doing
735 *shifting operation which may change a negative
736 *value to positive one, then the dbm value
737 *(which is supposed to be negative) is not
738 *correct anymore.
739 */
740 EVM = odm_evm_db_to_percentage(
741 (phy_sta_rpt
742 ->stream_rxevm[i])); /* dbm */
743
744 /* Fill value in RFD, Get the first spatial
745 * stream only
746 */
747 if (i == ODM_RF_PATH_A)
748 phy_info->signal_quality =
749 (u8)(EVM & 0xff);
750 phy_info->rx_mimo_signal_quality[i] =
751 (u8)(EVM & 0xff);
752 }
753 }
754
755 num_ss = phydm_rate_to_num_ss(dm, pktinfo->data_rate);
756 odm_parsing_cfo(dm, pktinfo, phy_sta_rpt->path_cfotail, num_ss);
757 }
758 /* UI BSS List signal strength(in percentage), make it good looking,
759 * from 0~100.
760 */
761 /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
762 if (is_cck_rate) {
763 phy_info->signal_strength = (u8)(
764 odm_signal_scale_mapping(dm, pwdb_all)); /*pwdb_all;*/
765 } else {
766 if (rf_rx_num != 0) {
767 phy_info->signal_strength =
768 (u8)(odm_signal_scale_mapping(dm, total_rssi /=
769 rf_rx_num));
770 }
771 }
772
773 /* For 92C/92D HW (Hybrid) Antenna Diversity */
774}
775
776static void
777odm_rx_phy_bw_jaguar_series_parsing(struct dm_phy_status_info *phy_info,
778 struct dm_per_pkt_info *pktinfo,
779 struct phy_status_rpt_8812 *phy_sta_rpt)
780{
781 if (pktinfo->data_rate <= ODM_RATE54M) {
782 switch (phy_sta_rpt->r_RFMOD) {
783 case 1:
784 if (phy_sta_rpt->sub_chnl == 0)
785 phy_info->band_width = 1;
786 else
787 phy_info->band_width = 0;
788 break;
789
790 case 2:
791 if (phy_sta_rpt->sub_chnl == 0)
792 phy_info->band_width = 2;
793 else if (phy_sta_rpt->sub_chnl == 9 ||
794 phy_sta_rpt->sub_chnl == 10)
795 phy_info->band_width = 1;
796 else
797 phy_info->band_width = 0;
798 break;
799
800 default:
801 case 0:
802 phy_info->band_width = 0;
803 break;
804 }
805 }
806}
807
808static void odm_rx_phy_status_jaguar_series_parsing(
809 struct phy_dm_struct *dm, struct dm_phy_status_info *phy_info,
810 u8 *phy_status, struct dm_per_pkt_info *pktinfo)
811{
812 u8 i, max_spatial_stream;
813 s8 rx_pwr[4], rx_pwr_all = 0;
814 u8 EVM = 0, evm_dbm, pwdb_all = 0, pwdb_all_bt;
815 u8 RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0;
816 u8 is_cck_rate = 0;
817 u8 rf_rx_num = 0;
818 u8 cck_highpwr = 0;
819 u8 LNA_idx, VGA_idx;
820 struct phy_status_rpt_8812 *phy_sta_rpt =
821 (struct phy_status_rpt_8812 *)phy_status;
822 struct fast_antenna_training *fat_tab = &dm->dm_fat_table;
823 u8 num_ss;
824
825 odm_rx_phy_bw_jaguar_series_parsing(phy_info, pktinfo, phy_sta_rpt);
826
827 if (pktinfo->data_rate <= ODM_RATE11M)
828 is_cck_rate = true;
829 else
830 is_cck_rate = false;
831
832 if (pktinfo->is_to_self)
833 dm->curr_station_id = pktinfo->station_id;
834 else
835 dm->curr_station_id = 0xff;
836
837 phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1;
838 phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
839 phy_info->rx_mimo_signal_quality[ODM_RF_PATH_C] = -1;
840 phy_info->rx_mimo_signal_quality[ODM_RF_PATH_D] = -1;
841
842 if (is_cck_rate) {
843 u8 cck_agc_rpt;
844
845 dm->phy_dbg_info.num_qry_phy_status_cck++;
846
847 /*(1)Hardware does not provide RSSI for CCK*/
848 /*(2)PWDB, Average PWDB calculated by hardware (for RA)*/
849
850 cck_highpwr = dm->is_cck_high_power;
851
852 cck_agc_rpt = phy_sta_rpt->cfosho[0];
853 LNA_idx = ((cck_agc_rpt & 0xE0) >> 5);
854 VGA_idx = (cck_agc_rpt & 0x1F);
855
856 if (dm->support_ic_type == ODM_RTL8812) {
857 rx_pwr_all =
858 phydm_get_rx_pwr(LNA_idx, VGA_idx, cck_highpwr);
859 rx_pwr_all += 6;
860 pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
861 pwdb_all = phydm_adjust_pwdb(cck_highpwr, pwdb_all);
862
863 } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
864 s8 pout = -6;
865
866 switch (LNA_idx) {
867 case 5:
868 rx_pwr_all = pout - 32 - (2 * VGA_idx);
869 break;
870 case 4:
871 rx_pwr_all = pout - 24 - (2 * VGA_idx);
872 break;
873 case 2:
874 rx_pwr_all = pout - 11 - (2 * VGA_idx);
875 break;
876 case 1:
877 rx_pwr_all = pout + 5 - (2 * VGA_idx);
878 break;
879 case 0:
880 rx_pwr_all = pout + 21 - (2 * VGA_idx);
881 break;
882 }
883 pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
884 } else if (dm->support_ic_type == ODM_RTL8814A ||
885 dm->support_ic_type == ODM_RTL8822B) {
886 s8 pout = -6;
887
888 switch (LNA_idx) {
889 /*CCK only use LNA: 2, 3, 5, 7*/
890 case 7:
891 rx_pwr_all = pout - 32 - (2 * VGA_idx);
892 break;
893 case 5:
894 rx_pwr_all = pout - 22 - (2 * VGA_idx);
895 break;
896 case 3:
897 rx_pwr_all = pout - 2 - (2 * VGA_idx);
898 break;
899 case 2:
900 rx_pwr_all = pout + 5 - (2 * VGA_idx);
901 break;
902 default:
903 break;
904 }
905 pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
906 }
907
908 dm->cck_lna_idx = LNA_idx;
909 dm->cck_vga_idx = VGA_idx;
910 phy_info->rx_pwdb_all = pwdb_all;
911 phy_info->bt_rx_rssi_percentage = pwdb_all;
912 phy_info->recv_signal_power = rx_pwr_all;
913 /*(3) Get Signal Quality (EVM)*/
914 {
915 u8 sq;
916
917 if ((dm->support_platform == ODM_WIN) &&
918 (dm->patch_id == RT_CID_819X_LENOVO))
919 sq = odm_sq_process_patch_rt_cid_819x_lenovo(
920 dm, is_cck_rate, pwdb_all, 0, 0);
921 else
922 sq = phydm_get_signal_quality_8812(phy_info, dm,
923 phy_sta_rpt);
924
925 phy_info->signal_quality = sq;
926 phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = sq;
927 }
928
929 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
930 if (i == 0)
931 phy_info->rx_mimo_signal_strength[0] = pwdb_all;
932 else
933 phy_info->rx_mimo_signal_strength[i] = 0;
934 }
935 } else {
936 /*is OFDM rate*/
937 fat_tab->hw_antsw_occur = phy_sta_rpt->hw_antsw_occur;
938
939 dm->phy_dbg_info.num_qry_phy_status_ofdm++;
940
941 /*(1)Get RSSI for OFDM rate*/
942
943 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
944 /*2008/01/30 MH we will judge RF RX path now.*/
945 if (dm->rf_path_rx_enable & BIT(i))
946 rf_rx_num++;
947 /*2012.05.25 LukeLee: Testchip AGC report is wrong,
948 *it should be restored back to old formula in MP chip
949 */
950 if (i < ODM_RF_PATH_C)
951 rx_pwr[i] = (phy_sta_rpt->gain_trsw[i] & 0x7F) -
952 110;
953 else
954 rx_pwr[i] = (phy_sta_rpt->gain_trsw_cd[i - 2] &
955 0x7F) -
956 110;
957
958 phy_info->rx_pwr[i] = rx_pwr[i];
959
960 /* Translate DBM to percentage. */
961 RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]);
962
963 /*total_rssi += RSSI;*/
964 /*Get the best two RSSI*/
965 if (RSSI > best_rssi && RSSI > second_rssi) {
966 second_rssi = best_rssi;
967 best_rssi = RSSI;
968 } else if (RSSI > second_rssi && RSSI <= best_rssi) {
969 second_rssi = RSSI;
970 }
971
972 phy_info->rx_mimo_signal_strength[i] = (u8)RSSI;
973
974 /*Get Rx snr value in DB*/
975 if (i < ODM_RF_PATH_C)
976 phy_info->rx_snr[i] =
977 dm->phy_dbg_info.rx_snr_db[i] =
978 phy_sta_rpt->rxsnr[i] / 2;
979 else if (dm->support_ic_type &
980 (ODM_RTL8814A | ODM_RTL8822B))
981 phy_info->rx_snr[i] = dm->phy_dbg_info
982 .rx_snr_db[i] =
983 phy_sta_rpt->csi_current[i - 2] / 2;
984
985 /*(2) CFO_short & CFO_tail*/
986 if (i < ODM_RF_PATH_C) {
987 phy_info->cfo_short[i] =
988 odm_cfo((phy_sta_rpt->cfosho[i]));
989 phy_info->cfo_tail[i] =
990 odm_cfo((phy_sta_rpt->cfotail[i]));
991 }
992 }
993
994 /*(3)PWDB, Average PWDB calculated by hardware (for RA)*/
995
996 /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be
997 *restored back to old formula in MP chip
998 */
999 if ((dm->support_ic_type &
1000 (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) &&
1001 (!dm->is_mp_chip))
1002 rx_pwr_all = (phy_sta_rpt->pwdb_all & 0x7f) - 110;
1003 else
1004 rx_pwr_all = (((phy_sta_rpt->pwdb_all) >> 1) & 0x7f) -
1005 110; /*OLD FORMULA*/
1006
1007 pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
1008 pwdb_all_bt = pwdb_all;
1009
1010 phy_info->rx_pwdb_all = pwdb_all;
1011 phy_info->bt_rx_rssi_percentage = pwdb_all_bt;
1012 phy_info->rx_power = rx_pwr_all;
1013 phy_info->recv_signal_power = rx_pwr_all;
1014
1015 if ((dm->support_platform == ODM_WIN) && (dm->patch_id == 19)) {
1016 /*do nothing*/
1017 } else {
1018 /*mgnt_info->customer_id != RT_CID_819X_LENOVO*/
1019
1020 /*(4)EVM of OFDM rate*/
1021
1022 if ((pktinfo->data_rate >= ODM_RATEMCS8) &&
1023 (pktinfo->data_rate <= ODM_RATEMCS15))
1024 max_spatial_stream = 2;
1025 else if ((pktinfo->data_rate >= ODM_RATEVHTSS2MCS0) &&
1026 (pktinfo->data_rate <= ODM_RATEVHTSS2MCS9))
1027 max_spatial_stream = 2;
1028 else if ((pktinfo->data_rate >= ODM_RATEMCS16) &&
1029 (pktinfo->data_rate <= ODM_RATEMCS23))
1030 max_spatial_stream = 3;
1031 else if ((pktinfo->data_rate >= ODM_RATEVHTSS3MCS0) &&
1032 (pktinfo->data_rate <= ODM_RATEVHTSS3MCS9))
1033 max_spatial_stream = 3;
1034 else
1035 max_spatial_stream = 1;
1036
1037 for (i = 0; i < max_spatial_stream; i++) {
1038 /*Don't use shift operation like "rx_evmX >>= 1"
1039 *because the compilor of free build environment
1040 *fill most significant bit to "zero" when doing
1041 *shifting operation which may change a negative
1042 *value to positive one, then the dbm value
1043 *(which is supposed to be negative) is not
1044 *correct anymore.
1045 */
1046
1047 EVM = phydm_get_odm_evm(i, pktinfo,
1048 phy_sta_rpt);
1049 evm_dbm = phydm_get_evm_dbm(i, EVM, phy_sta_rpt,
1050 phy_info);
1051 phy_info->rx_mimo_signal_quality[i] = EVM;
1052 phy_info->rx_mimo_evm_dbm[i] = evm_dbm;
1053 }
1054 }
1055
1056 num_ss = phydm_rate_to_num_ss(dm, pktinfo->data_rate);
1057 odm_parsing_cfo(dm, pktinfo, phy_sta_rpt->cfotail, num_ss);
1058 }
1059
1060 /*UI BSS List signal strength(in percentage), make it good looking,
1061 *from 0~100.
1062 */
1063 /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/
1064 if (is_cck_rate) {
1065 phy_info->signal_strength = (u8)(
1066 odm_signal_scale_mapping(dm, pwdb_all)); /*pwdb_all;*/
1067 } else {
1068 if (rf_rx_num != 0) {
1069 /* 2015/01 Sean, use the best two RSSI only,
1070 * suggested by Ynlin and ChenYu.
1071 */
1072 if (rf_rx_num == 1)
1073 avg_rssi = best_rssi;
1074 else
1075 avg_rssi = (best_rssi + second_rssi) / 2;
1076 phy_info->signal_strength =
1077 (u8)(odm_signal_scale_mapping(dm, avg_rssi));
1078 }
1079 }
1080 dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all;
1081
1082 dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->antidx_anta;
1083 dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->antidx_antb;
1084 dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antidx_antc;
1085 dm->dm_fat_table.antsel_rx_keep_3 = phy_sta_rpt->antidx_antd;
1086}
1087
1088void phydm_reset_rssi_for_dm(struct phy_dm_struct *dm, u8 station_id)
1089{
1090 struct rtl_sta_info *entry;
1091
1092 entry = dm->odm_sta_info[station_id];
1093
1094 if (!IS_STA_VALID(entry))
1095 return;
1096
1097 ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
1098 "Reset RSSI for macid = (( %d ))\n", station_id);
1099
1100 entry->rssi_stat.undecorated_smoothed_cck = -1;
1101 entry->rssi_stat.undecorated_smoothed_ofdm = -1;
1102 entry->rssi_stat.undecorated_smoothed_pwdb = -1;
1103 entry->rssi_stat.ofdm_pkt = 0;
1104 entry->rssi_stat.cck_pkt = 0;
1105 entry->rssi_stat.cck_sum_power = 0;
1106 entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;
1107 entry->rssi_stat.packet_map = 0;
1108 entry->rssi_stat.valid_bit = 0;
1109}
1110
1111void odm_init_rssi_for_dm(struct phy_dm_struct *dm) {}
1112
1113static void odm_process_rssi_for_dm(struct phy_dm_struct *dm,
1114 struct dm_phy_status_info *phy_info,
1115 struct dm_per_pkt_info *pktinfo)
1116{
1117 s32 undecorated_smoothed_pwdb, undecorated_smoothed_cck,
1118 undecorated_smoothed_ofdm;
1119 u8 is_cck_rate = 0;
1120 u8 send_rssi_2_fw = 0;
1121 struct rtl_sta_info *entry;
1122
1123 if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
1124 return;
1125
1126 /* 2012/05/30 MH/Luke.Lee Add some description */
1127 /* In windows driver: AP/IBSS mode STA */
1128 entry = dm->odm_sta_info[pktinfo->station_id];
1129
1130 if (!IS_STA_VALID(entry))
1131 return;
1132
1133 {
1134 if ((!pktinfo->is_packet_match_bssid)) /*data frame only*/
1135 return;
1136 }
1137
1138 if (pktinfo->is_packet_beacon)
1139 dm->phy_dbg_info.num_qry_beacon_pkt++;
1140
1141 is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false;
1142 dm->rx_rate = pktinfo->data_rate;
1143
1144 /* --------------Statistic for antenna/path diversity---------------- */
1145
1146 /* -----------------Smart Antenna Debug Message------------------ */
1147
1148 undecorated_smoothed_cck = entry->rssi_stat.undecorated_smoothed_cck;
1149 undecorated_smoothed_ofdm = entry->rssi_stat.undecorated_smoothed_ofdm;
1150 undecorated_smoothed_pwdb = entry->rssi_stat.undecorated_smoothed_pwdb;
1151
1152 if (pktinfo->is_packet_to_self || pktinfo->is_packet_beacon) {
1153 if (!is_cck_rate) /* ofdm rate */
1154 undecorated_smoothed_ofdm = phydm_process_rssi_ofdm(
1155 dm, phy_info, entry, undecorated_smoothed_ofdm);
1156 else
1157 undecorated_smoothed_cck = phydm_process_rssi_cck(
1158 dm, phy_info, entry, undecorated_smoothed_cck);
1159
1160 undecorated_smoothed_pwdb = phydm_process_rssi_pwdb(
1161 dm, entry, pktinfo, undecorated_smoothed_ofdm,
1162 undecorated_smoothed_cck);
1163
1164 if ((entry->rssi_stat.ofdm_pkt >= 1 ||
1165 entry->rssi_stat.cck_pkt >= 5) &&
1166 (entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) {
1167 send_rssi_2_fw = 1;
1168 entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_SEND;
1169 }
1170
1171 entry->rssi_stat.undecorated_smoothed_cck =
1172 undecorated_smoothed_cck;
1173 entry->rssi_stat.undecorated_smoothed_ofdm =
1174 undecorated_smoothed_ofdm;
1175 entry->rssi_stat.undecorated_smoothed_pwdb =
1176 undecorated_smoothed_pwdb;
1177
1178 if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
1179
1180 if (entry->rssi_stat.ofdm_pkt != 0)
1181 entry->rssi_stat.undecorated_smoothed_pwdb =
1182 undecorated_smoothed_ofdm;
1183
1184 ODM_RT_TRACE(
1185 dm, ODM_COMP_RSSI_MONITOR,
1186 "[Send to FW] PWDB = (( %d )), ofdm_pkt = (( %d )), cck_pkt = (( %d ))\n",
1187 undecorated_smoothed_pwdb,
1188 entry->rssi_stat.ofdm_pkt,
1189 entry->rssi_stat.cck_pkt);
1190 }
1191 }
1192}
1193
1194/*
1195 * Endianness before calling this API
1196 */
1197static void odm_phy_status_query_92c_series(struct phy_dm_struct *dm,
1198 struct dm_phy_status_info *phy_info,
1199 u8 *phy_status,
1200 struct dm_per_pkt_info *pktinfo)
1201{
1202 odm_rx_phy_status92c_series_parsing(dm, phy_info, phy_status, pktinfo);
1203 odm_process_rssi_for_dm(dm, phy_info, pktinfo);
1204}
1205
1206/*
1207 * Endianness before calling this API
1208 */
1209
1210static void odm_phy_status_query_jaguar_series(
1211 struct phy_dm_struct *dm, struct dm_phy_status_info *phy_info,
1212 u8 *phy_status, struct dm_per_pkt_info *pktinfo)
1213{
1214 odm_rx_phy_status_jaguar_series_parsing(dm, phy_info, phy_status,
1215 pktinfo);
1216 odm_process_rssi_for_dm(dm, phy_info, pktinfo);
1217}
1218
1219void odm_phy_status_query(struct phy_dm_struct *dm,
1220 struct dm_phy_status_info *phy_info, u8 *phy_status,
1221 struct dm_per_pkt_info *pktinfo)
1222{
1223 if (dm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) {
1224 phydm_rx_phy_status_new_type(dm, phy_status, pktinfo, phy_info);
1225 return;
1226 }
1227
1228 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
1229 odm_phy_status_query_jaguar_series(dm, phy_info, phy_status,
1230 pktinfo);
1231
1232 if (dm->support_ic_type & ODM_IC_11N_SERIES)
1233 odm_phy_status_query_92c_series(dm, phy_info, phy_status,
1234 pktinfo);
1235}
1236
1237/* For future use. */
1238void odm_mac_status_query(struct phy_dm_struct *dm, u8 *mac_status, u8 mac_id,
1239 bool is_packet_match_bssid, bool is_packet_to_self,
1240 bool is_packet_beacon)
1241{
1242 /* 2011/10/19 Driver team will handle in the future. */
1243}
1244
1245/*
1246 * If you want to add a new IC, Please follow below template and generate
1247 * a new one.
1248 */
1249
1250enum hal_status
1251odm_config_rf_with_header_file(struct phy_dm_struct *dm,
1252 enum odm_rf_config_type config_type,
1253 enum odm_rf_radio_path e_rf_path)
1254{
1255 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1256 "===>%s (%s)\n", __func__,
1257 (dm->is_mp_chip) ? "MPChip" : "TestChip");
1258 ODM_RT_TRACE(
1259 dm, ODM_COMP_INIT,
1260 "dm->support_platform: 0x%X, dm->support_interface: 0x%X, dm->board_type: 0x%X\n",
1261 dm->support_platform, dm->support_interface, dm->board_type);
1262
1263 /* 1 AP doesn't use PHYDM power tracking table in these ICs */
1264 /* JJ ADD 20161014 */
1265
1266 /* 1 All platforms support */
1267 if (dm->support_ic_type == ODM_RTL8822B) {
1268 if (config_type == CONFIG_RF_RADIO) {
1269 if (e_rf_path == ODM_RF_PATH_A)
1270 READ_AND_CONFIG_MP(8822b, _radioa);
1271 else if (e_rf_path == ODM_RF_PATH_B)
1272 READ_AND_CONFIG_MP(8822b, _radiob);
1273 } else if (config_type == CONFIG_RF_TXPWR_LMT) {
1274 if (dm->rfe_type == 5)
1275 READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5);
1276 else
1277 READ_AND_CONFIG_MP(8822b, _txpwr_lmt);
1278 }
1279 }
1280
1281 return HAL_STATUS_SUCCESS;
1282}
1283
1284enum hal_status
1285odm_config_rf_with_tx_pwr_track_header_file(struct phy_dm_struct *dm)
1286{
1287 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1288 "===>%s (%s)\n", __func__,
1289 (dm->is_mp_chip) ? "MPChip" : "TestChip");
1290 ODM_RT_TRACE(
1291 dm, ODM_COMP_INIT,
1292 "dm->support_platform: 0x%X, dm->support_interface: 0x%X, dm->board_type: 0x%X\n",
1293 dm->support_platform, dm->support_interface, dm->board_type);
1294
1295 /* 1 AP doesn't use PHYDM power tracking table in these ICs */
1296 /* JJ ADD 20161014 */
1297
1298 /* 1 All platforms support */
1299
1300 if (dm->support_ic_type == ODM_RTL8822B) {
1301 if (dm->rfe_type == 0)
1302 READ_AND_CONFIG_MP(8822b, _txpowertrack_type0);
1303 else if (dm->rfe_type == 1)
1304 READ_AND_CONFIG_MP(8822b, _txpowertrack_type1);
1305 else if (dm->rfe_type == 2)
1306 READ_AND_CONFIG_MP(8822b, _txpowertrack_type2);
1307 else if ((dm->rfe_type == 3) || (dm->rfe_type == 5))
1308 READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5);
1309 else if (dm->rfe_type == 4)
1310 READ_AND_CONFIG_MP(8822b, _txpowertrack_type4);
1311 else if (dm->rfe_type == 6)
1312 READ_AND_CONFIG_MP(8822b, _txpowertrack_type6);
1313 else if (dm->rfe_type == 7)
1314 READ_AND_CONFIG_MP(8822b, _txpowertrack_type7);
1315 else if (dm->rfe_type == 8)
1316 READ_AND_CONFIG_MP(8822b, _txpowertrack_type8);
1317 else if (dm->rfe_type == 9)
1318 READ_AND_CONFIG_MP(8822b, _txpowertrack_type9);
1319 else
1320 READ_AND_CONFIG_MP(8822b, _txpowertrack);
1321 }
1322
1323 return HAL_STATUS_SUCCESS;
1324}
1325
1326enum hal_status
1327odm_config_bb_with_header_file(struct phy_dm_struct *dm,
1328 enum odm_bb_config_type config_type)
1329{
1330 /* 1 AP doesn't use PHYDM initialization in these ICs */
1331 /* JJ ADD 20161014 */
1332
1333 /* 1 All platforms support */
1334 if (dm->support_ic_type == ODM_RTL8822B) {
1335 if (config_type == CONFIG_BB_PHY_REG)
1336 READ_AND_CONFIG_MP(8822b, _phy_reg);
1337 else if (config_type == CONFIG_BB_AGC_TAB)
1338 READ_AND_CONFIG_MP(8822b, _agc_tab);
1339 else if (config_type == CONFIG_BB_PHY_REG_PG)
1340 READ_AND_CONFIG_MP(8822b, _phy_reg_pg);
1341 /*else if (config_type == CONFIG_BB_PHY_REG_MP)*/
1342 /*READ_AND_CONFIG_MP(8822b, _phy_reg_mp);*/
1343 }
1344
1345 return HAL_STATUS_SUCCESS;
1346}
1347
1348enum hal_status odm_config_mac_with_header_file(struct phy_dm_struct *dm)
1349{
1350 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1351 "===>%s (%s)\n", __func__,
1352 (dm->is_mp_chip) ? "MPChip" : "TestChip");
1353 ODM_RT_TRACE(
1354 dm, ODM_COMP_INIT,
1355 "dm->support_platform: 0x%X, dm->support_interface: 0x%X, dm->board_type: 0x%X\n",
1356 dm->support_platform, dm->support_interface, dm->board_type);
1357
1358 /* 1 AP doesn't use PHYDM initialization in these ICs */
1359 /* JJ ADD 20161014 */
1360
1361 /* 1 All platforms support */
1362 if (dm->support_ic_type == ODM_RTL8822B)
1363 READ_AND_CONFIG_MP(8822b, _mac_reg);
1364
1365 return HAL_STATUS_SUCCESS;
1366}
1367
1368enum hal_status
1369odm_config_fw_with_header_file(struct phy_dm_struct *dm,
1370 enum odm_fw_config_type config_type,
1371 u8 *p_firmware, u32 *size)
1372{
1373 return HAL_STATUS_SUCCESS;
1374}
1375
1376u32 odm_get_hw_img_version(struct phy_dm_struct *dm)
1377{
1378 u32 version = 0;
1379
1380 /* 1 AP doesn't use PHYDM initialization in these ICs */
1381 /* JJ ADD 20161014 */
1382
1383 /*1 All platforms support*/
1384 if (dm->support_ic_type == ODM_RTL8822B)
1385 version = GET_VERSION_MP(8822b, _mac_reg);
1386
1387 return version;
1388}
1389
1390/* For 8822B only!! need to move to FW finally */
1391/*==============================================*/
1392
1393bool phydm_query_is_mu_api(struct phy_dm_struct *phydm, u8 ppdu_idx,
1394 u8 *p_data_rate, u8 *p_gid)
1395{
1396 u8 data_rate = 0, gid = 0;
1397 bool is_mu = false;
1398
1399 data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];
1400 gid = phydm->phy_dbg_info.gid_num[ppdu_idx];
1401
1402 if (data_rate & BIT(7)) {
1403 is_mu = true;
1404 data_rate = data_rate & ~(BIT(7));
1405 } else {
1406 is_mu = false;
1407 }
1408
1409 *p_data_rate = data_rate;
1410 *p_gid = gid;
1411
1412 return is_mu;
1413}
1414
1415static void phydm_rx_statistic_cal(struct phy_dm_struct *phydm, u8 *phy_status,
1416 struct dm_per_pkt_info *pktinfo)
1417{
1418 struct phy_status_rpt_jaguar2_type1 *phy_sta_rpt =
1419 (struct phy_status_rpt_jaguar2_type1 *)phy_status;
1420 u8 date_rate = pktinfo->data_rate & ~(BIT(7));
1421
1422 if ((phy_sta_rpt->gid != 0) && (phy_sta_rpt->gid != 63)) {
1423 if (date_rate >= ODM_RATEVHTSS1MCS0) {
1424 phydm->phy_dbg_info
1425 .num_qry_mu_vht_pkt[date_rate - 0x2C]++;
1426 phydm->phy_dbg_info.num_of_ppdu[pktinfo->ppdu_cnt] =
1427 date_rate | BIT(7);
1428 phydm->phy_dbg_info.gid_num[pktinfo->ppdu_cnt] =
1429 phy_sta_rpt->gid;
1430 }
1431
1432 } else {
1433 if (date_rate >= ODM_RATEVHTSS1MCS0) {
1434 phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - 0x2C]++;
1435 phydm->phy_dbg_info.num_of_ppdu[pktinfo->ppdu_cnt] =
1436 date_rate;
1437 phydm->phy_dbg_info.gid_num[pktinfo->ppdu_cnt] =
1438 phy_sta_rpt->gid;
1439 }
1440 }
1441}
1442
1443static void phydm_reset_phy_info(struct phy_dm_struct *phydm,
1444 struct dm_phy_status_info *phy_info)
1445{
1446 phy_info->rx_pwdb_all = 0;
1447 phy_info->signal_quality = 0;
1448 phy_info->band_width = 0;
1449 phy_info->rx_count = 0;
1450 odm_memory_set(phydm, phy_info->rx_mimo_signal_quality, 0, 4);
1451 odm_memory_set(phydm, phy_info->rx_mimo_signal_strength, 0, 4);
1452 odm_memory_set(phydm, phy_info->rx_snr, 0, 4);
1453
1454 phy_info->rx_power = -110;
1455 phy_info->recv_signal_power = -110;
1456 phy_info->bt_rx_rssi_percentage = 0;
1457 phy_info->signal_strength = 0;
1458 phy_info->bt_coex_pwr_adjust = 0;
1459 phy_info->channel = 0;
1460 phy_info->is_mu_packet = 0;
1461 phy_info->is_beamformed = 0;
1462 phy_info->rxsc = 0;
1463 odm_memory_set(phydm, phy_info->rx_pwr, -110, 4);
1464 odm_memory_set(phydm, phy_info->rx_mimo_evm_dbm, 0, 4);
1465 odm_memory_set(phydm, phy_info->cfo_short, 0, 8);
1466 odm_memory_set(phydm, phy_info->cfo_tail, 0, 8);
1467}
1468
1469static void phydm_set_per_path_phy_info(u8 rx_path, s8 rx_pwr, s8 rx_evm,
1470 s8 cfo_tail, s8 rx_snr,
1471 struct dm_phy_status_info *phy_info)
1472{
1473 u8 evm_dbm = 0;
1474 u8 evm_percentage = 0;
1475
1476 /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
1477
1478 if (rx_evm < 0) {
1479 /* Calculate EVM in dBm */
1480 evm_dbm = ((u8)(0 - rx_evm) >> 1);
1481
1482 /* Calculate EVM in percentage */
1483 if (evm_dbm >= 33)
1484 evm_percentage = 100;
1485 else
1486 evm_percentage = (evm_dbm << 1) + (evm_dbm);
1487 }
1488
1489 phy_info->rx_pwr[rx_path] = rx_pwr;
1490 phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
1491
1492 /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/
1493 phy_info->cfo_tail[rx_path] = cfo_tail;
1494 phy_info->cfo_tail[rx_path] = ((phy_info->cfo_tail[rx_path] << 5) +
1495 (phy_info->cfo_tail[rx_path] << 2) +
1496 (phy_info->cfo_tail[rx_path] << 1) +
1497 (phy_info->cfo_tail[rx_path])) >>
1498 9;
1499
1500 phy_info->rx_mimo_signal_strength[rx_path] =
1501 odm_query_rx_pwr_percentage(rx_pwr);
1502 phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
1503 phy_info->rx_snr[rx_path] = rx_snr >> 1;
1504}
1505
1506static void phydm_set_common_phy_info(s8 rx_power, u8 channel,
1507 bool is_beamformed, bool is_mu_packet,
1508 u8 bandwidth, u8 signal_quality, u8 rxsc,
1509 struct dm_phy_status_info *phy_info)
1510{
1511 phy_info->rx_power = rx_power; /* RSSI in dB */
1512 phy_info->recv_signal_power = rx_power; /* RSSI in dB */
1513 phy_info->channel = channel; /* channel number */
1514 phy_info->is_beamformed = is_beamformed; /* apply BF */
1515 phy_info->is_mu_packet = is_mu_packet; /* MU packet */
1516 phy_info->rxsc = rxsc;
1517 phy_info->rx_pwdb_all =
1518 odm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */
1519 phy_info->signal_quality = signal_quality; /* signal quality */
1520 phy_info->band_width = bandwidth; /* bandwidth */
1521}
1522
1523static void phydm_get_rx_phy_status_type0(struct phy_dm_struct *dm,
1524 u8 *phy_status,
1525 struct dm_per_pkt_info *pktinfo,
1526 struct dm_phy_status_info *phy_info)
1527{
1528 /* type 0 is used for cck packet */
1529
1530 struct phy_status_rpt_jaguar2_type0 *phy_sta_rpt =
1531 (struct phy_status_rpt_jaguar2_type0 *)phy_status;
1532 u8 sq = 0;
1533 s8 rx_power = phy_sta_rpt->pwdb - 110;
1534
1535 /* JJ ADD 20161014 */
1536
1537 /* Calculate Signal Quality*/
1538 if (pktinfo->is_packet_match_bssid) {
1539 if (phy_sta_rpt->signal_quality >= 64) {
1540 sq = 0;
1541 } else if (phy_sta_rpt->signal_quality <= 20) {
1542 sq = 100;
1543 } else {
1544 /* mapping to 2~99% */
1545 sq = 64 - phy_sta_rpt->signal_quality;
1546 sq = ((sq << 3) + sq) >> 2;
1547 }
1548 }
1549
1550 /* Modify CCK PWDB if old AGC */
1551 if (!dm->cck_new_agc) {
1552 u8 lna_idx, vga_idx;
1553
1554 lna_idx = ((phy_sta_rpt->lna_h << 3) | phy_sta_rpt->lna_l);
1555 vga_idx = phy_sta_rpt->vga;
1556
1557 /* JJ ADD 20161014 */
1558
1559 /* Need to do !! */
1560 /*if (dm->support_ic_type & ODM_RTL8822B) */
1561 /*rx_power = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/
1562 }
1563
1564 /* Update CCK packet counter */
1565 dm->phy_dbg_info.num_qry_phy_status_cck++;
1566
1567 /*CCK no STBC and LDPC*/
1568 dm->phy_dbg_info.is_ldpc_pkt = false;
1569 dm->phy_dbg_info.is_stbc_pkt = false;
1570
1571 /* Update Common information */
1572 phydm_set_common_phy_info(rx_power, phy_sta_rpt->channel, false, false,
1573 ODM_BW20M, sq, phy_sta_rpt->rxsc, phy_info);
1574
1575 /* Update CCK pwdb */
1576 /* Update per-path information */
1577 phydm_set_per_path_phy_info(ODM_RF_PATH_A, rx_power, 0, 0, 0, phy_info);
1578
1579 dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->antidx_a;
1580 dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->antidx_b;
1581 dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antidx_c;
1582 dm->dm_fat_table.antsel_rx_keep_3 = phy_sta_rpt->antidx_d;
1583}
1584
1585static void phydm_get_rx_phy_status_type1(struct phy_dm_struct *dm,
1586 u8 *phy_status,
1587 struct dm_per_pkt_info *pktinfo,
1588 struct dm_phy_status_info *phy_info)
1589{
1590 /* type 1 is used for ofdm packet */
1591
1592 struct phy_status_rpt_jaguar2_type1 *phy_sta_rpt =
1593 (struct phy_status_rpt_jaguar2_type1 *)phy_status;
1594 s8 rx_pwr_db = -120;
1595 u8 i, rxsc, bw = ODM_BW20M, rx_count = 0;
1596 bool is_mu;
1597 u8 num_ss;
1598
1599 /* Update OFDM packet counter */
1600 dm->phy_dbg_info.num_qry_phy_status_ofdm++;
1601
1602 /* Update per-path information */
1603 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
1604 if (dm->rx_ant_status & BIT(i)) {
1605 s8 rx_path_pwr_db;
1606
1607 /* RX path counter */
1608 rx_count++;
1609
1610 /* Update per-path information
1611 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
1612 */
1613 /* EVM report is reported by stream, not path */
1614 rx_path_pwr_db = phy_sta_rpt->pwdb[i] -
1615 110; /* per-path pwdb in dB domain */
1616 phydm_set_per_path_phy_info(
1617 i, rx_path_pwr_db,
1618 phy_sta_rpt->rxevm[rx_count - 1],
1619 phy_sta_rpt->cfo_tail[i], phy_sta_rpt->rxsnr[i],
1620 phy_info);
1621
1622 /* search maximum pwdb */
1623 if (rx_path_pwr_db > rx_pwr_db)
1624 rx_pwr_db = rx_path_pwr_db;
1625 }
1626 }
1627
1628 /* mapping RX counter from 1~4 to 0~3 */
1629 if (rx_count > 0)
1630 phy_info->rx_count = rx_count - 1;
1631
1632 /* Check if MU packet or not */
1633 if ((phy_sta_rpt->gid != 0) && (phy_sta_rpt->gid != 63)) {
1634 is_mu = true;
1635 dm->phy_dbg_info.num_qry_mu_pkt++;
1636 } else {
1637 is_mu = false;
1638 }
1639
1640 /* count BF packet */
1641 dm->phy_dbg_info.num_qry_bf_pkt =
1642 dm->phy_dbg_info.num_qry_bf_pkt + phy_sta_rpt->beamformed;
1643
1644 /*STBC or LDPC pkt*/
1645 dm->phy_dbg_info.is_ldpc_pkt = phy_sta_rpt->ldpc;
1646 dm->phy_dbg_info.is_stbc_pkt = phy_sta_rpt->stbc;
1647
1648 /* Check sub-channel */
1649 if ((pktinfo->data_rate > ODM_RATE11M) &&
1650 (pktinfo->data_rate < ODM_RATEMCS0))
1651 rxsc = phy_sta_rpt->l_rxsc;
1652 else
1653 rxsc = phy_sta_rpt->ht_rxsc;
1654
1655 /* Check RX bandwidth */
1656 if (dm->support_ic_type & ODM_RTL8822B) {
1657 if ((rxsc >= 1) && (rxsc <= 8))
1658 bw = ODM_BW20M;
1659 else if ((rxsc >= 9) && (rxsc <= 12))
1660 bw = ODM_BW40M;
1661 else if (rxsc >= 13)
1662 bw = ODM_BW80M;
1663 else
1664 bw = phy_sta_rpt->rf_mode;
1665 } else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D |
1666 ODM_RTL8710B)) { /* JJ ADD 20161014 */
1667 if (phy_sta_rpt->rf_mode == 0)
1668 bw = ODM_BW20M;
1669 else if ((rxsc == 1) || (rxsc == 2))
1670 bw = ODM_BW20M;
1671 else
1672 bw = ODM_BW40M;
1673 }
1674
1675 /* Update packet information */
1676 phydm_set_common_phy_info(
1677 rx_pwr_db, phy_sta_rpt->channel, (bool)phy_sta_rpt->beamformed,
1678 is_mu, bw, odm_evm_db_to_percentage(phy_sta_rpt->rxevm[0]),
1679 rxsc, phy_info);
1680
1681 num_ss = phydm_rate_to_num_ss(dm, pktinfo->data_rate);
1682
1683 odm_parsing_cfo(dm, pktinfo, phy_sta_rpt->cfo_tail, num_ss);
1684 dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->antidx_a;
1685 dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->antidx_b;
1686 dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antidx_c;
1687 dm->dm_fat_table.antsel_rx_keep_3 = phy_sta_rpt->antidx_d;
1688
1689 if (pktinfo->is_packet_match_bssid) {
1690 /* */
1691 phydm_rx_statistic_cal(dm, phy_status, pktinfo);
1692 }
1693}
1694
1695static void phydm_get_rx_phy_status_type2(struct phy_dm_struct *dm,
1696 u8 *phy_status,
1697 struct dm_per_pkt_info *pktinfo,
1698 struct dm_phy_status_info *phy_info)
1699{
1700 struct phy_status_rpt_jaguar2_type2 *phy_sta_rpt =
1701 (struct phy_status_rpt_jaguar2_type2 *)phy_status;
1702 s8 rx_pwr_db = -120;
1703 u8 i, rxsc, bw = ODM_BW20M, rx_count = 0;
1704
1705 /* Update OFDM packet counter */
1706 dm->phy_dbg_info.num_qry_phy_status_ofdm++;
1707
1708 /* Update per-path information */
1709 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
1710 if (dm->rx_ant_status & BIT(i)) {
1711 s8 rx_path_pwr_db;
1712
1713 /* RX path counter */
1714 rx_count++;
1715
1716 /* Update per-path information
1717 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
1718 */
1719 rx_path_pwr_db = phy_sta_rpt->pwdb[i] -
1720 110; /* per-path pwdb in dB domain */
1721
1722 phydm_set_per_path_phy_info(i, rx_path_pwr_db, 0, 0, 0,
1723 phy_info);
1724
1725 /* search maximum pwdb */
1726 if (rx_path_pwr_db > rx_pwr_db)
1727 rx_pwr_db = rx_path_pwr_db;
1728 }
1729 }
1730
1731 /* mapping RX counter from 1~4 to 0~3 */
1732 if (rx_count > 0)
1733 phy_info->rx_count = rx_count - 1;
1734
1735 /* Check RX sub-channel */
1736 if ((pktinfo->data_rate > ODM_RATE11M) &&
1737 (pktinfo->data_rate < ODM_RATEMCS0))
1738 rxsc = phy_sta_rpt->l_rxsc;
1739 else
1740 rxsc = phy_sta_rpt->ht_rxsc;
1741
1742 /*STBC or LDPC pkt*/
1743 dm->phy_dbg_info.is_ldpc_pkt = phy_sta_rpt->ldpc;
1744 dm->phy_dbg_info.is_stbc_pkt = phy_sta_rpt->stbc;
1745
1746 /* Check RX bandwidth */
1747 /* the BW information of sc=0 is useless, because there is
1748 * no information of RF mode
1749 */
1750
1751 if (dm->support_ic_type & ODM_RTL8822B) {
1752 if ((rxsc >= 1) && (rxsc <= 8))
1753 bw = ODM_BW20M;
1754 else if ((rxsc >= 9) && (rxsc <= 12))
1755 bw = ODM_BW40M;
1756 else if (rxsc >= 13)
1757 bw = ODM_BW80M;
1758 else
1759 bw = ODM_BW20M;
1760 } else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D |
1761 ODM_RTL8710B)) { /* JJ ADD 20161014 */
1762 if (rxsc == 3)
1763 bw = ODM_BW40M;
1764 else if ((rxsc == 1) || (rxsc == 2))
1765 bw = ODM_BW20M;
1766 else
1767 bw = ODM_BW20M;
1768 }
1769
1770 /* Update packet information */
1771 phydm_set_common_phy_info(rx_pwr_db, phy_sta_rpt->channel,
1772 (bool)phy_sta_rpt->beamformed, false, bw, 0,
1773 rxsc, phy_info);
1774}
1775
1776static void
1777phydm_process_rssi_for_dm_new_type(struct phy_dm_struct *dm,
1778 struct dm_phy_status_info *phy_info,
1779 struct dm_per_pkt_info *pktinfo)
1780{
1781 s32 undecorated_smoothed_pwdb, accumulate_pwdb;
1782 u32 rssi_ave;
1783 u8 i;
1784 struct rtl_sta_info *entry;
1785 u8 scaling_factor = 4;
1786
1787 if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
1788 return;
1789
1790 entry = dm->odm_sta_info[pktinfo->station_id];
1791
1792 if (!IS_STA_VALID(entry))
1793 return;
1794
1795 if ((!pktinfo->is_packet_match_bssid)) /*data frame only*/
1796 return;
1797
1798 if (pktinfo->is_packet_beacon)
1799 dm->phy_dbg_info.num_qry_beacon_pkt++;
1800
1801 if (pktinfo->is_packet_to_self || pktinfo->is_packet_beacon) {
1802 u32 rssi_linear = 0;
1803
1804 dm->rx_rate = pktinfo->data_rate;
1805 undecorated_smoothed_pwdb =
1806 entry->rssi_stat.undecorated_smoothed_pwdb;
1807 accumulate_pwdb = dm->accumulate_pwdb[pktinfo->station_id];
1808 dm->rssi_a = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
1809 dm->rssi_b = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
1810 dm->rssi_c = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C];
1811 dm->rssi_d = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D];
1812
1813 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
1814 if (phy_info->rx_mimo_signal_strength[i] != 0)
1815 rssi_linear += odm_convert_to_linear(
1816 phy_info->rx_mimo_signal_strength[i]);
1817 }
1818
1819 switch (phy_info->rx_count + 1) {
1820 case 2:
1821 rssi_linear = (rssi_linear >> 1);
1822 break;
1823 case 3:
1824 /* rssi_linear/3 ~ rssi_linear*11/32 */
1825 rssi_linear = ((rssi_linear) + (rssi_linear << 1) +
1826 (rssi_linear << 3)) >>
1827 5;
1828 break;
1829 case 4:
1830 rssi_linear = (rssi_linear >> 2);
1831 break;
1832 }
1833 rssi_ave = odm_convert_to_db(rssi_linear);
1834
1835 if (undecorated_smoothed_pwdb <= 0) {
1836 accumulate_pwdb =
1837 (phy_info->rx_pwdb_all << scaling_factor);
1838 undecorated_smoothed_pwdb = phy_info->rx_pwdb_all;
1839 } else {
1840 accumulate_pwdb = accumulate_pwdb -
1841 (accumulate_pwdb >> scaling_factor) +
1842 rssi_ave;
1843 undecorated_smoothed_pwdb =
1844 (accumulate_pwdb +
1845 (1 << (scaling_factor - 1))) >>
1846 scaling_factor;
1847 }
1848
1849 entry->rssi_stat.undecorated_smoothed_pwdb =
1850 undecorated_smoothed_pwdb;
1851 dm->accumulate_pwdb[pktinfo->station_id] = accumulate_pwdb;
1852 }
1853}
1854
1855void phydm_rx_phy_status_new_type(struct phy_dm_struct *phydm, u8 *phy_status,
1856 struct dm_per_pkt_info *pktinfo,
1857 struct dm_phy_status_info *phy_info)
1858{
1859 u8 phy_status_type = (*phy_status & 0xf);
1860
1861 /* Memory reset */
1862 phydm_reset_phy_info(phydm, phy_info);
1863
1864 /* Phy status parsing */
1865 switch (phy_status_type) {
1866 case 0: {
1867 phydm_get_rx_phy_status_type0(phydm, phy_status, pktinfo,
1868 phy_info);
1869 break;
1870 }
1871 case 1: {
1872 phydm_get_rx_phy_status_type1(phydm, phy_status, pktinfo,
1873 phy_info);
1874 break;
1875 }
1876 case 2: {
1877 phydm_get_rx_phy_status_type2(phydm, phy_status, pktinfo,
1878 phy_info);
1879 break;
1880 }
1881 default:
1882 return;
1883 }
1884
1885 /* Update signal strength to UI, and phy_info->rx_pwdb_all is the
1886 * maximum RSSI of all path
1887 */
1888 phy_info->signal_strength =
1889 (u8)(odm_signal_scale_mapping(phydm, phy_info->rx_pwdb_all));
1890
1891 /* Calculate average RSSI and smoothed RSSI */
1892 phydm_process_rssi_for_dm_new_type(phydm, phy_info, pktinfo);
1893}
1894
1895u32 query_phydm_trx_capability(struct phy_dm_struct *dm)
1896{
1897 u32 value32 = 0xFFFFFFFF;
1898
1899 return value32;
1900}
1901
1902u32 query_phydm_stbc_capability(struct phy_dm_struct *dm)
1903{
1904 u32 value32 = 0xFFFFFFFF;
1905
1906 return value32;
1907}
1908
1909u32 query_phydm_ldpc_capability(struct phy_dm_struct *dm)
1910{
1911 u32 value32 = 0xFFFFFFFF;
1912
1913 return value32;
1914}
1915
1916u32 query_phydm_txbf_parameters(struct phy_dm_struct *dm)
1917{
1918 u32 value32 = 0xFFFFFFFF;
1919
1920 return value32;
1921}
1922
1923u32 query_phydm_txbf_capability(struct phy_dm_struct *dm)
1924{
1925 u32 value32 = 0xFFFFFFFF;
1926
1927 return value32;
1928}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_hwconfig.h b/drivers/staging/rtlwifi/phydm/phydm_hwconfig.h
new file mode 100644
index 000000000000..ec94c61df2b9
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_hwconfig.h
@@ -0,0 +1,510 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __HALHWOUTSRC_H__
27#define __HALHWOUTSRC_H__
28
29/*--------------------------Define -------------------------------------------*/
30#define CCK_RSSI_INIT_COUNT 5
31
32#define RA_RSSI_STATE_INIT 0
33#define RA_RSSI_STATE_SEND 1
34#define RA_RSSI_STATE_HOLD 2
35
36#define CFO_HW_RPT_2_MHZ(val) ((val << 1) + (val >> 1))
37/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */
38
39#define AGC_DIFF_CONFIG_MP(ic, band) \
40 (odm_read_and_config_mp_##ic##_agc_tab_diff( \
41 dm, array_mp_##ic##_agc_tab_diff_##band, \
42 sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
43#define AGC_DIFF_CONFIG_TC(ic, band) \
44 (odm_read_and_config_tc_##ic##_agc_tab_diff( \
45 dm, array_tc_##ic##_agc_tab_diff_##band, \
46 sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
47
48#define AGC_DIFF_CONFIG(ic, band) \
49 do { \
50 if (dm->is_mp_chip) \
51 AGC_DIFF_CONFIG_MP(ic, band); \
52 else \
53 AGC_DIFF_CONFIG_TC(ic, band); \
54 } while (0)
55
56/* ************************************************************
57 * structure and define
58 * *************************************************************/
59
60struct phy_rx_agc_info {
61#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
62 u8 gain : 7, trsw : 1;
63#else
64 u8 trsw : 1, gain : 7;
65#endif
66};
67
68struct phy_status_rpt_8192cd {
69 struct phy_rx_agc_info path_agc[2];
70 u8 ch_corr[2];
71 u8 cck_sig_qual_ofdm_pwdb_all;
72 u8 cck_agc_rpt_ofdm_cfosho_a;
73 u8 cck_rpt_b_ofdm_cfosho_b;
74 u8 rsvd_1; /*ch_corr_msb;*/
75 u8 noise_power_db_msb;
76 s8 path_cfotail[2];
77 u8 pcts_mask[2];
78 s8 stream_rxevm[2];
79 u8 path_rxsnr[2];
80 u8 noise_power_db_lsb;
81 u8 rsvd_2[3];
82 u8 stream_csi[2];
83 u8 stream_target_csi[2];
84 s8 sig_evm;
85 u8 rsvd_3;
86
87#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
88 u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
89 u8 sgi_en : 1;
90 u8 rxsc : 2;
91 u8 idle_long : 1;
92 u8 r_ant_train_en : 1;
93 u8 ant_sel_b : 1;
94 u8 ant_sel : 1;
95#else /*_BIG_ENDIAN_ */
96 u8 ant_sel : 1;
97 u8 ant_sel_b : 1;
98 u8 r_ant_train_en : 1;
99 u8 idle_long : 1;
100 u8 rxsc : 2;
101 u8 sgi_en : 1;
102 u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
103#endif
104};
105
106struct phy_status_rpt_8812 {
107 /* DWORD 0*/
108 u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
109 u8 chl_num_LSB; /*channel number[7:0]*/
110#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
111 u8 chl_num_MSB : 2; /*channel number[9:8]*/
112 u8 sub_chnl : 4; /*sub-channel location[3:0]*/
113 u8 r_RFMOD : 2; /*RF mode[1:0]*/
114#else /*_BIG_ENDIAN_ */
115 u8 r_RFMOD : 2;
116 u8 sub_chnl : 4;
117 u8 chl_num_MSB : 2;
118#endif
119
120 /* DWORD 1*/
121 u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/
122 s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 */
123/*CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/
124#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
125 /*this should be checked again
126 *because the definition of 8812 and 8814 is different
127 */
128 u8 resvd_0 : 6;
129 u8 bt_RF_ch_MSB : 2; /*8812A:2'b0, 8814A: bt rf channel keep[7:6]*/
130#else /*_BIG_ENDIAN_*/
131 u8 bt_RF_ch_MSB : 2;
132 u8 resvd_0 : 6;
133#endif
134
135/* DWORD 2*/
136#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
137 u8 ant_div_sw_a : 1; /*8812A: ant_div_sw_a, 8814A: 1'b0*/
138 u8 ant_div_sw_b : 1; /*8812A: ant_div_sw_b, 8814A: 1'b0*/
139 u8 bt_RF_ch_LSB : 6; /*8812A: 6'b0, 8814A: bt rf channel keep[5:0]*/
140#else /*_BIG_ENDIAN_ */
141 u8 bt_RF_ch_LSB : 6;
142 u8 ant_div_sw_b : 1;
143 u8 ant_div_sw_a : 1;
144#endif
145 s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/
146 u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
147 u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
148
149 /* DWORD 3*/
150 s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/
151 s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/
152
153 /* DWORD 4*/
154 u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
155#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
156 u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/
157 u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/
158 u8 resvd_1 : 1; /*1'b0*/
159#else /*_BIG_ENDIAN_*/
160 u8 resvd_1 : 1;
161 u8 pcts_rpt_valid : 1;
162 u8 PCTS_MSK_RPT_3 : 6;
163#endif
164 s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 */
165 /* 8812A: 16'b0, 8814A: stream 3 and stream 4 RX EVM*/
166
167 /* DWORD 5*/
168 u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 */
169 /* 8812A: stream 1 and 2 CSI, 8814A: path-C and path-D RX SNR*/
170 u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 */
171 /* path-C and path-D {TRSW, gain[6:0] }*/
172
173 /* DWORD 6*/
174 s8 sigevm; /*signal field EVM*/
175#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
176 u8 antidx_antc : 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/
177 u8 antidx_antd : 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/
178 u8 dpdt_ctrl_keep : 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/
179 u8 GNT_BT_keep : 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/
180#else /*_BIG_ENDIAN_*/
181 u8 GNT_BT_keep : 1;
182 u8 dpdt_ctrl_keep : 1;
183 u8 antidx_antd : 3;
184 u8 antidx_antc : 3;
185#endif
186#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
187 u8 antidx_anta : 3; /*antidx_anta[2:0]*/
188 u8 antidx_antb : 3; /*antidx_antb[2:0]*/
189 u8 hw_antsw_occur : 2; /*1'b0*/
190#else /*_BIG_ENDIAN_*/
191 u8 hw_antsw_occur : 2;
192 u8 antidx_antb : 3;
193 u8 antidx_anta : 3;
194#endif
195};
196
197void phydm_reset_rssi_for_dm(struct phy_dm_struct *dm, u8 station_id);
198
199void odm_init_rssi_for_dm(struct phy_dm_struct *dm);
200
201void odm_phy_status_query(struct phy_dm_struct *dm,
202 struct dm_phy_status_info *phy_info, u8 *phy_status,
203 struct dm_per_pkt_info *pktinfo);
204
205void odm_mac_status_query(struct phy_dm_struct *dm, u8 *mac_status, u8 mac_id,
206 bool is_packet_match_bssid, bool is_packet_to_self,
207 bool is_packet_beacon);
208
209enum hal_status
210odm_config_rf_with_tx_pwr_track_header_file(struct phy_dm_struct *dm);
211
212enum hal_status
213odm_config_rf_with_header_file(struct phy_dm_struct *dm,
214 enum odm_rf_config_type config_type,
215 enum odm_rf_radio_path e_rf_path);
216
217enum hal_status
218odm_config_bb_with_header_file(struct phy_dm_struct *dm,
219 enum odm_bb_config_type config_type);
220
221enum hal_status odm_config_mac_with_header_file(struct phy_dm_struct *dm);
222
223enum hal_status
224odm_config_fw_with_header_file(struct phy_dm_struct *dm,
225 enum odm_fw_config_type config_type,
226 u8 *p_firmware, u32 *size);
227
228u32 odm_get_hw_img_version(struct phy_dm_struct *dm);
229
230s32 odm_signal_scale_mapping(struct phy_dm_struct *dm, s32 curr_sig);
231
232/*For 8822B only!! need to move to FW finally */
233/*==============================================*/
234void phydm_rx_phy_status_new_type(struct phy_dm_struct *phydm, u8 *phy_status,
235 struct dm_per_pkt_info *pktinfo,
236 struct dm_phy_status_info *phy_info);
237
238bool phydm_query_is_mu_api(struct phy_dm_struct *phydm, u8 ppdu_idx,
239 u8 *p_data_rate, u8 *p_gid);
240
241struct phy_status_rpt_jaguar2_type0 {
242 /* DW0 */
243 u8 page_num;
244 u8 pwdb;
245#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
246 u8 gain : 6;
247 u8 rsvd_0 : 1;
248 u8 trsw : 1;
249#else
250 u8 trsw : 1;
251 u8 rsvd_0 : 1;
252 u8 gain : 6;
253#endif
254 u8 rsvd_1;
255
256 /* DW1 */
257 u8 rsvd_2;
258#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
259 u8 rxsc : 4;
260 u8 agc_table : 4;
261#else
262 u8 agc_table : 4;
263 u8 rxsc : 4;
264#endif
265 u8 channel;
266 u8 band;
267
268 /* DW2 */
269 u16 length;
270#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
271 u8 antidx_a : 3;
272 u8 antidx_b : 3;
273 u8 rsvd_3 : 2;
274 u8 antidx_c : 3;
275 u8 antidx_d : 3;
276 u8 rsvd_4 : 2;
277#else
278 u8 rsvd_3 : 2;
279 u8 antidx_b : 3;
280 u8 antidx_a : 3;
281 u8 rsvd_4 : 2;
282 u8 antidx_d : 3;
283 u8 antidx_c : 3;
284#endif
285
286 /* DW3 */
287 u8 signal_quality;
288#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
289 u8 vga : 5;
290 u8 lna_l : 3;
291 u8 bb_power : 6;
292 u8 rsvd_9 : 1;
293 u8 lna_h : 1;
294#else
295 u8 lna_l : 3;
296 u8 vga : 5;
297 u8 lna_h : 1;
298 u8 rsvd_9 : 1;
299 u8 bb_power : 6;
300#endif
301 u8 rsvd_5;
302
303 /* DW4 */
304 u32 rsvd_6;
305
306 /* DW5 */
307 u32 rsvd_7;
308
309 /* DW6 */
310 u32 rsvd_8;
311};
312
313struct phy_status_rpt_jaguar2_type1 {
314 /* DW0 and DW1 */
315 u8 page_num;
316 u8 pwdb[4];
317#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
318 u8 l_rxsc : 4;
319 u8 ht_rxsc : 4;
320#else
321 u8 ht_rxsc : 4;
322 u8 l_rxsc : 4;
323#endif
324 u8 channel;
325#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
326 u8 band : 2;
327 u8 rsvd_0 : 1;
328 u8 hw_antsw_occu : 1;
329 u8 gnt_bt : 1;
330 u8 ldpc : 1;
331 u8 stbc : 1;
332 u8 beamformed : 1;
333#else
334 u8 beamformed : 1;
335 u8 stbc : 1;
336 u8 ldpc : 1;
337 u8 gnt_bt : 1;
338 u8 hw_antsw_occu : 1;
339 u8 rsvd_0 : 1;
340 u8 band : 2;
341#endif
342
343 /* DW2 */
344 u16 lsig_length;
345#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
346 u8 antidx_a : 3;
347 u8 antidx_b : 3;
348 u8 rsvd_1 : 2;
349 u8 antidx_c : 3;
350 u8 antidx_d : 3;
351 u8 rsvd_2 : 2;
352#else
353 u8 rsvd_1 : 2;
354 u8 antidx_b : 3;
355 u8 antidx_a : 3;
356 u8 rsvd_2 : 2;
357 u8 antidx_d : 3;
358 u8 antidx_c : 3;
359#endif
360
361 /* DW3 */
362 u8 paid;
363#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
364 u8 paid_msb : 1;
365 u8 gid : 6;
366 u8 rsvd_3 : 1;
367#else
368 u8 rsvd_3 : 1;
369 u8 gid : 6;
370 u8 paid_msb : 1;
371#endif
372 u8 intf_pos;
373#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
374 u8 intf_pos_msb : 1;
375 u8 rsvd_4 : 2;
376 u8 nb_intf_flag : 1;
377 u8 rf_mode : 2;
378 u8 rsvd_5 : 2;
379#else
380 u8 rsvd_5 : 2;
381 u8 rf_mode : 2;
382 u8 nb_intf_flag : 1;
383 u8 rsvd_4 : 2;
384 u8 intf_pos_msb : 1;
385#endif
386
387 /* DW4 */
388 s8 rxevm[4]; /* s(8,1) */
389
390 /* DW5 */
391 s8 cfo_tail[4]; /* s(8,7) */
392
393 /* DW6 */
394 s8 rxsnr[4]; /* s(8,1) */
395};
396
397struct phy_status_rpt_jaguar2_type2 {
398 /* DW0 ane DW1 */
399 u8 page_num;
400 u8 pwdb[4];
401#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
402 u8 l_rxsc : 4;
403 u8 ht_rxsc : 4;
404#else
405 u8 ht_rxsc : 4;
406 u8 l_rxsc : 4;
407#endif
408 u8 channel;
409#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
410 u8 band : 2;
411 u8 rsvd_0 : 1;
412 u8 hw_antsw_occu : 1;
413 u8 gnt_bt : 1;
414 u8 ldpc : 1;
415 u8 stbc : 1;
416 u8 beamformed : 1;
417#else
418 u8 beamformed : 1;
419 u8 stbc : 1;
420 u8 ldpc : 1;
421 u8 gnt_bt : 1;
422 u8 hw_antsw_occu : 1;
423 u8 rsvd_0 : 1;
424 u8 band : 2;
425#endif
426
427/* DW2 */
428#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
429 u8 shift_l_map : 6;
430 u8 rsvd_1 : 2;
431#else
432 u8 rsvd_1 : 2;
433 u8 shift_l_map : 6;
434#endif
435 u8 cnt_pw2cca;
436#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
437 u8 agc_table_a : 4;
438 u8 agc_table_b : 4;
439 u8 agc_table_c : 4;
440 u8 agc_table_d : 4;
441#else
442 u8 agc_table_b : 4;
443 u8 agc_table_a : 4;
444 u8 agc_table_d : 4;
445 u8 agc_table_c : 4;
446#endif
447
448 /* DW3 ~ DW6*/
449 u8 cnt_cca2agc_rdy;
450#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
451 u8 gain_a : 6;
452 u8 rsvd_2 : 1;
453 u8 trsw_a : 1;
454 u8 gain_b : 6;
455 u8 rsvd_3 : 1;
456 u8 trsw_b : 1;
457 u8 gain_c : 6;
458 u8 rsvd_4 : 1;
459 u8 trsw_c : 1;
460 u8 gain_d : 6;
461 u8 rsvd_5 : 1;
462 u8 trsw_d : 1;
463 u8 aagc_step_a : 2;
464 u8 aagc_step_b : 2;
465 u8 aagc_step_c : 2;
466 u8 aagc_step_d : 2;
467#else
468 u8 trsw_a : 1;
469 u8 rsvd_2 : 1;
470 u8 gain_a : 6;
471 u8 trsw_b : 1;
472 u8 rsvd_3 : 1;
473 u8 gain_b : 6;
474 u8 trsw_c : 1;
475 u8 rsvd_4 : 1;
476 u8 gain_c : 6;
477 u8 trsw_d : 1;
478 u8 rsvd_5 : 1;
479 u8 gain_d : 6;
480 u8 aagc_step_d : 2;
481 u8 aagc_step_c : 2;
482 u8 aagc_step_b : 2;
483 u8 aagc_step_a : 2;
484#endif
485 u8 ht_aagc_gain[4];
486 u8 dagc_gain[4];
487#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
488 u8 counter : 6;
489 u8 rsvd_6 : 2;
490 u8 syn_count : 5;
491 u8 rsvd_7 : 3;
492#else
493 u8 rsvd_6 : 2;
494 u8 counter : 6;
495 u8 rsvd_7 : 3;
496 u8 syn_count : 5;
497#endif
498};
499
500u32 query_phydm_trx_capability(struct phy_dm_struct *dm);
501
502u32 query_phydm_stbc_capability(struct phy_dm_struct *dm);
503
504u32 query_phydm_ldpc_capability(struct phy_dm_struct *dm);
505
506u32 query_phydm_txbf_parameters(struct phy_dm_struct *dm);
507
508u32 query_phydm_txbf_capability(struct phy_dm_struct *dm);
509
510#endif /*#ifndef __HALHWOUTSRC_H__*/
diff --git a/drivers/staging/rtlwifi/phydm/phydm_interface.c b/drivers/staging/rtlwifi/phydm/phydm_interface.c
new file mode 100644
index 000000000000..102576a46c04
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_interface.c
@@ -0,0 +1,341 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29
30#include "mp_precomp.h"
31#include "phydm_precomp.h"
32
33/*
34 * ODM IO Relative API.
35 */
36
37u8 odm_read_1byte(struct phy_dm_struct *dm, u32 reg_addr)
38{
39 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
40
41 return rtl_read_byte(rtlpriv, reg_addr);
42}
43
44u16 odm_read_2byte(struct phy_dm_struct *dm, u32 reg_addr)
45{
46 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
47
48 return rtl_read_word(rtlpriv, reg_addr);
49}
50
51u32 odm_read_4byte(struct phy_dm_struct *dm, u32 reg_addr)
52{
53 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
54
55 return rtl_read_dword(rtlpriv, reg_addr);
56}
57
58void odm_write_1byte(struct phy_dm_struct *dm, u32 reg_addr, u8 data)
59{
60 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
61
62 rtl_write_byte(rtlpriv, reg_addr, data);
63}
64
65void odm_write_2byte(struct phy_dm_struct *dm, u32 reg_addr, u16 data)
66{
67 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
68
69 rtl_write_word(rtlpriv, reg_addr, data);
70}
71
72void odm_write_4byte(struct phy_dm_struct *dm, u32 reg_addr, u32 data)
73{
74 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
75
76 rtl_write_dword(rtlpriv, reg_addr, data);
77}
78
79void odm_set_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
80 u32 data)
81{
82 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
83
84 rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
85}
86
87u32 odm_get_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask)
88{
89 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
90
91 return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
92}
93
94void odm_set_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
95 u32 data)
96{
97 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
98
99 rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
100}
101
102u32 odm_get_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask)
103{
104 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
105
106 return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
107}
108
109void odm_set_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
110 u32 reg_addr, u32 bit_mask, u32 data)
111{
112 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
113
114 rtl_set_rfreg(rtlpriv->hw, (enum radio_path)e_rf_path, reg_addr,
115 bit_mask, data);
116}
117
118u32 odm_get_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
119 u32 reg_addr, u32 bit_mask)
120{
121 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
122
123 return rtl_get_rfreg(rtlpriv->hw, (enum radio_path)e_rf_path, reg_addr,
124 bit_mask);
125}
126
127/*
128 * ODM Memory relative API.
129 */
130void odm_allocate_memory(struct phy_dm_struct *dm, void **ptr, u32 length)
131{
132 *ptr = kmalloc(length, GFP_ATOMIC);
133}
134
135/* length could be ignored, used to detect memory leakage. */
136void odm_free_memory(struct phy_dm_struct *dm, void *ptr, u32 length)
137{
138 kfree(ptr);
139}
140
141void odm_move_memory(struct phy_dm_struct *dm, void *p_dest, void *src,
142 u32 length)
143{
144 memcpy(p_dest, src, length);
145}
146
147void odm_memory_set(struct phy_dm_struct *dm, void *pbuf, s8 value, u32 length)
148{
149 memset(pbuf, value, length);
150}
151
152s32 odm_compare_memory(struct phy_dm_struct *dm, void *p_buf1, void *buf2,
153 u32 length)
154{
155 return memcmp(p_buf1, buf2, length);
156}
157
158/*
159 * ODM MISC relative API.
160 */
161void odm_acquire_spin_lock(struct phy_dm_struct *dm, enum rt_spinlock_type type)
162{
163}
164
165void odm_release_spin_lock(struct phy_dm_struct *dm, enum rt_spinlock_type type)
166{
167}
168
169/*
170 * ODM Timer relative API.
171 */
172void odm_stall_execution(u32 us_delay) { udelay(us_delay); }
173
174void ODM_delay_ms(u32 ms) { mdelay(ms); }
175
176void ODM_delay_us(u32 us) { udelay(us); }
177
178void ODM_sleep_ms(u32 ms) { msleep(ms); }
179
180void ODM_sleep_us(u32 us) { usleep_range(us, us + 1); }
181
182void odm_set_timer(struct phy_dm_struct *dm, struct timer_list *timer,
183 u32 ms_delay)
184{
185 mod_timer(timer, jiffies + msecs_to_jiffies(ms_delay));
186}
187
188void odm_initialize_timer(struct phy_dm_struct *dm, struct timer_list *timer,
189 void *call_back_func, void *context,
190 const char *sz_id)
191{
192 init_timer(timer);
193 timer->function = call_back_func;
194 timer->data = (unsigned long)dm;
195 /*mod_timer(timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */
196}
197
198void odm_cancel_timer(struct phy_dm_struct *dm, struct timer_list *timer)
199{
200 del_timer(timer);
201}
202
203void odm_release_timer(struct phy_dm_struct *dm, struct timer_list *timer) {}
204
205static u8 phydm_trans_h2c_id(struct phy_dm_struct *dm, u8 phydm_h2c_id)
206{
207 u8 platform_h2c_id = phydm_h2c_id;
208
209 switch (phydm_h2c_id) {
210 /* 1 [0] */
211 case ODM_H2C_RSSI_REPORT:
212
213 break;
214
215 /* 1 [3] */
216 case ODM_H2C_WIFI_CALIBRATION:
217
218 break;
219
220 /* 1 [4] */
221 case ODM_H2C_IQ_CALIBRATION:
222
223 break;
224 /* 1 [5] */
225 case ODM_H2C_RA_PARA_ADJUST:
226
227 break;
228
229 /* 1 [6] */
230 case PHYDM_H2C_DYNAMIC_TX_PATH:
231
232 break;
233
234 /* [7]*/
235 case PHYDM_H2C_FW_TRACE_EN:
236
237 platform_h2c_id = 0x49;
238
239 break;
240
241 case PHYDM_H2C_TXBF:
242 break;
243
244 case PHYDM_H2C_MU:
245 platform_h2c_id = 0x4a; /*H2C_MU*/
246 break;
247
248 default:
249 platform_h2c_id = phydm_h2c_id;
250 break;
251 }
252
253 return platform_h2c_id;
254}
255
256/*ODM FW relative API.*/
257
258void odm_fill_h2c_cmd(struct phy_dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len,
259 u8 *cmd_buffer)
260{
261 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
262 u8 platform_h2c_id;
263
264 platform_h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id);
265
266 ODM_RT_TRACE(dm, PHYDM_COMP_RA_DBG,
267 "[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id);
268
269 rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, platform_h2c_id, cmd_len,
270 cmd_buffer);
271}
272
273u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
274 u8 *tmp_buf)
275{
276 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
277 u8 extend_c2h_sub_id = 0;
278 u8 find_c2h_cmd = true;
279
280 switch (c2h_cmd_id) {
281 case PHYDM_C2H_DBG:
282 phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len);
283 break;
284
285 case PHYDM_C2H_RA_RPT:
286 phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len);
287 break;
288
289 case PHYDM_C2H_RA_PARA_RPT:
290 odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len);
291 break;
292
293 case PHYDM_C2H_DYNAMIC_TX_PATH_RPT:
294 break;
295
296 case PHYDM_C2H_IQK_FINISH:
297 break;
298
299 case PHYDM_C2H_DBG_CODE:
300 phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len);
301 break;
302
303 case PHYDM_C2H_EXTEND:
304 extend_c2h_sub_id = tmp_buf[0];
305 if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT)
306 phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len);
307
308 break;
309
310 default:
311 find_c2h_cmd = false;
312 break;
313 }
314
315 return find_c2h_cmd;
316}
317
318u64 odm_get_current_time(struct phy_dm_struct *dm) { return jiffies; }
319
320u64 odm_get_progressing_time(struct phy_dm_struct *dm, u64 start_time)
321{
322 return jiffies_to_msecs(jiffies - (u32)start_time);
323}
324
325void odm_set_tx_power_index_by_rate_section(struct phy_dm_struct *dm,
326 u8 rf_path, u8 channel,
327 u8 rate_section)
328{
329 void *adapter = dm->adapter;
330
331 phy_set_tx_power_index_by_rs(adapter, channel, rf_path, rate_section);
332}
333
334u8 odm_get_tx_power_index(struct phy_dm_struct *dm, u8 rf_path, u8 tx_rate,
335 u8 band_width, u8 channel)
336{
337 void *adapter = dm->adapter;
338
339 return phy_get_tx_power_index(adapter, (enum odm_rf_radio_path)rf_path,
340 tx_rate, band_width, channel);
341}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_interface.h b/drivers/staging/rtlwifi/phydm/phydm_interface.h
new file mode 100644
index 000000000000..d315c79c962a
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_interface.h
@@ -0,0 +1,205 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __ODM_INTERFACE_H__
27#define __ODM_INTERFACE_H__
28
29#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/
30
31/*
32 * =========== Constant/Structure/Enum/... Define
33 */
34
35/*
36 * =========== Macro Define
37 */
38
39#define _reg_all(_name) ODM_##_name
40#define _reg_ic(_name, _ic) ODM_##_name##_ic
41#define _bit_all(_name) BIT_##_name
42#define _bit_ic(_name, _ic) BIT_##_name##_ic
43
44/* _cat: implemented by Token-Pasting Operator. */
45
46/*===================================
47 *
48 * #define ODM_REG_DIG_11N 0xC50
49 * #define ODM_REG_DIG_11AC 0xDDD
50 *
51 * ODM_REG(DIG,_pdm_odm)
52 * ===================================
53 */
54
55#define _reg_11N(_name) ODM_REG_##_name##_11N
56#define _reg_11AC(_name) ODM_REG_##_name##_11AC
57#define _bit_11N(_name) ODM_BIT_##_name##_11N
58#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
59
60#define _cat(_name, _ic_type, _func) \
61 (((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
62 _func##_11AC(_name))
63
64/* _name: name of register or bit.
65 * Example: "ODM_REG(R_A_AGC_CORE1, dm)"
66 * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C",
67 * depends on support_ic_type.
68 */
69#define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg)
70#define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit)
71enum phydm_h2c_cmd {
72 PHYDM_H2C_TXBF = 0x41,
73 ODM_H2C_RSSI_REPORT = 0x42,
74 ODM_H2C_IQ_CALIBRATION = 0x45,
75 ODM_H2C_RA_PARA_ADJUST = 0x47,
76 PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
77 PHYDM_H2C_FW_TRACE_EN = 0x49,
78 ODM_H2C_WIFI_CALIBRATION = 0x6d,
79 PHYDM_H2C_MU = 0x4a,
80 ODM_MAX_H2CCMD
81};
82
83enum phydm_c2h_evt {
84 PHYDM_C2H_DBG = 0,
85 PHYDM_C2H_LB = 1,
86 PHYDM_C2H_XBF = 2,
87 PHYDM_C2H_TX_REPORT = 3,
88 PHYDM_C2H_INFO = 9,
89 PHYDM_C2H_BT_MP = 11,
90 PHYDM_C2H_RA_RPT = 12,
91 PHYDM_C2H_RA_PARA_RPT = 14,
92 PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
93 PHYDM_C2H_IQK_FINISH = 17, /*0x11*/
94 PHYDM_C2H_DBG_CODE = 0xFE,
95 PHYDM_C2H_EXTEND = 0xFF,
96};
97
98enum phydm_extend_c2h_evt {
99 PHYDM_EXTEND_C2H_DBG_PRINT = 0
100
101};
102
103/*
104 * =========== Extern Variable ??? It should be forbidden.
105 */
106
107/*
108 * =========== EXtern Function Prototype
109 */
110
111u8 odm_read_1byte(struct phy_dm_struct *dm, u32 reg_addr);
112
113u16 odm_read_2byte(struct phy_dm_struct *dm, u32 reg_addr);
114
115u32 odm_read_4byte(struct phy_dm_struct *dm, u32 reg_addr);
116
117void odm_write_1byte(struct phy_dm_struct *dm, u32 reg_addr, u8 data);
118
119void odm_write_2byte(struct phy_dm_struct *dm, u32 reg_addr, u16 data);
120
121void odm_write_4byte(struct phy_dm_struct *dm, u32 reg_addr, u32 data);
122
123void odm_set_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
124 u32 data);
125
126u32 odm_get_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask);
127
128void odm_set_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
129 u32 data);
130
131u32 odm_get_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask);
132
133void odm_set_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
134 u32 reg_addr, u32 bit_mask, u32 data);
135
136u32 odm_get_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
137 u32 reg_addr, u32 bit_mask);
138
139/*
140 * Memory Relative Function.
141 */
142void odm_allocate_memory(struct phy_dm_struct *dm, void **ptr, u32 length);
143void odm_free_memory(struct phy_dm_struct *dm, void *ptr, u32 length);
144
145void odm_move_memory(struct phy_dm_struct *dm, void *p_dest, void *src,
146 u32 length);
147
148s32 odm_compare_memory(struct phy_dm_struct *dm, void *p_buf1, void *buf2,
149 u32 length);
150
151void odm_memory_set(struct phy_dm_struct *dm, void *pbuf, s8 value, u32 length);
152
153/*
154 * ODM MISC-spin lock relative API.
155 */
156void odm_acquire_spin_lock(struct phy_dm_struct *dm,
157 enum rt_spinlock_type type);
158
159void odm_release_spin_lock(struct phy_dm_struct *dm,
160 enum rt_spinlock_type type);
161
162/*
163 * ODM Timer relative API.
164 */
165void odm_stall_execution(u32 us_delay);
166
167void ODM_delay_ms(u32 ms);
168
169void ODM_delay_us(u32 us);
170
171void ODM_sleep_ms(u32 ms);
172
173void ODM_sleep_us(u32 us);
174
175void odm_set_timer(struct phy_dm_struct *dm, struct timer_list *timer,
176 u32 ms_delay);
177
178void odm_initialize_timer(struct phy_dm_struct *dm, struct timer_list *timer,
179 void *call_back_func, void *context,
180 const char *sz_id);
181
182void odm_cancel_timer(struct phy_dm_struct *dm, struct timer_list *timer);
183
184void odm_release_timer(struct phy_dm_struct *dm, struct timer_list *timer);
185
186/*
187 * ODM FW relative API.
188 */
189void odm_fill_h2c_cmd(struct phy_dm_struct *dm, u8 element_id, u32 cmd_len,
190 u8 *cmd_buffer);
191
192u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
193 u8 *tmp_buf);
194
195u64 odm_get_current_time(struct phy_dm_struct *dm);
196u64 odm_get_progressing_time(struct phy_dm_struct *dm, u64 start_time);
197
198void odm_set_tx_power_index_by_rate_section(struct phy_dm_struct *dm,
199 u8 rf_path, u8 channel,
200 u8 rate_section);
201
202u8 odm_get_tx_power_index(struct phy_dm_struct *dm, u8 rf_path, u8 tx_rate,
203 u8 band_width, u8 channel);
204
205#endif /* __ODM_INTERFACE_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/phydm_iqk.h b/drivers/staging/rtlwifi/phydm/phydm_iqk.h
new file mode 100644
index 000000000000..0d45bf099aeb
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_iqk.h
@@ -0,0 +1,76 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMIQK_H__
27#define __PHYDMIQK_H__
28
29/*--------------------------Define Parameters-------------------------------*/
30#define LOK_delay 1
31#define WBIQK_delay 10
32#define TX_IQK 0
33#define RX_IQK 1
34#define TXIQK 0
35#define RXIQK1 1
36#define RXIQK2 2
37#define GSRXK1 0
38#define GSRXK2 1
39#define kcount_limit_80m 2
40#define kcount_limit_others 4
41#define rxiqk_gs_limit 4
42
43#define NUM 4
44/*----------------------End Define Parameters-------------------------------*/
45
46struct dm_iqk_info {
47 bool lok_fail[NUM];
48 bool iqk_fail[2][NUM];
49 u32 iqc_matrix[2][NUM];
50 u8 iqk_times;
51 u32 rf_reg18;
52 u32 lna_idx;
53 u8 rxiqk_step;
54 u8 tmp1bcc;
55 u8 kcount;
56
57 u32 iqk_channel[2];
58 bool iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
59 u32 iqk_cfir_real[2][4][2]
60 [8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
61 u32 iqk_cfir_imag[2][4][2]
62 [8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
63 u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
64 u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
65 u8 rxiqk_fail_code[2][4]; /* channel / path
66 * 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail
67 */
68 u32 lok_idac[2][4]; /*channel / path*/
69 u16 rxiqk_agc[2][4]; /*channel / path*/
70 u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
71 u32 tmp_gntwl;
72 bool is_btg;
73 bool isbnd;
74};
75
76#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_kfree.c b/drivers/staging/rtlwifi/phydm/phydm_kfree.c
new file mode 100644
index 000000000000..5f3582341806
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_kfree.c
@@ -0,0 +1,228 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/*============================================================*/
27/*include files*/
28/*============================================================*/
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31
32/*<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
33/*This is a phydm API*/
34
35static void phydm_set_kfree_to_rf_8814a(void *dm_void, u8 e_rf_path, u8 data)
36{
37 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
38 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
39 bool is_odd;
40
41 if ((data % 2) != 0) { /*odd->positive*/
42 data = data - 1;
43 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19),
44 1);
45 is_odd = true;
46 } else { /*even->negative*/
47 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19),
48 0);
49 is_odd = false;
50 }
51 ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): RF_0x55[19]= %d\n", __func__,
52 is_odd);
53 switch (data) {
54 case 0:
55 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
56 0);
57 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
58 BIT(17) | BIT(16) | BIT(15), 0);
59 cali_info->kfree_offset[e_rf_path] = 0;
60 break;
61 case 2:
62 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
63 1);
64 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
65 BIT(17) | BIT(16) | BIT(15), 0);
66 cali_info->kfree_offset[e_rf_path] = 0;
67 break;
68 case 4:
69 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
70 0);
71 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
72 BIT(17) | BIT(16) | BIT(15), 1);
73 cali_info->kfree_offset[e_rf_path] = 1;
74 break;
75 case 6:
76 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
77 1);
78 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
79 BIT(17) | BIT(16) | BIT(15), 1);
80 cali_info->kfree_offset[e_rf_path] = 1;
81 break;
82 case 8:
83 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
84 0);
85 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
86 BIT(17) | BIT(16) | BIT(15), 2);
87 cali_info->kfree_offset[e_rf_path] = 2;
88 break;
89 case 10:
90 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
91 1);
92 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
93 BIT(17) | BIT(16) | BIT(15), 2);
94 cali_info->kfree_offset[e_rf_path] = 2;
95 break;
96 case 12:
97 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
98 0);
99 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
100 BIT(17) | BIT(16) | BIT(15), 3);
101 cali_info->kfree_offset[e_rf_path] = 3;
102 break;
103 case 14:
104 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
105 1);
106 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
107 BIT(17) | BIT(16) | BIT(15), 3);
108 cali_info->kfree_offset[e_rf_path] = 3;
109 break;
110 case 16:
111 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
112 0);
113 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
114 BIT(17) | BIT(16) | BIT(15), 4);
115 cali_info->kfree_offset[e_rf_path] = 4;
116 break;
117 case 18:
118 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
119 1);
120 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
121 BIT(17) | BIT(16) | BIT(15), 4);
122 cali_info->kfree_offset[e_rf_path] = 4;
123 break;
124 case 20:
125 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
126 0);
127 odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
128 BIT(17) | BIT(16) | BIT(15), 5);
129 cali_info->kfree_offset[e_rf_path] = 5;
130 break;
131
132 default:
133 break;
134 }
135
136 if (!is_odd) {
137 /*that means Kfree offset is negative, we need to record it.*/
138 cali_info->kfree_offset[e_rf_path] =
139 (-1) * cali_info->kfree_offset[e_rf_path];
140 ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): kfree_offset = %d\n",
141 __func__, cali_info->kfree_offset[e_rf_path]);
142 } else {
143 ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): kfree_offset = %d\n",
144 __func__, cali_info->kfree_offset[e_rf_path]);
145 }
146}
147
148static void phydm_set_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
149{
150 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
151
152 if (dm->support_ic_type & ODM_RTL8814A)
153 phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data);
154}
155
156void phydm_config_kfree(void *dm_void, u8 channel_to_sw, u8 *kfree_table)
157{
158 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
159 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
160 u8 rfpath = 0, max_rf_path = 0;
161 u8 channel_idx = 0;
162
163 if (dm->support_ic_type & ODM_RTL8814A)
164 max_rf_path = 4; /*0~3*/
165 else if (dm->support_ic_type &
166 (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B))
167 max_rf_path = 2; /*0~1*/
168 else
169 max_rf_path = 1;
170
171 ODM_RT_TRACE(dm, ODM_COMP_MP, "===>%s()\n", __func__);
172
173 if (cali_info->reg_rf_kfree_enable == 2) {
174 ODM_RT_TRACE(dm, ODM_COMP_MP,
175 "%s(): reg_rf_kfree_enable == 2, Disable\n",
176 __func__);
177 return;
178 }
179
180 if (cali_info->reg_rf_kfree_enable != 1 &&
181 cali_info->reg_rf_kfree_enable != 0) {
182 ODM_RT_TRACE(dm, ODM_COMP_MP, "<===%s()\n", __func__);
183 return;
184 }
185
186 ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): reg_rf_kfree_enable == true\n",
187 __func__);
188 /*Make sure the targetval is defined*/
189 if (((cali_info->reg_rf_kfree_enable == 1) &&
190 (kfree_table[0] != 0xFF)) ||
191 cali_info->rf_kfree_enable) {
192 /*if kfree_table[0] == 0xff, means no Kfree*/
193 if (*dm->band_type == ODM_BAND_2_4G) {
194 if (channel_to_sw <= 14 && channel_to_sw >= 1)
195 channel_idx = PHYDM_2G;
196 } else if (*dm->band_type == ODM_BAND_5G) {
197 if (channel_to_sw >= 36 && channel_to_sw <= 48)
198 channel_idx = PHYDM_5GLB1;
199 if (channel_to_sw >= 52 && channel_to_sw <= 64)
200 channel_idx = PHYDM_5GLB2;
201 if (channel_to_sw >= 100 && channel_to_sw <= 120)
202 channel_idx = PHYDM_5GMB1;
203 if (channel_to_sw >= 124 && channel_to_sw <= 144)
204 channel_idx = PHYDM_5GMB2;
205 if (channel_to_sw >= 149 && channel_to_sw <= 177)
206 channel_idx = PHYDM_5GHB;
207 }
208
209 for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) {
210 ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): PATH_%d: %#x\n",
211 __func__, rfpath,
212 kfree_table[channel_idx * max_rf_path +
213 rfpath]);
214 phydm_set_kfree_to_rf(
215 dm, rfpath,
216 kfree_table[channel_idx * max_rf_path +
217 rfpath]);
218 }
219 } else {
220 ODM_RT_TRACE(
221 dm, ODM_COMP_MP,
222 "%s(): targetval not defined, Don't execute KFree Process.\n",
223 __func__);
224 return;
225 }
226
227 ODM_RT_TRACE(dm, ODM_COMP_MP, "<===%s()\n", __func__);
228}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_kfree.h b/drivers/staging/rtlwifi/phydm/phydm_kfree.h
new file mode 100644
index 000000000000..1ee60059afc1
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_kfree.h
@@ -0,0 +1,42 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMKFREE_H__
27#define __PHYDKFREE_H__
28
29#define KFREE_VERSION "1.0"
30
31enum phydm_kfree_channeltosw {
32 PHYDM_2G = 0,
33 PHYDM_5GLB1 = 1,
34 PHYDM_5GLB2 = 2,
35 PHYDM_5GMB1 = 3,
36 PHYDM_5GMB2 = 4,
37 PHYDM_5GHB = 5,
38};
39
40void phydm_config_kfree(void *dm_void, u8 channel_to_sw, u8 *kfree_table);
41
42#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_noisemonitor.c b/drivers/staging/rtlwifi/phydm/phydm_noisemonitor.c
new file mode 100644
index 000000000000..8d79a5add1b4
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_noisemonitor.c
@@ -0,0 +1,330 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31#include "phydm_noisemonitor.h"
32
33/* *************************************************
34 * This function is for inband noise test utility only
35 * To obtain the inband noise level(dbm), do the following.
36 * 1. disable DIG and Power Saving
37 * 2. Set initial gain = 0x1a
38 * 3. Stop updating idle time pwer report (for driver read)
39 * - 0x80c[25]
40 *
41 * **************************************************/
42
43#define VALID_MIN -35
44#define VALID_MAX 10
45#define VALID_CNT 5
46
47static inline void phydm_set_noise_data_sum(struct noise_level *noise_data,
48 u8 max_rf_path)
49{
50 u8 rf_path;
51
52 for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
53 if (noise_data->valid_cnt[rf_path])
54 noise_data->sum[rf_path] /=
55 noise_data->valid_cnt[rf_path];
56 else
57 noise_data->sum[rf_path] = 0;
58 }
59}
60
61static s16 odm_inband_noise_monitor_n_series(struct phy_dm_struct *dm,
62 u8 is_pause_dig, u8 igi_value,
63 u32 max_time)
64{
65 u32 tmp4b;
66 u8 max_rf_path = 0, rf_path;
67 u8 reg_c50, reg_c58, valid_done = 0;
68 struct noise_level noise_data;
69 u64 start = 0, func_start = 0, func_end = 0;
70
71 func_start = odm_get_current_time(dm);
72 dm->noise_level.noise_all = 0;
73
74 if ((dm->rf_type == ODM_1T2R) || (dm->rf_type == ODM_2T2R))
75 max_rf_path = 2;
76 else
77 max_rf_path = 1;
78
79 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() ==>\n", __func__);
80
81 odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
82
83 /* */
84 /* step 1. Disable DIG && Set initial gain. */
85 /* */
86
87 if (is_pause_dig)
88 odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
89 /* */
90 /* step 2. Disable all power save for read registers */
91 /* */
92 /* dcmd_DebugControlPowerSave(adapter, PSDisable); */
93
94 /* */
95 /* step 3. Get noise power level */
96 /* */
97 start = odm_get_current_time(dm);
98 while (1) {
99 /* Stop updating idle time pwer report (for driver read) */
100 odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
101
102 /* Read Noise Floor Report */
103 tmp4b = odm_get_bb_reg(dm, 0x8f8, MASKDWORD);
104 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
105 "Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b);
106
107 /* update idle time pwer report per 5us */
108 odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
109
110 noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff);
111 noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
112
113 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
114 "value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
115 noise_data.value[ODM_RF_PATH_A],
116 noise_data.value[ODM_RF_PATH_A],
117 noise_data.value[ODM_RF_PATH_B],
118 noise_data.value[ODM_RF_PATH_B]);
119
120 for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path;
121 rf_path++) {
122 noise_data.sval[rf_path] =
123 (s8)noise_data.value[rf_path];
124 noise_data.sval[rf_path] /= 2;
125 }
126
127 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "sval_a = %d, sval_b = %d\n",
128 noise_data.sval[ODM_RF_PATH_A],
129 noise_data.sval[ODM_RF_PATH_B]);
130
131 for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path;
132 rf_path++) {
133 if (!(noise_data.valid_cnt[rf_path] < VALID_CNT) ||
134 !(noise_data.sval[rf_path] < VALID_MAX &&
135 noise_data.sval[rf_path] >= VALID_MIN)) {
136 continue;
137 }
138
139 noise_data.valid_cnt[rf_path]++;
140 noise_data.sum[rf_path] += noise_data.sval[rf_path];
141 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
142 "rf_path:%d Valid sval = %d\n", rf_path,
143 noise_data.sval[rf_path]);
144 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "Sum of sval = %d,\n",
145 noise_data.sum[rf_path]);
146 if (noise_data.valid_cnt[rf_path] == VALID_CNT) {
147 valid_done++;
148 ODM_RT_TRACE(
149 dm, ODM_COMP_COMMON,
150 "After divided, rf_path:%d,sum = %d\n",
151 rf_path, noise_data.sum[rf_path]);
152 }
153 }
154
155 if ((valid_done == max_rf_path) ||
156 (odm_get_progressing_time(dm, start) > max_time)) {
157 phydm_set_noise_data_sum(&noise_data, max_rf_path);
158 break;
159 }
160 }
161 reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
162 reg_c50 &= ~BIT(7);
163 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "0x%x = 0x%02x(%d)\n",
164 REG_OFDM_0_XA_AGC_CORE1, reg_c50, reg_c50);
165 dm->noise_level.noise[ODM_RF_PATH_A] =
166 (u8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]);
167 dm->noise_level.noise_all += dm->noise_level.noise[ODM_RF_PATH_A];
168
169 if (max_rf_path == 2) {
170 reg_c58 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XB_AGC_CORE1,
171 MASKBYTE0);
172 reg_c58 &= ~BIT(7);
173 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "0x%x = 0x%02x(%d)\n",
174 REG_OFDM_0_XB_AGC_CORE1, reg_c58, reg_c58);
175 dm->noise_level.noise[ODM_RF_PATH_B] =
176 (u8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]);
177 dm->noise_level.noise_all +=
178 dm->noise_level.noise[ODM_RF_PATH_B];
179 }
180 dm->noise_level.noise_all /= max_rf_path;
181
182 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "noise_a = %d, noise_b = %d\n",
183 dm->noise_level.noise[ODM_RF_PATH_A],
184 dm->noise_level.noise[ODM_RF_PATH_B]);
185
186 /* */
187 /* step 4. Recover the Dig */
188 /* */
189 if (is_pause_dig)
190 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
191 func_end = odm_get_progressing_time(dm, func_start);
192
193 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() <==\n", __func__);
194 return dm->noise_level.noise_all;
195}
196
197static s16 odm_inband_noise_monitor_ac_series(struct phy_dm_struct *dm,
198 u8 is_pause_dig, u8 igi_value,
199 u32 max_time)
200{
201 s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
202 s32 value32, pwdb_A = 0, sval, noise, sum;
203 bool pd_flag;
204 u8 valid_cnt;
205 u64 start = 0, func_start = 0, func_end = 0;
206
207 if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
208 return 0;
209
210 func_start = odm_get_current_time(dm);
211 dm->noise_level.noise_all = 0;
212
213 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() ==>\n", __func__);
214
215 /* step 1. Disable DIG && Set initial gain. */
216 if (is_pause_dig)
217 odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
218
219 /* step 2. Disable all power save for read registers */
220 /*dcmd_DebugControlPowerSave(adapter, PSDisable); */
221
222 /* step 3. Get noise power level */
223 start = odm_get_current_time(dm);
224
225 /* reset counters */
226 sum = 0;
227 valid_cnt = 0;
228
229 /* step 3. Get noise power level */
230 while (1) {
231 /*Set IGI=0x1C */
232 odm_write_dig(dm, 0x1C);
233 /*stop CK320&CK88 */
234 odm_set_bb_reg(dm, 0x8B4, BIT(6), 1);
235 /*Read path-A */
236 odm_set_bb_reg(dm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/
237 value32 = odm_get_bb_reg(dm, 0xFA0,
238 MASKDWORD); /*read debug port*/
239
240 rxi_buf_anta = (value32 & 0xFFC00) >>
241 10; /*rxi_buf_anta=RegFA0[19:10]*/
242 rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
243
244 pd_flag = (bool)((value32 & BIT(31)) >> 31);
245
246 /*Not in packet detection period or Tx state */
247 if ((!pd_flag) || (rxi_buf_anta != 0x200)) {
248 /*sign conversion*/
249 rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
250 rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
251
252 pwdb_A = odm_pwdb_conversion(
253 rxi_buf_anta * rxi_buf_anta +
254 rxq_buf_anta * rxq_buf_anta,
255 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/
256
257 ODM_RT_TRACE(
258 dm, ODM_COMP_COMMON,
259 "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n",
260 pwdb_A, rxi_buf_anta & 0x3FF,
261 rxq_buf_anta & 0x3FF);
262 }
263 /*Start CK320&CK88*/
264 odm_set_bb_reg(dm, 0x8B4, BIT(6), 0);
265 /*BB Reset*/
266 odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) & (~BIT(0)));
267 odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) | BIT(0));
268 /*PMAC Reset*/
269 odm_write_1byte(dm, 0xB03,
270 odm_read_1byte(dm, 0xB03) & (~BIT(0)));
271 odm_write_1byte(dm, 0xB03, odm_read_1byte(dm, 0xB03) | BIT(0));
272 /*CCK Reset*/
273 if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
274 odm_write_1byte(dm, 0x80B,
275 odm_read_1byte(dm, 0x80B) & (~BIT(4)));
276 odm_write_1byte(dm, 0x80B,
277 odm_read_1byte(dm, 0x80B) | BIT(4));
278 }
279
280 sval = pwdb_A;
281
282 if ((sval < 0 && sval >= -27) && (valid_cnt < VALID_CNT)) {
283 valid_cnt++;
284 sum += sval;
285 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "Valid sval = %d\n",
286 sval);
287 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "Sum of sval = %d,\n",
288 sum);
289 if ((valid_cnt >= VALID_CNT) ||
290 (odm_get_progressing_time(dm, start) > max_time)) {
291 sum /= VALID_CNT;
292 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
293 "After divided, sum = %d\n", sum);
294 break;
295 }
296 }
297 }
298
299 /*ADC backoff is 12dB,*/
300 /*Ptarget=0x1C-110=-82dBm*/
301 noise = sum + 12 + 0x1C - 110;
302
303 /*Offset*/
304 noise = noise - 3;
305 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "noise = %d\n", noise);
306 dm->noise_level.noise_all = (s16)noise;
307
308 /* step 4. Recover the Dig*/
309 if (is_pause_dig)
310 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
311
312 func_end = odm_get_progressing_time(dm, func_start);
313
314 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() <==\n", __func__);
315
316 return dm->noise_level.noise_all;
317}
318
319s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
320 u32 max_time)
321{
322 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
323
324 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
325 return odm_inband_noise_monitor_ac_series(dm, is_pause_dig,
326 igi_value, max_time);
327 else
328 return odm_inband_noise_monitor_n_series(dm, is_pause_dig,
329 igi_value, max_time);
330}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_noisemonitor.h b/drivers/staging/rtlwifi/phydm/phydm_noisemonitor.h
new file mode 100644
index 000000000000..a711b7954985
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_noisemonitor.h
@@ -0,0 +1,46 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __ODMNOISEMONITOR_H__
26#define __ODMNOISEMONITOR_H__
27
28#define ODM_MAX_CHANNEL_NUM 38 /* 14+24 */
29struct noise_level {
30 u8 value[MAX_RF_PATH];
31 s8 sval[MAX_RF_PATH];
32
33 s32 sum[MAX_RF_PATH];
34 u8 valid[MAX_RF_PATH];
35 u8 valid_cnt[MAX_RF_PATH];
36};
37
38struct odm_noise_monitor {
39 s8 noise[MAX_RF_PATH];
40 s16 noise_all;
41};
42
43s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
44 u32 max_time);
45
46#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_powertracking_ce.c b/drivers/staging/rtlwifi/phydm/phydm_powertracking_ce.c
new file mode 100644
index 000000000000..48e73eb1622b
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_powertracking_ce.c
@@ -0,0 +1,644 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/*============================================================ */
27/* include files */
28/*============================================================ */
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31
32/* ************************************************************
33 * Global var
34 * *************************************************************/
35
36u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
37 0x7f8001fe, /* 0, +6.0dB */
38 0x788001e2, /* 1, +5.5dB */
39 0x71c001c7, /* 2, +5.0dB*/
40 0x6b8001ae, /* 3, +4.5dB*/
41 0x65400195, /* 4, +4.0dB*/
42 0x5fc0017f, /* 5, +3.5dB*/
43 0x5a400169, /* 6, +3.0dB*/
44 0x55400155, /* 7, +2.5dB*/
45 0x50800142, /* 8, +2.0dB*/
46 0x4c000130, /* 9, +1.5dB*/
47 0x47c0011f, /* 10, +1.0dB*/
48 0x43c0010f, /* 11, +0.5dB*/
49 0x40000100, /* 12, +0dB*/
50 0x3c8000f2, /* 13, -0.5dB*/
51 0x390000e4, /* 14, -1.0dB*/
52 0x35c000d7, /* 15, -1.5dB*/
53 0x32c000cb, /* 16, -2.0dB*/
54 0x300000c0, /* 17, -2.5dB*/
55 0x2d4000b5, /* 18, -3.0dB*/
56 0x2ac000ab, /* 19, -3.5dB*/
57 0x288000a2, /* 20, -4.0dB*/
58 0x26000098, /* 21, -4.5dB*/
59 0x24000090, /* 22, -5.0dB*/
60 0x22000088, /* 23, -5.5dB*/
61 0x20000080, /* 24, -6.0dB*/
62 0x1e400079, /* 25, -6.5dB*/
63 0x1c800072, /* 26, -7.0dB*/
64 0x1b00006c, /* 27. -7.5dB*/
65 0x19800066, /* 28, -8.0dB*/
66 0x18000060, /* 29, -8.5dB*/
67 0x16c0005b, /* 30, -9.0dB*/
68 0x15800056, /* 31, -9.5dB*/
69 0x14400051, /* 32, -10.0dB*/
70 0x1300004c, /* 33, -10.5dB*/
71 0x12000048, /* 34, -11.0dB*/
72 0x11000044, /* 35, -11.5dB*/
73 0x10000040, /* 36, -12.0dB*/
74};
75
76u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
77 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
78 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
79 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/
80 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/
81 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
82 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/
83 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/
84 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/
85 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
86 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/
87 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
88 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/
89 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04,
90 0x02}, /* 12, -6.0dB <== default */
91 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/
92 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
93 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/
94 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
95 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/
96 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
97 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/
98 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
99 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
100 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
101 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
102 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
103 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
104 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
105 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
106 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
107 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
108 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
109 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
110 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
111};
112
113u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
114 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
115 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
116 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
117 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/
118 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
119 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/
120 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
121 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
122 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
123 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/
124 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
125 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/
126 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00,
127 0x00}, /* 12, -6.0dB <== default*/
128 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
129 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
130 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/
131 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
132 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/
133 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
134 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/
135 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
136 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
137 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
138 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
139 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
140 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
141 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
142 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
143 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
144 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
145 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
146 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
147 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
148};
149
150u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
151 0x0b40002d, /* 0, -15.0dB */
152 0x0c000030, /* 1, -14.5dB*/
153 0x0cc00033, /* 2, -14.0dB*/
154 0x0d800036, /* 3, -13.5dB*/
155 0x0e400039, /* 4, -13.0dB */
156 0x0f00003c, /* 5, -12.5dB*/
157 0x10000040, /* 6, -12.0dB*/
158 0x11000044, /* 7, -11.5dB*/
159 0x12000048, /* 8, -11.0dB*/
160 0x1300004c, /* 9, -10.5dB*/
161 0x14400051, /* 10, -10.0dB*/
162 0x15800056, /* 11, -9.5dB*/
163 0x16c0005b, /* 12, -9.0dB*/
164 0x18000060, /* 13, -8.5dB*/
165 0x19800066, /* 14, -8.0dB*/
166 0x1b00006c, /* 15, -7.5dB*/
167 0x1c800072, /* 16, -7.0dB*/
168 0x1e400079, /* 17, -6.5dB*/
169 0x20000080, /* 18, -6.0dB*/
170 0x22000088, /* 19, -5.5dB*/
171 0x24000090, /* 20, -5.0dB*/
172 0x26000098, /* 21, -4.5dB*/
173 0x288000a2, /* 22, -4.0dB*/
174 0x2ac000ab, /* 23, -3.5dB*/
175 0x2d4000b5, /* 24, -3.0dB*/
176 0x300000c0, /* 25, -2.5dB*/
177 0x32c000cb, /* 26, -2.0dB*/
178 0x35c000d7, /* 27, -1.5dB*/
179 0x390000e4, /* 28, -1.0dB*/
180 0x3c8000f2, /* 29, -0.5dB*/
181 0x40000100, /* 30, +0dB*/
182 0x43c0010f, /* 31, +0.5dB*/
183 0x47c0011f, /* 32, +1.0dB*/
184 0x4c000130, /* 33, +1.5dB*/
185 0x50800142, /* 34, +2.0dB*/
186 0x55400155, /* 35, +2.5dB*/
187 0x5a400169, /* 36, +3.0dB*/
188 0x5fc0017f, /* 37, +3.5dB*/
189 0x65400195, /* 38, +4.0dB*/
190 0x6b8001ae, /* 39, +4.5dB*/
191 0x71c001c7, /* 40, +5.0dB*/
192 0x788001e2, /* 41, +5.5dB*/
193 0x7f8001fe /* 42, +6.0dB*/
194};
195
196u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
197 {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00,
198 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
199 {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00,
200 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
201 {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00,
202 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
203 {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00,
204 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
205 {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00,
206 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
207 {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00,
208 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
209 {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00,
210 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
211 {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00,
212 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
213 {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00,
214 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
215 {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00,
216 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
217 {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00,
218 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
219 {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00,
220 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
221 {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00,
222 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
223 {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00,
224 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
225 {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00,
226 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
227 {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00,
228 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
229 {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00,
230 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
231 {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00,
232 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
233 {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00,
234 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
235 {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00,
236 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
237 {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00,
238 0x00, 0x00, 0x00, 0x00} /*-6dB*/
239};
240
241u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
242 {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00,
243 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
244 {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00,
245 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
246 {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00,
247 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
248 {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00,
249 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
250 {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00,
251 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
252 {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00,
253 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
254 {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00,
255 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
256 {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
258 {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
260 {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
262 {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00,
263 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
264 {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00,
265 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
266 {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00,
267 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
268 {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00,
269 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
270 {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00,
271 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
272 {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00,
273 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
274 {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00,
275 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
276 {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00,
277 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
278 {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00,
279 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
280 {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00,
281 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
282 {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00,
283 0x00, 0x00, 0x00, 0x00} /*-6dB*/
284};
285
286u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
287 {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
288 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
289 {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
290 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
291 {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
292 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
293 {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
294 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
295 {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
296 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
297 {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
298 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
299 {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
300 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
301 {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
302 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
303 {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
304 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
305 {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
306 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
307 {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
308 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
309 {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
310 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
311 {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
312 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
313 {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
314 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
315 {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
316 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
317 {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
318 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
319 {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
320 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
321 {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
322 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
323 {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
324 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
325 {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
326 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
327 {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
328 0x00, 0x00, 0x00, 0x00} /*-6dB*/
329};
330
331u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
332 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/
333 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/
334 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/
335 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/
336 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/
337 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/
338 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/
339 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/
340 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/
341 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/
342 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/
343 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/
344 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/
345 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/
346 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
347 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/
348 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
349 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/
350 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
351 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/
352 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */
353 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/
354 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
355 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/
356 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
357 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/
358 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/
359 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/
360 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
361 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/
362 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/
363 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/
364 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/
365};
366
367u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
368 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/
369 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
370 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/
371 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
372 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/
373 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
374 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
375 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/
376 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
377 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
378 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
379 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
380 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
381 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
382 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
383 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
384 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
385 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
386 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
387 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
388 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
389 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
390 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
391 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
392 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
393 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
394 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
395 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
396 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
397 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
398 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
399 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
400 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
401};
402
403u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
404 0x0CD, /*0 , -20dB*/
405 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158, 0x16C,
406 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263, 0x287,
407 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F, 0x47F,
408 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C, 0x7FF,
409};
410
411/* JJ ADD 20161014 */
412u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
413 0x0CD, /*0 , -20dB*/
414 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158, 0x16C,
415 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263, 0x287,
416 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F, 0x47F,
417 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C, 0x7FF,
418};
419
420u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
421 0x081, /* 0, -12.0dB*/
422 0x088, /* 1, -11.5dB*/
423 0x090, /* 2, -11.0dB*/
424 0x099, /* 3, -10.5dB*/
425 0x0A2, /* 4, -10.0dB*/
426 0x0AC, /* 5, -9.5dB*/
427 0x0B6, /* 6, -9.0dB*/
428 0x0C0, /*7, -8.5dB*/
429 0x0CC, /* 8, -8.0dB*/
430 0x0D8, /* 9, -7.5dB*/
431 0x0E5, /* 10, -7.0dB*/
432 0x0F2, /* 11, -6.5dB*/
433 0x101, /* 12, -6.0dB*/
434 0x110, /* 13, -5.5dB*/
435 0x120, /* 14, -5.0dB*/
436 0x131, /* 15, -4.5dB*/
437 0x143, /* 16, -4.0dB*/
438 0x156, /* 17, -3.5dB*/
439 0x16A, /* 18, -3.0dB*/
440 0x180, /* 19, -2.5dB*/
441 0x197, /* 20, -2.0dB*/
442 0x1AF, /* 21, -1.5dB*/
443 0x1C8, /* 22, -1.0dB*/
444 0x1E3, /* 23, -0.5dB*/
445 0x200, /* 24, +0 dB*/
446 0x21E, /* 25, +0.5dB*/
447 0x23E, /* 26, +1.0dB*/
448 0x261, /* 27, +1.5dB*/
449 0x285, /* 28, +2.0dB*/
450 0x2AB, /* 29, +2.5dB*/
451 0x2D3, /*30, +3.0dB*/
452 0x2FE, /* 31, +3.5dB*/
453 0x32B, /* 32, +4.0dB*/
454 0x35C, /* 33, +4.5dB*/
455 0x38E, /* 34, +5.0dB*/
456 0x3C4, /* 35, +5.5dB*/
457 0x3FE /* 36, +6.0dB */
458};
459
460void odm_txpowertracking_init(void *dm_void)
461{
462 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
463
464 odm_txpowertracking_thermal_meter_init(dm);
465}
466
467static u8 get_swing_index(void *dm_void)
468{
469 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
470 u8 i = 0;
471 u32 bb_swing;
472 u32 swing_table_size;
473 u32 *swing_table;
474
475 if (dm->support_ic_type == ODM_RTL8188E ||
476 dm->support_ic_type == ODM_RTL8723B ||
477 dm->support_ic_type == ODM_RTL8192E ||
478 dm->support_ic_type == ODM_RTL8188F ||
479 dm->support_ic_type == ODM_RTL8703B) {
480 bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
481 0xFFC00000);
482
483 swing_table = ofdm_swing_table_new;
484 swing_table_size = OFDM_TABLE_SIZE;
485 } else {
486 {
487 bb_swing = 0;
488 swing_table = ofdm_swing_table;
489 swing_table_size = OFDM_TABLE_SIZE;
490 }
491 }
492
493 for (i = 0; i < swing_table_size; ++i) {
494 u32 table_value = swing_table[i];
495
496 if (table_value >= 0x100000)
497 table_value >>= 22;
498 if (bb_swing == table_value)
499 break;
500 }
501 return i;
502}
503
504void odm_txpowertracking_thermal_meter_init(void *dm_void)
505{
506 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
507 u8 default_swing_index = get_swing_index(dm);
508 u8 p = 0;
509 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
510 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
511 struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
512
513 cali_info->is_txpowertracking = true;
514 cali_info->tx_powercount = 0;
515 cali_info->is_txpowertracking_init = false;
516
517 if (!dm->mp_mode)
518 cali_info->txpowertrack_control = true;
519 else
520 cali_info->txpowertrack_control = false;
521
522 if (!dm->mp_mode)
523 cali_info->txpowertrack_control = true;
524
525 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "dm txpowertrack_control = %d\n",
526 cali_info->txpowertrack_control);
527
528 /* dm->rf_calibrate_info.txpowertrack_control = true; */
529 cali_info->thermal_value = rtlefu->eeprom_thermalmeter;
530 cali_info->thermal_value_iqk = rtlefu->eeprom_thermalmeter;
531 cali_info->thermal_value_lck = rtlefu->eeprom_thermalmeter;
532
533 if (!cali_info->default_bb_swing_index_flag) {
534 /*The index of "0 dB" in SwingTable.*/
535 if (dm->support_ic_type == ODM_RTL8188E ||
536 dm->support_ic_type == ODM_RTL8723B ||
537 dm->support_ic_type == ODM_RTL8192E ||
538 dm->support_ic_type == ODM_RTL8703B) {
539 cali_info->default_ofdm_index =
540 (default_swing_index >= OFDM_TABLE_SIZE) ?
541 30 :
542 default_swing_index;
543 cali_info->default_cck_index = 20;
544 } else if (dm->support_ic_type ==
545 ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
546 cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
547 cali_info->default_cck_index = 20; /*CCK:-6dB*/
548 } else if (dm->support_ic_type ==
549 ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
550 cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
551 cali_info->default_cck_index = 28; /*CCK: -6dB*/
552 } else if (dm->support_ic_type ==
553 ODM_RTL8710B) { /* JJ ADD 20161014 */
554 cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
555 cali_info->default_cck_index = 28; /*CCK: -6dB*/
556 } else {
557 cali_info->default_ofdm_index =
558 (default_swing_index >= TXSCALE_TABLE_SIZE) ?
559 24 :
560 default_swing_index;
561 cali_info->default_cck_index = 24;
562 }
563 cali_info->default_bb_swing_index_flag = true;
564 }
565
566 cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
567 cali_info->CCK_index = cali_info->default_cck_index;
568
569 for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
570 cali_info->bb_swing_idx_ofdm_base[p] =
571 cali_info->default_ofdm_index;
572 cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
573 cali_info->delta_power_index[p] = 0;
574 cali_info->delta_power_index_last[p] = 0;
575 cali_info->power_index_offset[p] = 0;
576 }
577 cali_info->modify_tx_agc_value_ofdm = 0;
578 cali_info->modify_tx_agc_value_cck = 0;
579}
580
581void odm_txpowertracking_check(void *dm_void)
582{
583 /* 2011/09/29 MH In HW integration first stage, we provide 4 different
584 * handle to operate at the same time.
585 * In the stage2/3, we need to prive universal interface and merge all
586 * HW dynamic mechanism.
587 */
588 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
589
590 switch (dm->support_platform) {
591 case ODM_WIN:
592 odm_txpowertracking_check_mp(dm);
593 break;
594
595 case ODM_CE:
596 odm_txpowertracking_check_ce(dm);
597 break;
598
599 case ODM_AP:
600 odm_txpowertracking_check_ap(dm);
601 break;
602
603 default:
604 break;
605 }
606}
607
608void odm_txpowertracking_check_ce(void *dm_void)
609{
610 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
611 void *adapter = dm->adapter;
612
613 if (!(dm->support_ability & ODM_RF_TX_PWR_TRACK))
614 return;
615
616 if (!dm->rf_calibrate_info.tm_trigger) {
617 if (IS_HARDWARE_TYPE_8188E(adapter) ||
618 IS_HARDWARE_TYPE_8188F(adapter) ||
619 IS_HARDWARE_TYPE_8192E(adapter) ||
620 IS_HARDWARE_TYPE_8723B(adapter) ||
621 IS_HARDWARE_TYPE_JAGUAR(adapter) ||
622 IS_HARDWARE_TYPE_8814A(adapter) ||
623 IS_HARDWARE_TYPE_8703B(adapter) ||
624 IS_HARDWARE_TYPE_8723D(adapter) ||
625 IS_HARDWARE_TYPE_8822B(adapter) ||
626 IS_HARDWARE_TYPE_8821C(adapter) ||
627 (dm->support_ic_type == ODM_RTL8710B)) /* JJ ADD 20161014 */
628 odm_set_rf_reg(dm, ODM_RF_PATH_A, RF_T_METER_NEW,
629 (BIT(17) | BIT(16)), 0x03);
630 else
631 odm_set_rf_reg(dm, ODM_RF_PATH_A, RF_T_METER_OLD,
632 RFREGOFFSETMASK, 0x60);
633
634 dm->rf_calibrate_info.tm_trigger = 1;
635 return;
636 }
637
638 odm_txpowertracking_callback_thermal_meter(dm);
639 dm->rf_calibrate_info.tm_trigger = 0;
640}
641
642void odm_txpowertracking_check_mp(void *dm_void) {}
643
644void odm_txpowertracking_check_ap(void *dm_void) {}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_powertracking_ce.h b/drivers/staging/rtlwifi/phydm/phydm_powertracking_ce.h
new file mode 100644
index 000000000000..757d7720d931
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_powertracking_ce.h
@@ -0,0 +1,293 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMPOWERTRACKING_H__
27#define __PHYDMPOWERTRACKING_H__
28
29#define POWRTRACKING_VERSION "1.1"
30
31#define DPK_DELTA_MAPPING_NUM 13
32#define index_mapping_HP_NUM 15
33#define OFDM_TABLE_SIZE 43
34#define CCK_TABLE_SIZE 33
35#define CCK_TABLE_SIZE_88F 21
36#define TXSCALE_TABLE_SIZE 37
37#define CCK_TABLE_SIZE_8723D 41
38/* JJ ADD 20161014 */
39#define CCK_TABLE_SIZE_8710B 41
40
41#define TXPWR_TRACK_TABLE_SIZE 30
42#define DELTA_SWINGIDX_SIZE 30
43#define DELTA_SWINTSSI_SIZE 61
44#define BAND_NUM 4
45
46#define AVG_THERMAL_NUM 8
47#define HP_THERMAL_NUM 8
48#define IQK_MAC_REG_NUM 4
49#define IQK_ADDA_REG_NUM 16
50#define IQK_BB_REG_NUM_MAX 10
51
52#define IQK_BB_REG_NUM 9
53
54#define iqk_matrix_reg_num 8
55
56extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
57extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
58extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
59
60extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
61extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
62extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
63extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
64extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
65extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
66extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
67/* JJ ADD 20161014 */
68extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
69
70extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
71
72/* <20121018, Kordan> In case fail to read TxPowerTrack.txt,
73 * we use the table of 88E as the default table.
74 */
75
76#define dm_check_txpowertracking odm_txpowertracking_check
77
78struct iqk_matrix_regs_setting {
79 bool is_iqk_done;
80 s32 value[3][iqk_matrix_reg_num];
81 bool is_bw_iqk_result_saved[3];
82};
83
84struct dm_rf_calibration_struct {
85 /* for tx power tracking */
86
87 u32 rega24; /* for TempCCK */
88 s32 rege94;
89 s32 rege9c;
90 s32 regeb4;
91 s32 regebc;
92
93 u8 tx_powercount;
94 bool is_txpowertracking_init;
95 bool is_txpowertracking;
96 /* for mp mode, turn off txpwrtracking as default */
97 u8 txpowertrack_control;
98 u8 tm_trigger;
99 u8 internal_pa_5g[2]; /* pathA / pathB */
100
101 u8 thermal_meter
102 [2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
103 u8 thermal_value;
104 u8 thermal_value_lck;
105 u8 thermal_value_iqk;
106 s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
107 u8 thermal_value_dpk;
108 u8 thermal_value_avg[AVG_THERMAL_NUM];
109 u8 thermal_value_avg_index;
110 u8 thermal_value_rx_gain;
111 u8 thermal_value_crystal;
112 u8 thermal_value_dpk_store;
113 u8 thermal_value_dpk_track;
114 bool txpowertracking_in_progress;
115
116 bool is_reloadtxpowerindex;
117 u8 is_rf_pi_enable;
118 u32 txpowertracking_callback_cnt; /* cosa add for debug */
119
120 /* ---------------------- Tx power Tracking ------------------------- */
121 u8 is_cck_in_ch14;
122 u8 CCK_index;
123 u8 OFDM_index[MAX_RF_PATH];
124 s8 power_index_offset[MAX_RF_PATH];
125 s8 delta_power_index[MAX_RF_PATH];
126 s8 delta_power_index_last[MAX_RF_PATH];
127 bool is_tx_power_changed;
128 s8 xtal_offset;
129 s8 xtal_offset_last;
130
131 u8 thermal_value_hp[HP_THERMAL_NUM];
132 u8 thermal_value_hp_index;
133 struct iqk_matrix_regs_setting
134 iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
135 u8 delta_lck;
136 s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
137 u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
138 u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
139 u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
140 u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
141 u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
142 u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
143 u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
144 u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
145 u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
146 u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
147 u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
148 u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
149 u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
150 u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
151 u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
152 u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
153 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
154 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
155 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
156 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
157 u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
158 u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
159 u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
160 u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
161 u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
162 u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
163 u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
164 u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
165 u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
166 u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
167 u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
168 u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
169 u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
170 u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
171 u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
172 u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
173 s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
174 s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
175 u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
176 u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
177
178 u8 bb_swing_idx_ofdm[MAX_RF_PATH];
179 u8 bb_swing_idx_ofdm_current;
180 u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
181 bool default_bb_swing_index_flag;
182 bool bb_swing_flag_ofdm;
183 u8 bb_swing_idx_cck;
184 u8 bb_swing_idx_cck_current;
185 u8 bb_swing_idx_cck_base;
186 u8 default_ofdm_index;
187 u8 default_cck_index;
188 bool bb_swing_flag_cck;
189
190 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
191 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
192 s8 absolute_cck_swing_idx[MAX_RF_PATH];
193 s8 remnant_cck_swing_idx;
194 s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
195 bool modify_tx_agc_flag_path_a;
196 bool modify_tx_agc_flag_path_b;
197 bool modify_tx_agc_flag_path_c;
198 bool modify_tx_agc_flag_path_d;
199 bool modify_tx_agc_flag_path_a_cck;
200
201 s8 kfree_offset[MAX_RF_PATH];
202
203 /* ------------------------------------------------------------------ */
204
205 /* for IQK */
206 u32 regc04;
207 u32 reg874;
208 u32 regc08;
209 u32 regb68;
210 u32 regb6c;
211 u32 reg870;
212 u32 reg860;
213 u32 reg864;
214
215 bool is_iqk_initialized;
216 bool is_lck_in_progress;
217 bool is_antenna_detected;
218 bool is_need_iqk;
219 bool is_iqk_in_progress;
220 bool is_iqk_pa_off;
221 u8 delta_iqk;
222 u32 ADDA_backup[IQK_ADDA_REG_NUM];
223 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
224 u32 IQK_BB_backup_recover[9];
225 /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
226 u32 IQK_BB_backup[IQK_BB_REG_NUM];
227 u32 tx_iqc_8723b[2][3][2];
228 /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
229 u32 rx_iqc_8723b[2][2][2];
230 /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
231 u32 tx_iqc_8703b[3][2];
232 /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
233 u32 rx_iqc_8703b[2][2];
234 /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
235 u32 tx_iqc_8723d[2][3][2];
236 /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
237 u32 rx_iqc_8723d[2][2][2];
238 /* JJ ADD 20161014 */
239 /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
240 u32 tx_iqc_8710b[2][3][2];
241 /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
242 u32 rx_iqc_8710b[2][2][2];
243
244 u8 iqk_step;
245 u8 kcount;
246 u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
247 bool is_mp_mode;
248
249 /* <James> IQK time measurement */
250 u64 iqk_start_time;
251 u64 iqk_progressing_time;
252 u64 iqk_total_progressing_time;
253
254 u32 lok_result;
255
256 /* for APK */
257 u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
258 u8 is_ap_kdone;
259 u8 is_apk_thermal_meter_ignore;
260
261 /* DPK */
262 bool is_dpk_fail;
263 u8 is_dp_done;
264 u8 is_dp_path_aok;
265 u8 is_dp_path_bok;
266
267 u32 tx_lok[2];
268 u32 dpk_tx_agc;
269 s32 dpk_gain;
270 u32 dpk_thermal[4];
271 s8 modify_tx_agc_value_ofdm;
272 s8 modify_tx_agc_value_cck;
273
274 /*Add by Yuchen for Kfree Phydm*/
275 u8 reg_rf_kfree_enable; /*for registry*/
276 u8 rf_kfree_enable; /*for efuse enable check*/
277};
278
279void odm_txpowertracking_check(void *dm_void);
280
281void odm_txpowertracking_init(void *dm_void);
282
283void odm_txpowertracking_check_ap(void *dm_void);
284
285void odm_txpowertracking_thermal_meter_init(void *dm_void);
286
287void odm_txpowertracking_init(void *dm_void);
288
289void odm_txpowertracking_check_mp(void *dm_void);
290
291void odm_txpowertracking_check_ce(void *dm_void);
292
293#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_pre_define.h b/drivers/staging/rtlwifi/phydm/phydm_pre_define.h
new file mode 100644
index 000000000000..6c301fe87b3d
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_pre_define.h
@@ -0,0 +1,613 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMPREDEFINE_H__
27#define __PHYDMPREDEFINE_H__
28
29/* 1 ============================================================
30 * 1 Definition
31 * 1 ============================================================
32 */
33
34#define PHYDM_CODE_BASE "PHYDM_TRUNK"
35#define PHYDM_RELEASE_DATE "00000000"
36
37/* Max path of IC */
38#define MAX_PATH_NUM_8188E 1
39#define MAX_PATH_NUM_8192E 2
40#define MAX_PATH_NUM_8723B 1
41#define MAX_PATH_NUM_8812A 2
42#define MAX_PATH_NUM_8821A 1
43#define MAX_PATH_NUM_8814A 4
44#define MAX_PATH_NUM_8822B 2
45#define MAX_PATH_NUM_8821B 2
46#define MAX_PATH_NUM_8703B 1
47#define MAX_PATH_NUM_8188F 1
48#define MAX_PATH_NUM_8723D 1
49#define MAX_PATH_NUM_8197F 2
50#define MAX_PATH_NUM_8821C 1
51/* JJ ADD 20161014 */
52#define MAX_PATH_NUM_8710B 1
53
54/* Max RF path */
55#define ODM_RF_PATH_MAX 2
56#define ODM_RF_PATH_MAX_JAGUAR 4
57
58/*Bit define path*/
59#define PHYDM_A BIT(0)
60#define PHYDM_B BIT(1)
61#define PHYDM_C BIT(2)
62#define PHYDM_D BIT(3)
63#define PHYDM_AB (BIT(0) | BIT(1))
64#define PHYDM_AC (BIT(0) | BIT(2))
65#define PHYDM_AD (BIT(0) | BIT(3))
66#define PHYDM_BC (BIT(1) | BIT(2))
67#define PHYDM_BD (BIT(1) | BIT(3))
68#define PHYDM_CD (BIT(2) | BIT(3))
69#define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2))
70#define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3))
71#define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3))
72#define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3))
73#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
74
75/* number of entry */
76/* defined in wifi.h (32+1) */
77#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
78
79#define RX_SMOOTH_FACTOR 20
80
81/* -----MGN rate--------------------------------- */
82
83enum ODM_MGN_RATE {
84 ODM_MGN_1M = 0x02,
85 ODM_MGN_2M = 0x04,
86 ODM_MGN_5_5M = 0x0B,
87 ODM_MGN_6M = 0x0C,
88 ODM_MGN_9M = 0x12,
89 ODM_MGN_11M = 0x16,
90 ODM_MGN_12M = 0x18,
91 ODM_MGN_18M = 0x24,
92 ODM_MGN_24M = 0x30,
93 ODM_MGN_36M = 0x48,
94 ODM_MGN_48M = 0x60,
95 ODM_MGN_54M = 0x6C,
96 ODM_MGN_MCS32 = 0x7F,
97 ODM_MGN_MCS0,
98 ODM_MGN_MCS1,
99 ODM_MGN_MCS2,
100 ODM_MGN_MCS3,
101 ODM_MGN_MCS4,
102 ODM_MGN_MCS5,
103 ODM_MGN_MCS6,
104 ODM_MGN_MCS7,
105 ODM_MGN_MCS8,
106 ODM_MGN_MCS9,
107 ODM_MGN_MCS10,
108 ODM_MGN_MCS11,
109 ODM_MGN_MCS12,
110 ODM_MGN_MCS13,
111 ODM_MGN_MCS14,
112 ODM_MGN_MCS15,
113 ODM_MGN_MCS16,
114 ODM_MGN_MCS17,
115 ODM_MGN_MCS18,
116 ODM_MGN_MCS19,
117 ODM_MGN_MCS20,
118 ODM_MGN_MCS21,
119 ODM_MGN_MCS22,
120 ODM_MGN_MCS23,
121 ODM_MGN_MCS24,
122 ODM_MGN_MCS25,
123 ODM_MGN_MCS26,
124 ODM_MGN_MCS27,
125 ODM_MGN_MCS28,
126 ODM_MGN_MCS29,
127 ODM_MGN_MCS30,
128 ODM_MGN_MCS31,
129 ODM_MGN_VHT1SS_MCS0,
130 ODM_MGN_VHT1SS_MCS1,
131 ODM_MGN_VHT1SS_MCS2,
132 ODM_MGN_VHT1SS_MCS3,
133 ODM_MGN_VHT1SS_MCS4,
134 ODM_MGN_VHT1SS_MCS5,
135 ODM_MGN_VHT1SS_MCS6,
136 ODM_MGN_VHT1SS_MCS7,
137 ODM_MGN_VHT1SS_MCS8,
138 ODM_MGN_VHT1SS_MCS9,
139 ODM_MGN_VHT2SS_MCS0,
140 ODM_MGN_VHT2SS_MCS1,
141 ODM_MGN_VHT2SS_MCS2,
142 ODM_MGN_VHT2SS_MCS3,
143 ODM_MGN_VHT2SS_MCS4,
144 ODM_MGN_VHT2SS_MCS5,
145 ODM_MGN_VHT2SS_MCS6,
146 ODM_MGN_VHT2SS_MCS7,
147 ODM_MGN_VHT2SS_MCS8,
148 ODM_MGN_VHT2SS_MCS9,
149 ODM_MGN_VHT3SS_MCS0,
150 ODM_MGN_VHT3SS_MCS1,
151 ODM_MGN_VHT3SS_MCS2,
152 ODM_MGN_VHT3SS_MCS3,
153 ODM_MGN_VHT3SS_MCS4,
154 ODM_MGN_VHT3SS_MCS5,
155 ODM_MGN_VHT3SS_MCS6,
156 ODM_MGN_VHT3SS_MCS7,
157 ODM_MGN_VHT3SS_MCS8,
158 ODM_MGN_VHT3SS_MCS9,
159 ODM_MGN_VHT4SS_MCS0,
160 ODM_MGN_VHT4SS_MCS1,
161 ODM_MGN_VHT4SS_MCS2,
162 ODM_MGN_VHT4SS_MCS3,
163 ODM_MGN_VHT4SS_MCS4,
164 ODM_MGN_VHT4SS_MCS5,
165 ODM_MGN_VHT4SS_MCS6,
166 ODM_MGN_VHT4SS_MCS7,
167 ODM_MGN_VHT4SS_MCS8,
168 ODM_MGN_VHT4SS_MCS9,
169 ODM_MGN_UNKNOWN
170};
171
172#define ODM_MGN_MCS0_SG 0xc0
173#define ODM_MGN_MCS1_SG 0xc1
174#define ODM_MGN_MCS2_SG 0xc2
175#define ODM_MGN_MCS3_SG 0xc3
176#define ODM_MGN_MCS4_SG 0xc4
177#define ODM_MGN_MCS5_SG 0xc5
178#define ODM_MGN_MCS6_SG 0xc6
179#define ODM_MGN_MCS7_SG 0xc7
180#define ODM_MGN_MCS8_SG 0xc8
181#define ODM_MGN_MCS9_SG 0xc9
182#define ODM_MGN_MCS10_SG 0xca
183#define ODM_MGN_MCS11_SG 0xcb
184#define ODM_MGN_MCS12_SG 0xcc
185#define ODM_MGN_MCS13_SG 0xcd
186#define ODM_MGN_MCS14_SG 0xce
187#define ODM_MGN_MCS15_SG 0xcf
188
189/* -----DESC rate--------------------------------- */
190
191#define ODM_RATEMCS15_SG 0x1c
192#define ODM_RATEMCS32 0x20
193
194/* CCK Rates, TxHT = 0 */
195#define ODM_RATE1M 0x00
196#define ODM_RATE2M 0x01
197#define ODM_RATE5_5M 0x02
198#define ODM_RATE11M 0x03
199/* OFDM Rates, TxHT = 0 */
200#define ODM_RATE6M 0x04
201#define ODM_RATE9M 0x05
202#define ODM_RATE12M 0x06
203#define ODM_RATE18M 0x07
204#define ODM_RATE24M 0x08
205#define ODM_RATE36M 0x09
206#define ODM_RATE48M 0x0A
207#define ODM_RATE54M 0x0B
208/* MCS Rates, TxHT = 1 */
209#define ODM_RATEMCS0 0x0C
210#define ODM_RATEMCS1 0x0D
211#define ODM_RATEMCS2 0x0E
212#define ODM_RATEMCS3 0x0F
213#define ODM_RATEMCS4 0x10
214#define ODM_RATEMCS5 0x11
215#define ODM_RATEMCS6 0x12
216#define ODM_RATEMCS7 0x13
217#define ODM_RATEMCS8 0x14
218#define ODM_RATEMCS9 0x15
219#define ODM_RATEMCS10 0x16
220#define ODM_RATEMCS11 0x17
221#define ODM_RATEMCS12 0x18
222#define ODM_RATEMCS13 0x19
223#define ODM_RATEMCS14 0x1A
224#define ODM_RATEMCS15 0x1B
225#define ODM_RATEMCS16 0x1C
226#define ODM_RATEMCS17 0x1D
227#define ODM_RATEMCS18 0x1E
228#define ODM_RATEMCS19 0x1F
229#define ODM_RATEMCS20 0x20
230#define ODM_RATEMCS21 0x21
231#define ODM_RATEMCS22 0x22
232#define ODM_RATEMCS23 0x23
233#define ODM_RATEMCS24 0x24
234#define ODM_RATEMCS25 0x25
235#define ODM_RATEMCS26 0x26
236#define ODM_RATEMCS27 0x27
237#define ODM_RATEMCS28 0x28
238#define ODM_RATEMCS29 0x29
239#define ODM_RATEMCS30 0x2A
240#define ODM_RATEMCS31 0x2B
241#define ODM_RATEVHTSS1MCS0 0x2C
242#define ODM_RATEVHTSS1MCS1 0x2D
243#define ODM_RATEVHTSS1MCS2 0x2E
244#define ODM_RATEVHTSS1MCS3 0x2F
245#define ODM_RATEVHTSS1MCS4 0x30
246#define ODM_RATEVHTSS1MCS5 0x31
247#define ODM_RATEVHTSS1MCS6 0x32
248#define ODM_RATEVHTSS1MCS7 0x33
249#define ODM_RATEVHTSS1MCS8 0x34
250#define ODM_RATEVHTSS1MCS9 0x35
251#define ODM_RATEVHTSS2MCS0 0x36
252#define ODM_RATEVHTSS2MCS1 0x37
253#define ODM_RATEVHTSS2MCS2 0x38
254#define ODM_RATEVHTSS2MCS3 0x39
255#define ODM_RATEVHTSS2MCS4 0x3A
256#define ODM_RATEVHTSS2MCS5 0x3B
257#define ODM_RATEVHTSS2MCS6 0x3C
258#define ODM_RATEVHTSS2MCS7 0x3D
259#define ODM_RATEVHTSS2MCS8 0x3E
260#define ODM_RATEVHTSS2MCS9 0x3F
261#define ODM_RATEVHTSS3MCS0 0x40
262#define ODM_RATEVHTSS3MCS1 0x41
263#define ODM_RATEVHTSS3MCS2 0x42
264#define ODM_RATEVHTSS3MCS3 0x43
265#define ODM_RATEVHTSS3MCS4 0x44
266#define ODM_RATEVHTSS3MCS5 0x45
267#define ODM_RATEVHTSS3MCS6 0x46
268#define ODM_RATEVHTSS3MCS7 0x47
269#define ODM_RATEVHTSS3MCS8 0x48
270#define ODM_RATEVHTSS3MCS9 0x49
271#define ODM_RATEVHTSS4MCS0 0x4A
272#define ODM_RATEVHTSS4MCS1 0x4B
273#define ODM_RATEVHTSS4MCS2 0x4C
274#define ODM_RATEVHTSS4MCS3 0x4D
275#define ODM_RATEVHTSS4MCS4 0x4E
276#define ODM_RATEVHTSS4MCS5 0x4F
277#define ODM_RATEVHTSS4MCS6 0x50
278#define ODM_RATEVHTSS4MCS7 0x51
279#define ODM_RATEVHTSS4MCS8 0x52
280#define ODM_RATEVHTSS4MCS9 0x53
281
282#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
283
284/* 1 ============================================================
285 * 1 enumeration
286 * 1 ============================================================
287 */
288
289/* ODM_CMNINFO_INTERFACE */
290enum odm_interface {
291 ODM_ITRF_PCIE = 0x1,
292 ODM_ITRF_USB = 0x2,
293 ODM_ITRF_SDIO = 0x4,
294 ODM_ITRF_ALL = 0x7,
295};
296
297/* ODM_CMNINFO_IC_TYPE */
298enum odm_ic_type {
299 ODM_RTL8188E = BIT(0),
300 ODM_RTL8812 = BIT(1),
301 ODM_RTL8821 = BIT(2),
302 ODM_RTL8192E = BIT(3),
303 ODM_RTL8723B = BIT(4),
304 ODM_RTL8814A = BIT(5),
305 ODM_RTL8881A = BIT(6),
306 ODM_RTL8822B = BIT(7),
307 ODM_RTL8703B = BIT(8),
308 ODM_RTL8195A = BIT(9),
309 ODM_RTL8188F = BIT(10),
310 ODM_RTL8723D = BIT(11),
311 ODM_RTL8197F = BIT(12),
312 ODM_RTL8821C = BIT(13),
313 ODM_RTL8814B = BIT(14),
314 ODM_RTL8198F = BIT(15),
315 /* JJ ADD 20161014 */
316 ODM_RTL8710B = BIT(16),
317};
318
319/* JJ ADD 20161014 */
320#define ODM_IC_1SS \
321 (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | \
322 ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | \
323 ODM_RTL8195A | ODM_RTL8710B)
324#define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B)
325#define ODM_IC_3SS (ODM_RTL8814A)
326#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F)
327
328/* JJ ADD 20161014 */
329#define ODM_IC_11N_SERIES \
330 (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | \
331 ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B)
332#define ODM_IC_11AC_SERIES \
333 (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | \
334 ODM_RTL8822B | ODM_RTL8821C)
335#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
336#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
337#define ODM_IC_TXBF_SUPPORT \
338 (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | \
339 ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
340#define ODM_IC_11N_GAIN_IDX_EDCCA \
341 (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | \
342 ODM_RTL8197F | ODM_RTL8710B)
343#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
344#define ODM_IC_PHY_STATUE_NEW_TYPE \
345 (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | \
346 ODM_RTL8710B)
347
348#define PHYDM_IC_8051_SERIES \
349 (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E | \
350 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F)
351#define PHYDM_IC_3081_SERIES \
352 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
353
354#define PHYDM_IC_SUPPORT_LA_MODE \
355 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
356
357/* JJ ADD 20161014 */
358
359/* ODM_CMNINFO_CUT_VER */
360enum odm_cut_version {
361 ODM_CUT_A = 0,
362 ODM_CUT_B = 1,
363 ODM_CUT_C = 2,
364 ODM_CUT_D = 3,
365 ODM_CUT_E = 4,
366 ODM_CUT_F = 5,
367
368 ODM_CUT_I = 8,
369 ODM_CUT_J = 9,
370 ODM_CUT_K = 10,
371 ODM_CUT_TEST = 15,
372};
373
374/* ODM_CMNINFO_FAB_VER */
375enum odm_fab {
376 ODM_TSMC = 0,
377 ODM_UMC = 1,
378};
379
380/* ODM_CMNINFO_RF_TYPE
381 *
382 * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5))
383 */
384enum odm_rf_path {
385 ODM_RF_A = BIT(0),
386 ODM_RF_B = BIT(1),
387 ODM_RF_C = BIT(2),
388 ODM_RF_D = BIT(3),
389};
390
391enum odm_rf_tx_num {
392 ODM_1T = 1,
393 ODM_2T = 2,
394 ODM_3T = 3,
395 ODM_4T = 4,
396};
397
398enum odm_rf_type {
399 ODM_1T1R,
400 ODM_1T2R,
401 ODM_2T2R,
402 ODM_2T2R_GREEN,
403 ODM_2T3R,
404 ODM_2T4R,
405 ODM_3T3R,
406 ODM_3T4R,
407 ODM_4T4R,
408 ODM_XTXR
409};
410
411enum odm_mac_phy_mode {
412 ODM_SMSP = 0,
413 ODM_DMSP = 1,
414 ODM_DMDP = 2,
415};
416
417enum odm_bt_coexist {
418 ODM_BT_BUSY = 1,
419 ODM_BT_ON = 2,
420 ODM_BT_OFF = 3,
421 ODM_BT_NONE = 4,
422};
423
424/* ODM_CMNINFO_OP_MODE */
425enum odm_operation_mode {
426 ODM_NO_LINK = BIT(0),
427 ODM_LINK = BIT(1),
428 ODM_SCAN = BIT(2),
429 ODM_POWERSAVE = BIT(3),
430 ODM_AP_MODE = BIT(4),
431 ODM_CLIENT_MODE = BIT(5),
432 ODM_AD_HOC = BIT(6),
433 ODM_WIFI_DIRECT = BIT(7),
434 ODM_WIFI_DISPLAY = BIT(8),
435};
436
437/* ODM_CMNINFO_WM_MODE */
438enum odm_wireless_mode {
439 ODM_WM_UNKNOWN = 0x0,
440 ODM_WM_B = BIT(0),
441 ODM_WM_G = BIT(1),
442 ODM_WM_A = BIT(2),
443 ODM_WM_N24G = BIT(3),
444 ODM_WM_N5G = BIT(4),
445 ODM_WM_AUTO = BIT(5),
446 ODM_WM_AC = BIT(6),
447};
448
449/* ODM_CMNINFO_BAND */
450enum odm_band_type {
451 ODM_BAND_2_4G = 0,
452 ODM_BAND_5G,
453 ODM_BAND_ON_BOTH,
454 ODM_BANDMAX
455};
456
457/* ODM_CMNINFO_SEC_CHNL_OFFSET */
458enum phydm_sec_chnl_offset {
459 PHYDM_DONT_CARE = 0,
460 PHYDM_BELOW = 1,
461 PHYDM_ABOVE = 2
462};
463
464/* ODM_CMNINFO_SEC_MODE */
465enum odm_security {
466 ODM_SEC_OPEN = 0,
467 ODM_SEC_WEP40 = 1,
468 ODM_SEC_TKIP = 2,
469 ODM_SEC_RESERVE = 3,
470 ODM_SEC_AESCCMP = 4,
471 ODM_SEC_WEP104 = 5,
472 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
473 ODM_SEC_SMS4 = 7,
474};
475
476/* ODM_CMNINFO_BW */
477enum odm_bw {
478 ODM_BW20M = 0,
479 ODM_BW40M = 1,
480 ODM_BW80M = 2,
481 ODM_BW160M = 3,
482 ODM_BW5M = 4,
483 ODM_BW10M = 5,
484 ODM_BW_MAX = 6
485};
486
487/* ODM_CMNINFO_CHNL */
488
489/* ODM_CMNINFO_BOARD_TYPE */
490enum odm_board_type {
491 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
492 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */
493 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
494 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
495 ODM_BOARD_EXT_PA =
496 BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */
497 ODM_BOARD_EXT_LNA =
498 BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
499 ODM_BOARD_EXT_TRSW =
500 BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */
501 ODM_BOARD_EXT_PA_5G =
502 BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */
503 ODM_BOARD_EXT_LNA_5G =
504 BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
505};
506
507enum odm_package_type {
508 ODM_PACKAGE_DEFAULT = 0,
509 ODM_PACKAGE_QFN68 = BIT(0),
510 ODM_PACKAGE_TFBGA90 = BIT(1),
511 ODM_PACKAGE_TFBGA79 = BIT(2),
512};
513
514enum odm_type_gpa {
515 TYPE_GPA0 = 0x0000,
516 TYPE_GPA1 = 0x0055,
517 TYPE_GPA2 = 0x00AA,
518 TYPE_GPA3 = 0x00FF,
519 TYPE_GPA4 = 0x5500,
520 TYPE_GPA5 = 0x5555,
521 TYPE_GPA6 = 0x55AA,
522 TYPE_GPA7 = 0x55FF,
523 TYPE_GPA8 = 0xAA00,
524 TYPE_GPA9 = 0xAA55,
525 TYPE_GPA10 = 0xAAAA,
526 TYPE_GPA11 = 0xAAFF,
527 TYPE_GPA12 = 0xFF00,
528 TYPE_GPA13 = 0xFF55,
529 TYPE_GPA14 = 0xFFAA,
530 TYPE_GPA15 = 0xFFFF,
531};
532
533enum odm_type_apa {
534 TYPE_APA0 = 0x0000,
535 TYPE_APA1 = 0x0055,
536 TYPE_APA2 = 0x00AA,
537 TYPE_APA3 = 0x00FF,
538 TYPE_APA4 = 0x5500,
539 TYPE_APA5 = 0x5555,
540 TYPE_APA6 = 0x55AA,
541 TYPE_APA7 = 0x55FF,
542 TYPE_APA8 = 0xAA00,
543 TYPE_APA9 = 0xAA55,
544 TYPE_APA10 = 0xAAAA,
545 TYPE_APA11 = 0xAAFF,
546 TYPE_APA12 = 0xFF00,
547 TYPE_APA13 = 0xFF55,
548 TYPE_APA14 = 0xFFAA,
549 TYPE_APA15 = 0xFFFF,
550};
551
552enum odm_type_glna {
553 TYPE_GLNA0 = 0x0000,
554 TYPE_GLNA1 = 0x0055,
555 TYPE_GLNA2 = 0x00AA,
556 TYPE_GLNA3 = 0x00FF,
557 TYPE_GLNA4 = 0x5500,
558 TYPE_GLNA5 = 0x5555,
559 TYPE_GLNA6 = 0x55AA,
560 TYPE_GLNA7 = 0x55FF,
561 TYPE_GLNA8 = 0xAA00,
562 TYPE_GLNA9 = 0xAA55,
563 TYPE_GLNA10 = 0xAAAA,
564 TYPE_GLNA11 = 0xAAFF,
565 TYPE_GLNA12 = 0xFF00,
566 TYPE_GLNA13 = 0xFF55,
567 TYPE_GLNA14 = 0xFFAA,
568 TYPE_GLNA15 = 0xFFFF,
569};
570
571enum odm_type_alna {
572 TYPE_ALNA0 = 0x0000,
573 TYPE_ALNA1 = 0x0055,
574 TYPE_ALNA2 = 0x00AA,
575 TYPE_ALNA3 = 0x00FF,
576 TYPE_ALNA4 = 0x5500,
577 TYPE_ALNA5 = 0x5555,
578 TYPE_ALNA6 = 0x55AA,
579 TYPE_ALNA7 = 0x55FF,
580 TYPE_ALNA8 = 0xAA00,
581 TYPE_ALNA9 = 0xAA55,
582 TYPE_ALNA10 = 0xAAAA,
583 TYPE_ALNA11 = 0xAAFF,
584 TYPE_ALNA12 = 0xFF00,
585 TYPE_ALNA13 = 0xFF55,
586 TYPE_ALNA14 = 0xFFAA,
587 TYPE_ALNA15 = 0xFFFF,
588};
589
590enum odm_rf_radio_path {
591 ODM_RF_PATH_A = 0, /* Radio path A */
592 ODM_RF_PATH_B = 1, /* Radio path B */
593 ODM_RF_PATH_C = 2, /* Radio path C */
594 ODM_RF_PATH_D = 3, /* Radio path D */
595 ODM_RF_PATH_AB,
596 ODM_RF_PATH_AC,
597 ODM_RF_PATH_AD,
598 ODM_RF_PATH_BC,
599 ODM_RF_PATH_BD,
600 ODM_RF_PATH_CD,
601 ODM_RF_PATH_ABC,
602 ODM_RF_PATH_ACD,
603 ODM_RF_PATH_BCD,
604 ODM_RF_PATH_ABCD,
605 /* ODM_RF_PATH_MAX, */ /* Max RF number 90 support */
606};
607
608enum odm_parameter_init {
609 ODM_PRE_SETTING = 0,
610 ODM_POST_SETTING = 1,
611};
612
613#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_precomp.h b/drivers/staging/rtlwifi/phydm/phydm_precomp.h
new file mode 100644
index 000000000000..bada15c4d2d8
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_precomp.h
@@ -0,0 +1,85 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __ODM_PRECOMP_H__
27#define __ODM_PRECOMP_H__
28
29#include "phydm_types.h"
30
31/* 2 Config Flags and Structs - defined by each ODM type */
32
33#include "../wifi.h"
34#include "rtl_phydm.h"
35
36/* 2 OutSrc Header Files */
37
38#include "phydm.h"
39#include "phydm_hwconfig.h"
40#include "phydm_debug.h"
41#include "phydm_regdefine11ac.h"
42#include "phydm_regdefine11n.h"
43#include "phydm_interface.h"
44#include "phydm_reg.h"
45
46#include "phydm_adc_sampling.h"
47
48/* JJ ADD 20161014 */
49
50#include "../halmac/halmac_reg2.h"
51
52#define LDPC_HT_ENABLE_RX BIT(0)
53#define LDPC_HT_ENABLE_TX BIT(1)
54#define LDPC_HT_TEST_TX_ENABLE BIT(2)
55#define LDPC_HT_CAP_TX BIT(3)
56
57#define STBC_HT_ENABLE_RX BIT(0)
58#define STBC_HT_ENABLE_TX BIT(1)
59#define STBC_HT_TEST_TX_ENABLE BIT(2)
60#define STBC_HT_CAP_TX BIT(3)
61
62#define LDPC_VHT_ENABLE_RX BIT(0)
63#define LDPC_VHT_ENABLE_TX BIT(1)
64#define LDPC_VHT_TEST_TX_ENABLE BIT(2)
65#define LDPC_VHT_CAP_TX BIT(3)
66
67#define STBC_VHT_ENABLE_RX BIT(0)
68#define STBC_VHT_ENABLE_TX BIT(1)
69#define STBC_VHT_TEST_TX_ENABLE BIT(2)
70#define STBC_VHT_CAP_TX BIT(3)
71
72#include "rtl8822b/halhwimg8822b_mac.h"
73#include "rtl8822b/halhwimg8822b_rf.h"
74#include "rtl8822b/halhwimg8822b_bb.h"
75#include "rtl8822b/phydm_regconfig8822b.h"
76#include "rtl8822b/halphyrf_8822b.h"
77#include "rtl8822b/phydm_rtl8822b.h"
78#include "rtl8822b/phydm_hal_api8822b.h"
79#include "rtl8822b/version_rtl8822b.h"
80
81#include "../halmac/halmac_reg_8822b.h"
82
83/* JJ ADD 20161014 */
84
85#endif /* __ODM_PRECOMP_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/phydm_psd.c b/drivers/staging/rtlwifi/phydm/phydm_psd.c
new file mode 100644
index 000000000000..48f8776bc8f9
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_psd.c
@@ -0,0 +1,422 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/*============================================================
27 * include files
28 *============================================================
29 */
30#include "mp_precomp.h"
31#include "phydm_precomp.h"
32
33u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
34{
35 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
36 struct psd_info *dm_psd_table = &dm->dm_psd_table;
37 u32 psd_report = 0;
38
39 odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
40
41 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22),
42 1); /*PSD trigger start*/
43 ODM_delay_us(10);
44 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22),
45 0); /*PSD trigger stop*/
46
47 psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, 0xffff);
48 psd_report = odm_convert_to_db(psd_report) + igi;
49
50 return psd_report;
51}
52
53static u8 phydm_psd_stop_trx(void *dm_void)
54{
55 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
56 u32 i;
57 u8 trx_idle_success = false;
58 u32 dbg_port_value = 0;
59
60 /*[Stop TRX]----------------------------------------------------------*/
61 if (!phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3,
62 0x0)) /*set debug port to 0x0*/
63 return STOP_TRX_FAIL;
64
65 for (i = 0; i < 10000; i++) {
66 dbg_port_value = phydm_get_bb_dbg_port_value(dm);
67 if ((dbg_port_value & (BIT(17) | BIT(3))) ==
68 0) /* PHYTXON && CCA_all */ {
69 ODM_RT_TRACE(dm, ODM_COMP_API,
70 "PSD wait for ((%d)) times\n", i);
71
72 trx_idle_success = true;
73 break;
74 }
75 }
76
77 if (trx_idle_success) {
78 /*pause all TX queue*/
79 odm_set_bb_reg(dm, 0x520, 0xff0000, 0xff);
80
81 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
82 /*disable CCK block*/
83 odm_set_bb_reg(dm, 0x808, BIT(28), 0);
84 /*disable OFDM RX CCA*/
85 odm_set_bb_reg(dm, 0x838, BIT(1), 1);
86 } else {
87 /*TBD*/
88 /* disable whole CCK block */
89 odm_set_bb_reg(dm, 0x800, BIT(24), 0);
90 /*[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA]*/
91 odm_set_bb_reg(dm, 0xC14, MASKDWORD, 0x0);
92 }
93
94 } else {
95 return STOP_TRX_FAIL;
96 }
97
98 phydm_release_bb_dbg_port(dm);
99
100 return STOP_TRX_SUCCESS;
101}
102
103static u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
104static u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
105
106void phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
107{
108 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
109 struct psd_info *dm_psd_table = &dm->dm_psd_table;
110 u32 i = 0, mod_tone_idx;
111 u32 t = 0;
112 u16 fft_max_half_bw;
113 u32 psd_igi_a_reg;
114 u32 psd_igi_b_reg;
115 u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
116 u8 ag_rf_mode_reg = 0;
117 u8 rf_reg18_9_8 = 0;
118 u32 psd_result_tmp = 0;
119 u8 psd_result = 0;
120 u8 psd_result_cali_tone[7] = {0};
121 u8 psd_result_cali_val[7] = {0};
122 u8 noise_table_idx = 0;
123
124 if (dm->support_ic_type == ODM_RTL8821) {
125 odm_move_memory(dm, psd_result_cali_tone,
126 psd_result_cali_tone_8821, 7);
127 odm_move_memory(dm, psd_result_cali_val,
128 psd_result_cali_val_8821, 7);
129 }
130
131 dm_psd_table->psd_in_progress = 1;
132
133 /*[Stop DIG]*/
134 dm->support_ability &= ~(ODM_BB_DIG);
135 dm->support_ability &= ~(ODM_BB_FA_CNT);
136
137 ODM_RT_TRACE(dm, ODM_COMP_API, "PSD Start =>\n");
138
139 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
140 psd_igi_a_reg = 0xc50;
141 psd_igi_b_reg = 0xe50;
142 } else {
143 psd_igi_a_reg = 0xc50;
144 psd_igi_b_reg = 0xc58;
145 }
146
147 /*[back up IGI]*/
148 dm_psd_table->initial_gain_backup =
149 odm_get_bb_reg(dm, psd_igi_a_reg, 0xff);
150 odm_set_bb_reg(dm, psd_igi_a_reg, 0xff,
151 0x6e); /*IGI target at 0dBm & make it can't CCA*/
152 odm_set_bb_reg(dm, psd_igi_b_reg, 0xff,
153 0x6e); /*IGI target at 0dBm & make it can't CCA*/
154 ODM_delay_us(10);
155
156 if (phydm_psd_stop_trx(dm) == STOP_TRX_FAIL) {
157 ODM_RT_TRACE(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
158 return;
159 }
160
161 /*[Set IGI]*/
162 odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, igi);
163 odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, igi);
164
165 /*[Backup RF Reg]*/
166 dm_psd_table->rf_0x18_bkp =
167 odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK);
168
169 if (psd_fc_channel > 14) {
170 rf_reg18_9_8 = 1;
171
172 if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
173 ag_rf_mode_reg = 0x1;
174 else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
175 ag_rf_mode_reg = 0x3;
176 else if (psd_fc_channel > 140)
177 ag_rf_mode_reg = 0x5;
178 }
179
180 /* Set RF fc*/
181 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xff, psd_fc_channel);
182 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0x300, rf_reg18_9_8);
183 /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
184 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xc00,
185 dm_psd_table->psd_bw_rf_reg);
186 /* Set RF ag fc mode*/
187 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg);
188
189 ODM_RT_TRACE(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
190 odm_get_bb_reg(dm, 0xc50, MASKDWORD));
191 ODM_RT_TRACE(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
192 odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK));
193
194 /*[Stop 3-wires]*/
195 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
196 odm_set_bb_reg(dm, 0xc00, 0xf, 0x4); /* hardware 3-wire off */
197 odm_set_bb_reg(dm, 0xe00, 0xf, 0x4); /* hardware 3-wire off */
198 } else {
199 odm_set_bb_reg(dm, 0x88c, 0xf00000,
200 0xf); /* 3 wire Disable 88c[23:20]=0xf */
201 }
202 ODM_delay_us(10);
203
204 if (stop_point > (dm_psd_table->fft_smp_point - 1))
205 stop_point = (dm_psd_table->fft_smp_point - 1);
206
207 if (start_point > (dm_psd_table->fft_smp_point - 1))
208 start_point = (dm_psd_table->fft_smp_point - 1);
209
210 if (start_point > stop_point)
211 stop_point = start_point;
212
213 if (stop_point > 127) /* limit of psd_result[128] */
214 stop_point = 127;
215
216 for (i = start_point; i <= stop_point; i++) {
217 fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
218
219 if (i < fft_max_half_bw)
220 mod_tone_idx = i + fft_max_half_bw;
221 else
222 mod_tone_idx = i - fft_max_half_bw;
223
224 psd_result_tmp = 0;
225 for (t = 0; t < dm_psd_table->sw_avg_time; t++)
226 psd_result_tmp +=
227 phydm_get_psd_data(dm, mod_tone_idx, igi);
228 psd_result =
229 (u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
230 dm_psd_table->psd_pwr_common_offset;
231
232 if (dm_psd_table->fft_smp_point == 128 &&
233 (dm_psd_table->noise_k_en)) {
234 if (i > psd_result_cali_tone[noise_table_idx])
235 noise_table_idx++;
236
237 if (noise_table_idx > 6)
238 noise_table_idx = 6;
239
240 if (psd_result >= psd_result_cali_val[noise_table_idx])
241 psd_result =
242 psd_result -
243 psd_result_cali_val[noise_table_idx];
244 else
245 psd_result = 0;
246
247 dm_psd_table->psd_result[i] = psd_result;
248 }
249
250 ODM_RT_TRACE(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
251 mod_tone_idx, psd_result_cali_val[noise_table_idx],
252 psd_result);
253 }
254
255 /*[Start 3-wires]*/
256 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
257 odm_set_bb_reg(dm, 0xc00, 0xf, 0x7); /* hardware 3-wire on */
258 odm_set_bb_reg(dm, 0xe00, 0xf, 0x7); /* hardware 3-wire on */
259 } else {
260 odm_set_bb_reg(dm, 0x88c, 0xf00000,
261 0x0); /* 3 wire enable 88c[23:20]=0x0 */
262 }
263 ODM_delay_us(10);
264
265 /*[Revert Reg]*/
266 odm_set_bb_reg(dm, 0x520, 0xff0000, 0x0); /*start all TX queue*/
267 odm_set_bb_reg(dm, 0x808, BIT(28), 1); /*enable CCK block*/
268 odm_set_bb_reg(dm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/
269
270 odm_set_bb_reg(dm, psd_igi_a_reg, 0xff,
271 dm_psd_table->initial_gain_backup);
272 odm_set_bb_reg(dm, psd_igi_b_reg, 0xff,
273 dm_psd_table->initial_gain_backup);
274
275 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK,
276 dm_psd_table->rf_0x18_bkp);
277
278 ODM_RT_TRACE(dm, ODM_COMP_API, "PSD finished\n\n");
279
280 dm->support_ability |= ODM_BB_DIG;
281 dm->support_ability |= ODM_BB_FA_CNT;
282 dm_psd_table->psd_in_progress = 0;
283}
284
285void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
286 u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
287 u8 psd_input, u8 channel, u8 noise_k_en)
288{
289 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
290 struct psd_info *dm_psd_table = &dm->dm_psd_table;
291 u8 fft_smp_point_idx = 0;
292
293 dm_psd_table->fft_smp_point = fft_smp_point;
294
295 if (sw_avg_time == 0)
296 sw_avg_time = 1;
297
298 dm_psd_table->sw_avg_time = sw_avg_time;
299 dm_psd_table->psd_fc_channel = channel;
300 dm_psd_table->noise_k_en = noise_k_en;
301
302 if (fft_smp_point == 128)
303 fft_smp_point_idx = 0;
304 else if (fft_smp_point == 256)
305 fft_smp_point_idx = 1;
306 else if (fft_smp_point == 512)
307 fft_smp_point_idx = 2;
308 else if (fft_smp_point == 1024)
309 fft_smp_point_idx = 3;
310
311 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
312 odm_set_bb_reg(dm, 0x910, BIT(11) | BIT(10), i_q_setting);
313 odm_set_bb_reg(dm, 0x910, BIT(13) | BIT(12), hw_avg_time);
314 odm_set_bb_reg(dm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx);
315 odm_set_bb_reg(dm, 0x910, BIT(17) | BIT(16), ant_sel);
316 odm_set_bb_reg(dm, 0x910, BIT(23), psd_input);
317 }
318
319 /*bw = (*dm->band_width); //ODM_BW20M */
320 /*channel = *(dm->channel);*/
321}
322
323void phydm_psd_init(void *dm_void)
324{
325 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
326 struct psd_info *dm_psd_table = &dm->dm_psd_table;
327
328 ODM_RT_TRACE(dm, ODM_COMP_API, "PSD para init\n");
329
330 dm_psd_table->psd_in_progress = false;
331
332 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
333 dm_psd_table->psd_reg = 0x910;
334 dm_psd_table->psd_report_reg = 0xF44;
335
336 if (ODM_IC_11AC_2_SERIES)
337 dm_psd_table->psd_bw_rf_reg =
338 1; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
339 else
340 dm_psd_table->psd_bw_rf_reg =
341 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
342
343 } else {
344 dm_psd_table->psd_reg = 0x808;
345 dm_psd_table->psd_report_reg = 0x8B4;
346 dm_psd_table->psd_bw_rf_reg =
347 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
348 }
349
350 if (dm->support_ic_type == ODM_RTL8812)
351 dm_psd_table->psd_pwr_common_offset = 0;
352 else if (dm->support_ic_type == ODM_RTL8821)
353 dm_psd_table->psd_pwr_common_offset = 0;
354 else
355 dm_psd_table->psd_pwr_common_offset = 0;
356
357 phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
358 /*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
359}
360
361void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used, char *output,
362 u32 *_out_len, u32 input_num)
363{
364 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
365 char help[] = "-h";
366 u32 var1[10] = {0};
367 u32 used = *_used;
368 u32 out_len = *_out_len;
369 u8 i;
370
371 if ((strcmp(input[1], help) == 0)) {
372 PHYDM_SNPRINTF(
373 output + used, out_len - used,
374 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
375 PHYDM_SNPRINTF(output + used, out_len - used,
376 "{1} {IGI(hex)} {start_point} {stop_point}\n");
377 return;
378 }
379
380 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
381
382 if (var1[0] == 0) {
383 for (i = 1; i < 10; i++) {
384 if (input[i + 1])
385 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
386 &var1[i]);
387 }
388
389 PHYDM_SNPRINTF(
390 output + used, out_len - used,
391 "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
392 var1[1], var1[2], var1[3], var1[4], var1[5], var1[6],
393 (u8)var1[7], (u8)var1[8]);
394 phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
395 (u8)var1[3], (u16)var1[4], (u8)var1[5],
396 (u8)var1[6], (u8)var1[7], (u8)var1[8]);
397
398 } else if (var1[0] == 1) {
399 PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
400 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
401 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
402 PHYDM_SNPRINTF(
403 output + used, out_len - used,
404 "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
405 var1[1], var1[2], var1[3]);
406 dm->debug_components |= ODM_COMP_API;
407 phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]);
408 dm->debug_components &= (~ODM_COMP_API);
409 }
410}
411
412u8 phydm_get_psd_result_table(void *dm_void, int index)
413{
414 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
415 struct psd_info *dm_psd_table = &dm->dm_psd_table;
416 u8 temp_result = 0;
417
418 if (index < 128)
419 temp_result = dm_psd_table->psd_result[index];
420
421 return temp_result;
422}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_psd.h b/drivers/staging/rtlwifi/phydm/phydm_psd.h
new file mode 100644
index 000000000000..aeb70751d80b
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_psd.h
@@ -0,0 +1,67 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMPSD_H__
27#define __PHYDMPSD_H__
28
29/*#define PSD_VERSION "1.0"*/ /*2016.09.22 Dino*/
30#define PSD_VERSION "1.1" /*2016.10.07 Dino, Add Option for PSD Tone index
31 *Selection
32 */
33
34#define STOP_TRX_SUCCESS 1
35#define STOP_TRX_FAIL 0
36
37struct psd_info {
38 u8 psd_in_progress;
39 u32 psd_reg;
40 u32 psd_report_reg;
41 u8 psd_pwr_common_offset;
42 u16 sw_avg_time;
43 u16 fft_smp_point;
44 u32 initial_gain_backup;
45 u32 rf_0x18_bkp;
46 u16 psd_fc_channel;
47 u32 psd_bw_rf_reg;
48 u8 psd_result[128];
49 u8 noise_k_en;
50};
51
52u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi);
53
54void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used, char *output,
55 u32 *_out_len, u32 input_num);
56
57void phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point);
58
59void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
60 u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
61 u8 psd_input, u8 channel, u8 noise_k_en);
62
63void phydm_psd_init(void *dm_void);
64
65u8 phydm_get_psd_result_table(void *dm_void, int index);
66
67#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_rainfo.c b/drivers/staging/rtlwifi/phydm/phydm_rainfo.c
new file mode 100644
index 000000000000..8c08c76d4eda
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_rainfo.c
@@ -0,0 +1,1208 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/* ************************************************************
27 * include files
28 * *************************************************************/
29#include "mp_precomp.h"
30#include "phydm_precomp.h"
31
32void phydm_h2C_debug(void *dm_void, u32 *const dm_value, u32 *_used,
33 char *output, u32 *_out_len)
34{
35 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
36 u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
37 u8 phydm_h2c_id = (u8)dm_value[0];
38 u8 i;
39 u32 used = *_used;
40 u32 out_len = *_out_len;
41
42 PHYDM_SNPRINTF(output + used, out_len - used,
43 "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id);
44 for (i = 0; i < H2C_MAX_LENGTH; i++) {
45 h2c_parameter[i] = (u8)dm_value[i + 1];
46 PHYDM_SNPRINTF(output + used, out_len - used,
47 "H2C: Byte[%d] = ((0x%x))\n", i,
48 h2c_parameter[i]);
49 }
50
51 odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
52}
53
54void phydm_RA_debug_PCR(void *dm_void, u32 *const dm_value, u32 *_used,
55 char *output, u32 *_out_len)
56{
57 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
58 struct ra_table *ra_tab = &dm->dm_ra_table;
59 u32 used = *_used;
60 u32 out_len = *_out_len;
61
62 if (dm_value[0] == 100) {
63 PHYDM_SNPRINTF(
64 output + used, out_len - used,
65 "[Get] PCR RA_threshold_offset = (( %s%d ))\n",
66 ((ra_tab->RA_threshold_offset == 0) ?
67 " " :
68 ((ra_tab->RA_offset_direction) ? "+" : "-")),
69 ra_tab->RA_threshold_offset);
70 /**/
71 } else if (dm_value[0] == 0) {
72 ra_tab->RA_offset_direction = 0;
73 ra_tab->RA_threshold_offset = (u8)dm_value[1];
74 PHYDM_SNPRINTF(output + used, out_len - used,
75 "[Set] PCR RA_threshold_offset = (( -%d ))\n",
76 ra_tab->RA_threshold_offset);
77 } else if (dm_value[0] == 1) {
78 ra_tab->RA_offset_direction = 1;
79 ra_tab->RA_threshold_offset = (u8)dm_value[1];
80 PHYDM_SNPRINTF(output + used, out_len - used,
81 "[Set] PCR RA_threshold_offset = (( +%d ))\n",
82 ra_tab->RA_threshold_offset);
83 } else {
84 PHYDM_SNPRINTF(output + used, out_len - used, "[Set] Error\n");
85 /**/
86 }
87}
88
89void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
90{
91 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
92
93 u8 para_idx = cmd_buf[0]; /*Retry Penalty, NH, NL*/
94 u8 i;
95
96 ODM_RT_TRACE(dm, PHYDM_COMP_RA_DBG,
97 "[ From FW C2H RA Para ] cmd_buf[0]= (( %d ))\n",
98 cmd_buf[0]);
99
100 if (para_idx == RADBG_DEBUG_MONITOR1) {
101 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
102 "-------------------------------\n");
103 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
104 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
105 "RSSI =", cmd_buf[1]);
106 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
107 "rate =", cmd_buf[2] & 0x7f);
108 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
109 "SGI =", (cmd_buf[2] & 0x80) >> 7);
110 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
111 "BW =", cmd_buf[3]);
112 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
113 "BW_max =", cmd_buf[4]);
114 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
115 "multi_rate0 =", cmd_buf[5]);
116 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
117 "multi_rate1 =", cmd_buf[6]);
118 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
119 "DISRA =", cmd_buf[7]);
120 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
121 "VHT_EN =", cmd_buf[8]);
122 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
123 "SGI_support =", cmd_buf[9]);
124 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
125 "try_ness =", cmd_buf[10]);
126 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
127 "pre_rate =", cmd_buf[11]);
128 } else {
129 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
130 "RSSI =", cmd_buf[1]);
131 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %x\n",
132 "BW =", cmd_buf[2]);
133 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
134 "DISRA =", cmd_buf[3]);
135 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
136 "VHT_EN =", cmd_buf[4]);
137 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
138 "Hightest rate =", cmd_buf[5]);
139 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
140 "Lowest rate =", cmd_buf[6]);
141 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
142 "SGI_support =", cmd_buf[7]);
143 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
144 "Rate_ID =", cmd_buf[8]);
145 ;
146 }
147 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
148 "-------------------------------\n");
149 } else if (para_idx == RADBG_DEBUG_MONITOR2) {
150 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
151 "-------------------------------\n");
152 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
153 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
154 "rate_id =", cmd_buf[1]);
155 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
156 "highest_rate =", cmd_buf[2]);
157 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
158 "lowest_rate =", cmd_buf[3]);
159
160 for (i = 4; i <= 11; i++)
161 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
162 "RAMASK = 0x%x\n", cmd_buf[i]);
163 } else {
164 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
165 "%5s %x%x %x%x %x%x %x%x\n",
166 "RA Mask:", cmd_buf[8], cmd_buf[7],
167 cmd_buf[6], cmd_buf[5], cmd_buf[4],
168 cmd_buf[3], cmd_buf[2], cmd_buf[1]);
169 }
170 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
171 "-------------------------------\n");
172 } else if (para_idx == RADBG_DEBUG_MONITOR3) {
173 for (i = 0; i < (cmd_len - 1); i++)
174 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
175 "content[%d] = %d\n", i, cmd_buf[1 + i]);
176 } else if (para_idx == RADBG_DEBUG_MONITOR4) {
177 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s {%d.%d}\n",
178 "RA version =", cmd_buf[1], cmd_buf[2]);
179 } else if (para_idx == RADBG_DEBUG_MONITOR5) {
180 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
181 "Current rate =", cmd_buf[1]);
182 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
183 "Retry ratio =", cmd_buf[2]);
184 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
185 "rate down ratio =", cmd_buf[3]);
186 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
187 "highest rate =", cmd_buf[4]);
188 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s {0x%x 0x%x}\n",
189 "Muti-try =", cmd_buf[5], cmd_buf[6]);
190 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x%x%x%x%x\n",
191 "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9],
192 cmd_buf[8], cmd_buf[7]);
193 }
194}
195
196void phydm_ra_dynamic_retry_count(void *dm_void)
197{
198 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
199
200 if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
201 return;
202
203 if (dm->pre_b_noisy != dm->noisy_decision) {
204 if (dm->noisy_decision) {
205 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
206 "->Noisy Env. RA fallback value\n");
207 odm_set_mac_reg(dm, 0x430, MASKDWORD, 0x0);
208 odm_set_mac_reg(dm, 0x434, MASKDWORD, 0x04030201);
209 } else {
210 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
211 "->Clean Env. RA fallback value\n");
212 odm_set_mac_reg(dm, 0x430, MASKDWORD, 0x01000000);
213 odm_set_mac_reg(dm, 0x434, MASKDWORD, 0x06050402);
214 }
215 dm->pre_b_noisy = dm->noisy_decision;
216 }
217}
218
219void phydm_ra_dynamic_retry_limit(void *dm_void) {}
220
221void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)
222{
223 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
224 u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
225 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
226 u8 vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0;
227 u8 b_sgi = (rate & 0x80) >> 7;
228
229 ODM_RT_TRACE(dm, dbg_component, "( %s%s%s%s%d%s%s)\n",
230 ((rate_idx >= ODM_RATEVHTSS1MCS0) &&
231 (rate_idx <= ODM_RATEVHTSS1MCS9)) ?
232 "VHT 1ss " :
233 "",
234 ((rate_idx >= ODM_RATEVHTSS2MCS0) &&
235 (rate_idx <= ODM_RATEVHTSS2MCS9)) ?
236 "VHT 2ss " :
237 "",
238 ((rate_idx >= ODM_RATEVHTSS3MCS0) &&
239 (rate_idx <= ODM_RATEVHTSS3MCS9)) ?
240 "VHT 3ss " :
241 "",
242 (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
243 (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) :
244 ((rate_idx >= ODM_RATEMCS0) ?
245 (rate_idx - ODM_RATEMCS0) :
246 ((rate_idx <= ODM_RATE54M) ?
247 legacy_table[rate_idx] :
248 0)),
249 (b_sgi) ? "-S" : " ",
250 (rate_idx >= ODM_RATEMCS0) ? "" : "M");
251}
252
253void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
254{
255 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
256 struct ra_table *ra_tab = &dm->dm_ra_table;
257 u8 macid = cmd_buf[1];
258 u8 rate = cmd_buf[0];
259 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
260 u8 rate_order;
261
262 if (cmd_len >= 4) {
263 if (cmd_buf[3] == 0) {
264 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
265 "TX Init-rate Update[%d]:", macid);
266 /**/
267 } else if (cmd_buf[3] == 0xff) {
268 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
269 "FW Level: Fix rate[%d]:", macid);
270 /**/
271 } else if (cmd_buf[3] == 1) {
272 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
273 "Try Success[%d]:", macid);
274 /**/
275 } else if (cmd_buf[3] == 2) {
276 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
277 "Try Fail & Try Again[%d]:", macid);
278 /**/
279 } else if (cmd_buf[3] == 3) {
280 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
281 "rate Back[%d]:", macid);
282 /**/
283 } else if (cmd_buf[3] == 4) {
284 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
285 "start rate by RSSI[%d]:", macid);
286 /**/
287 } else if (cmd_buf[3] == 5) {
288 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
289 "Try rate[%d]:", macid);
290 /**/
291 }
292 } else {
293 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE, "Tx rate Update[%d]:",
294 macid);
295 /**/
296 }
297
298 phydm_print_rate(dm, rate, ODM_COMP_RATE_ADAPTIVE);
299
300 ra_tab->link_tx_rate[macid] = rate;
301
302 /*trigger power training*/
303
304 rate_order = phydm_rate_order_compute(dm, rate_idx);
305
306 if ((dm->is_one_entry_only) ||
307 ((rate_order > ra_tab->highest_client_tx_order) &&
308 (ra_tab->power_tracking_flag == 1))) {
309 phydm_update_pwr_track(dm, rate_idx);
310 ra_tab->power_tracking_flag = 0;
311 }
312
313 /*trigger dynamic rate ID*/
314}
315
316void odm_rssi_monitor_init(void *dm_void)
317{
318 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
319 struct ra_table *ra_tab = &dm->dm_ra_table;
320
321 ra_tab->firstconnect = false;
322}
323
324void odm_ra_post_action_on_assoc(void *dm_void) {}
325
326void phydm_init_ra_info(void *dm_void)
327{
328 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
329
330 if (dm->support_ic_type == ODM_RTL8822B) {
331 u32 ret_value;
332
333 ret_value = odm_get_bb_reg(dm, 0x4c8, MASKBYTE2);
334 odm_set_bb_reg(dm, 0x4cc, MASKBYTE3, (ret_value - 1));
335 }
336}
337
338void phydm_modify_RA_PCR_threshold(void *dm_void, u8 RA_offset_direction,
339 u8 RA_threshold_offset
340
341 )
342{
343 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
344 struct ra_table *ra_tab = &dm->dm_ra_table;
345
346 ra_tab->RA_offset_direction = RA_offset_direction;
347 ra_tab->RA_threshold_offset = RA_threshold_offset;
348 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
349 "Set RA_threshold_offset = (( %s%d ))\n",
350 ((RA_threshold_offset == 0) ?
351 " " :
352 ((RA_offset_direction) ? "+" : "-")),
353 RA_threshold_offset);
354}
355
356static void odm_rssi_monitor_check_mp(void *dm_void) {}
357
358static void odm_rssi_monitor_check_ce(void *dm_void)
359{
360 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
361 struct ra_table *ra_tab = &dm->dm_ra_table;
362 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
363 struct rtl_mac *mac = rtl_mac(rtlpriv);
364 struct rtl_sta_info *entry;
365 int i;
366 int tmp_entry_min_pwdb = 0xff;
367 unsigned long cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0;
368 u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0;
369 u8 h2c_parameter[H2C_0X42_LENGTH] = {0};
370 u8 cmdlen = H2C_0X42_LENGTH;
371 u8 macid = 0;
372
373 if (!dm->is_linked)
374 return;
375
376 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
377 entry = (struct rtl_sta_info *)dm->odm_sta_info[i];
378 if (!IS_STA_VALID(entry))
379 continue;
380
381 if (is_multicast_ether_addr(entry->mac_addr) ||
382 is_broadcast_ether_addr(entry->mac_addr))
383 continue;
384
385 if (entry->rssi_stat.undecorated_smoothed_pwdb == (-1))
386 continue;
387
388 /* calculate min_pwdb */
389 if (entry->rssi_stat.undecorated_smoothed_pwdb <
390 tmp_entry_min_pwdb)
391 tmp_entry_min_pwdb =
392 entry->rssi_stat.undecorated_smoothed_pwdb;
393
394 /* report RSSI */
395 cur_tx_ok_cnt = rtlpriv->stats.txbytesunicast_inperiod;
396 cur_rx_ok_cnt = rtlpriv->stats.rxbytesunicast_inperiod;
397
398 if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6))
399 UL_DL_STATE = 1;
400 else
401 UL_DL_STATE = 0;
402
403 if (mac->opmode == NL80211_IFTYPE_AP ||
404 mac->opmode == NL80211_IFTYPE_ADHOC) {
405 struct ieee80211_sta *sta = container_of(
406 (void *)entry, struct ieee80211_sta, drv_priv);
407 macid = sta->aid + 1;
408 }
409
410 h2c_parameter[0] = macid;
411 h2c_parameter[2] =
412 entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F;
413
414 if (UL_DL_STATE)
415 h2c_parameter[3] |= RAINFO_BE_RX_STATE;
416
417 if (tx_bf_en)
418 h2c_parameter[3] |= RAINFO_BF_STATE;
419 if (STBC_TX)
420 h2c_parameter[3] |= RAINFO_STBC_STATE;
421 if (dm->noisy_decision)
422 h2c_parameter[3] |= RAINFO_NOISY_STATE;
423
424 if (entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND) {
425 h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
426 entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD;
427 }
428
429 h2c_parameter[4] = (ra_tab->RA_threshold_offset & 0x7f) |
430 (ra_tab->RA_offset_direction << 7);
431
432 odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, cmdlen,
433 h2c_parameter);
434 }
435
436 if (tmp_entry_min_pwdb != 0xff)
437 dm->rssi_min = tmp_entry_min_pwdb;
438}
439
440static void odm_rssi_monitor_check_ap(void *dm_void) {}
441
442void odm_rssi_monitor_check(void *dm_void)
443{
444 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
445
446 if (!(dm->support_ability & ODM_BB_RSSI_MONITOR))
447 return;
448
449 switch (dm->support_platform) {
450 case ODM_WIN:
451 odm_rssi_monitor_check_mp(dm);
452 break;
453
454 case ODM_CE:
455 odm_rssi_monitor_check_ce(dm);
456 break;
457
458 case ODM_AP:
459 odm_rssi_monitor_check_ap(dm);
460 break;
461
462 default:
463 break;
464 }
465}
466
467void odm_rate_adaptive_mask_init(void *dm_void)
468{
469 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
470 struct odm_rate_adaptive *odm_ra = &dm->rate_adaptive;
471
472 odm_ra->type = dm_type_by_driver;
473 if (odm_ra->type == dm_type_by_driver)
474 dm->is_use_ra_mask = true;
475 else
476 dm->is_use_ra_mask = false;
477
478 odm_ra->ratr_state = DM_RATR_STA_INIT;
479
480 odm_ra->ldpc_thres = 35;
481 odm_ra->is_use_ldpc = false;
482
483 odm_ra->high_rssi_thresh = 50;
484 odm_ra->low_rssi_thresh = 20;
485}
486
487/*-----------------------------------------------------------------------------
488 * Function: odm_refresh_rate_adaptive_mask()
489 *
490 * Overview: Update rate table mask according to rssi
491 *
492 * Input: NONE
493 *
494 * Output: NONE
495 *
496 * Return: NONE
497 *
498 * Revised History:
499 * When Who Remark
500 * 05/27/2009 hpfan Create version 0.
501 *
502 *---------------------------------------------------------------------------
503 */
504void odm_refresh_rate_adaptive_mask(void *dm_void)
505{
506 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
507 struct ra_table *ra_tab = &dm->dm_ra_table;
508
509 if (!dm->is_linked)
510 return;
511
512 if (!(dm->support_ability & ODM_BB_RA_MASK)) {
513 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
514 "%s(): Return cos not supported\n", __func__);
515 return;
516 }
517
518 ra_tab->force_update_ra_mask_count++;
519 /* 2011/09/29 MH In HW integration first stage, we provide 4 different
520 * handle to operate at the same time.
521 * In the stage2/3, we need to prive universal interface and merge all
522 * HW dynamic mechanism.
523 */
524 switch (dm->support_platform) {
525 case ODM_WIN:
526 odm_refresh_rate_adaptive_mask_mp(dm);
527 break;
528
529 case ODM_CE:
530 odm_refresh_rate_adaptive_mask_ce(dm);
531 break;
532
533 case ODM_AP:
534 odm_refresh_rate_adaptive_mask_apadsl(dm);
535 break;
536 }
537}
538
539static u8 phydm_trans_platform_bw(void *dm_void, u8 BW)
540{
541 if (BW == HT_CHANNEL_WIDTH_20)
542 BW = PHYDM_BW_20;
543
544 else if (BW == HT_CHANNEL_WIDTH_20_40)
545 BW = PHYDM_BW_40;
546
547 else if (BW == HT_CHANNEL_WIDTH_80)
548 BW = PHYDM_BW_80;
549
550 return BW;
551}
552
553static u8 phydm_trans_platform_rf_type(void *dm_void, u8 rf_type)
554{
555 if (rf_type == RF_1T2R)
556 rf_type = PHYDM_RF_1T2R;
557
558 else if (rf_type == RF_2T4R)
559 rf_type = PHYDM_RF_2T4R;
560
561 else if (rf_type == RF_2T2R)
562 rf_type = PHYDM_RF_2T2R;
563
564 else if (rf_type == RF_1T1R)
565 rf_type = PHYDM_RF_1T1R;
566
567 else if (rf_type == RF_2T2R_GREEN)
568 rf_type = PHYDM_RF_2T2R_GREEN;
569
570 else if (rf_type == RF_3T3R)
571 rf_type = PHYDM_RF_3T3R;
572
573 else if (rf_type == RF_4T4R)
574 rf_type = PHYDM_RF_4T4R;
575
576 else if (rf_type == RF_2T3R)
577 rf_type = PHYDM_RF_1T2R;
578
579 else if (rf_type == RF_3T4R)
580 rf_type = PHYDM_RF_3T4R;
581
582 return rf_type;
583}
584
585static u32 phydm_trans_platform_wireless_mode(void *dm_void, u32 wireless_mode)
586{
587 return wireless_mode;
588}
589
590u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)
591{
592 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
593 u8 vht_en_out = 0;
594
595 if ((wireless_mode == PHYDM_WIRELESS_MODE_AC_5G) ||
596 (wireless_mode == PHYDM_WIRELESS_MODE_AC_24G) ||
597 (wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)) {
598 vht_en_out = 1;
599 /**/
600 }
601
602 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
603 "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n",
604 wireless_mode, vht_en_out);
605 return vht_en_out;
606}
607
608u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)
609{
610 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
611 u8 rate_id_idx = 0;
612 u8 phydm_BW;
613 u8 phydm_rf_type;
614
615 phydm_BW = phydm_trans_platform_bw(dm, bw);
616 phydm_rf_type = phydm_trans_platform_rf_type(dm, rf_type);
617 wireless_mode = phydm_trans_platform_wireless_mode(dm, wireless_mode);
618
619 ODM_RT_TRACE(
620 dm, ODM_COMP_RA_MASK,
621 "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
622 wireless_mode, phydm_rf_type, phydm_BW);
623
624 switch (wireless_mode) {
625 case PHYDM_WIRELESS_MODE_N_24G: {
626 if (phydm_BW == PHYDM_BW_40) {
627 if (phydm_rf_type == PHYDM_RF_1T1R)
628 rate_id_idx = PHYDM_BGN_40M_1SS;
629 else if (phydm_rf_type == PHYDM_RF_2T2R)
630 rate_id_idx = PHYDM_BGN_40M_2SS;
631 else
632 rate_id_idx = PHYDM_ARFR5_N_3SS;
633
634 } else {
635 if (phydm_rf_type == PHYDM_RF_1T1R)
636 rate_id_idx = PHYDM_BGN_20M_1SS;
637 else if (phydm_rf_type == PHYDM_RF_2T2R)
638 rate_id_idx = PHYDM_BGN_20M_2SS;
639 else
640 rate_id_idx = PHYDM_ARFR5_N_3SS;
641 }
642 } break;
643
644 case PHYDM_WIRELESS_MODE_N_5G: {
645 if (phydm_rf_type == PHYDM_RF_1T1R)
646 rate_id_idx = PHYDM_GN_N1SS;
647 else if (phydm_rf_type == PHYDM_RF_2T2R)
648 rate_id_idx = PHYDM_GN_N2SS;
649 else
650 rate_id_idx = PHYDM_ARFR5_N_3SS;
651 }
652
653 break;
654
655 case PHYDM_WIRELESS_MODE_G:
656 rate_id_idx = PHYDM_BG;
657 break;
658
659 case PHYDM_WIRELESS_MODE_A:
660 rate_id_idx = PHYDM_G;
661 break;
662
663 case PHYDM_WIRELESS_MODE_B:
664 rate_id_idx = PHYDM_B_20M;
665 break;
666
667 case PHYDM_WIRELESS_MODE_AC_5G:
668 case PHYDM_WIRELESS_MODE_AC_ONLY: {
669 if (phydm_rf_type == PHYDM_RF_1T1R)
670 rate_id_idx = PHYDM_ARFR1_AC_1SS;
671 else if (phydm_rf_type == PHYDM_RF_2T2R)
672 rate_id_idx = PHYDM_ARFR0_AC_2SS;
673 else
674 rate_id_idx = PHYDM_ARFR4_AC_3SS;
675 } break;
676
677 case PHYDM_WIRELESS_MODE_AC_24G: {
678 /*Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS
679 *in 2.4G/5G
680 */
681 if (phydm_BW >= PHYDM_BW_80) {
682 if (phydm_rf_type == PHYDM_RF_1T1R)
683 rate_id_idx = PHYDM_ARFR1_AC_1SS;
684 else if (phydm_rf_type == PHYDM_RF_2T2R)
685 rate_id_idx = PHYDM_ARFR0_AC_2SS;
686 else
687 rate_id_idx = PHYDM_ARFR4_AC_3SS;
688 } else {
689 if (phydm_rf_type == PHYDM_RF_1T1R)
690 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
691 else if (phydm_rf_type == PHYDM_RF_2T2R)
692 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
693 else
694 rate_id_idx = PHYDM_ARFR4_AC_3SS;
695 }
696 } break;
697
698 default:
699 rate_id_idx = 0;
700 break;
701 }
702
703 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "RA rate ID = (( 0x%x ))\n",
704 rate_id_idx);
705
706 return rate_id_idx;
707}
708
709void phydm_update_hal_ra_mask(void *dm_void, u32 wireless_mode, u8 rf_type,
710 u8 BW, u8 mimo_ps_enable, u8 disable_cck_rate,
711 u32 *ratr_bitmap_msb_in, u32 *ratr_bitmap_lsb_in,
712 u8 tx_rate_level)
713{
714 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
715 u8 phydm_rf_type;
716 u8 phydm_BW;
717 u32 ratr_bitmap = *ratr_bitmap_lsb_in,
718 ratr_bitmap_msb = *ratr_bitmap_msb_in;
719
720 wireless_mode = phydm_trans_platform_wireless_mode(dm, wireless_mode);
721
722 phydm_rf_type = phydm_trans_platform_rf_type(dm, rf_type);
723 phydm_BW = phydm_trans_platform_bw(dm, BW);
724
725 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
726 "Platfoem original RA Mask = (( 0x %x | %x ))\n",
727 ratr_bitmap_msb, ratr_bitmap);
728
729 switch (wireless_mode) {
730 case PHYDM_WIRELESS_MODE_B: {
731 ratr_bitmap &= 0x0000000f;
732 } break;
733
734 case PHYDM_WIRELESS_MODE_G: {
735 ratr_bitmap &= 0x00000ff5;
736 } break;
737
738 case PHYDM_WIRELESS_MODE_A: {
739 ratr_bitmap &= 0x00000ff0;
740 } break;
741
742 case PHYDM_WIRELESS_MODE_N_24G:
743 case PHYDM_WIRELESS_MODE_N_5G: {
744 if (mimo_ps_enable)
745 phydm_rf_type = PHYDM_RF_1T1R;
746
747 if (phydm_rf_type == PHYDM_RF_1T1R) {
748 if (phydm_BW == PHYDM_BW_40)
749 ratr_bitmap &= 0x000ff015;
750 else
751 ratr_bitmap &= 0x000ff005;
752 } else if (phydm_rf_type == PHYDM_RF_2T2R ||
753 phydm_rf_type == PHYDM_RF_2T4R ||
754 phydm_rf_type == PHYDM_RF_2T3R) {
755 if (phydm_BW == PHYDM_BW_40)
756 ratr_bitmap &= 0x0ffff015;
757 else
758 ratr_bitmap &= 0x0ffff005;
759 } else { /*3T*/
760
761 ratr_bitmap &= 0xfffff015;
762 ratr_bitmap_msb &= 0xf;
763 }
764 } break;
765
766 case PHYDM_WIRELESS_MODE_AC_24G: {
767 if (phydm_rf_type == PHYDM_RF_1T1R) {
768 ratr_bitmap &= 0x003ff015;
769 } else if (phydm_rf_type == PHYDM_RF_2T2R ||
770 phydm_rf_type == PHYDM_RF_2T4R ||
771 phydm_rf_type == PHYDM_RF_2T3R) {
772 ratr_bitmap &= 0xfffff015;
773 } else { /*3T*/
774
775 ratr_bitmap &= 0xfffff010;
776 ratr_bitmap_msb &= 0x3ff;
777 }
778
779 if (phydm_BW ==
780 PHYDM_BW_20) { /* AC 20MHz doesn't support MCS9 */
781 ratr_bitmap &= 0x7fdfffff;
782 ratr_bitmap_msb &= 0x1ff;
783 }
784 } break;
785
786 case PHYDM_WIRELESS_MODE_AC_5G: {
787 if (phydm_rf_type == PHYDM_RF_1T1R) {
788 ratr_bitmap &= 0x003ff010;
789 } else if (phydm_rf_type == PHYDM_RF_2T2R ||
790 phydm_rf_type == PHYDM_RF_2T4R ||
791 phydm_rf_type == PHYDM_RF_2T3R) {
792 ratr_bitmap &= 0xfffff010;
793 } else { /*3T*/
794
795 ratr_bitmap &= 0xfffff010;
796 ratr_bitmap_msb &= 0x3ff;
797 }
798
799 if (phydm_BW ==
800 PHYDM_BW_20) { /* AC 20MHz doesn't support MCS9 */
801 ratr_bitmap &= 0x7fdfffff;
802 ratr_bitmap_msb &= 0x1ff;
803 }
804 } break;
805
806 default:
807 break;
808 }
809
810 if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
811 if (tx_rate_level == 0)
812 ratr_bitmap &= 0xffffffff;
813 else if (tx_rate_level == 1)
814 ratr_bitmap &= 0xfffffff0;
815 else if (tx_rate_level == 2)
816 ratr_bitmap &= 0xffffefe0;
817 else if (tx_rate_level == 3)
818 ratr_bitmap &= 0xffffcfc0;
819 else if (tx_rate_level == 4)
820 ratr_bitmap &= 0xffff8f80;
821 else if (tx_rate_level >= 5)
822 ratr_bitmap &= 0xffff0f00;
823 }
824
825 if (disable_cck_rate)
826 ratr_bitmap &= 0xfffffff0;
827
828 ODM_RT_TRACE(
829 dm, ODM_COMP_RA_MASK,
830 "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
831 wireless_mode, phydm_rf_type, phydm_BW, mimo_ps_enable,
832 tx_rate_level);
833
834 *ratr_bitmap_lsb_in = ratr_bitmap;
835 *ratr_bitmap_msb_in = ratr_bitmap_msb;
836 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
837 "Phydm modified RA Mask = (( 0x %x | %x ))\n",
838 *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);
839}
840
841u8 phydm_RA_level_decision(void *dm_void, u32 rssi, u8 ratr_state)
842{
843 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
844 u8 ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {
845 20, 34, 38, 42,
846 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
847 u8 new_ratr_state = 0;
848 u8 i;
849
850 ODM_RT_TRACE(
851 dm, ODM_COMP_RA_MASK,
852 "curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n",
853 ratr_state, ra_rate_floor_table[0], ra_rate_floor_table[1],
854 ra_rate_floor_table[2], ra_rate_floor_table[3],
855 ra_rate_floor_table[4], ra_rate_floor_table[5]);
856
857 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
858 if (i >= (ratr_state))
859 ra_rate_floor_table[i] += RA_FLOOR_UP_GAP;
860 }
861
862 ODM_RT_TRACE(
863 dm, ODM_COMP_RA_MASK,
864 "RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n",
865 rssi, ra_rate_floor_table[0], ra_rate_floor_table[1],
866 ra_rate_floor_table[2], ra_rate_floor_table[3],
867 ra_rate_floor_table[4], ra_rate_floor_table[5]);
868
869 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
870 if (rssi < ra_rate_floor_table[i]) {
871 new_ratr_state = i;
872 break;
873 }
874 }
875
876 return new_ratr_state;
877}
878
879void odm_refresh_rate_adaptive_mask_mp(void *dm_void) {}
880
881void odm_refresh_rate_adaptive_mask_ce(void *dm_void)
882{
883 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
884 struct ra_table *ra_tab = &dm->dm_ra_table;
885 void *adapter = dm->adapter;
886 u32 i;
887 struct rtl_sta_info *entry;
888 u8 ratr_state_new;
889
890 if (!dm->is_use_ra_mask) {
891 ODM_RT_TRACE(
892 dm, ODM_COMP_RA_MASK,
893 "<---- %s(): driver does not control rate adaptive mask\n",
894 __func__);
895 return;
896 }
897
898 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
899 entry = dm->odm_sta_info[i];
900
901 if (!IS_STA_VALID(entry))
902 continue;
903
904 if (is_multicast_ether_addr(entry->mac_addr))
905 continue;
906 else if (is_broadcast_ether_addr(entry->mac_addr))
907 continue;
908
909 ratr_state_new = phydm_RA_level_decision(
910 dm, entry->rssi_stat.undecorated_smoothed_pwdb,
911 entry->rssi_level);
912
913 if ((entry->rssi_level != ratr_state_new) ||
914 (ra_tab->force_update_ra_mask_count >=
915 FORCED_UPDATE_RAMASK_PERIOD)) {
916 ra_tab->force_update_ra_mask_count = 0;
917 ODM_RT_TRACE(
918 dm, ODM_COMP_RA_MASK,
919 "Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n",
920 entry->rssi_level, ratr_state_new,
921 entry->rssi_stat.undecorated_smoothed_pwdb);
922
923 entry->rssi_level = ratr_state_new;
924 rtl_hal_update_ra_mask(adapter, entry,
925 entry->rssi_level);
926 } else {
927 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
928 "Stay in RA level = (( %d ))\n\n",
929 ratr_state_new);
930 /**/
931 }
932 }
933}
934
935void odm_refresh_rate_adaptive_mask_apadsl(void *dm_void) {}
936
937void odm_refresh_basic_rate_mask(void *dm_void) {}
938
939u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
940{
941 u8 rate_order = 0;
942
943 if (rate_idx >= ODM_RATEVHTSS4MCS0) {
944 rate_idx -= ODM_RATEVHTSS4MCS0;
945 /**/
946 } else if (rate_idx >= ODM_RATEVHTSS3MCS0) {
947 rate_idx -= ODM_RATEVHTSS3MCS0;
948 /**/
949 } else if (rate_idx >= ODM_RATEVHTSS2MCS0) {
950 rate_idx -= ODM_RATEVHTSS2MCS0;
951 /**/
952 } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
953 rate_idx -= ODM_RATEVHTSS1MCS0;
954 /**/
955 } else if (rate_idx >= ODM_RATEMCS24) {
956 rate_idx -= ODM_RATEMCS24;
957 /**/
958 } else if (rate_idx >= ODM_RATEMCS16) {
959 rate_idx -= ODM_RATEMCS16;
960 /**/
961 } else if (rate_idx >= ODM_RATEMCS8) {
962 rate_idx -= ODM_RATEMCS8;
963 /**/
964 }
965 rate_order = rate_idx;
966
967 return rate_order;
968}
969
970static void phydm_ra_common_info_update(void *dm_void)
971{
972 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
973 struct ra_table *ra_tab = &dm->dm_ra_table;
974 u16 macid;
975 u8 rate_order_tmp;
976 u8 cnt = 0;
977
978 ra_tab->highest_client_tx_order = 0;
979 ra_tab->power_tracking_flag = 1;
980
981 if (dm->number_linked_client != 0) {
982 for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
983 rate_order_tmp = phydm_rate_order_compute(
984 dm, ((ra_tab->link_tx_rate[macid]) & 0x7f));
985
986 if (rate_order_tmp >=
987 (ra_tab->highest_client_tx_order)) {
988 ra_tab->highest_client_tx_order =
989 rate_order_tmp;
990 ra_tab->highest_client_tx_rate_order = macid;
991 }
992
993 cnt++;
994
995 if (cnt == dm->number_linked_client)
996 break;
997 }
998 ODM_RT_TRACE(
999 dm, ODM_COMP_RATE_ADAPTIVE,
1000 "MACID[%d], Highest Tx order Update for power traking: %d\n",
1001 (ra_tab->highest_client_tx_rate_order),
1002 (ra_tab->highest_client_tx_order));
1003 }
1004}
1005
1006void phydm_ra_info_watchdog(void *dm_void)
1007{
1008 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1009
1010 phydm_ra_common_info_update(dm);
1011 phydm_ra_dynamic_retry_limit(dm);
1012 phydm_ra_dynamic_retry_count(dm);
1013 odm_refresh_rate_adaptive_mask(dm);
1014 odm_refresh_basic_rate_mask(dm);
1015}
1016
1017void phydm_ra_info_init(void *dm_void)
1018{
1019 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1020 struct ra_table *ra_tab = &dm->dm_ra_table;
1021
1022 ra_tab->highest_client_tx_rate_order = 0;
1023 ra_tab->highest_client_tx_order = 0;
1024 ra_tab->RA_threshold_offset = 0;
1025 ra_tab->RA_offset_direction = 0;
1026}
1027
1028u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, bool is_erp_protect)
1029{
1030 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1031 u8 rts_ini_rate = ODM_RATE6M;
1032
1033 if (is_erp_protect) { /* use CCK rate as RTS*/
1034 rts_ini_rate = ODM_RATE1M;
1035 } else {
1036 switch (tx_rate) {
1037 case ODM_RATEVHTSS3MCS9:
1038 case ODM_RATEVHTSS3MCS8:
1039 case ODM_RATEVHTSS3MCS7:
1040 case ODM_RATEVHTSS3MCS6:
1041 case ODM_RATEVHTSS3MCS5:
1042 case ODM_RATEVHTSS3MCS4:
1043 case ODM_RATEVHTSS3MCS3:
1044 case ODM_RATEVHTSS2MCS9:
1045 case ODM_RATEVHTSS2MCS8:
1046 case ODM_RATEVHTSS2MCS7:
1047 case ODM_RATEVHTSS2MCS6:
1048 case ODM_RATEVHTSS2MCS5:
1049 case ODM_RATEVHTSS2MCS4:
1050 case ODM_RATEVHTSS2MCS3:
1051 case ODM_RATEVHTSS1MCS9:
1052 case ODM_RATEVHTSS1MCS8:
1053 case ODM_RATEVHTSS1MCS7:
1054 case ODM_RATEVHTSS1MCS6:
1055 case ODM_RATEVHTSS1MCS5:
1056 case ODM_RATEVHTSS1MCS4:
1057 case ODM_RATEVHTSS1MCS3:
1058 case ODM_RATEMCS15:
1059 case ODM_RATEMCS14:
1060 case ODM_RATEMCS13:
1061 case ODM_RATEMCS12:
1062 case ODM_RATEMCS11:
1063 case ODM_RATEMCS7:
1064 case ODM_RATEMCS6:
1065 case ODM_RATEMCS5:
1066 case ODM_RATEMCS4:
1067 case ODM_RATEMCS3:
1068 case ODM_RATE54M:
1069 case ODM_RATE48M:
1070 case ODM_RATE36M:
1071 case ODM_RATE24M:
1072 rts_ini_rate = ODM_RATE24M;
1073 break;
1074 case ODM_RATEVHTSS3MCS2:
1075 case ODM_RATEVHTSS3MCS1:
1076 case ODM_RATEVHTSS2MCS2:
1077 case ODM_RATEVHTSS2MCS1:
1078 case ODM_RATEVHTSS1MCS2:
1079 case ODM_RATEVHTSS1MCS1:
1080 case ODM_RATEMCS10:
1081 case ODM_RATEMCS9:
1082 case ODM_RATEMCS2:
1083 case ODM_RATEMCS1:
1084 case ODM_RATE18M:
1085 case ODM_RATE12M:
1086 rts_ini_rate = ODM_RATE12M;
1087 break;
1088 case ODM_RATEVHTSS3MCS0:
1089 case ODM_RATEVHTSS2MCS0:
1090 case ODM_RATEVHTSS1MCS0:
1091 case ODM_RATEMCS8:
1092 case ODM_RATEMCS0:
1093 case ODM_RATE9M:
1094 case ODM_RATE6M:
1095 rts_ini_rate = ODM_RATE6M;
1096 break;
1097 case ODM_RATE11M:
1098 case ODM_RATE5_5M:
1099 case ODM_RATE2M:
1100 case ODM_RATE1M:
1101 rts_ini_rate = ODM_RATE1M;
1102 break;
1103 default:
1104 rts_ini_rate = ODM_RATE6M;
1105 break;
1106 }
1107 }
1108
1109 if (*dm->band_type == 1) {
1110 if (rts_ini_rate < ODM_RATE6M)
1111 rts_ini_rate = ODM_RATE6M;
1112 }
1113 return rts_ini_rate;
1114}
1115
1116static void odm_set_ra_dm_arfb_by_noisy(struct phy_dm_struct *dm) {}
1117
1118void odm_update_noisy_state(void *dm_void, bool is_noisy_state_from_c2h)
1119{
1120 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1121
1122 /* JJ ADD 20161014 */
1123 if (dm->support_ic_type == ODM_RTL8821 ||
1124 dm->support_ic_type == ODM_RTL8812 ||
1125 dm->support_ic_type == ODM_RTL8723B ||
1126 dm->support_ic_type == ODM_RTL8192E ||
1127 dm->support_ic_type == ODM_RTL8188E ||
1128 dm->support_ic_type == ODM_RTL8723D ||
1129 dm->support_ic_type == ODM_RTL8710B)
1130 dm->is_noisy_state = is_noisy_state_from_c2h;
1131 odm_set_ra_dm_arfb_by_noisy(dm);
1132};
1133
1134void phydm_update_pwr_track(void *dm_void, u8 rate)
1135{
1136 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1137
1138 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n",
1139 rate);
1140
1141 dm->tx_rate = rate;
1142}
1143
1144/* RA_MASK_PHYDMLIZE, will delete it later*/
1145
1146bool odm_ra_state_check(void *dm_void, s32 rssi, bool is_force_update,
1147 u8 *ra_tr_state)
1148{
1149 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1150 struct odm_rate_adaptive *ra = &dm->rate_adaptive;
1151 const u8 go_up_gap = 5;
1152 u8 high_rssi_thresh_for_ra = ra->high_rssi_thresh;
1153 u8 low_rssi_thresh_for_ra = ra->low_rssi_thresh;
1154 u8 ratr_state;
1155
1156 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1157 "RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", rssi,
1158 *ra_tr_state);
1159 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1160 "[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n",
1161 high_rssi_thresh_for_ra, low_rssi_thresh_for_ra);
1162 /* threshold Adjustment:
1163 * when RSSI state trends to go up one or two levels, make sure RSSI is
1164 * high enough. Here go_up_gap is added to solve the boundary's level
1165 * alternation issue.
1166 */
1167
1168 switch (*ra_tr_state) {
1169 case DM_RATR_STA_INIT:
1170 case DM_RATR_STA_HIGH:
1171 break;
1172
1173 case DM_RATR_STA_MIDDLE:
1174 high_rssi_thresh_for_ra += go_up_gap;
1175 break;
1176
1177 case DM_RATR_STA_LOW:
1178 high_rssi_thresh_for_ra += go_up_gap;
1179 low_rssi_thresh_for_ra += go_up_gap;
1180 break;
1181
1182 default:
1183 WARN_ONCE(true, "wrong rssi level setting %d !", *ra_tr_state);
1184 break;
1185 }
1186
1187 /* Decide ratr_state by RSSI.*/
1188 if (rssi > high_rssi_thresh_for_ra)
1189 ratr_state = DM_RATR_STA_HIGH;
1190 else if (rssi > low_rssi_thresh_for_ra)
1191 ratr_state = DM_RATR_STA_MIDDLE;
1192
1193 else
1194 ratr_state = DM_RATR_STA_LOW;
1195 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1196 "[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n",
1197 high_rssi_thresh_for_ra, low_rssi_thresh_for_ra);
1198
1199 if (*ra_tr_state != ratr_state || is_force_update) {
1200 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1201 "[RSSI Level Update] %d->%d\n", *ra_tr_state,
1202 ratr_state);
1203 *ra_tr_state = ratr_state;
1204 return true;
1205 }
1206
1207 return false;
1208}
diff --git a/drivers/staging/rtlwifi/phydm/phydm_rainfo.h b/drivers/staging/rtlwifi/phydm/phydm_rainfo.h
new file mode 100644
index 000000000000..c14ed9bda0af
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_rainfo.h
@@ -0,0 +1,269 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __PHYDMRAINFO_H__
27#define __PHYDMRAINFO_H__
28
29/*#define RAINFO_VERSION "2.0"*/ /*2014.11.04*/
30/*#define RAINFO_VERSION "3.0"*/ /*2015.01.13 Dino*/
31/*#define RAINFO_VERSION "3.1"*/ /*2015.01.14 Dino*/
32/*#define RAINFO_VERSION "3.3"*/ /*2015.07.29 YuChen*/
33/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
34/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask
35 *state and Phydm-lize partial ra mask
36 *function
37 */
38/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to
39 *adjust PCR RA threshold
40 */
41/*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */
42#define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem*/
43
44#define FORCED_UPDATE_RAMASK_PERIOD 5
45
46#define H2C_0X42_LENGTH 5
47#define H2C_MAX_LENGTH 7
48
49#define RA_FLOOR_UP_GAP 3
50#define RA_FLOOR_TABLE_SIZE 7
51
52#define ACTIVE_TP_THRESHOLD 150
53#define RA_RETRY_DESCEND_NUM 2
54#define RA_RETRY_LIMIT_LOW 4
55#define RA_RETRY_LIMIT_HIGH 32
56
57#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */
58#define RAINFO_STBC_STATE BIT(1)
59/* #define RAINFO_LDPC_STATE BIT2 */
60#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */
61#define RAINFO_SHURTCUT_STATE BIT(3)
62#define RAINFO_SHURTCUT_FLAG BIT(4)
63#define RAINFO_INIT_RSSI_RATE_STATE BIT(5)
64#define RAINFO_BF_STATE BIT(6)
65#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */
66
67#define RA_MASK_CCK 0xf
68#define RA_MASK_OFDM 0xff0
69#define RA_MASK_HT1SS 0xff000
70#define RA_MASK_HT2SS 0xff00000
71/*#define RA_MASK_MCS3SS */
72#define RA_MASK_HT4SS 0xff0
73#define RA_MASK_VHT1SS 0x3ff000
74#define RA_MASK_VHT2SS 0xffc00000
75
76#define RA_FIRST_MACID 0
77
78#define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init
79
80#define DM_RATR_STA_INIT 0
81#define DM_RATR_STA_HIGH 1
82#define DM_RATR_STA_MIDDLE 2
83#define DM_RATR_STA_LOW 3
84#define DM_RATR_STA_ULTRA_LOW 4
85
86enum phydm_ra_arfr_num {
87 ARFR_0_RATE_ID = 0x9,
88 ARFR_1_RATE_ID = 0xa,
89 ARFR_2_RATE_ID = 0xb,
90 ARFR_3_RATE_ID = 0xc,
91 ARFR_4_RATE_ID = 0xd,
92 ARFR_5_RATE_ID = 0xe
93};
94
95enum phydm_ra_dbg_para {
96 RADBG_PCR_TH_OFFSET = 0,
97 RADBG_RTY_PENALTY = 1,
98 RADBG_N_HIGH = 2,
99 RADBG_N_LOW = 3,
100 RADBG_TRATE_UP_TABLE = 4,
101 RADBG_TRATE_DOWN_TABLE = 5,
102 RADBG_TRYING_NECESSARY = 6,
103 RADBG_TDROPING_NECESSARY = 7,
104 RADBG_RATE_UP_RTY_RATIO = 8,
105 RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
106
107 RADBG_DEBUG_MONITOR1 = 0xc,
108 RADBG_DEBUG_MONITOR2 = 0xd,
109 RADBG_DEBUG_MONITOR3 = 0xe,
110 RADBG_DEBUG_MONITOR4 = 0xf,
111 RADBG_DEBUG_MONITOR5 = 0x10,
112 NUM_RA_PARA
113};
114
115enum phydm_wireless_mode {
116 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
117 PHYDM_WIRELESS_MODE_A = 0x01,
118 PHYDM_WIRELESS_MODE_B = 0x02,
119 PHYDM_WIRELESS_MODE_G = 0x04,
120 PHYDM_WIRELESS_MODE_AUTO = 0x08,
121 PHYDM_WIRELESS_MODE_N_24G = 0x10,
122 PHYDM_WIRELESS_MODE_N_5G = 0x20,
123 PHYDM_WIRELESS_MODE_AC_5G = 0x40,
124 PHYDM_WIRELESS_MODE_AC_24G = 0x80,
125 PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
126 PHYDM_WIRELESS_MODE_MAX = 0x800,
127 PHYDM_WIRELESS_MODE_ALL = 0xFFFF
128};
129
130enum phydm_rateid_idx {
131 PHYDM_BGN_40M_2SS = 0,
132 PHYDM_BGN_40M_1SS = 1,
133 PHYDM_BGN_20M_2SS = 2,
134 PHYDM_BGN_20M_1SS = 3,
135 PHYDM_GN_N2SS = 4,
136 PHYDM_GN_N1SS = 5,
137 PHYDM_BG = 6,
138 PHYDM_G = 7,
139 PHYDM_B_20M = 8,
140 PHYDM_ARFR0_AC_2SS = 9,
141 PHYDM_ARFR1_AC_1SS = 10,
142 PHYDM_ARFR2_AC_2G_1SS = 11,
143 PHYDM_ARFR3_AC_2G_2SS = 12,
144 PHYDM_ARFR4_AC_3SS = 13,
145 PHYDM_ARFR5_N_3SS = 14
146};
147
148enum phydm_rf_type_def {
149 PHYDM_RF_1T1R = 0,
150 PHYDM_RF_1T2R,
151 PHYDM_RF_2T2R,
152 PHYDM_RF_2T2R_GREEN,
153 PHYDM_RF_2T3R,
154 PHYDM_RF_2T4R,
155 PHYDM_RF_3T3R,
156 PHYDM_RF_3T4R,
157 PHYDM_RF_4T4R,
158 PHYDM_RF_MAX_TYPE
159};
160
161enum phydm_bw {
162 PHYDM_BW_20 = 0,
163 PHYDM_BW_40,
164 PHYDM_BW_80,
165 PHYDM_BW_80_80,
166 PHYDM_BW_160,
167 PHYDM_BW_10,
168 PHYDM_BW_5
169};
170
171struct ra_table {
172 u8 firstconnect;
173
174 u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
175 u8 highest_client_tx_order;
176 u16 highest_client_tx_rate_order;
177 u8 power_tracking_flag;
178 u8 RA_threshold_offset;
179 u8 RA_offset_direction;
180 u8 force_update_ra_mask_count;
181};
182
183struct odm_rate_adaptive {
184 /* dm_type_by_fw/dm_type_by_driver */
185 u8 type;
186 /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */
187 u8 high_rssi_thresh;
188 /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */
189 u8 low_rssi_thresh;
190 /* Cur RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW*/
191 u8 ratr_state;
192
193 /* if RSSI > ldpc_thres => switch from LPDC to BCC */
194 u8 ldpc_thres;
195 bool is_lower_rts_rate;
196
197 bool is_use_ldpc;
198};
199
200void phydm_h2C_debug(void *dm_void, u32 *const dm_value, u32 *_used,
201 char *output, u32 *_out_len);
202
203void phydm_RA_debug_PCR(void *dm_void, u32 *const dm_value, u32 *_used,
204 char *output, u32 *_out_len);
205
206void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
207
208void odm_ra_para_adjust(void *dm_void);
209
210void phydm_ra_dynamic_retry_count(void *dm_void);
211
212void phydm_ra_dynamic_retry_limit(void *dm_void);
213
214void phydm_ra_dynamic_rate_id_on_assoc(void *dm_void, u8 wireless_mode,
215 u8 init_rate_id);
216
217void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
218
219void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
220
221u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
222
223void phydm_ra_info_watchdog(void *dm_void);
224
225void phydm_ra_info_init(void *dm_void);
226
227void odm_rssi_monitor_init(void *dm_void);
228
229void phydm_modify_RA_PCR_threshold(void *dm_void, u8 RA_offset_direction,
230 u8 RA_threshold_offset);
231
232void odm_rssi_monitor_check(void *dm_void);
233
234void phydm_init_ra_info(void *dm_void);
235
236u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);
237
238u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);
239
240void phydm_update_hal_ra_mask(void *dm_void, u32 wireless_mode, u8 rf_type,
241 u8 BW, u8 mimo_ps_enable, u8 disable_cck_rate,
242 u32 *ratr_bitmap_msb_in, u32 *ratr_bitmap_in,
243 u8 tx_rate_level);
244
245void odm_rate_adaptive_mask_init(void *dm_void);
246
247void odm_refresh_rate_adaptive_mask(void *dm_void);
248
249void odm_refresh_rate_adaptive_mask_mp(void *dm_void);
250
251void odm_refresh_rate_adaptive_mask_ce(void *dm_void);
252
253void odm_refresh_rate_adaptive_mask_apadsl(void *dm_void);
254
255u8 phydm_RA_level_decision(void *dm_void, u32 rssi, u8 ratr_state);
256
257bool odm_ra_state_check(void *dm_void, s32 RSSI, bool is_force_update,
258 u8 *ra_tr_state);
259
260void odm_refresh_basic_rate_mask(void *dm_void);
261void odm_ra_post_action_on_assoc(void *dm);
262
263u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, bool is_erp_protect);
264
265void odm_update_noisy_state(void *dm_void, bool is_noisy_state_from_c2h);
266
267void phydm_update_pwr_track(void *dm_void, u8 rate);
268
269#endif /*#ifndef __ODMRAINFO_H__*/
diff --git a/drivers/staging/rtlwifi/phydm/phydm_reg.h b/drivers/staging/rtlwifi/phydm/phydm_reg.h
new file mode 100644
index 000000000000..d9d878e4c925
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_reg.h
@@ -0,0 +1,151 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25/* ************************************************************
26 * File Name: odm_reg.h
27 *
28 * Description:
29 *
30 * This file is for general register definition.
31 *
32 *
33 * *************************************************************/
34#ifndef __HAL_ODM_REG_H__
35#define __HAL_ODM_REG_H__
36
37/*
38 * Register Definition
39 */
40
41/* MAC REG */
42#define ODM_BB_RESET 0x002
43#define ODM_DUMMY 0x4fe
44#define RF_T_METER_OLD 0x24
45#define RF_T_METER_NEW 0x42
46
47#define ODM_EDCA_VO_PARAM 0x500
48#define ODM_EDCA_VI_PARAM 0x504
49#define ODM_EDCA_BE_PARAM 0x508
50#define ODM_EDCA_BK_PARAM 0x50C
51#define ODM_TXPAUSE 0x522
52
53/* LTE_COEX */
54#define REG_LTECOEX_CTRL 0x07C0
55#define REG_LTECOEX_WRITE_DATA 0x07C4
56#define REG_LTECOEX_READ_DATA 0x07C8
57#define REG_LTECOEX_PATH_CONTROL 0x70
58
59/* BB REG */
60#define ODM_FPGA_PHY0_PAGE8 0x800
61#define ODM_PSD_SETTING 0x808
62#define ODM_AFE_SETTING 0x818
63#define ODM_TXAGC_B_6_18 0x830
64#define ODM_TXAGC_B_24_54 0x834
65#define ODM_TXAGC_B_MCS32_5 0x838
66#define ODM_TXAGC_B_MCS0_MCS3 0x83c
67#define ODM_TXAGC_B_MCS4_MCS7 0x848
68#define ODM_TXAGC_B_MCS8_MCS11 0x84c
69#define ODM_ANALOG_REGISTER 0x85c
70#define ODM_RF_INTERFACE_OUTPUT 0x860
71#define ODM_TXAGC_B_MCS12_MCS15 0x868
72#define ODM_TXAGC_B_11_A_2_11 0x86c
73#define ODM_AD_DA_LSB_MASK 0x874
74#define ODM_ENABLE_3_WIRE 0x88c
75#define ODM_PSD_REPORT 0x8b4
76#define ODM_R_ANT_SELECT 0x90c
77#define ODM_CCK_ANT_SELECT 0xa07
78#define ODM_CCK_PD_THRESH 0xa0a
79#define ODM_CCK_RF_REG1 0xa11
80#define ODM_CCK_MATCH_FILTER 0xa20
81#define ODM_CCK_RAKE_MAC 0xa2e
82#define ODM_CCK_CNT_RESET 0xa2d
83#define ODM_CCK_TX_DIVERSITY 0xa2f
84#define ODM_CCK_FA_CNT_MSB 0xa5b
85#define ODM_CCK_FA_CNT_LSB 0xa5c
86#define ODM_CCK_NEW_FUNCTION 0xa75
87#define ODM_OFDM_PHY0_PAGE_C 0xc00
88#define ODM_OFDM_RX_ANT 0xc04
89#define ODM_R_A_RXIQI 0xc14
90#define ODM_R_A_AGC_CORE1 0xc50
91#define ODM_R_A_AGC_CORE2 0xc54
92#define ODM_R_B_AGC_CORE1 0xc58
93#define ODM_R_AGC_PAR 0xc70
94#define ODM_R_HTSTF_AGC_PAR 0xc7c
95#define ODM_TX_PWR_TRAINING_A 0xc90
96#define ODM_TX_PWR_TRAINING_B 0xc98
97#define ODM_OFDM_FA_CNT1 0xcf0
98#define ODM_OFDM_PHY0_PAGE_D 0xd00
99#define ODM_OFDM_FA_CNT2 0xda0
100#define ODM_OFDM_FA_CNT3 0xda4
101#define ODM_OFDM_FA_CNT4 0xda8
102#define ODM_TXAGC_A_6_18 0xe00
103#define ODM_TXAGC_A_24_54 0xe04
104#define ODM_TXAGC_A_1_MCS32 0xe08
105#define ODM_TXAGC_A_MCS0_MCS3 0xe10
106#define ODM_TXAGC_A_MCS4_MCS7 0xe14
107#define ODM_TXAGC_A_MCS8_MCS11 0xe18
108#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
109
110/* RF REG */
111#define ODM_GAIN_SETTING 0x00
112#define ODM_CHANNEL 0x18
113#define ODM_RF_T_METER 0x24
114#define ODM_RF_T_METER_92D 0x42
115#define ODM_RF_T_METER_88E 0x42
116#define ODM_RF_T_METER_92E 0x42
117#define ODM_RF_T_METER_8812 0x42
118#define REG_RF_TX_GAIN_OFFSET 0x55
119
120/* ant Detect Reg */
121#define ODM_DPDT 0x300
122
123/* PSD Init */
124#define ODM_PSDREG 0x808
125
126/* 92D path Div */
127#define PATHDIV_REG 0xB30
128#define PATHDIV_TRI 0xBA0
129
130/*
131 * Bitmap Definition
132 */
133
134#define BIT_FA_RESET BIT(0)
135
136#define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0xC80
137#define REG_OFDM_0_ECCA_THRESHOLD 0xC4C
138#define REG_FPGA0_XB_LSSI_READ_BACK 0x8A4
139#define REG_FPGA0_TX_GAIN_STAGE 0x80C
140#define REG_OFDM_0_XA_AGC_CORE1 0xC50
141#define REG_OFDM_0_XB_AGC_CORE1 0xC58
142#define REG_A_TX_SCALE_JAGUAR 0xC1C
143#define REG_B_TX_SCALE_JAGUAR 0xE1C
144
145#define REG_AFE_XTAL_CTRL 0x0024
146#define REG_AFE_PLL_CTRL 0x0028
147#define REG_MAC_PHY_CTRL 0x002C
148
149#define RF_CHNLBW 0x18
150
151#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_regdefine11ac.h b/drivers/staging/rtlwifi/phydm/phydm_regdefine11ac.h
new file mode 100644
index 000000000000..28d48415ac99
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_regdefine11ac.h
@@ -0,0 +1,94 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __ODM_REGDEFINE11AC_H__
27#define __ODM_REGDEFINE11AC_H__
28
29/* 2 RF REG LIST */
30
31/* 2 BB REG LIST */
32/* PAGE 8 */
33#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
34#define ODM_REG_BB_RX_PATH_11AC 0x808
35#define ODM_REG_BB_TX_PATH_11AC 0x80c
36#define ODM_REG_BB_ATC_11AC 0x860
37#define ODM_REG_EDCCA_POWER_CAL 0x8dc
38#define ODM_REG_DBG_RPT_11AC 0x8fc
39/* PAGE 9 */
40#define ODM_REG_EDCCA_DOWN_OPT 0x900
41#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
42#define odm_adc_trigger_jaguar2 0x95C /*ADC sample mode*/
43#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
44#define ODM_REG_CCX_PERIOD_11AC 0x990
45#define ODM_REG_NHM_TH9_TH10_11AC 0x994
46#define ODM_REG_CLM_11AC 0x994
47#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
48#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
49#define ODM_REG_NHM_TH8_11AC 0x9a0
50#define ODM_REG_NHM_9E8_11AC 0x9e8
51#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
52/* PAGE A */
53#define ODM_REG_CCK_CCA_11AC 0xA0A
54#define ODM_REG_CCK_FA_RST_11AC 0xA2C
55#define ODM_REG_CCK_FA_11AC 0xA5C
56/* PAGE B */
57#define ODM_REG_RST_RPT_11AC 0xB58
58/* PAGE C */
59#define ODM_REG_TRMUX_11AC 0xC08
60#define ODM_REG_IGI_A_11AC 0xC50
61/* PAGE E */
62#define ODM_REG_IGI_B_11AC 0xE50
63#define ODM_REG_TRMUX_11AC_B 0xE08
64/* PAGE F */
65#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04
66#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
67#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c
68#define ODM_REG_HT_CRC32_CNT_11AC 0xF10
69#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14
70#define ODM_REG_OFDM_FA_11AC 0xF48
71#define ODM_REG_RPT_11AC 0xfa0
72#define ODM_REG_CLM_RESULT_11AC 0xfa4
73#define ODM_REG_NHM_CNT_11AC 0xfa8
74#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
75
76#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
77#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
78#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
79/* PAGE 18 */
80#define ODM_REG_IGI_C_11AC 0x1850
81/* PAGE 1A */
82#define ODM_REG_IGI_D_11AC 0x1A50
83
84/* 2 MAC REG LIST */
85#define ODM_REG_RESP_TX_11AC 0x6D8
86
87/* DIG Related */
88#define ODM_BIT_IGI_11AC 0xFFFFFFFF
89#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16)
90#define ODM_BIT_BB_RX_PATH_11AC 0xF
91#define ODM_BIT_BB_TX_PATH_11AC 0xF
92#define ODM_BIT_BB_ATC_11AC BIT(14)
93
94#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_regdefine11n.h b/drivers/staging/rtlwifi/phydm/phydm_regdefine11n.h
new file mode 100644
index 000000000000..0b6581c50ab3
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_regdefine11n.h
@@ -0,0 +1,213 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __ODM_REGDEFINE11N_H__
27#define __ODM_REGDEFINE11N_H__
28
29/* 2 RF REG LIST */
30#define ODM_REG_RF_MODE_11N 0x00
31#define ODM_REG_RF_0B_11N 0x0B
32#define ODM_REG_CHNBW_11N 0x18
33#define ODM_REG_T_METER_11N 0x24
34#define ODM_REG_RF_25_11N 0x25
35#define ODM_REG_RF_26_11N 0x26
36#define ODM_REG_RF_27_11N 0x27
37#define ODM_REG_RF_2B_11N 0x2B
38#define ODM_REG_RF_2C_11N 0x2C
39#define ODM_REG_RXRF_A3_11N 0x3C
40#define ODM_REG_T_METER_92D_11N 0x42
41#define ODM_REG_T_METER_88E_11N 0x42
42
43/* 2 BB REG LIST */
44/* PAGE 8 */
45#define ODM_REG_BB_CTRL_11N 0x800
46#define ODM_REG_RF_PIN_11N 0x804
47#define ODM_REG_PSD_CTRL_11N 0x808
48#define ODM_REG_TX_ANT_CTRL_11N 0x80C
49#define ODM_REG_BB_PWR_SAV5_11N 0x818
50#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
51#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
52#define ODM_REG_RX_DEFAULT_A_11N 0x858
53#define ODM_REG_RX_DEFAULT_B_11N 0x85A
54#define ODM_REG_BB_PWR_SAV3_11N 0x85C
55#define ODM_REG_ANTSEL_CTRL_11N 0x860
56#define ODM_REG_RX_ANT_CTRL_11N 0x864
57#define ODM_REG_PIN_CTRL_11N 0x870
58#define ODM_REG_BB_PWR_SAV1_11N 0x874
59#define ODM_REG_ANTSEL_PATH_11N 0x878
60#define ODM_REG_BB_3WIRE_11N 0x88C
61#define ODM_REG_SC_CNT_11N 0x8C4
62#define ODM_REG_PSD_DATA_11N 0x8B4
63#define ODM_REG_CCX_PERIOD_11N 0x894
64#define ODM_REG_NHM_TH9_TH10_11N 0x890
65#define ODM_REG_CLM_11N 0x890
66#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
67#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
68#define ODM_REG_NHM_TH8_11N 0xe28
69#define ODM_REG_CLM_READY_11N 0x8b4
70#define ODM_REG_CLM_RESULT_11N 0x8d0
71#define ODM_REG_NHM_CNT_11N 0x8d8
72
73/* For struct acs_info, Jeffery, 2014-12-26 */
74#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
75#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
76#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
77
78/* PAGE 9 */
79#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
80#define ODM_REG_DBG_RPT_11N 0x908
81#define ODM_REG_BB_TX_PATH_11N 0x90c
82#define ODM_REG_ANT_MAPPING1_11N 0x914
83#define ODM_REG_ANT_MAPPING2_11N 0x918
84#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
85#define ODM_REG_RX_DFIR_MOD_97F 0x948
86
87/* PAGE A */
88#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
89#define ODM_REG_CCK_ANT_SEL_11N 0xA04
90#define ODM_REG_CCK_CCA_11N 0xA0A
91#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
92#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
93#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
94#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
95#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
96#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
97#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
98#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
99#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
100#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
101#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
102#define ODM_REG_CCK_FA_RST_11N 0xA2C
103#define ODM_REG_CCK_FA_MSB_11N 0xA58
104#define ODM_REG_CCK_FA_LSB_11N 0xA5C
105#define ODM_REG_CCK_CCA_CNT_11N 0xA60
106#define ODM_REG_BB_PWR_SAV4_11N 0xA74
107/* PAGE B */
108#define ODM_REG_LNA_SWITCH_11N 0xB2C
109#define ODM_REG_PATH_SWITCH_11N 0xB30
110#define ODM_REG_RSSI_CTRL_11N 0xB38
111#define ODM_REG_CONFIG_ANTA_11N 0xB68
112#define ODM_REG_RSSI_BT_11N 0xB9C
113#define ODM_REG_RXCK_RFMOD 0xBB0
114#define ODM_REG_EDCCA_DCNF_97F 0xBC0
115
116/* PAGE C */
117#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
118#define ODM_REG_BB_RX_PATH_11N 0xC04
119#define ODM_REG_TRMUX_11N 0xC08
120#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
121#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
122#define ODM_REG_RXIQI_MATRIX_11N 0xC14
123#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
124#define ODM_REG_IGI_A_11N 0xC50
125#define ODM_REG_ANTDIV_PARA2_11N 0xC54
126#define ODM_REG_IGI_B_11N 0xC58
127#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
128#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
129#define ODM_REG_BB_PWR_SAV2_11N 0xC70
130#define ODM_REG_BB_AGC_SET_2_11N 0xc74
131#define ODM_REG_RX_OFF_11N 0xC7C
132#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
133#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
134#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
135#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
136#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
137#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
138#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
139#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
140/* PAGE D */
141#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
142#define ODM_REG_BB_RX_ANT_11N 0xD04
143#define ODM_REG_BB_ATC_11N 0xD2C
144#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
145#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
146#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
147#define ODM_REG_RPT_11N 0xDF4
148/* PAGE E */
149#define ODM_REG_TXAGC_A_6_18_11N 0xE00
150#define ODM_REG_TXAGC_A_24_54_11N 0xE04
151#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
152#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
153#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
154#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
155#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
156#define ODM_REG_EDCCA_DCNF_11N 0xE24
157#define ODM_REG_TAP_UPD_97F 0xE24
158#define ODM_REG_FPGA0_IQK_11N 0xE28
159#define ODM_REG_PAGE_B1_97F 0xE28
160#define ODM_REG_TXIQK_TONE_A_11N 0xE30
161#define ODM_REG_RXIQK_TONE_A_11N 0xE34
162#define ODM_REG_TXIQK_PI_A_11N 0xE38
163#define ODM_REG_RXIQK_PI_A_11N 0xE3C
164#define ODM_REG_TXIQK_11N 0xE40
165#define ODM_REG_RXIQK_11N 0xE44
166#define ODM_REG_IQK_AGC_PTS_11N 0xE48
167#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
168#define ODM_REG_BLUETOOTH_11N 0xE6C
169#define ODM_REG_RX_WAIT_CCA_11N 0xE70
170#define ODM_REG_TX_CCK_RFON_11N 0xE74
171#define ODM_REG_TX_CCK_BBON_11N 0xE78
172#define ODM_REG_OFDM_RFON_11N 0xE7C
173#define ODM_REG_OFDM_BBON_11N 0xE80
174#define ODM_REG_TX2RX_11N 0xE84
175#define ODM_REG_TX2TX_11N 0xE88
176#define ODM_REG_RX_CCK_11N 0xE8C
177#define ODM_REG_RX_OFDM_11N 0xED0
178#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
179#define ODM_REG_RX2RX_11N 0xED8
180#define ODM_REG_STANDBY_11N 0xEDC
181#define ODM_REG_SLEEP_11N 0xEE0
182#define ODM_REG_PMPD_ANAEN_11N 0xEEC
183/* PAGE F */
184#define ODM_REG_PAGE_F_RST_11N 0xF14
185#define ODM_REG_IGI_C_11N 0xF84
186#define ODM_REG_IGI_D_11N 0xF88
187#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
188#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
189#define ODM_REG_HT_CRC32_CNT_11N 0xF90
190#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
191
192/* 2 MAC REG LIST */
193#define ODM_REG_BB_RST_11N 0x02
194#define ODM_REG_ANTSEL_PIN_11N 0x4C
195#define ODM_REG_EARLY_MODE_11N 0x4D0
196#define ODM_REG_RSSI_MONITOR_11N 0x4FE
197#define ODM_REG_EDCA_VO_11N 0x500
198#define ODM_REG_EDCA_VI_11N 0x504
199#define ODM_REG_EDCA_BE_11N 0x508
200#define ODM_REG_EDCA_BK_11N 0x50C
201#define ODM_REG_TXPAUSE_11N 0x522
202#define ODM_REG_RESP_TX_11N 0x6D8
203#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
204#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
205
206/* DIG Related */
207#define ODM_BIT_IGI_11N 0x0000007F
208#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9)
209#define ODM_BIT_BB_RX_PATH_11N 0xF
210#define ODM_BIT_BB_TX_PATH_11N 0xF
211#define ODM_BIT_BB_ATC_11N BIT(11)
212
213#endif
diff --git a/drivers/staging/rtlwifi/phydm/phydm_types.h b/drivers/staging/rtlwifi/phydm/phydm_types.h
new file mode 100644
index 000000000000..a34ebe876528
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/phydm_types.h
@@ -0,0 +1,130 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __ODM_TYPES_H__
26#define __ODM_TYPES_H__
27
28/*Define Different SW team support*/
29#define ODM_AP 0x01 /*BIT0*/
30#define ODM_CE 0x04 /*BIT2*/
31#define ODM_WIN 0x08 /*BIT3*/
32#define ODM_ADSL 0x10 /*BIT4*/
33#define ODM_IOT 0x20 /*BIT5*/
34
35/*Deifne HW endian support*/
36#define ODM_ENDIAN_BIG 0
37#define ODM_ENDIAN_LITTLE 1
38
39#define GET_PDM_ODM(__padapter) \
40 ((struct phy_dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv))
41
42enum hal_status {
43 HAL_STATUS_SUCCESS,
44 HAL_STATUS_FAILURE,
45};
46
47/*
48 * Declare for ODM spin lock definition temporarily fro compile pass.
49 */
50enum rt_spinlock_type {
51 RT_TX_SPINLOCK = 1,
52 RT_RX_SPINLOCK = 2,
53 RT_RM_SPINLOCK = 3,
54 RT_CAM_SPINLOCK = 4,
55 RT_SCAN_SPINLOCK = 5,
56 RT_LOG_SPINLOCK = 7,
57 RT_BW_SPINLOCK = 8,
58 RT_CHNLOP_SPINLOCK = 9,
59 RT_RF_OPERATE_SPINLOCK = 10,
60 RT_INITIAL_SPINLOCK = 11,
61 RT_RF_STATE_SPINLOCK =
62 12, /* For RF state. Added by Bruce, 2007-10-30. */
63 /* Shall we define Ndis 6.2 SpinLock Here ? */
64 RT_PORT_SPINLOCK = 16,
65 RT_VNIC_SPINLOCK = 17,
66 RT_HVL_SPINLOCK = 18,
67 RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */
68
69 rt_bt_data_spinlock = 25,
70
71 RT_WAPI_OPTION_SPINLOCK = 26,
72 RT_WAPI_RX_SPINLOCK = 27,
73
74 /* add for 92D CCK control issue */
75 RT_CCK_PAGEA_SPINLOCK = 28,
76 RT_BUFFER_SPINLOCK = 29,
77 RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
78 RT_GEN_TEMP_BUF_SPINLOCK = 31,
79 RT_AWB_SPINLOCK = 32,
80 RT_FW_PS_SPINLOCK = 33,
81 RT_HW_TIMER_SPIN_LOCK = 34,
82 RT_MPT_WI_SPINLOCK = 35,
83 RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */
84 RT_DBG_SPIN_LOCK = 37,
85 RT_IQK_SPINLOCK = 38,
86 RT_PENDED_OID_SPINLOCK = 39,
87 RT_CHNLLIST_SPINLOCK = 40,
88 RT_INDIC_SPINLOCK = 41, /* protect indication */
89 RT_RFD_SPINLOCK = 42,
90 RT_SYNC_IO_CNT_SPINLOCK = 43,
91 RT_LAST_SPINLOCK,
92};
93
94#include <asm/byteorder.h>
95
96#if defined(__LITTLE_ENDIAN)
97#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
98#elif defined(__BIG_ENDIAN)
99#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
100#else
101#error
102#endif
103
104#define COND_ELSE 2
105#define COND_ENDIF 3
106
107#define MASKBYTE0 0xff
108#define MASKBYTE1 0xff00
109#define MASKBYTE2 0xff0000
110#define MASKBYTE3 0xff000000
111#define MASKHWORD 0xffff0000
112#define MASKLWORD 0x0000ffff
113#define MASKDWORD 0xffffffff
114#define MASK7BITS 0x7f
115#define MASK12BITS 0xfff
116#define MASKH4BITS 0xf0000000
117#define MASK20BITS 0xfffff
118#define MASKOFDM_D 0xffc00000
119#define MASKCCK 0x3f3f3f3f
120#define RFREGOFFSETMASK 0xfffff
121#define MASKH3BYTES 0xffffff00
122#define MASKL3BYTES 0x00ffffff
123#define MASKBYTE2HIGHNIBBLE 0x00f00000
124#define MASKBYTE3LOWNIBBLE 0x0f000000
125#define MASKL3BYTES 0x00ffffff
126#define RFREGOFFSETMASK 0xfffff
127
128#include "phydm_features.h"
129
130#endif /* __ODM_TYPES_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_bb.c b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_bb.c
new file mode 100644
index 000000000000..4e7946019fcb
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_bb.c
@@ -0,0 +1,1969 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/*Image2HeaderVersion: 3.2*/
27#include "../mp_precomp.h"
28#include "../phydm_precomp.h"
29
30static bool check_positive(struct phy_dm_struct *dm, const u32 condition1,
31 const u32 condition2, const u32 condition3,
32 const u32 condition4)
33{
34 u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
35 ((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
36 ((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
37 ((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
38 ((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
39
40 u32 cond1 = condition1, cond2 = condition2, cond3 = condition3,
41 cond4 = condition4;
42
43 u8 cut_version_for_para =
44 (dm->cut_version == ODM_CUT_A) ? 14 : dm->cut_version;
45 u8 pkg_type_for_para = (dm->package_type == 0) ? 14 : dm->package_type;
46
47 u32 driver1 = cut_version_for_para << 24 |
48 (dm->support_interface & 0xF0) << 16 |
49 dm->support_platform << 16 | pkg_type_for_para << 12 |
50 (dm->support_interface & 0x0F) << 8 | _board_type;
51
52 u32 driver2 = (dm->type_glna & 0xFF) << 0 | (dm->type_gpa & 0xFF) << 8 |
53 (dm->type_alna & 0xFF) << 16 |
54 (dm->type_apa & 0xFF) << 24;
55
56 u32 driver3 = 0;
57
58 u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | (dm->type_gpa & 0xFF00) |
59 (dm->type_alna & 0xFF00) << 8 |
60 (dm->type_apa & 0xFF00) << 16;
61
62 ODM_RT_TRACE(
63 dm, ODM_COMP_INIT,
64 "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
65 __func__, cond1, cond2, cond3, cond4);
66 ODM_RT_TRACE(
67 dm, ODM_COMP_INIT,
68 "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
69 __func__, driver1, driver2, driver3, driver4);
70
71 ODM_RT_TRACE(dm, ODM_COMP_INIT,
72 " (Platform, Interface) = (0x%X, 0x%X)\n",
73 dm->support_platform, dm->support_interface);
74 ODM_RT_TRACE(dm, ODM_COMP_INIT,
75 " (Board, Package) = (0x%X, 0x%X)\n",
76 dm->board_type, dm->package_type);
77
78 /*============== value Defined Check ===============*/
79 /*QFN type [15:12] and cut version [27:24] need to do value check*/
80
81 if (((cond1 & 0x0000F000) != 0) &&
82 ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
83 return false;
84 if (((cond1 & 0x0F000000) != 0) &&
85 ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
86 return false;
87
88 /*=============== Bit Defined Check ================*/
89 /* We don't care [31:28] */
90
91 cond1 &= 0x00FF0FFF;
92 driver1 &= 0x00FF0FFF;
93
94 if ((cond1 & driver1) == cond1) {
95 u32 bit_mask = 0;
96
97 if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
98 return true;
99
100 if ((cond1 & BIT(0)) != 0) /*GLNA*/
101 bit_mask |= 0x000000FF;
102 if ((cond1 & BIT(1)) != 0) /*GPA*/
103 bit_mask |= 0x0000FF00;
104 if ((cond1 & BIT(2)) != 0) /*ALNA*/
105 bit_mask |= 0x00FF0000;
106 if ((cond1 & BIT(3)) != 0) /*APA*/
107 bit_mask |= 0xFF000000;
108
109 if (((cond2 & bit_mask) == (driver2 & bit_mask)) &&
110 ((cond4 & bit_mask) ==
111 (driver4 &
112 bit_mask))) /* board_type of each RF path is matched*/
113 return true;
114 else
115 return false;
116 } else {
117 return false;
118 }
119}
120
121/******************************************************************************
122 * agc_tab.TXT
123 ******************************************************************************/
124
125static u32 array_mp_8822b_agc_tab[] = {
126 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x81C, 0xFF000003,
127 0x81C, 0xF5000003, 0x81C, 0xF4020003, 0x81C, 0xF3040003,
128 0x81C, 0xF2060003, 0x81C, 0xF1080003, 0x81C, 0xF00A0003,
129 0x81C, 0xEF0C0003, 0x81C, 0xEE0E0003, 0x81C, 0xED100003,
130 0x81C, 0xEC120003, 0x81C, 0xEB140003, 0x81C, 0xEA160003,
131 0x81C, 0xE9180003, 0x81C, 0xE81A0003, 0x81C, 0xE71C0003,
132 0x81C, 0xE61E0003, 0x81C, 0xE5200003, 0x81C, 0xE4220003,
133 0x81C, 0xE3240003, 0x81C, 0xE2260003, 0x81C, 0xE1280003,
134 0x81C, 0xE02A0003, 0x81C, 0xC32C0003, 0x81C, 0xC22E0003,
135 0x81C, 0xC1300003, 0x81C, 0xC0320003, 0x81C, 0xA4340003,
136 0x81C, 0xA3360003, 0x81C, 0xA2380003, 0x81C, 0xA13A0003,
137 0x81C, 0xA03C0003, 0x81C, 0x823E0003, 0x81C, 0x81400003,
138 0x81C, 0x80420003, 0x81C, 0x64440003, 0x81C, 0x63460003,
139 0x81C, 0x62480003, 0x81C, 0x614A0003, 0x81C, 0x604C0003,
140 0x81C, 0x454E0003, 0x81C, 0x44500003, 0x81C, 0x43520003,
141 0x81C, 0x42540003, 0x81C, 0x41560003, 0x81C, 0x40580003,
142 0x81C, 0x055A0003, 0x81C, 0x045C0003, 0x81C, 0x035E0003,
143 0x81C, 0x02600003, 0x81C, 0x01620003, 0x81C, 0x00640003,
144 0x81C, 0x00660003, 0x81C, 0x00680003, 0x81C, 0x006A0003,
145 0x81C, 0x006C0003, 0x81C, 0x006E0003, 0x81C, 0x00700003,
146 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
147 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
148 0x81C, 0x007E0003, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
149 0x81C, 0xFF000003, 0x81C, 0xF5000003, 0x81C, 0xF4020003,
150 0x81C, 0xF3040003, 0x81C, 0xF2060003, 0x81C, 0xF1080003,
151 0x81C, 0xF00A0003, 0x81C, 0xEF0C0003, 0x81C, 0xEE0E0003,
152 0x81C, 0xED100003, 0x81C, 0xEC120003, 0x81C, 0xEB140003,
153 0x81C, 0xEA160003, 0x81C, 0xE9180003, 0x81C, 0xE81A0003,
154 0x81C, 0xE71C0003, 0x81C, 0xE61E0003, 0x81C, 0xE5200003,
155 0x81C, 0xE4220003, 0x81C, 0xE3240003, 0x81C, 0xE2260003,
156 0x81C, 0xE1280003, 0x81C, 0xE02A0003, 0x81C, 0xC32C0003,
157 0x81C, 0xC22E0003, 0x81C, 0xC1300003, 0x81C, 0xC0320003,
158 0x81C, 0xA4340003, 0x81C, 0xA3360003, 0x81C, 0xA2380003,
159 0x81C, 0xA13A0003, 0x81C, 0xA03C0003, 0x81C, 0x823E0003,
160 0x81C, 0x81400003, 0x81C, 0x80420003, 0x81C, 0x64440003,
161 0x81C, 0x63460003, 0x81C, 0x62480003, 0x81C, 0x614A0003,
162 0x81C, 0x604C0003, 0x81C, 0x454E0003, 0x81C, 0x44500003,
163 0x81C, 0x43520003, 0x81C, 0x42540003, 0x81C, 0x41560003,
164 0x81C, 0x40580003, 0x81C, 0x055A0003, 0x81C, 0x045C0003,
165 0x81C, 0x035E0003, 0x81C, 0x02600003, 0x81C, 0x01620003,
166 0x81C, 0x00640003, 0x81C, 0x00660003, 0x81C, 0x00680003,
167 0x81C, 0x006A0003, 0x81C, 0x006C0003, 0x81C, 0x006E0003,
168 0x81C, 0x00700003, 0x81C, 0x00720003, 0x81C, 0x00740003,
169 0x81C, 0x00760003, 0x81C, 0x00780003, 0x81C, 0x007A0003,
170 0x81C, 0x007C0003, 0x81C, 0x007E0003, 0x9000100f, 0x00000000,
171 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xF5000003,
172 0x81C, 0xF4020003, 0x81C, 0xF3040003, 0x81C, 0xF2060003,
173 0x81C, 0xF1080003, 0x81C, 0xF00A0003, 0x81C, 0xEF0C0003,
174 0x81C, 0xEE0E0003, 0x81C, 0xED100003, 0x81C, 0xEC120003,
175 0x81C, 0xEB140003, 0x81C, 0xEA160003, 0x81C, 0xE9180003,
176 0x81C, 0xE81A0003, 0x81C, 0xE71C0003, 0x81C, 0xE61E0003,
177 0x81C, 0xE5200003, 0x81C, 0xE4220003, 0x81C, 0xE3240003,
178 0x81C, 0xE2260003, 0x81C, 0xE1280003, 0x81C, 0xE02A0003,
179 0x81C, 0xC32C0003, 0x81C, 0xC22E0003, 0x81C, 0xC1300003,
180 0x81C, 0xC0320003, 0x81C, 0xA4340003, 0x81C, 0xA3360003,
181 0x81C, 0xA2380003, 0x81C, 0xA13A0003, 0x81C, 0xA03C0003,
182 0x81C, 0x823E0003, 0x81C, 0x81400003, 0x81C, 0x80420003,
183 0x81C, 0x64440003, 0x81C, 0x63460003, 0x81C, 0x62480003,
184 0x81C, 0x614A0003, 0x81C, 0x604C0003, 0x81C, 0x454E0003,
185 0x81C, 0x44500003, 0x81C, 0x43520003, 0x81C, 0x42540003,
186 0x81C, 0x41560003, 0x81C, 0x40580003, 0x81C, 0x055A0003,
187 0x81C, 0x045C0003, 0x81C, 0x035E0003, 0x81C, 0x02600003,
188 0x81C, 0x01620003, 0x81C, 0x00640003, 0x81C, 0x00660003,
189 0x81C, 0x00680003, 0x81C, 0x006A0003, 0x81C, 0x006C0003,
190 0x81C, 0x006E0003, 0x81C, 0x00700003, 0x81C, 0x00720003,
191 0x81C, 0x00740003, 0x81C, 0x00760003, 0x81C, 0x00780003,
192 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003,
193 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003,
194 0x81C, 0xF5000003, 0x81C, 0xF4020003, 0x81C, 0xF3040003,
195 0x81C, 0xF2060003, 0x81C, 0xF1080003, 0x81C, 0xF00A0003,
196 0x81C, 0xEF0C0003, 0x81C, 0xEE0E0003, 0x81C, 0xED100003,
197 0x81C, 0xEC120003, 0x81C, 0xEB140003, 0x81C, 0xEA160003,
198 0x81C, 0xE9180003, 0x81C, 0xE81A0003, 0x81C, 0xE71C0003,
199 0x81C, 0xE61E0003, 0x81C, 0xE5200003, 0x81C, 0xE4220003,
200 0x81C, 0xE3240003, 0x81C, 0xE2260003, 0x81C, 0xE1280003,
201 0x81C, 0xE02A0003, 0x81C, 0xC32C0003, 0x81C, 0xC22E0003,
202 0x81C, 0xC1300003, 0x81C, 0xC0320003, 0x81C, 0xA4340003,
203 0x81C, 0xA3360003, 0x81C, 0xA2380003, 0x81C, 0xA13A0003,
204 0x81C, 0xA03C0003, 0x81C, 0x823E0003, 0x81C, 0x81400003,
205 0x81C, 0x80420003, 0x81C, 0x64440003, 0x81C, 0x63460003,
206 0x81C, 0x62480003, 0x81C, 0x614A0003, 0x81C, 0x604C0003,
207 0x81C, 0x454E0003, 0x81C, 0x44500003, 0x81C, 0x43520003,
208 0x81C, 0x42540003, 0x81C, 0x41560003, 0x81C, 0x40580003,
209 0x81C, 0x055A0003, 0x81C, 0x045C0003, 0x81C, 0x035E0003,
210 0x81C, 0x02600003, 0x81C, 0x01620003, 0x81C, 0x00640003,
211 0x81C, 0x00660003, 0x81C, 0x00680003, 0x81C, 0x006A0003,
212 0x81C, 0x006C0003, 0x81C, 0x006E0003, 0x81C, 0x00700003,
213 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
214 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
215 0x81C, 0x007E0003, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
216 0x81C, 0xFF000003, 0x81C, 0xFD000003, 0x81C, 0xFC020003,
217 0x81C, 0xFB040003, 0x81C, 0xFA060003, 0x81C, 0xF9080003,
218 0x81C, 0xF80A0003, 0x81C, 0xF70C0003, 0x81C, 0xF60E0003,
219 0x81C, 0xF5100003, 0x81C, 0xF4120003, 0x81C, 0xF3140003,
220 0x81C, 0xF2160003, 0x81C, 0xF1180003, 0x81C, 0xF01A0003,
221 0x81C, 0xEF1C0003, 0x81C, 0xEE1E0003, 0x81C, 0xED200003,
222 0x81C, 0xEC220003, 0x81C, 0xEB240003, 0x81C, 0xEA260003,
223 0x81C, 0xE9280003, 0x81C, 0xE82A0003, 0x81C, 0xE72C0003,
224 0x81C, 0xE62E0003, 0x81C, 0xE5300003, 0x81C, 0xC8320003,
225 0x81C, 0xC7340003, 0x81C, 0xC6360003, 0x81C, 0xC5380003,
226 0x81C, 0xC43A0003, 0x81C, 0xC33C0003, 0x81C, 0xC23E0003,
227 0x81C, 0xC1400003, 0x81C, 0xC0420003, 0x81C, 0xA5440003,
228 0x81C, 0xA4460003, 0x81C, 0xA3480003, 0x81C, 0xA24A0003,
229 0x81C, 0xA14C0003, 0x81C, 0x834E0003, 0x81C, 0x82500003,
230 0x81C, 0x81520003, 0x81C, 0x80540003, 0x81C, 0x65560003,
231 0x81C, 0x64580003, 0x81C, 0x635A0003, 0x81C, 0x625C0003,
232 0x81C, 0x435E0003, 0x81C, 0x42600003, 0x81C, 0x41620003,
233 0x81C, 0x40640003, 0x81C, 0x06660003, 0x81C, 0x05680003,
234 0x81C, 0x046A0003, 0x81C, 0x036C0003, 0x81C, 0x026E0003,
235 0x81C, 0x01700003, 0x81C, 0x00720003, 0x81C, 0x00740003,
236 0x81C, 0x00760003, 0x81C, 0x00780003, 0x81C, 0x007A0003,
237 0x81C, 0x007C0003, 0x81C, 0x007E0003, 0x90012100, 0x00000000,
238 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xFE000003,
239 0x81C, 0xFD020003, 0x81C, 0xFC040003, 0x81C, 0xFB060003,
240 0x81C, 0xFA080003, 0x81C, 0xF90A0003, 0x81C, 0xF80C0003,
241 0x81C, 0xF70E0003, 0x81C, 0xF6100003, 0x81C, 0xF5120003,
242 0x81C, 0xF4140003, 0x81C, 0xF3160003, 0x81C, 0xF2180003,
243 0x81C, 0xF11A0003, 0x81C, 0xF01C0003, 0x81C, 0xEF1E0003,
244 0x81C, 0xEE200003, 0x81C, 0xED220003, 0x81C, 0xEC240003,
245 0x81C, 0xEB260003, 0x81C, 0xEA280003, 0x81C, 0xE92A0003,
246 0x81C, 0xE82C0003, 0x81C, 0xE72E0003, 0x81C, 0xE6300003,
247 0x81C, 0xE5320003, 0x81C, 0xC8340003, 0x81C, 0xC7360003,
248 0x81C, 0xC6380003, 0x81C, 0xC53A0003, 0x81C, 0xC43C0003,
249 0x81C, 0xC33E0003, 0x81C, 0xC2400003, 0x81C, 0xC1420003,
250 0x81C, 0xC0440003, 0x81C, 0xA3460003, 0x81C, 0xA2480003,
251 0x81C, 0xA14A0003, 0x81C, 0xA04C0003, 0x81C, 0x824E0003,
252 0x81C, 0x81500003, 0x81C, 0x80520003, 0x81C, 0x64540003,
253 0x81C, 0x63560003, 0x81C, 0x62580003, 0x81C, 0x445A0003,
254 0x81C, 0x435C0003, 0x81C, 0x425E0003, 0x81C, 0x41600003,
255 0x81C, 0x40620003, 0x81C, 0x05640003, 0x81C, 0x04660003,
256 0x81C, 0x03680003, 0x81C, 0x026A0003, 0x81C, 0x016C0003,
257 0x81C, 0x006E0003, 0x81C, 0x00700003, 0x81C, 0x00720003,
258 0x81C, 0x00740003, 0x81C, 0x00760003, 0x81C, 0x00780003,
259 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003,
260 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003,
261 0x81C, 0xF5000003, 0x81C, 0xF4020003, 0x81C, 0xF3040003,
262 0x81C, 0xF2060003, 0x81C, 0xF1080003, 0x81C, 0xF00A0003,
263 0x81C, 0xEF0C0003, 0x81C, 0xEE0E0003, 0x81C, 0xED100003,
264 0x81C, 0xEC120003, 0x81C, 0xEB140003, 0x81C, 0xEA160003,
265 0x81C, 0xE9180003, 0x81C, 0xE81A0003, 0x81C, 0xE71C0003,
266 0x81C, 0xE61E0003, 0x81C, 0xE5200003, 0x81C, 0xE4220003,
267 0x81C, 0xE3240003, 0x81C, 0xE2260003, 0x81C, 0xE1280003,
268 0x81C, 0xE02A0003, 0x81C, 0xC32C0003, 0x81C, 0xC22E0003,
269 0x81C, 0xC1300003, 0x81C, 0xC0320003, 0x81C, 0xA4340003,
270 0x81C, 0xA3360003, 0x81C, 0xA2380003, 0x81C, 0xA13A0003,
271 0x81C, 0xA03C0003, 0x81C, 0x823E0003, 0x81C, 0x81400003,
272 0x81C, 0x80420003, 0x81C, 0x64440003, 0x81C, 0x63460003,
273 0x81C, 0x62480003, 0x81C, 0x614A0003, 0x81C, 0x604C0003,
274 0x81C, 0x454E0003, 0x81C, 0x44500003, 0x81C, 0x43520003,
275 0x81C, 0x42540003, 0x81C, 0x41560003, 0x81C, 0x40580003,
276 0x81C, 0x055A0003, 0x81C, 0x045C0003, 0x81C, 0x035E0003,
277 0x81C, 0x02600003, 0x81C, 0x01620003, 0x81C, 0x00640003,
278 0x81C, 0x00660003, 0x81C, 0x00680003, 0x81C, 0x006A0003,
279 0x81C, 0x006C0003, 0x81C, 0x006E0003, 0x81C, 0x00700003,
280 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
281 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
282 0x81C, 0x007E0003, 0x90011000, 0x00000000, 0x40000000, 0x00000000,
283 0x81C, 0xFF000003, 0x81C, 0xFE000003, 0x81C, 0xFD020003,
284 0x81C, 0xFC040003, 0x81C, 0xFB060003, 0x81C, 0xFA080003,
285 0x81C, 0xF90A0003, 0x81C, 0xF80C0003, 0x81C, 0xF70E0003,
286 0x81C, 0xF6100003, 0x81C, 0xF5120003, 0x81C, 0xF4140003,
287 0x81C, 0xF3160003, 0x81C, 0xF2180003, 0x81C, 0xF11A0003,
288 0x81C, 0xF01C0003, 0x81C, 0xEF1E0003, 0x81C, 0xEE200003,
289 0x81C, 0xED220003, 0x81C, 0xEC240003, 0x81C, 0xEB260003,
290 0x81C, 0xEA280003, 0x81C, 0xE92A0003, 0x81C, 0xE82C0003,
291 0x81C, 0xE72E0003, 0x81C, 0xE6300003, 0x81C, 0xE5320003,
292 0x81C, 0xC8340003, 0x81C, 0xC7360003, 0x81C, 0xC6380003,
293 0x81C, 0xC53A0003, 0x81C, 0xC43C0003, 0x81C, 0xC33E0003,
294 0x81C, 0xC2400003, 0x81C, 0xC1420003, 0x81C, 0xC0440003,
295 0x81C, 0xA3460003, 0x81C, 0xA2480003, 0x81C, 0xA14A0003,
296 0x81C, 0xA04C0003, 0x81C, 0x824E0003, 0x81C, 0x81500003,
297 0x81C, 0x80520003, 0x81C, 0x64540003, 0x81C, 0x63560003,
298 0x81C, 0x62580003, 0x81C, 0x445A0003, 0x81C, 0x435C0003,
299 0x81C, 0x425E0003, 0x81C, 0x41600003, 0x81C, 0x40620003,
300 0x81C, 0x05640003, 0x81C, 0x04660003, 0x81C, 0x03680003,
301 0x81C, 0x026A0003, 0x81C, 0x016C0003, 0x81C, 0x006E0003,
302 0x81C, 0x00700003, 0x81C, 0x00720003, 0x81C, 0x00740003,
303 0x81C, 0x00760003, 0x81C, 0x00780003, 0x81C, 0x007A0003,
304 0x81C, 0x007C0003, 0x81C, 0x007E0003, 0x90002100, 0x00000000,
305 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xFD000003,
306 0x81C, 0xFC020003, 0x81C, 0xFB040003, 0x81C, 0xFA060003,
307 0x81C, 0xF9080003, 0x81C, 0xF80A0003, 0x81C, 0xF70C0003,
308 0x81C, 0xF60E0003, 0x81C, 0xF5100003, 0x81C, 0xF4120003,
309 0x81C, 0xF3140003, 0x81C, 0xF2160003, 0x81C, 0xF1180003,
310 0x81C, 0xF01A0003, 0x81C, 0xEF1C0003, 0x81C, 0xEE1E0003,
311 0x81C, 0xED200003, 0x81C, 0xEC220003, 0x81C, 0xEB240003,
312 0x81C, 0xEA260003, 0x81C, 0xE9280003, 0x81C, 0xE82A0003,
313 0x81C, 0xE72C0003, 0x81C, 0xE62E0003, 0x81C, 0xE5300003,
314 0x81C, 0xC8320003, 0x81C, 0xC7340003, 0x81C, 0xC6360003,
315 0x81C, 0xC5380003, 0x81C, 0xC43A0003, 0x81C, 0xC33C0003,
316 0x81C, 0xC23E0003, 0x81C, 0xC1400003, 0x81C, 0xC0420003,
317 0x81C, 0xA5440003, 0x81C, 0xA4460003, 0x81C, 0xA3480003,
318 0x81C, 0xA24A0003, 0x81C, 0xA14C0003, 0x81C, 0x834E0003,
319 0x81C, 0x82500003, 0x81C, 0x81520003, 0x81C, 0x80540003,
320 0x81C, 0x65560003, 0x81C, 0x64580003, 0x81C, 0x635A0003,
321 0x81C, 0x625C0003, 0x81C, 0x435E0003, 0x81C, 0x42600003,
322 0x81C, 0x41620003, 0x81C, 0x40640003, 0x81C, 0x06660003,
323 0x81C, 0x05680003, 0x81C, 0x046A0003, 0x81C, 0x036C0003,
324 0x81C, 0x026E0003, 0x81C, 0x01700003, 0x81C, 0x00720003,
325 0x81C, 0x00740003, 0x81C, 0x00760003, 0x81C, 0x00780003,
326 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003,
327 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003,
328 0x81C, 0xFD000003, 0x81C, 0xFC020003, 0x81C, 0xFB040003,
329 0x81C, 0xFA060003, 0x81C, 0xF9080003, 0x81C, 0xF80A0003,
330 0x81C, 0xF70C0003, 0x81C, 0xF60E0003, 0x81C, 0xF5100003,
331 0x81C, 0xF4120003, 0x81C, 0xF3140003, 0x81C, 0xF2160003,
332 0x81C, 0xF1180003, 0x81C, 0xF01A0003, 0x81C, 0xEF1C0003,
333 0x81C, 0xEE1E0003, 0x81C, 0xED200003, 0x81C, 0xEC220003,
334 0x81C, 0xEB240003, 0x81C, 0xEA260003, 0x81C, 0xE9280003,
335 0x81C, 0xE82A0003, 0x81C, 0xE72C0003, 0x81C, 0xE62E0003,
336 0x81C, 0xE5300003, 0x81C, 0xC8320003, 0x81C, 0xC7340003,
337 0x81C, 0xC6360003, 0x81C, 0xC5380003, 0x81C, 0xC43A0003,
338 0x81C, 0xC33C0003, 0x81C, 0xC23E0003, 0x81C, 0xC1400003,
339 0x81C, 0xC0420003, 0x81C, 0xA5440003, 0x81C, 0xA4460003,
340 0x81C, 0xA3480003, 0x81C, 0xA24A0003, 0x81C, 0xA14C0003,
341 0x81C, 0x834E0003, 0x81C, 0x82500003, 0x81C, 0x81520003,
342 0x81C, 0x80540003, 0x81C, 0x65560003, 0x81C, 0x64580003,
343 0x81C, 0x635A0003, 0x81C, 0x625C0003, 0x81C, 0x435E0003,
344 0x81C, 0x42600003, 0x81C, 0x41620003, 0x81C, 0x40640003,
345 0x81C, 0x06660003, 0x81C, 0x05680003, 0x81C, 0x046A0003,
346 0x81C, 0x036C0003, 0x81C, 0x026E0003, 0x81C, 0x01700003,
347 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
348 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
349 0x81C, 0x007E0003, 0xA0000000, 0x00000000, 0x81C, 0xFF000003,
350 0x81C, 0xFE000003, 0x81C, 0xFD020003, 0x81C, 0xFC040003,
351 0x81C, 0xFB060003, 0x81C, 0xFA080003, 0x81C, 0xF90A0003,
352 0x81C, 0xF80C0003, 0x81C, 0xF70E0003, 0x81C, 0xF6100003,
353 0x81C, 0xF5120003, 0x81C, 0xF4140003, 0x81C, 0xF3160003,
354 0x81C, 0xF2180003, 0x81C, 0xF11A0003, 0x81C, 0xF01C0003,
355 0x81C, 0xEF1E0003, 0x81C, 0xEE200003, 0x81C, 0xED220003,
356 0x81C, 0xEC240003, 0x81C, 0xEB260003, 0x81C, 0xEA280003,
357 0x81C, 0xE92A0003, 0x81C, 0xE82C0003, 0x81C, 0xE72E0003,
358 0x81C, 0xE6300003, 0x81C, 0xE5320003, 0x81C, 0xC8340003,
359 0x81C, 0xC7360003, 0x81C, 0xC6380003, 0x81C, 0xC53A0003,
360 0x81C, 0xC43C0003, 0x81C, 0xC33E0003, 0x81C, 0xC2400003,
361 0x81C, 0xC1420003, 0x81C, 0xC0440003, 0x81C, 0xA3460003,
362 0x81C, 0xA2480003, 0x81C, 0xA14A0003, 0x81C, 0xA04C0003,
363 0x81C, 0x824E0003, 0x81C, 0x81500003, 0x81C, 0x80520003,
364 0x81C, 0x64540003, 0x81C, 0x63560003, 0x81C, 0x62580003,
365 0x81C, 0x445A0003, 0x81C, 0x435C0003, 0x81C, 0x425E0003,
366 0x81C, 0x41600003, 0x81C, 0x40620003, 0x81C, 0x05640003,
367 0x81C, 0x04660003, 0x81C, 0x03680003, 0x81C, 0x026A0003,
368 0x81C, 0x016C0003, 0x81C, 0x006E0003, 0x81C, 0x00700003,
369 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
370 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
371 0x81C, 0x007E0003, 0xB0000000, 0x00000000, 0x8000100f, 0x0a0a0a0a,
372 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
373 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
374 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
375 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
376 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
377 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
378 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
379 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xE22C0103,
380 0x81C, 0xC32E0103, 0x81C, 0xC2300103, 0x81C, 0xC1320103,
381 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
382 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
383 0x81C, 0x80400103, 0x81C, 0x64420103, 0x81C, 0x63440103,
384 0x81C, 0x62460103, 0x81C, 0x61480103, 0x81C, 0x434A0103,
385 0x81C, 0x424C0103, 0x81C, 0x414E0103, 0x81C, 0x40500103,
386 0x81C, 0x22520103, 0x81C, 0x21540103, 0x81C, 0x20560103,
387 0x81C, 0x04580103, 0x81C, 0x035A0103, 0x81C, 0x025C0103,
388 0x81C, 0x015E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
389 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
390 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
391 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
392 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
393 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000100f, 0x05050505,
394 0x40000000, 0x00000000, 0x81C, 0xFA000103, 0x81C, 0xF9020103,
395 0x81C, 0xF8040103, 0x81C, 0xF7060103, 0x81C, 0xF6080103,
396 0x81C, 0xF50A0103, 0x81C, 0xF40C0103, 0x81C, 0xF30E0103,
397 0x81C, 0xF2100103, 0x81C, 0xF1120103, 0x81C, 0xF0140103,
398 0x81C, 0xEF160103, 0x81C, 0xEE180103, 0x81C, 0xED1A0103,
399 0x81C, 0xEC1C0103, 0x81C, 0xEB1E0103, 0x81C, 0xEA200103,
400 0x81C, 0xE9220103, 0x81C, 0xE8240103, 0x81C, 0xE7260103,
401 0x81C, 0xE6280103, 0x81C, 0xE52A0103, 0x81C, 0xC42C0103,
402 0x81C, 0xC32E0103, 0x81C, 0xC2300103, 0x81C, 0xC1320103,
403 0x81C, 0xA4340103, 0x81C, 0xA3360103, 0x81C, 0xA2380103,
404 0x81C, 0xA13A0103, 0x81C, 0x833C0103, 0x81C, 0x823E0103,
405 0x81C, 0x81400103, 0x81C, 0x63420103, 0x81C, 0x62440103,
406 0x81C, 0x61460103, 0x81C, 0x60480103, 0x81C, 0x424A0103,
407 0x81C, 0x414C0103, 0x81C, 0x404E0103, 0x81C, 0x22500103,
408 0x81C, 0x21520103, 0x81C, 0x20540103, 0x81C, 0x03560103,
409 0x81C, 0x02580103, 0x81C, 0x015A0103, 0x81C, 0x005C0103,
410 0x81C, 0x005E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
411 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
412 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
413 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
414 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
415 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000100f, 0x00000000,
416 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
417 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
418 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
419 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
420 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
421 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
422 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
423 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xC32C0103,
424 0x81C, 0xC22E0103, 0x81C, 0xC1300103, 0x81C, 0xC0320103,
425 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
426 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
427 0x81C, 0x80400103, 0x81C, 0x63420103, 0x81C, 0x62440103,
428 0x81C, 0x61460103, 0x81C, 0x60480103, 0x81C, 0x424A0103,
429 0x81C, 0x414C0103, 0x81C, 0x404E0103, 0x81C, 0x06500103,
430 0x81C, 0x05520103, 0x81C, 0x04540103, 0x81C, 0x03560103,
431 0x81C, 0x02580103, 0x81C, 0x015A0103, 0x81C, 0x005C0103,
432 0x81C, 0x005E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
433 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
434 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
435 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
436 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
437 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000200f, 0x00000000,
438 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
439 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
440 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
441 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
442 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
443 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
444 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
445 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xC32C0103,
446 0x81C, 0xC22E0103, 0x81C, 0xC1300103, 0x81C, 0xC0320103,
447 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
448 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
449 0x81C, 0x80400103, 0x81C, 0x63420103, 0x81C, 0x62440103,
450 0x81C, 0x61460103, 0x81C, 0x60480103, 0x81C, 0x424A0103,
451 0x81C, 0x414C0103, 0x81C, 0x404E0103, 0x81C, 0x22500103,
452 0x81C, 0x21520103, 0x81C, 0x20540103, 0x81C, 0x03560103,
453 0x81C, 0x02580103, 0x81C, 0x015A0103, 0x81C, 0x005C0103,
454 0x81C, 0x005E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
455 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
456 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
457 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
458 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
459 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000200c, 0x00000000,
460 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
461 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
462 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
463 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
464 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
465 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
466 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
467 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xC32C0103,
468 0x81C, 0xC22E0103, 0x81C, 0xC1300103, 0x81C, 0xC0320103,
469 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
470 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
471 0x81C, 0x80400103, 0x81C, 0x63420103, 0x81C, 0x62440103,
472 0x81C, 0x61460103, 0x81C, 0x60480103, 0x81C, 0x424A0103,
473 0x81C, 0x414C0103, 0x81C, 0x404E0103, 0x81C, 0x22500103,
474 0x81C, 0x21520103, 0x81C, 0x20540103, 0x81C, 0x03560103,
475 0x81C, 0x02580103, 0x81C, 0x015A0103, 0x81C, 0x005C0103,
476 0x81C, 0x005E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
477 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
478 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
479 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
480 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
481 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90012100, 0x00000000,
482 0x40000000, 0x00000000, 0x81C, 0xFD000103, 0x81C, 0xFC020103,
483 0x81C, 0xFB040103, 0x81C, 0xFA060103, 0x81C, 0xF9080103,
484 0x81C, 0xF80A0103, 0x81C, 0xF70C0103, 0x81C, 0xF60E0103,
485 0x81C, 0xF5100103, 0x81C, 0xF4120103, 0x81C, 0xF3140103,
486 0x81C, 0xF2160103, 0x81C, 0xF1180103, 0x81C, 0xF01A0103,
487 0x81C, 0xEF1C0103, 0x81C, 0xEE1E0103, 0x81C, 0xED200103,
488 0x81C, 0xEC220103, 0x81C, 0xEB240103, 0x81C, 0xEA260103,
489 0x81C, 0xE9280103, 0x81C, 0xE82A0103, 0x81C, 0xE72C0103,
490 0x81C, 0xE62E0103, 0x81C, 0xE5300103, 0x81C, 0xE4320103,
491 0x81C, 0xE3340103, 0x81C, 0xC6360103, 0x81C, 0xC5380103,
492 0x81C, 0xC43A0103, 0x81C, 0xC33C0103, 0x81C, 0xC23E0103,
493 0x81C, 0xA5400103, 0x81C, 0xA4420103, 0x81C, 0xA3440103,
494 0x81C, 0xA2460103, 0x81C, 0xA1480103, 0x81C, 0x834A0103,
495 0x81C, 0x824C0103, 0x81C, 0x814E0103, 0x81C, 0x63500103,
496 0x81C, 0x62520103, 0x81C, 0x61540103, 0x81C, 0x43560103,
497 0x81C, 0x42580103, 0x81C, 0x245A0103, 0x81C, 0x235C0103,
498 0x81C, 0x225E0103, 0x81C, 0x21600103, 0x81C, 0x04620103,
499 0x81C, 0x03640103, 0x81C, 0x02660103, 0x81C, 0x01680103,
500 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
501 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
502 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
503 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90001004, 0x00000000,
504 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
505 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
506 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
507 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
508 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
509 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
510 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
511 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xE22C0103,
512 0x81C, 0xC32E0103, 0x81C, 0xC2300103, 0x81C, 0xC1320103,
513 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
514 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
515 0x81C, 0x80400103, 0x81C, 0x64420103, 0x81C, 0x63440103,
516 0x81C, 0x62460103, 0x81C, 0x61480103, 0x81C, 0x434A0103,
517 0x81C, 0x424C0103, 0x81C, 0x414E0103, 0x81C, 0x40500103,
518 0x81C, 0x22520103, 0x81C, 0x21540103, 0x81C, 0x20560103,
519 0x81C, 0x04580103, 0x81C, 0x035A0103, 0x81C, 0x025C0103,
520 0x81C, 0x015E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
521 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
522 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
523 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
524 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
525 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90011000, 0x00000000,
526 0x40000000, 0x00000000, 0x81C, 0xFD000103, 0x81C, 0xFC020103,
527 0x81C, 0xFB040103, 0x81C, 0xFA060103, 0x81C, 0xF9080103,
528 0x81C, 0xF80A0103, 0x81C, 0xF70C0103, 0x81C, 0xF60E0103,
529 0x81C, 0xF5100103, 0x81C, 0xF4120103, 0x81C, 0xF3140103,
530 0x81C, 0xF2160103, 0x81C, 0xF1180103, 0x81C, 0xF01A0103,
531 0x81C, 0xEE1C0103, 0x81C, 0xED1E0103, 0x81C, 0xEC200103,
532 0x81C, 0xEB220103, 0x81C, 0xEA240103, 0x81C, 0xE9260103,
533 0x81C, 0xE8280103, 0x81C, 0xE72A0103, 0x81C, 0xE62C0103,
534 0x81C, 0xE52E0103, 0x81C, 0xE4300103, 0x81C, 0xE3320103,
535 0x81C, 0xE2340103, 0x81C, 0xC5360103, 0x81C, 0xC4380103,
536 0x81C, 0xC33A0103, 0x81C, 0xC23C0103, 0x81C, 0xA53E0103,
537 0x81C, 0xA4400103, 0x81C, 0xA3420103, 0x81C, 0xA2440103,
538 0x81C, 0xA1460103, 0x81C, 0x83480103, 0x81C, 0x824A0103,
539 0x81C, 0x814C0103, 0x81C, 0x804E0103, 0x81C, 0x63500103,
540 0x81C, 0x62520103, 0x81C, 0x61540103, 0x81C, 0x43560103,
541 0x81C, 0x42580103, 0x81C, 0x415A0103, 0x81C, 0x405C0103,
542 0x81C, 0x225E0103, 0x81C, 0x21600103, 0x81C, 0x20620103,
543 0x81C, 0x03640103, 0x81C, 0x02660103, 0x81C, 0x01680103,
544 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
545 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
546 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
547 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90002100, 0x00000000,
548 0x40000000, 0x00000000, 0x81C, 0xFD000103, 0x81C, 0xFC020103,
549 0x81C, 0xFB040103, 0x81C, 0xFA060103, 0x81C, 0xF9080103,
550 0x81C, 0xF80A0103, 0x81C, 0xF70C0103, 0x81C, 0xF60E0103,
551 0x81C, 0xF5100103, 0x81C, 0xF4120103, 0x81C, 0xF3140103,
552 0x81C, 0xF2160103, 0x81C, 0xF1180103, 0x81C, 0xF01A0103,
553 0x81C, 0xEF1C0103, 0x81C, 0xEE1E0103, 0x81C, 0xED200103,
554 0x81C, 0xEC220103, 0x81C, 0xEB240103, 0x81C, 0xEA260103,
555 0x81C, 0xE9280103, 0x81C, 0xE82A0103, 0x81C, 0xE72C0103,
556 0x81C, 0xE62E0103, 0x81C, 0xE5300103, 0x81C, 0xE4320103,
557 0x81C, 0xE3340103, 0x81C, 0xE2360103, 0x81C, 0xC5380103,
558 0x81C, 0xC43A0103, 0x81C, 0xC33C0103, 0x81C, 0xC23E0103,
559 0x81C, 0xA5400103, 0x81C, 0xA4420103, 0x81C, 0xA3440103,
560 0x81C, 0xA2460103, 0x81C, 0xA1480103, 0x81C, 0x834A0103,
561 0x81C, 0x824C0103, 0x81C, 0x814E0103, 0x81C, 0x64500103,
562 0x81C, 0x63520103, 0x81C, 0x62540103, 0x81C, 0x61560103,
563 0x81C, 0x42580103, 0x81C, 0x415A0103, 0x81C, 0x405C0103,
564 0x81C, 0x065E0103, 0x81C, 0x05600103, 0x81C, 0x04620103,
565 0x81C, 0x03640103, 0x81C, 0x02660103, 0x81C, 0x01680103,
566 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
567 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
568 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
569 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90002000, 0x00000000,
570 0x40000000, 0x00000000, 0x81C, 0xFE000103, 0x81C, 0xFD020103,
571 0x81C, 0xFC040103, 0x81C, 0xFB060103, 0x81C, 0xFA080103,
572 0x81C, 0xF90A0103, 0x81C, 0xF80C0103, 0x81C, 0xF70E0103,
573 0x81C, 0xF6100103, 0x81C, 0xF5120103, 0x81C, 0xF4140103,
574 0x81C, 0xF3160103, 0x81C, 0xF2180103, 0x81C, 0xF11A0103,
575 0x81C, 0xF01C0103, 0x81C, 0xEF1E0103, 0x81C, 0xEE200103,
576 0x81C, 0xED220103, 0x81C, 0xEC240103, 0x81C, 0xEB260103,
577 0x81C, 0xEA280103, 0x81C, 0xE92A0103, 0x81C, 0xE82C0103,
578 0x81C, 0xE72E0103, 0x81C, 0xE6300103, 0x81C, 0xE5320103,
579 0x81C, 0xE4340103, 0x81C, 0xE3360103, 0x81C, 0xC6380103,
580 0x81C, 0xC53A0103, 0x81C, 0xC43C0103, 0x81C, 0xC33E0103,
581 0x81C, 0xA5400103, 0x81C, 0xA4420103, 0x81C, 0xA3440103,
582 0x81C, 0xA2460103, 0x81C, 0xA1480103, 0x81C, 0xA04A0103,
583 0x81C, 0x824C0103, 0x81C, 0x814E0103, 0x81C, 0x80500103,
584 0x81C, 0x64520103, 0x81C, 0x63540103, 0x81C, 0x62560103,
585 0x81C, 0x61580103, 0x81C, 0x605A0103, 0x81C, 0x235C0103,
586 0x81C, 0x225E0103, 0x81C, 0x21600103, 0x81C, 0x20620103,
587 0x81C, 0x03640103, 0x81C, 0x02660103, 0x81C, 0x01680103,
588 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
589 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
590 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
591 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0xA0000000, 0x00000000,
592 0x81C, 0xFE000103, 0x81C, 0xFD020103, 0x81C, 0xFC040103,
593 0x81C, 0xFB060103, 0x81C, 0xFA080103, 0x81C, 0xF90A0103,
594 0x81C, 0xF80C0103, 0x81C, 0xF70E0103, 0x81C, 0xF6100103,
595 0x81C, 0xF5120103, 0x81C, 0xF4140103, 0x81C, 0xF3160103,
596 0x81C, 0xF2180103, 0x81C, 0xF11A0103, 0x81C, 0xF01C0103,
597 0x81C, 0xEF1E0103, 0x81C, 0xEE200103, 0x81C, 0xED220103,
598 0x81C, 0xEC240103, 0x81C, 0xEB260103, 0x81C, 0xEA280103,
599 0x81C, 0xE92A0103, 0x81C, 0xE82C0103, 0x81C, 0xE72E0103,
600 0x81C, 0xE6300103, 0x81C, 0xE5320103, 0x81C, 0xE4340103,
601 0x81C, 0xE3360103, 0x81C, 0xC6380103, 0x81C, 0xC53A0103,
602 0x81C, 0xC43C0103, 0x81C, 0xC33E0103, 0x81C, 0xA5400103,
603 0x81C, 0xA4420103, 0x81C, 0xA3440103, 0x81C, 0xA2460103,
604 0x81C, 0xA1480103, 0x81C, 0xA04A0103, 0x81C, 0x824C0103,
605 0x81C, 0x814E0103, 0x81C, 0x80500103, 0x81C, 0x64520103,
606 0x81C, 0x63540103, 0x81C, 0x62560103, 0x81C, 0x61580103,
607 0x81C, 0x605A0103, 0x81C, 0x235C0103, 0x81C, 0x225E0103,
608 0x81C, 0x21600103, 0x81C, 0x20620103, 0x81C, 0x03640103,
609 0x81C, 0x02660103, 0x81C, 0x01680103, 0x81C, 0x006A0103,
610 0x81C, 0x006C0103, 0x81C, 0x006E0103, 0x81C, 0x00700103,
611 0x81C, 0x00720103, 0x81C, 0x00740103, 0x81C, 0x00760103,
612 0x81C, 0x00780103, 0x81C, 0x007A0103, 0x81C, 0x007C0103,
613 0x81C, 0x007E0103, 0xB0000000, 0x00000000, 0x8000100f, 0x0a0a0a0a,
614 0x40000000, 0x00000000, 0x81C, 0xF8000203, 0x81C, 0xF7020203,
615 0x81C, 0xF6040203, 0x81C, 0xF5060203, 0x81C, 0xF4080203,
616 0x81C, 0xF30A0203, 0x81C, 0xF20C0203, 0x81C, 0xF10E0203,
617 0x81C, 0xF0100203, 0x81C, 0xEF120203, 0x81C, 0xEE140203,
618 0x81C, 0xED160203, 0x81C, 0xEC180203, 0x81C, 0xEB1A0203,
619 0x81C, 0xEA1C0203, 0x81C, 0xE91E0203, 0x81C, 0xE8200203,
620 0x81C, 0xE7220203, 0x81C, 0xE6240203, 0x81C, 0xE5260203,
621 0x81C, 0xE4280203, 0x81C, 0xE32A0203, 0x81C, 0xC42C0203,
622 0x81C, 0xC32E0203, 0x81C, 0xC2300203, 0x81C, 0xC1320203,
623 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
624 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
625 0x81C, 0x80400203, 0x81C, 0x65420203, 0x81C, 0x64440203,
626 0x81C, 0x63460203, 0x81C, 0x62480203, 0x81C, 0x614A0203,
627 0x81C, 0x424C0203, 0x81C, 0x414E0203, 0x81C, 0x40500203,
628 0x81C, 0x22520203, 0x81C, 0x21540203, 0x81C, 0x20560203,
629 0x81C, 0x04580203, 0x81C, 0x035A0203, 0x81C, 0x025C0203,
630 0x81C, 0x015E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
631 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
632 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
633 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
634 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
635 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x9000100f, 0x05050505,
636 0x40000000, 0x00000000, 0x81C, 0xF9000203, 0x81C, 0xF8020203,
637 0x81C, 0xF7040203, 0x81C, 0xF6060203, 0x81C, 0xF5080203,
638 0x81C, 0xF40A0203, 0x81C, 0xF30C0203, 0x81C, 0xF20E0203,
639 0x81C, 0xF1100203, 0x81C, 0xF0120203, 0x81C, 0xEF140203,
640 0x81C, 0xEE160203, 0x81C, 0xED180203, 0x81C, 0xEC1A0203,
641 0x81C, 0xEB1C0203, 0x81C, 0xEA1E0203, 0x81C, 0xE9200203,
642 0x81C, 0xE8220203, 0x81C, 0xE7240203, 0x81C, 0xE6260203,
643 0x81C, 0xE5280203, 0x81C, 0xC42A0203, 0x81C, 0xC32C0203,
644 0x81C, 0xC22E0203, 0x81C, 0xC1300203, 0x81C, 0xC0320203,
645 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
646 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
647 0x81C, 0x80400203, 0x81C, 0x64420203, 0x81C, 0x63440203,
648 0x81C, 0x62460203, 0x81C, 0x61480203, 0x81C, 0x604A0203,
649 0x81C, 0x414C0203, 0x81C, 0x404E0203, 0x81C, 0x22500203,
650 0x81C, 0x21520203, 0x81C, 0x20540203, 0x81C, 0x03560203,
651 0x81C, 0x02580203, 0x81C, 0x015A0203, 0x81C, 0x005C0203,
652 0x81C, 0x005E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
653 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
654 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
655 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
656 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
657 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x9000100f, 0x00000000,
658 0x40000000, 0x00000000, 0x81C, 0xF7000203, 0x81C, 0xF6020203,
659 0x81C, 0xF5040203, 0x81C, 0xF4060203, 0x81C, 0xF3080203,
660 0x81C, 0xF20A0203, 0x81C, 0xF10C0203, 0x81C, 0xF00E0203,
661 0x81C, 0xEF100203, 0x81C, 0xEE120203, 0x81C, 0xED140203,
662 0x81C, 0xEC160203, 0x81C, 0xEB180203, 0x81C, 0xEA1A0203,
663 0x81C, 0xE91C0203, 0x81C, 0xE81E0203, 0x81C, 0xE7200203,
664 0x81C, 0xE6220203, 0x81C, 0xE5240203, 0x81C, 0xE4260203,
665 0x81C, 0xE3280203, 0x81C, 0xC42A0203, 0x81C, 0xC32C0203,
666 0x81C, 0xC22E0203, 0x81C, 0xC1300203, 0x81C, 0xC0320203,
667 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
668 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
669 0x81C, 0x80400203, 0x81C, 0x63420203, 0x81C, 0x62440203,
670 0x81C, 0x61460203, 0x81C, 0x60480203, 0x81C, 0x424A0203,
671 0x81C, 0x414C0203, 0x81C, 0x404E0203, 0x81C, 0x06500203,
672 0x81C, 0x05520203, 0x81C, 0x04540203, 0x81C, 0x03560203,
673 0x81C, 0x02580203, 0x81C, 0x015A0203, 0x81C, 0x005C0203,
674 0x81C, 0x005E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
675 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
676 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
677 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
678 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
679 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x9000200f, 0x00000000,
680 0x40000000, 0x00000000, 0x81C, 0xF7000203, 0x81C, 0xF6020203,
681 0x81C, 0xF5040203, 0x81C, 0xF4060203, 0x81C, 0xF3080203,
682 0x81C, 0xF20A0203, 0x81C, 0xF10C0203, 0x81C, 0xF00E0203,
683 0x81C, 0xEF100203, 0x81C, 0xEE120203, 0x81C, 0xED140203,
684 0x81C, 0xEC160203, 0x81C, 0xEB180203, 0x81C, 0xEA1A0203,
685 0x81C, 0xE91C0203, 0x81C, 0xE81E0203, 0x81C, 0xE7200203,
686 0x81C, 0xE6220203, 0x81C, 0xE5240203, 0x81C, 0xE4260203,
687 0x81C, 0xE3280203, 0x81C, 0xC42A0203, 0x81C, 0xC32C0203,
688 0x81C, 0xC22E0203, 0x81C, 0xC1300203, 0x81C, 0xC0320203,
689 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
690 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
691 0x81C, 0x80400203, 0x81C, 0x64420203, 0x81C, 0x63440203,
692 0x81C, 0x62460203, 0x81C, 0x61480203, 0x81C, 0x604A0203,
693 0x81C, 0x414C0203, 0x81C, 0x404E0203, 0x81C, 0x22500203,
694 0x81C, 0x21520203, 0x81C, 0x20540203, 0x81C, 0x03560203,
695 0x81C, 0x02580203, 0x81C, 0x015A0203, 0x81C, 0x005C0203,
696 0x81C, 0x005E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
697 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
698 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
699 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
700 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
701 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x9000200c, 0x00000000,
702 0x40000000, 0x00000000, 0x81C, 0xF7000203, 0x81C, 0xF6020203,
703 0x81C, 0xF5040203, 0x81C, 0xF4060203, 0x81C, 0xF3080203,
704 0x81C, 0xF20A0203, 0x81C, 0xF10C0203, 0x81C, 0xF00E0203,
705 0x81C, 0xEF100203, 0x81C, 0xEE120203, 0x81C, 0xED140203,
706 0x81C, 0xEC160203, 0x81C, 0xEB180203, 0x81C, 0xEA1A0203,
707 0x81C, 0xE91C0203, 0x81C, 0xE81E0203, 0x81C, 0xE7200203,
708 0x81C, 0xE6220203, 0x81C, 0xE5240203, 0x81C, 0xE4260203,
709 0x81C, 0xE3280203, 0x81C, 0xC42A0203, 0x81C, 0xC32C0203,
710 0x81C, 0xC22E0203, 0x81C, 0xC1300203, 0x81C, 0xC0320203,
711 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
712 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
713 0x81C, 0x80400203, 0x81C, 0x64420203, 0x81C, 0x63440203,
714 0x81C, 0x62460203, 0x81C, 0x61480203, 0x81C, 0x604A0203,
715 0x81C, 0x414C0203, 0x81C, 0x404E0203, 0x81C, 0x22500203,
716 0x81C, 0x21520203, 0x81C, 0x20540203, 0x81C, 0x03560203,
717 0x81C, 0x02580203, 0x81C, 0x015A0203, 0x81C, 0x005C0203,
718 0x81C, 0x005E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
719 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
720 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
721 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
722 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
723 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90012100, 0x00000000,
724 0x40000000, 0x00000000, 0x81C, 0xFB000203, 0x81C, 0xFA020203,
725 0x81C, 0xF9040203, 0x81C, 0xF8060203, 0x81C, 0xF7080203,
726 0x81C, 0xF60A0203, 0x81C, 0xF50C0203, 0x81C, 0xF40E0203,
727 0x81C, 0xF3100203, 0x81C, 0xF2120203, 0x81C, 0xF1140203,
728 0x81C, 0xF0160203, 0x81C, 0xEF180203, 0x81C, 0xEE1A0203,
729 0x81C, 0xED1C0203, 0x81C, 0xEC1E0203, 0x81C, 0xEB200203,
730 0x81C, 0xEA220203, 0x81C, 0xE9240203, 0x81C, 0xE8260203,
731 0x81C, 0xE7280203, 0x81C, 0xE62A0203, 0x81C, 0xE52C0203,
732 0x81C, 0xE42E0203, 0x81C, 0xE3300203, 0x81C, 0xE2320203,
733 0x81C, 0xC6340203, 0x81C, 0xC5360203, 0x81C, 0xC4380203,
734 0x81C, 0xC33A0203, 0x81C, 0xC23C0203, 0x81C, 0xC13E0203,
735 0x81C, 0xC0400203, 0x81C, 0xA3420203, 0x81C, 0xA2440203,
736 0x81C, 0xA1460203, 0x81C, 0xA0480203, 0x81C, 0x824A0203,
737 0x81C, 0x814C0203, 0x81C, 0x804E0203, 0x81C, 0x63500203,
738 0x81C, 0x62520203, 0x81C, 0x61540203, 0x81C, 0x60560203,
739 0x81C, 0x24580203, 0x81C, 0x235A0203, 0x81C, 0x225C0203,
740 0x81C, 0x215E0203, 0x81C, 0x20600203, 0x81C, 0x03620203,
741 0x81C, 0x02640203, 0x81C, 0x01660203, 0x81C, 0x00680203,
742 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
743 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
744 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
745 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90001004, 0x00000000,
746 0x40000000, 0x00000000, 0x81C, 0xF8000203, 0x81C, 0xF7020203,
747 0x81C, 0xF6040203, 0x81C, 0xF5060203, 0x81C, 0xF4080203,
748 0x81C, 0xF30A0203, 0x81C, 0xF20C0203, 0x81C, 0xF10E0203,
749 0x81C, 0xF0100203, 0x81C, 0xEF120203, 0x81C, 0xEE140203,
750 0x81C, 0xED160203, 0x81C, 0xEC180203, 0x81C, 0xEB1A0203,
751 0x81C, 0xEA1C0203, 0x81C, 0xE91E0203, 0x81C, 0xE8200203,
752 0x81C, 0xE7220203, 0x81C, 0xE6240203, 0x81C, 0xE5260203,
753 0x81C, 0xE4280203, 0x81C, 0xE32A0203, 0x81C, 0xC42C0203,
754 0x81C, 0xC32E0203, 0x81C, 0xC2300203, 0x81C, 0xC1320203,
755 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
756 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
757 0x81C, 0x80400203, 0x81C, 0x65420203, 0x81C, 0x64440203,
758 0x81C, 0x63460203, 0x81C, 0x62480203, 0x81C, 0x614A0203,
759 0x81C, 0x424C0203, 0x81C, 0x414E0203, 0x81C, 0x40500203,
760 0x81C, 0x22520203, 0x81C, 0x21540203, 0x81C, 0x20560203,
761 0x81C, 0x04580203, 0x81C, 0x035A0203, 0x81C, 0x025C0203,
762 0x81C, 0x015E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
763 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
764 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
765 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
766 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
767 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90011000, 0x00000000,
768 0x40000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203,
769 0x81C, 0xFA040203, 0x81C, 0xF9060203, 0x81C, 0xF8080203,
770 0x81C, 0xF70A0203, 0x81C, 0xF60C0203, 0x81C, 0xF50E0203,
771 0x81C, 0xF4100203, 0x81C, 0xF3120203, 0x81C, 0xF2140203,
772 0x81C, 0xF1160203, 0x81C, 0xF0180203, 0x81C, 0xEE1A0203,
773 0x81C, 0xED1C0203, 0x81C, 0xEC1E0203, 0x81C, 0xEB200203,
774 0x81C, 0xEA220203, 0x81C, 0xE9240203, 0x81C, 0xE8260203,
775 0x81C, 0xE7280203, 0x81C, 0xE62A0203, 0x81C, 0xE52C0203,
776 0x81C, 0xE42E0203, 0x81C, 0xE3300203, 0x81C, 0xE2320203,
777 0x81C, 0xC6340203, 0x81C, 0xC5360203, 0x81C, 0xC4380203,
778 0x81C, 0xC33A0203, 0x81C, 0xA63C0203, 0x81C, 0xA53E0203,
779 0x81C, 0xA4400203, 0x81C, 0xA3420203, 0x81C, 0xA2440203,
780 0x81C, 0xA1460203, 0x81C, 0x83480203, 0x81C, 0x824A0203,
781 0x81C, 0x814C0203, 0x81C, 0x804E0203, 0x81C, 0x63500203,
782 0x81C, 0x62520203, 0x81C, 0x61540203, 0x81C, 0x42560203,
783 0x81C, 0x41580203, 0x81C, 0x405A0203, 0x81C, 0x225C0203,
784 0x81C, 0x215E0203, 0x81C, 0x20600203, 0x81C, 0x04620203,
785 0x81C, 0x03640203, 0x81C, 0x02660203, 0x81C, 0x01680203,
786 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
787 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
788 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
789 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90002100, 0x00000000,
790 0x40000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203,
791 0x81C, 0xFA040203, 0x81C, 0xF9060203, 0x81C, 0xF8080203,
792 0x81C, 0xF70A0203, 0x81C, 0xF60C0203, 0x81C, 0xF50E0203,
793 0x81C, 0xF4100203, 0x81C, 0xF3120203, 0x81C, 0xF2140203,
794 0x81C, 0xF1160203, 0x81C, 0xF0180203, 0x81C, 0xEF1A0203,
795 0x81C, 0xEE1C0203, 0x81C, 0xED1E0203, 0x81C, 0xEC200203,
796 0x81C, 0xEB220203, 0x81C, 0xEA240203, 0x81C, 0xE9260203,
797 0x81C, 0xE8280203, 0x81C, 0xE72A0203, 0x81C, 0xE62C0203,
798 0x81C, 0xE52E0203, 0x81C, 0xE4300203, 0x81C, 0xE3320203,
799 0x81C, 0xE2340203, 0x81C, 0xE1360203, 0x81C, 0xC5380203,
800 0x81C, 0xC43A0203, 0x81C, 0xC33C0203, 0x81C, 0xC23E0203,
801 0x81C, 0xC1400203, 0x81C, 0xA3420203, 0x81C, 0xA2440203,
802 0x81C, 0xA1460203, 0x81C, 0xA0480203, 0x81C, 0x834A0203,
803 0x81C, 0x824C0203, 0x81C, 0x814E0203, 0x81C, 0x64500203,
804 0x81C, 0x63520203, 0x81C, 0x62540203, 0x81C, 0x61560203,
805 0x81C, 0x25580203, 0x81C, 0x245A0203, 0x81C, 0x235C0203,
806 0x81C, 0x225E0203, 0x81C, 0x21600203, 0x81C, 0x04620203,
807 0x81C, 0x03640203, 0x81C, 0x02660203, 0x81C, 0x01680203,
808 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
809 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
810 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
811 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90002000, 0x00000000,
812 0x40000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203,
813 0x81C, 0xFA040203, 0x81C, 0xF9060203, 0x81C, 0xF8080203,
814 0x81C, 0xF70A0203, 0x81C, 0xF60C0203, 0x81C, 0xF50E0203,
815 0x81C, 0xF4100203, 0x81C, 0xF3120203, 0x81C, 0xF2140203,
816 0x81C, 0xF1160203, 0x81C, 0xF0180203, 0x81C, 0xEF1A0203,
817 0x81C, 0xEE1C0203, 0x81C, 0xED1E0203, 0x81C, 0xEC200203,
818 0x81C, 0xEB220203, 0x81C, 0xEA240203, 0x81C, 0xE9260203,
819 0x81C, 0xE8280203, 0x81C, 0xE72A0203, 0x81C, 0xE62C0203,
820 0x81C, 0xE52E0203, 0x81C, 0xE4300203, 0x81C, 0xE3320203,
821 0x81C, 0xE2340203, 0x81C, 0xC6360203, 0x81C, 0xC5380203,
822 0x81C, 0xC43A0203, 0x81C, 0xC33C0203, 0x81C, 0xA63E0203,
823 0x81C, 0xA5400203, 0x81C, 0xA4420203, 0x81C, 0xA3440203,
824 0x81C, 0xA2460203, 0x81C, 0xA1480203, 0x81C, 0x834A0203,
825 0x81C, 0x824C0203, 0x81C, 0x814E0203, 0x81C, 0x64500203,
826 0x81C, 0x63520203, 0x81C, 0x62540203, 0x81C, 0x61560203,
827 0x81C, 0x60580203, 0x81C, 0x405A0203, 0x81C, 0x215C0203,
828 0x81C, 0x205E0203, 0x81C, 0x03600203, 0x81C, 0x02620203,
829 0x81C, 0x01640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
830 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
831 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
832 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
833 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0xA0000000, 0x00000000,
834 0x81C, 0xFD000203, 0x81C, 0xFC020203, 0x81C, 0xFB040203,
835 0x81C, 0xFA060203, 0x81C, 0xF9080203, 0x81C, 0xF80A0203,
836 0x81C, 0xF70C0203, 0x81C, 0xF60E0203, 0x81C, 0xF5100203,
837 0x81C, 0xF4120203, 0x81C, 0xF3140203, 0x81C, 0xF2160203,
838 0x81C, 0xF1180203, 0x81C, 0xF01A0203, 0x81C, 0xEF1C0203,
839 0x81C, 0xEE1E0203, 0x81C, 0xED200203, 0x81C, 0xEC220203,
840 0x81C, 0xEB240203, 0x81C, 0xEA260203, 0x81C, 0xE9280203,
841 0x81C, 0xE82A0203, 0x81C, 0xE72C0203, 0x81C, 0xE62E0203,
842 0x81C, 0xE5300203, 0x81C, 0xE4320203, 0x81C, 0xE3340203,
843 0x81C, 0xC6360203, 0x81C, 0xC5380203, 0x81C, 0xC43A0203,
844 0x81C, 0xC33C0203, 0x81C, 0xA63E0203, 0x81C, 0xA5400203,
845 0x81C, 0xA4420203, 0x81C, 0xA3440203, 0x81C, 0xA2460203,
846 0x81C, 0xA1480203, 0x81C, 0x834A0203, 0x81C, 0x824C0203,
847 0x81C, 0x814E0203, 0x81C, 0x64500203, 0x81C, 0x63520203,
848 0x81C, 0x62540203, 0x81C, 0x61560203, 0x81C, 0x60580203,
849 0x81C, 0x235A0203, 0x81C, 0x225C0203, 0x81C, 0x215E0203,
850 0x81C, 0x20600203, 0x81C, 0x03620203, 0x81C, 0x02640203,
851 0x81C, 0x01660203, 0x81C, 0x00680203, 0x81C, 0x006A0203,
852 0x81C, 0x006C0203, 0x81C, 0x006E0203, 0x81C, 0x00700203,
853 0x81C, 0x00720203, 0x81C, 0x00740203, 0x81C, 0x00760203,
854 0x81C, 0x00780203, 0x81C, 0x007A0203, 0x81C, 0x007C0203,
855 0x81C, 0x007E0203, 0xB0000000, 0x00000000, 0x8000100f, 0x0a0a0a0a,
856 0x40000000, 0x00000000, 0x81C, 0xF8000303, 0x81C, 0xF7020303,
857 0x81C, 0xF6040303, 0x81C, 0xF5060303, 0x81C, 0xF4080303,
858 0x81C, 0xF30A0303, 0x81C, 0xF20C0303, 0x81C, 0xF10E0303,
859 0x81C, 0xF0100303, 0x81C, 0xEF120303, 0x81C, 0xEE140303,
860 0x81C, 0xED160303, 0x81C, 0xEC180303, 0x81C, 0xEB1A0303,
861 0x81C, 0xEA1C0303, 0x81C, 0xE91E0303, 0x81C, 0xCA200303,
862 0x81C, 0xC9220303, 0x81C, 0xC8240303, 0x81C, 0xC7260303,
863 0x81C, 0xC6280303, 0x81C, 0xC52A0303, 0x81C, 0xC42C0303,
864 0x81C, 0xC32E0303, 0x81C, 0xC2300303, 0x81C, 0xC1320303,
865 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
866 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
867 0x81C, 0x80400303, 0x81C, 0x65420303, 0x81C, 0x64440303,
868 0x81C, 0x63460303, 0x81C, 0x62480303, 0x81C, 0x614A0303,
869 0x81C, 0x424C0303, 0x81C, 0x414E0303, 0x81C, 0x40500303,
870 0x81C, 0x22520303, 0x81C, 0x21540303, 0x81C, 0x20560303,
871 0x81C, 0x04580303, 0x81C, 0x035A0303, 0x81C, 0x025C0303,
872 0x81C, 0x015E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
873 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
874 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
875 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
876 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
877 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x9000100f, 0x05050505,
878 0x40000000, 0x00000000, 0x81C, 0xF9000303, 0x81C, 0xF8020303,
879 0x81C, 0xF7040303, 0x81C, 0xF6060303, 0x81C, 0xF5080303,
880 0x81C, 0xF40A0303, 0x81C, 0xF30C0303, 0x81C, 0xF20E0303,
881 0x81C, 0xF1100303, 0x81C, 0xF0120303, 0x81C, 0xEF140303,
882 0x81C, 0xEE160303, 0x81C, 0xED180303, 0x81C, 0xEC1A0303,
883 0x81C, 0xEB1C0303, 0x81C, 0xEA1E0303, 0x81C, 0xC9200303,
884 0x81C, 0xC8220303, 0x81C, 0xC7240303, 0x81C, 0xC6260303,
885 0x81C, 0xC5280303, 0x81C, 0xC42A0303, 0x81C, 0xC32C0303,
886 0x81C, 0xC22E0303, 0x81C, 0xC1300303, 0x81C, 0xC0320303,
887 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
888 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
889 0x81C, 0x80400303, 0x81C, 0x64420303, 0x81C, 0x63440303,
890 0x81C, 0x62460303, 0x81C, 0x61480303, 0x81C, 0x604A0303,
891 0x81C, 0x414C0303, 0x81C, 0x404E0303, 0x81C, 0x22500303,
892 0x81C, 0x21520303, 0x81C, 0x20540303, 0x81C, 0x03560303,
893 0x81C, 0x02580303, 0x81C, 0x015A0303, 0x81C, 0x005C0303,
894 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
895 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
896 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
897 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
898 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
899 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x9000100f, 0x00000000,
900 0x40000000, 0x00000000, 0x81C, 0xF7000303, 0x81C, 0xF6020303,
901 0x81C, 0xF5040303, 0x81C, 0xF4060303, 0x81C, 0xF3080303,
902 0x81C, 0xF20A0303, 0x81C, 0xF10C0303, 0x81C, 0xF00E0303,
903 0x81C, 0xEF100303, 0x81C, 0xEE120303, 0x81C, 0xED140303,
904 0x81C, 0xEC160303, 0x81C, 0xEB180303, 0x81C, 0xEA1A0303,
905 0x81C, 0xE91C0303, 0x81C, 0xCA1E0303, 0x81C, 0xC9200303,
906 0x81C, 0xC8220303, 0x81C, 0xC7240303, 0x81C, 0xC6260303,
907 0x81C, 0xC5280303, 0x81C, 0xC42A0303, 0x81C, 0xC32C0303,
908 0x81C, 0xC22E0303, 0x81C, 0xC1300303, 0x81C, 0xA4320303,
909 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
910 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
911 0x81C, 0x80400303, 0x81C, 0x64420303, 0x81C, 0x63440303,
912 0x81C, 0x62460303, 0x81C, 0x61480303, 0x81C, 0x604A0303,
913 0x81C, 0x414C0303, 0x81C, 0x404E0303, 0x81C, 0x06500303,
914 0x81C, 0x05520303, 0x81C, 0x04540303, 0x81C, 0x03560303,
915 0x81C, 0x02580303, 0x81C, 0x015A0303, 0x81C, 0x005C0303,
916 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
917 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
918 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
919 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
920 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
921 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x9000200f, 0x00000000,
922 0x40000000, 0x00000000, 0x81C, 0xF7000303, 0x81C, 0xF6020303,
923 0x81C, 0xF5040303, 0x81C, 0xF4060303, 0x81C, 0xF3080303,
924 0x81C, 0xF20A0303, 0x81C, 0xF10C0303, 0x81C, 0xF00E0303,
925 0x81C, 0xEF100303, 0x81C, 0xEE120303, 0x81C, 0xED140303,
926 0x81C, 0xEC160303, 0x81C, 0xEB180303, 0x81C, 0xEA1A0303,
927 0x81C, 0xE91C0303, 0x81C, 0xCA1E0303, 0x81C, 0xC9200303,
928 0x81C, 0xC8220303, 0x81C, 0xC7240303, 0x81C, 0xC6260303,
929 0x81C, 0xC5280303, 0x81C, 0xC42A0303, 0x81C, 0xC32C0303,
930 0x81C, 0xC22E0303, 0x81C, 0xC1300303, 0x81C, 0xA4320303,
931 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
932 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
933 0x81C, 0x80400303, 0x81C, 0x64420303, 0x81C, 0x63440303,
934 0x81C, 0x62460303, 0x81C, 0x61480303, 0x81C, 0x604A0303,
935 0x81C, 0x414C0303, 0x81C, 0x404E0303, 0x81C, 0x22500303,
936 0x81C, 0x21520303, 0x81C, 0x20540303, 0x81C, 0x03560303,
937 0x81C, 0x02580303, 0x81C, 0x015A0303, 0x81C, 0x005C0303,
938 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
939 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
940 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
941 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
942 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
943 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x9000200c, 0x00000000,
944 0x40000000, 0x00000000, 0x81C, 0xF7000303, 0x81C, 0xF6020303,
945 0x81C, 0xF5040303, 0x81C, 0xF4060303, 0x81C, 0xF3080303,
946 0x81C, 0xF20A0303, 0x81C, 0xF10C0303, 0x81C, 0xF00E0303,
947 0x81C, 0xEF100303, 0x81C, 0xEE120303, 0x81C, 0xED140303,
948 0x81C, 0xEC160303, 0x81C, 0xEB180303, 0x81C, 0xEA1A0303,
949 0x81C, 0xE91C0303, 0x81C, 0xCA1E0303, 0x81C, 0xC9200303,
950 0x81C, 0xC8220303, 0x81C, 0xC7240303, 0x81C, 0xC6260303,
951 0x81C, 0xC5280303, 0x81C, 0xC42A0303, 0x81C, 0xC32C0303,
952 0x81C, 0xC22E0303, 0x81C, 0xC1300303, 0x81C, 0xA4320303,
953 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
954 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
955 0x81C, 0x80400303, 0x81C, 0x64420303, 0x81C, 0x63440303,
956 0x81C, 0x62460303, 0x81C, 0x61480303, 0x81C, 0x604A0303,
957 0x81C, 0x414C0303, 0x81C, 0x404E0303, 0x81C, 0x22500303,
958 0x81C, 0x21520303, 0x81C, 0x20540303, 0x81C, 0x03560303,
959 0x81C, 0x02580303, 0x81C, 0x015A0303, 0x81C, 0x005C0303,
960 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
961 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
962 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
963 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
964 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
965 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90012100, 0x00000000,
966 0x40000000, 0x00000000, 0x81C, 0xFB000303, 0x81C, 0xFA020303,
967 0x81C, 0xF9040303, 0x81C, 0xF8060303, 0x81C, 0xF7080303,
968 0x81C, 0xF60A0303, 0x81C, 0xF50C0303, 0x81C, 0xF40E0303,
969 0x81C, 0xF3100303, 0x81C, 0xF2120303, 0x81C, 0xF1140303,
970 0x81C, 0xF0160303, 0x81C, 0xEF180303, 0x81C, 0xEE1A0303,
971 0x81C, 0xED1C0303, 0x81C, 0xEC1E0303, 0x81C, 0xEB200303,
972 0x81C, 0xEA220303, 0x81C, 0xE9240303, 0x81C, 0xE8260303,
973 0x81C, 0xE7280303, 0x81C, 0xE62A0303, 0x81C, 0xE52C0303,
974 0x81C, 0xE42E0303, 0x81C, 0xE3300303, 0x81C, 0xE2320303,
975 0x81C, 0xC6340303, 0x81C, 0xC5360303, 0x81C, 0xC4380303,
976 0x81C, 0xC33A0303, 0x81C, 0xC23C0303, 0x81C, 0xC13E0303,
977 0x81C, 0xA4400303, 0x81C, 0xA3420303, 0x81C, 0xA2440303,
978 0x81C, 0xA1460303, 0x81C, 0x83480303, 0x81C, 0x824A0303,
979 0x81C, 0x814C0303, 0x81C, 0x804E0303, 0x81C, 0x63500303,
980 0x81C, 0x62520303, 0x81C, 0x43540303, 0x81C, 0x42560303,
981 0x81C, 0x41580303, 0x81C, 0x235A0303, 0x81C, 0x225C0303,
982 0x81C, 0x215E0303, 0x81C, 0x20600303, 0x81C, 0x04620303,
983 0x81C, 0x03640303, 0x81C, 0x02660303, 0x81C, 0x01680303,
984 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
985 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
986 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
987 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90001004, 0x00000000,
988 0x40000000, 0x00000000, 0x81C, 0xF8000303, 0x81C, 0xF7020303,
989 0x81C, 0xF6040303, 0x81C, 0xF5060303, 0x81C, 0xF4080303,
990 0x81C, 0xF30A0303, 0x81C, 0xF20C0303, 0x81C, 0xF10E0303,
991 0x81C, 0xF0100303, 0x81C, 0xEF120303, 0x81C, 0xEE140303,
992 0x81C, 0xED160303, 0x81C, 0xEC180303, 0x81C, 0xEB1A0303,
993 0x81C, 0xEA1C0303, 0x81C, 0xE91E0303, 0x81C, 0xCA200303,
994 0x81C, 0xC9220303, 0x81C, 0xC8240303, 0x81C, 0xC7260303,
995 0x81C, 0xC6280303, 0x81C, 0xC52A0303, 0x81C, 0xC42C0303,
996 0x81C, 0xC32E0303, 0x81C, 0xC2300303, 0x81C, 0xC1320303,
997 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
998 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
999 0x81C, 0x80400303, 0x81C, 0x65420303, 0x81C, 0x64440303,
1000 0x81C, 0x63460303, 0x81C, 0x62480303, 0x81C, 0x614A0303,
1001 0x81C, 0x424C0303, 0x81C, 0x414E0303, 0x81C, 0x40500303,
1002 0x81C, 0x22520303, 0x81C, 0x21540303, 0x81C, 0x20560303,
1003 0x81C, 0x04580303, 0x81C, 0x035A0303, 0x81C, 0x025C0303,
1004 0x81C, 0x015E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
1005 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
1006 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
1007 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
1008 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
1009 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90011000, 0x00000000,
1010 0x40000000, 0x00000000, 0x81C, 0xFB000303, 0x81C, 0xFA020303,
1011 0x81C, 0xF9040303, 0x81C, 0xF8060303, 0x81C, 0xF7080303,
1012 0x81C, 0xF60A0303, 0x81C, 0xF50C0303, 0x81C, 0xF40E0303,
1013 0x81C, 0xF3100303, 0x81C, 0xF2120303, 0x81C, 0xF1140303,
1014 0x81C, 0xF0160303, 0x81C, 0xEE180303, 0x81C, 0xED1A0303,
1015 0x81C, 0xEC1C0303, 0x81C, 0xEB1E0303, 0x81C, 0xEA200303,
1016 0x81C, 0xE9220303, 0x81C, 0xE8240303, 0x81C, 0xE7260303,
1017 0x81C, 0xE6280303, 0x81C, 0xE52A0303, 0x81C, 0xE42C0303,
1018 0x81C, 0xE32E0303, 0x81C, 0xE2300303, 0x81C, 0xE1320303,
1019 0x81C, 0xC6340303, 0x81C, 0xC5360303, 0x81C, 0xC4380303,
1020 0x81C, 0xC33A0303, 0x81C, 0xA63C0303, 0x81C, 0xA53E0303,
1021 0x81C, 0xA4400303, 0x81C, 0xA3420303, 0x81C, 0xA2440303,
1022 0x81C, 0xA1460303, 0x81C, 0x83480303, 0x81C, 0x824A0303,
1023 0x81C, 0x814C0303, 0x81C, 0x804E0303, 0x81C, 0x63500303,
1024 0x81C, 0x62520303, 0x81C, 0x61540303, 0x81C, 0x42560303,
1025 0x81C, 0x41580303, 0x81C, 0x405A0303, 0x81C, 0x225C0303,
1026 0x81C, 0x215E0303, 0x81C, 0x20600303, 0x81C, 0x04620303,
1027 0x81C, 0x03640303, 0x81C, 0x02660303, 0x81C, 0x01680303,
1028 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
1029 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
1030 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
1031 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90002100, 0x00000000,
1032 0x40000000, 0x00000000, 0x81C, 0xFB000303, 0x81C, 0xFA020303,
1033 0x81C, 0xF9040303, 0x81C, 0xF8060303, 0x81C, 0xF7080303,
1034 0x81C, 0xF60A0303, 0x81C, 0xF50C0303, 0x81C, 0xF40E0303,
1035 0x81C, 0xF3100303, 0x81C, 0xF2120303, 0x81C, 0xF1140303,
1036 0x81C, 0xF0160303, 0x81C, 0xEF180303, 0x81C, 0xEE1A0303,
1037 0x81C, 0xED1C0303, 0x81C, 0xEC1E0303, 0x81C, 0xEB200303,
1038 0x81C, 0xEA220303, 0x81C, 0xE9240303, 0x81C, 0xE8260303,
1039 0x81C, 0xE7280303, 0x81C, 0xE62A0303, 0x81C, 0xE52C0303,
1040 0x81C, 0xE42E0303, 0x81C, 0xE3300303, 0x81C, 0xE2320303,
1041 0x81C, 0xE1340303, 0x81C, 0xC5360303, 0x81C, 0xC4380303,
1042 0x81C, 0xC33A0303, 0x81C, 0xC23C0303, 0x81C, 0xC13E0303,
1043 0x81C, 0xA4400303, 0x81C, 0xA3420303, 0x81C, 0xA2440303,
1044 0x81C, 0xA1460303, 0x81C, 0x83480303, 0x81C, 0x824A0303,
1045 0x81C, 0x814C0303, 0x81C, 0x804E0303, 0x81C, 0x64500303,
1046 0x81C, 0x63520303, 0x81C, 0x62540303, 0x81C, 0x61560303,
1047 0x81C, 0x60580303, 0x81C, 0x235A0303, 0x81C, 0x225C0303,
1048 0x81C, 0x215E0303, 0x81C, 0x20600303, 0x81C, 0x04620303,
1049 0x81C, 0x03640303, 0x81C, 0x02660303, 0x81C, 0x01680303,
1050 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
1051 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
1052 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
1053 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90002000, 0x00000000,
1054 0x40000000, 0x00000000, 0x81C, 0xFC000303, 0x81C, 0xFB020303,
1055 0x81C, 0xFA040303, 0x81C, 0xF9060303, 0x81C, 0xF8080303,
1056 0x81C, 0xF70A0303, 0x81C, 0xF60C0303, 0x81C, 0xF50E0303,
1057 0x81C, 0xF4100303, 0x81C, 0xF3120303, 0x81C, 0xF2140303,
1058 0x81C, 0xF1160303, 0x81C, 0xF0180303, 0x81C, 0xEF1A0303,
1059 0x81C, 0xEE1C0303, 0x81C, 0xED1E0303, 0x81C, 0xEC200303,
1060 0x81C, 0xEB220303, 0x81C, 0xEA240303, 0x81C, 0xE9260303,
1061 0x81C, 0xE8280303, 0x81C, 0xE72A0303, 0x81C, 0xE62C0303,
1062 0x81C, 0xE52E0303, 0x81C, 0xE4300303, 0x81C, 0xE3320303,
1063 0x81C, 0xE2340303, 0x81C, 0xC6360303, 0x81C, 0xC5380303,
1064 0x81C, 0xC43A0303, 0x81C, 0xC33C0303, 0x81C, 0xA63E0303,
1065 0x81C, 0xA5400303, 0x81C, 0xA4420303, 0x81C, 0xA3440303,
1066 0x81C, 0xA2460303, 0x81C, 0x84480303, 0x81C, 0x834A0303,
1067 0x81C, 0x824C0303, 0x81C, 0x814E0303, 0x81C, 0x80500303,
1068 0x81C, 0x63520303, 0x81C, 0x62540303, 0x81C, 0x61560303,
1069 0x81C, 0x60580303, 0x81C, 0x225A0303, 0x81C, 0x055C0303,
1070 0x81C, 0x045E0303, 0x81C, 0x03600303, 0x81C, 0x02620303,
1071 0x81C, 0x01640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
1072 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
1073 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
1074 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
1075 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0xA0000000, 0x00000000,
1076 0x81C, 0xFC000303, 0x81C, 0xFB020303, 0x81C, 0xFA040303,
1077 0x81C, 0xF9060303, 0x81C, 0xF8080303, 0x81C, 0xF70A0303,
1078 0x81C, 0xF60C0303, 0x81C, 0xF50E0303, 0x81C, 0xF4100303,
1079 0x81C, 0xF3120303, 0x81C, 0xF2140303, 0x81C, 0xF1160303,
1080 0x81C, 0xF0180303, 0x81C, 0xEF1A0303, 0x81C, 0xEE1C0303,
1081 0x81C, 0xED1E0303, 0x81C, 0xEC200303, 0x81C, 0xEB220303,
1082 0x81C, 0xEA240303, 0x81C, 0xE9260303, 0x81C, 0xE8280303,
1083 0x81C, 0xE72A0303, 0x81C, 0xE62C0303, 0x81C, 0xE52E0303,
1084 0x81C, 0xE4300303, 0x81C, 0xE3320303, 0x81C, 0xE2340303,
1085 0x81C, 0xC6360303, 0x81C, 0xC5380303, 0x81C, 0xC43A0303,
1086 0x81C, 0xC33C0303, 0x81C, 0xA63E0303, 0x81C, 0xA5400303,
1087 0x81C, 0xA4420303, 0x81C, 0xA3440303, 0x81C, 0xA2460303,
1088 0x81C, 0x84480303, 0x81C, 0x834A0303, 0x81C, 0x824C0303,
1089 0x81C, 0x814E0303, 0x81C, 0x80500303, 0x81C, 0x63520303,
1090 0x81C, 0x62540303, 0x81C, 0x61560303, 0x81C, 0x60580303,
1091 0x81C, 0x235A0303, 0x81C, 0x225C0303, 0x81C, 0x215E0303,
1092 0x81C, 0x20600303, 0x81C, 0x03620303, 0x81C, 0x02640303,
1093 0x81C, 0x01660303, 0x81C, 0x00680303, 0x81C, 0x006A0303,
1094 0x81C, 0x006C0303, 0x81C, 0x006E0303, 0x81C, 0x00700303,
1095 0x81C, 0x00720303, 0x81C, 0x00740303, 0x81C, 0x00760303,
1096 0x81C, 0x00780303, 0x81C, 0x007A0303, 0x81C, 0x007C0303,
1097 0x81C, 0x007E0303, 0xB0000000, 0x00000000, 0x8000100f, 0x0a0a0a0a,
1098 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403,
1099 0x81C, 0xF4020403, 0x81C, 0xF3040403, 0x81C, 0xF2060403,
1100 0x81C, 0xF1080403, 0x81C, 0xF00A0403, 0x81C, 0xEF0C0403,
1101 0x81C, 0xEE0E0403, 0x81C, 0xED100403, 0x81C, 0xEC120403,
1102 0x81C, 0xEB140403, 0x81C, 0xEA160403, 0x81C, 0xE9180403,
1103 0x81C, 0xE81A0403, 0x81C, 0xE71C0403, 0x81C, 0xE61E0403,
1104 0x81C, 0xE5200403, 0x81C, 0xE4220403, 0x81C, 0xE3240403,
1105 0x81C, 0xE2260403, 0x81C, 0xE1280403, 0x81C, 0xE02A0403,
1106 0x81C, 0xC32C0403, 0x81C, 0xC22E0403, 0x81C, 0xC1300403,
1107 0x81C, 0xC0320403, 0x81C, 0xA4340403, 0x81C, 0xA3360403,
1108 0x81C, 0xA2380403, 0x81C, 0xA13A0403, 0x81C, 0xA03C0403,
1109 0x81C, 0x823E0403, 0x81C, 0x81400403, 0x81C, 0x80420403,
1110 0x81C, 0x64440403, 0x81C, 0x63460403, 0x81C, 0x62480403,
1111 0x81C, 0x614A0403, 0x81C, 0x604C0403, 0x81C, 0x454E0403,
1112 0x81C, 0x44500403, 0x81C, 0x43520403, 0x81C, 0x42540403,
1113 0x81C, 0x41560403, 0x81C, 0x40580403, 0x81C, 0x055A0403,
1114 0x81C, 0x045C0403, 0x81C, 0x035E0403, 0x81C, 0x02600403,
1115 0x81C, 0x01620403, 0x81C, 0x00640403, 0x81C, 0x00660403,
1116 0x81C, 0x00680403, 0x81C, 0x006A0403, 0x81C, 0x006C0403,
1117 0x81C, 0x006E0403, 0x81C, 0x00700403, 0x81C, 0x00720403,
1118 0x81C, 0x00740403, 0x81C, 0x00760403, 0x81C, 0x00780403,
1119 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
1120 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x81C, 0xFF000403,
1121 0x81C, 0xF5000403, 0x81C, 0xF4020403, 0x81C, 0xF3040403,
1122 0x81C, 0xF2060403, 0x81C, 0xF1080403, 0x81C, 0xF00A0403,
1123 0x81C, 0xEF0C0403, 0x81C, 0xEE0E0403, 0x81C, 0xED100403,
1124 0x81C, 0xEC120403, 0x81C, 0xEB140403, 0x81C, 0xEA160403,
1125 0x81C, 0xE9180403, 0x81C, 0xE81A0403, 0x81C, 0xE71C0403,
1126 0x81C, 0xE61E0403, 0x81C, 0xE5200403, 0x81C, 0xE4220403,
1127 0x81C, 0xE3240403, 0x81C, 0xE2260403, 0x81C, 0xE1280403,
1128 0x81C, 0xE02A0403, 0x81C, 0xC32C0403, 0x81C, 0xC22E0403,
1129 0x81C, 0xC1300403, 0x81C, 0xC0320403, 0x81C, 0xA4340403,
1130 0x81C, 0xA3360403, 0x81C, 0xA2380403, 0x81C, 0xA13A0403,
1131 0x81C, 0xA03C0403, 0x81C, 0x823E0403, 0x81C, 0x81400403,
1132 0x81C, 0x80420403, 0x81C, 0x64440403, 0x81C, 0x63460403,
1133 0x81C, 0x62480403, 0x81C, 0x614A0403, 0x81C, 0x604C0403,
1134 0x81C, 0x454E0403, 0x81C, 0x44500403, 0x81C, 0x43520403,
1135 0x81C, 0x42540403, 0x81C, 0x41560403, 0x81C, 0x40580403,
1136 0x81C, 0x055A0403, 0x81C, 0x045C0403, 0x81C, 0x035E0403,
1137 0x81C, 0x02600403, 0x81C, 0x01620403, 0x81C, 0x00640403,
1138 0x81C, 0x00660403, 0x81C, 0x00680403, 0x81C, 0x006A0403,
1139 0x81C, 0x006C0403, 0x81C, 0x006E0403, 0x81C, 0x00700403,
1140 0x81C, 0x00720403, 0x81C, 0x00740403, 0x81C, 0x00760403,
1141 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403,
1142 0x81C, 0x007E0403, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
1143 0x81C, 0xFF000403, 0x81C, 0xF5000403, 0x81C, 0xF4020403,
1144 0x81C, 0xF3040403, 0x81C, 0xF2060403, 0x81C, 0xF1080403,
1145 0x81C, 0xF00A0403, 0x81C, 0xEF0C0403, 0x81C, 0xEE0E0403,
1146 0x81C, 0xED100403, 0x81C, 0xEC120403, 0x81C, 0xEB140403,
1147 0x81C, 0xEA160403, 0x81C, 0xE9180403, 0x81C, 0xE81A0403,
1148 0x81C, 0xE71C0403, 0x81C, 0xE61E0403, 0x81C, 0xE5200403,
1149 0x81C, 0xE4220403, 0x81C, 0xE3240403, 0x81C, 0xE2260403,
1150 0x81C, 0xE1280403, 0x81C, 0xE02A0403, 0x81C, 0xC32C0403,
1151 0x81C, 0xC22E0403, 0x81C, 0xC1300403, 0x81C, 0xC0320403,
1152 0x81C, 0xA4340403, 0x81C, 0xA3360403, 0x81C, 0xA2380403,
1153 0x81C, 0xA13A0403, 0x81C, 0xA03C0403, 0x81C, 0x823E0403,
1154 0x81C, 0x81400403, 0x81C, 0x80420403, 0x81C, 0x64440403,
1155 0x81C, 0x63460403, 0x81C, 0x62480403, 0x81C, 0x614A0403,
1156 0x81C, 0x604C0403, 0x81C, 0x454E0403, 0x81C, 0x44500403,
1157 0x81C, 0x43520403, 0x81C, 0x42540403, 0x81C, 0x41560403,
1158 0x81C, 0x40580403, 0x81C, 0x055A0403, 0x81C, 0x045C0403,
1159 0x81C, 0x035E0403, 0x81C, 0x02600403, 0x81C, 0x01620403,
1160 0x81C, 0x00640403, 0x81C, 0x00660403, 0x81C, 0x00680403,
1161 0x81C, 0x006A0403, 0x81C, 0x006C0403, 0x81C, 0x006E0403,
1162 0x81C, 0x00700403, 0x81C, 0x00720403, 0x81C, 0x00740403,
1163 0x81C, 0x00760403, 0x81C, 0x00780403, 0x81C, 0x007A0403,
1164 0x81C, 0x007C0403, 0x81C, 0x007E0403, 0x9000200f, 0x00000000,
1165 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403,
1166 0x81C, 0xF4020403, 0x81C, 0xF3040403, 0x81C, 0xF2060403,
1167 0x81C, 0xF1080403, 0x81C, 0xF00A0403, 0x81C, 0xEF0C0403,
1168 0x81C, 0xEE0E0403, 0x81C, 0xED100403, 0x81C, 0xEC120403,
1169 0x81C, 0xEB140403, 0x81C, 0xEA160403, 0x81C, 0xE9180403,
1170 0x81C, 0xE81A0403, 0x81C, 0xE71C0403, 0x81C, 0xE61E0403,
1171 0x81C, 0xE5200403, 0x81C, 0xE4220403, 0x81C, 0xE3240403,
1172 0x81C, 0xE2260403, 0x81C, 0xE1280403, 0x81C, 0xE02A0403,
1173 0x81C, 0xC32C0403, 0x81C, 0xC22E0403, 0x81C, 0xC1300403,
1174 0x81C, 0xC0320403, 0x81C, 0xA4340403, 0x81C, 0xA3360403,
1175 0x81C, 0xA2380403, 0x81C, 0xA13A0403, 0x81C, 0xA03C0403,
1176 0x81C, 0x823E0403, 0x81C, 0x81400403, 0x81C, 0x80420403,
1177 0x81C, 0x64440403, 0x81C, 0x63460403, 0x81C, 0x62480403,
1178 0x81C, 0x614A0403, 0x81C, 0x604C0403, 0x81C, 0x454E0403,
1179 0x81C, 0x44500403, 0x81C, 0x43520403, 0x81C, 0x42540403,
1180 0x81C, 0x41560403, 0x81C, 0x40580403, 0x81C, 0x055A0403,
1181 0x81C, 0x045C0403, 0x81C, 0x035E0403, 0x81C, 0x02600403,
1182 0x81C, 0x01620403, 0x81C, 0x00640403, 0x81C, 0x00660403,
1183 0x81C, 0x00680403, 0x81C, 0x006A0403, 0x81C, 0x006C0403,
1184 0x81C, 0x006E0403, 0x81C, 0x00700403, 0x81C, 0x00720403,
1185 0x81C, 0x00740403, 0x81C, 0x00760403, 0x81C, 0x00780403,
1186 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
1187 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403,
1188 0x81C, 0xFF000403, 0x81C, 0xFF020403, 0x81C, 0xFE040403,
1189 0x81C, 0xFD060403, 0x81C, 0xFC080403, 0x81C, 0xFB0A0403,
1190 0x81C, 0xFA0C0403, 0x81C, 0xF90E0403, 0x81C, 0xF8100403,
1191 0x81C, 0xF7120403, 0x81C, 0xF6140403, 0x81C, 0xF5160403,
1192 0x81C, 0xF4180403, 0x81C, 0xF31A0403, 0x81C, 0xF21C0403,
1193 0x81C, 0xD51E0403, 0x81C, 0xD4200403, 0x81C, 0xD3220403,
1194 0x81C, 0xD2240403, 0x81C, 0xB6260403, 0x81C, 0xB5280403,
1195 0x81C, 0xB42A0403, 0x81C, 0xB32C0403, 0x81C, 0xB22E0403,
1196 0x81C, 0xB1300403, 0x81C, 0xB0320403, 0x81C, 0xAF340403,
1197 0x81C, 0xAE360403, 0x81C, 0xAD380403, 0x81C, 0xAC3A0403,
1198 0x81C, 0xAB3C0403, 0x81C, 0xAA3E0403, 0x81C, 0xA9400403,
1199 0x81C, 0xA8420403, 0x81C, 0xA7440403, 0x81C, 0xA6460403,
1200 0x81C, 0xA5480403, 0x81C, 0xA44A0403, 0x81C, 0xA34C0403,
1201 0x81C, 0x854E0403, 0x81C, 0x84500403, 0x81C, 0x83520403,
1202 0x81C, 0x82540403, 0x81C, 0x81560403, 0x81C, 0x80580403,
1203 0x81C, 0x485A0403, 0x81C, 0x475C0403, 0x81C, 0x465E0403,
1204 0x81C, 0x45600403, 0x81C, 0x44620403, 0x81C, 0x0A640403,
1205 0x81C, 0x09660403, 0x81C, 0x08680403, 0x81C, 0x076A0403,
1206 0x81C, 0x066C0403, 0x81C, 0x056E0403, 0x81C, 0x04700403,
1207 0x81C, 0x03720403, 0x81C, 0x02740403, 0x81C, 0x01760403,
1208 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403,
1209 0x81C, 0x007E0403, 0x90012100, 0x00000000, 0x40000000, 0x00000000,
1210 0x81C, 0xFF000403, 0x81C, 0xFF000403, 0x81C, 0xFF020403,
1211 0x81C, 0xFE040403, 0x81C, 0xFD060403, 0x81C, 0xFC080403,
1212 0x81C, 0xFB0A0403, 0x81C, 0xFA0C0403, 0x81C, 0xF90E0403,
1213 0x81C, 0xF8100403, 0x81C, 0xF7120403, 0x81C, 0xF6140403,
1214 0x81C, 0xF5160403, 0x81C, 0xF4180403, 0x81C, 0xF31A0403,
1215 0x81C, 0xF21C0403, 0x81C, 0xD51E0403, 0x81C, 0xD4200403,
1216 0x81C, 0xD3220403, 0x81C, 0xD2240403, 0x81C, 0xB6260403,
1217 0x81C, 0xB5280403, 0x81C, 0xB42A0403, 0x81C, 0xB32C0403,
1218 0x81C, 0xB22E0403, 0x81C, 0xB1300403, 0x81C, 0xB0320403,
1219 0x81C, 0xAF340403, 0x81C, 0xAE360403, 0x81C, 0xAD380403,
1220 0x81C, 0xAC3A0403, 0x81C, 0xAB3C0403, 0x81C, 0xAA3E0403,
1221 0x81C, 0xA9400403, 0x81C, 0xA8420403, 0x81C, 0xA7440403,
1222 0x81C, 0xA6460403, 0x81C, 0xA5480403, 0x81C, 0xA44A0403,
1223 0x81C, 0xA34C0403, 0x81C, 0x854E0403, 0x81C, 0x84500403,
1224 0x81C, 0x83520403, 0x81C, 0x82540403, 0x81C, 0x81560403,
1225 0x81C, 0x80580403, 0x81C, 0x485A0403, 0x81C, 0x475C0403,
1226 0x81C, 0x465E0403, 0x81C, 0x45600403, 0x81C, 0x44620403,
1227 0x81C, 0x0A640403, 0x81C, 0x09660403, 0x81C, 0x08680403,
1228 0x81C, 0x076A0403, 0x81C, 0x066C0403, 0x81C, 0x056E0403,
1229 0x81C, 0x04700403, 0x81C, 0x03720403, 0x81C, 0x02740403,
1230 0x81C, 0x01760403, 0x81C, 0x00780403, 0x81C, 0x007A0403,
1231 0x81C, 0x007C0403, 0x81C, 0x007E0403, 0x90001004, 0x00000000,
1232 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403,
1233 0x81C, 0xF4020403, 0x81C, 0xF3040403, 0x81C, 0xF2060403,
1234 0x81C, 0xF1080403, 0x81C, 0xF00A0403, 0x81C, 0xEF0C0403,
1235 0x81C, 0xEE0E0403, 0x81C, 0xED100403, 0x81C, 0xEC120403,
1236 0x81C, 0xEB140403, 0x81C, 0xEA160403, 0x81C, 0xE9180403,
1237 0x81C, 0xE81A0403, 0x81C, 0xE71C0403, 0x81C, 0xE61E0403,
1238 0x81C, 0xE5200403, 0x81C, 0xE4220403, 0x81C, 0xE3240403,
1239 0x81C, 0xE2260403, 0x81C, 0xE1280403, 0x81C, 0xE02A0403,
1240 0x81C, 0xC32C0403, 0x81C, 0xC22E0403, 0x81C, 0xC1300403,
1241 0x81C, 0xC0320403, 0x81C, 0xA4340403, 0x81C, 0xA3360403,
1242 0x81C, 0xA2380403, 0x81C, 0xA13A0403, 0x81C, 0xA03C0403,
1243 0x81C, 0x823E0403, 0x81C, 0x81400403, 0x81C, 0x80420403,
1244 0x81C, 0x64440403, 0x81C, 0x63460403, 0x81C, 0x62480403,
1245 0x81C, 0x614A0403, 0x81C, 0x604C0403, 0x81C, 0x454E0403,
1246 0x81C, 0x44500403, 0x81C, 0x43520403, 0x81C, 0x42540403,
1247 0x81C, 0x41560403, 0x81C, 0x40580403, 0x81C, 0x055A0403,
1248 0x81C, 0x045C0403, 0x81C, 0x035E0403, 0x81C, 0x02600403,
1249 0x81C, 0x01620403, 0x81C, 0x00640403, 0x81C, 0x00660403,
1250 0x81C, 0x00680403, 0x81C, 0x006A0403, 0x81C, 0x006C0403,
1251 0x81C, 0x006E0403, 0x81C, 0x00700403, 0x81C, 0x00720403,
1252 0x81C, 0x00740403, 0x81C, 0x00760403, 0x81C, 0x00780403,
1253 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
1254 0x90011000, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403,
1255 0x81C, 0xFF000403, 0x81C, 0xFF020403, 0x81C, 0xFE040403,
1256 0x81C, 0xFD060403, 0x81C, 0xFC080403, 0x81C, 0xFB0A0403,
1257 0x81C, 0xFA0C0403, 0x81C, 0xF90E0403, 0x81C, 0xF8100403,
1258 0x81C, 0xF7120403, 0x81C, 0xF6140403, 0x81C, 0xF5160403,
1259 0x81C, 0xF4180403, 0x81C, 0xF31A0403, 0x81C, 0xF21C0403,
1260 0x81C, 0xD51E0403, 0x81C, 0xD4200403, 0x81C, 0xD3220403,
1261 0x81C, 0xD2240403, 0x81C, 0xB6260403, 0x81C, 0xB5280403,
1262 0x81C, 0xB42A0403, 0x81C, 0xB32C0403, 0x81C, 0xB22E0403,
1263 0x81C, 0xB1300403, 0x81C, 0xB0320403, 0x81C, 0xAF340403,
1264 0x81C, 0xAE360403, 0x81C, 0xAD380403, 0x81C, 0xAC3A0403,
1265 0x81C, 0xAB3C0403, 0x81C, 0xAA3E0403, 0x81C, 0xA9400403,
1266 0x81C, 0xA8420403, 0x81C, 0xA7440403, 0x81C, 0xA6460403,
1267 0x81C, 0xA5480403, 0x81C, 0xA44A0403, 0x81C, 0xA34C0403,
1268 0x81C, 0x854E0403, 0x81C, 0x84500403, 0x81C, 0x83520403,
1269 0x81C, 0x82540403, 0x81C, 0x81560403, 0x81C, 0x80580403,
1270 0x81C, 0x485A0403, 0x81C, 0x475C0403, 0x81C, 0x465E0403,
1271 0x81C, 0x45600403, 0x81C, 0x44620403, 0x81C, 0x0A640403,
1272 0x81C, 0x09660403, 0x81C, 0x08680403, 0x81C, 0x076A0403,
1273 0x81C, 0x066C0403, 0x81C, 0x056E0403, 0x81C, 0x04700403,
1274 0x81C, 0x03720403, 0x81C, 0x02740403, 0x81C, 0x01760403,
1275 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403,
1276 0x81C, 0x007E0403, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
1277 0x81C, 0xFF000403, 0x81C, 0xFF000403, 0x81C, 0xFF020403,
1278 0x81C, 0xFE040403, 0x81C, 0xFD060403, 0x81C, 0xFC080403,
1279 0x81C, 0xFB0A0403, 0x81C, 0xFA0C0403, 0x81C, 0xF90E0403,
1280 0x81C, 0xF8100403, 0x81C, 0xF7120403, 0x81C, 0xF6140403,
1281 0x81C, 0xF5160403, 0x81C, 0xF4180403, 0x81C, 0xF31A0403,
1282 0x81C, 0xF21C0403, 0x81C, 0xD51E0403, 0x81C, 0xD4200403,
1283 0x81C, 0xD3220403, 0x81C, 0xD2240403, 0x81C, 0xB6260403,
1284 0x81C, 0xB5280403, 0x81C, 0xB42A0403, 0x81C, 0xB32C0403,
1285 0x81C, 0xB22E0403, 0x81C, 0xB1300403, 0x81C, 0xB0320403,
1286 0x81C, 0xAF340403, 0x81C, 0xAE360403, 0x81C, 0xAD380403,
1287 0x81C, 0xAC3A0403, 0x81C, 0xAB3C0403, 0x81C, 0xAA3E0403,
1288 0x81C, 0xA9400403, 0x81C, 0xA8420403, 0x81C, 0xA7440403,
1289 0x81C, 0xA6460403, 0x81C, 0xA5480403, 0x81C, 0xA44A0403,
1290 0x81C, 0xA34C0403, 0x81C, 0x854E0403, 0x81C, 0x84500403,
1291 0x81C, 0x83520403, 0x81C, 0x82540403, 0x81C, 0x81560403,
1292 0x81C, 0x80580403, 0x81C, 0x485A0403, 0x81C, 0x475C0403,
1293 0x81C, 0x465E0403, 0x81C, 0x45600403, 0x81C, 0x44620403,
1294 0x81C, 0x0A640403, 0x81C, 0x09660403, 0x81C, 0x08680403,
1295 0x81C, 0x076A0403, 0x81C, 0x066C0403, 0x81C, 0x056E0403,
1296 0x81C, 0x04700403, 0x81C, 0x03720403, 0x81C, 0x02740403,
1297 0x81C, 0x01760403, 0x81C, 0x00780403, 0x81C, 0x007A0403,
1298 0x81C, 0x007C0403, 0x81C, 0x007E0403, 0x90002000, 0x00000000,
1299 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xFF000403,
1300 0x81C, 0xFF020403, 0x81C, 0xFE040403, 0x81C, 0xFD060403,
1301 0x81C, 0xFC080403, 0x81C, 0xFB0A0403, 0x81C, 0xFA0C0403,
1302 0x81C, 0xF90E0403, 0x81C, 0xF8100403, 0x81C, 0xF7120403,
1303 0x81C, 0xF6140403, 0x81C, 0xF5160403, 0x81C, 0xF4180403,
1304 0x81C, 0xF31A0403, 0x81C, 0xF21C0403, 0x81C, 0xD51E0403,
1305 0x81C, 0xD4200403, 0x81C, 0xD3220403, 0x81C, 0xD2240403,
1306 0x81C, 0xB6260403, 0x81C, 0xB5280403, 0x81C, 0xB42A0403,
1307 0x81C, 0xB32C0403, 0x81C, 0xB22E0403, 0x81C, 0xB1300403,
1308 0x81C, 0xB0320403, 0x81C, 0xAF340403, 0x81C, 0xAE360403,
1309 0x81C, 0xAD380403, 0x81C, 0xAC3A0403, 0x81C, 0xAB3C0403,
1310 0x81C, 0xAA3E0403, 0x81C, 0xA9400403, 0x81C, 0xA8420403,
1311 0x81C, 0xA7440403, 0x81C, 0xA6460403, 0x81C, 0xA5480403,
1312 0x81C, 0xA44A0403, 0x81C, 0xA34C0403, 0x81C, 0x854E0403,
1313 0x81C, 0x84500403, 0x81C, 0x83520403, 0x81C, 0x82540403,
1314 0x81C, 0x81560403, 0x81C, 0x80580403, 0x81C, 0x485A0403,
1315 0x81C, 0x475C0403, 0x81C, 0x465E0403, 0x81C, 0x45600403,
1316 0x81C, 0x44620403, 0x81C, 0x0A640403, 0x81C, 0x09660403,
1317 0x81C, 0x08680403, 0x81C, 0x076A0403, 0x81C, 0x066C0403,
1318 0x81C, 0x056E0403, 0x81C, 0x04700403, 0x81C, 0x03720403,
1319 0x81C, 0x02740403, 0x81C, 0x01760403, 0x81C, 0x00780403,
1320 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
1321 0xA0000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xFF000403,
1322 0x81C, 0xFF020403, 0x81C, 0xFE040403, 0x81C, 0xFD060403,
1323 0x81C, 0xFC080403, 0x81C, 0xFB0A0403, 0x81C, 0xFA0C0403,
1324 0x81C, 0xF90E0403, 0x81C, 0xF8100403, 0x81C, 0xF7120403,
1325 0x81C, 0xF6140403, 0x81C, 0xF5160403, 0x81C, 0xF4180403,
1326 0x81C, 0xF31A0403, 0x81C, 0xF21C0403, 0x81C, 0xD51E0403,
1327 0x81C, 0xD4200403, 0x81C, 0xD3220403, 0x81C, 0xD2240403,
1328 0x81C, 0xB6260403, 0x81C, 0xB5280403, 0x81C, 0xB42A0403,
1329 0x81C, 0xB32C0403, 0x81C, 0xB22E0403, 0x81C, 0xB1300403,
1330 0x81C, 0xB0320403, 0x81C, 0xAF340403, 0x81C, 0xAE360403,
1331 0x81C, 0xAD380403, 0x81C, 0xAC3A0403, 0x81C, 0xAB3C0403,
1332 0x81C, 0xAA3E0403, 0x81C, 0xA9400403, 0x81C, 0xA8420403,
1333 0x81C, 0xA7440403, 0x81C, 0xA6460403, 0x81C, 0xA5480403,
1334 0x81C, 0xA44A0403, 0x81C, 0xA34C0403, 0x81C, 0x854E0403,
1335 0x81C, 0x84500403, 0x81C, 0x83520403, 0x81C, 0x82540403,
1336 0x81C, 0x81560403, 0x81C, 0x80580403, 0x81C, 0x485A0403,
1337 0x81C, 0x475C0403, 0x81C, 0x465E0403, 0x81C, 0x45600403,
1338 0x81C, 0x44620403, 0x81C, 0x0A640403, 0x81C, 0x09660403,
1339 0x81C, 0x08680403, 0x81C, 0x076A0403, 0x81C, 0x066C0403,
1340 0x81C, 0x056E0403, 0x81C, 0x04700403, 0x81C, 0x03720403,
1341 0x81C, 0x02740403, 0x81C, 0x01760403, 0x81C, 0x00780403,
1342 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
1343 0xB0000000, 0x00000000, 0xC50, 0x00000022, 0xC50, 0x00000020,
1344 0xE50, 0x00000022, 0xE50, 0x00000020,
1345
1346};
1347
1348void odm_read_and_config_mp_8822b_agc_tab(struct phy_dm_struct *dm)
1349{
1350 u32 i = 0;
1351 u8 c_cond;
1352 bool is_matched = true, is_skipped = false;
1353 u32 array_len = sizeof(array_mp_8822b_agc_tab) / sizeof(u32);
1354 u32 *array = array_mp_8822b_agc_tab;
1355
1356 u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
1357
1358 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1359 "===> %s\n", __func__);
1360
1361 for (; (i + 1) < array_len; i = i + 2) {
1362 v1 = array[i];
1363 v2 = array[i + 1];
1364
1365 if (v1 & BIT(31)) { /* positive condition*/
1366 c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
1367 if (c_cond == COND_ENDIF) { /*end*/
1368 is_matched = true;
1369 is_skipped = false;
1370 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
1371 } else if (c_cond == COND_ELSE) { /*else*/
1372 is_matched = is_skipped ? false : true;
1373 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
1374 } else { /*if , else if*/
1375 pre_v1 = v1;
1376 pre_v2 = v2;
1377 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1378 "IF or ELSE IF\n");
1379 }
1380 } else if (v1 & BIT(30)) { /*negative condition*/
1381 if (is_skipped) {
1382 is_matched = false;
1383 continue;
1384 }
1385
1386 if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
1387 is_matched = true;
1388 is_skipped = true;
1389 } else {
1390 is_matched = false;
1391 is_skipped = false;
1392 }
1393 } else if (is_matched) {
1394 odm_config_bb_agc_8822b(dm, v1, MASKDWORD, v2);
1395 }
1396 }
1397}
1398
1399u32 odm_get_version_mp_8822b_agc_tab(void) { return 67; }
1400
1401/******************************************************************************
1402 * phy_reg.TXT
1403 ******************************************************************************/
1404
1405static u32 array_mp_8822b_phy_reg[] = {
1406 0x800, 0x9020D010, 0x804, 0x800181A0, 0x808, 0x0E028233,
1407 0x80C, 0x10000013, 0x810, 0x21101263, 0x814, 0x020C3D10,
1408 0x818, 0x84A10385, 0x81C, 0x1E1E081F, 0x820, 0x0001AAAA,
1409 0x824, 0x00030FE0, 0x828, 0x0000CCCC, 0x82C, 0x75CB7010,
1410 0x830, 0x79A0EA2A, 0x834, 0x072E6986, 0x838, 0x87766441,
1411 0x83C, 0x9194B2B6, 0x840, 0x171740E0, 0x844, 0x4D3D7CDB,
1412 0x848, 0x4AD0408B, 0x84C, 0x6AFBF7A5, 0x850, 0x28A74706,
1413 0x854, 0x0001520C, 0x858, 0x4060C000, 0x85C, 0x74010160,
1414 0x860, 0x68A7C321, 0x864, 0x79F27432, 0x868, 0x8CA7A314,
1415 0x86C, 0x778C2878, 0x870, 0x77777777, 0x874, 0x27612C2E,
1416 0x878, 0xC0003152, 0x87C, 0x5C8FC000, 0x880, 0x00000000,
1417 0x884, 0x00000000, 0x888, 0x00000000, 0x88C, 0x00000000,
1418 0x890, 0x00000000, 0x894, 0x00000000, 0x898, 0x00000000,
1419 0x89C, 0x00000000, 0x8A0, 0x00000013, 0x8A4, 0x7F7F7F7F,
1420 0x8A8, 0x2202033E, 0x8AC, 0xF00F000A, 0x8B0, 0x00000600,
1421 0x8B4, 0x000FC080, 0x8B8, 0xEC0057F7, 0x8BC, 0xACB520A3,
1422 0x8C0, 0xFFE04020, 0x8C4, 0x47C00000, 0x8C8, 0x000251A5,
1423 0x8CC, 0x08108000, 0x8D0, 0x0000B800, 0x8D4, 0x860308A0,
1424 0x8D8, 0x21095612, 0x8DC, 0x00000000, 0x8E0, 0x32D16777,
1425 0x8E4, 0x4C098935, 0x8E8, 0xFFFFC42C, 0x8EC, 0x99999999,
1426 0x8F0, 0x00009999, 0x8F4, 0x00D80FA1, 0x8F8, 0x40000080,
1427 0x8FC, 0x00000130, 0x900, 0x00800000, 0x904, 0x00000000,
1428 0x908, 0x00000000, 0x90C, 0xD3000000, 0x910, 0x0000FC00,
1429 0x914, 0xC6380000, 0x918, 0x1C1028C0, 0x91C, 0x64B11A1C,
1430 0x920, 0xE0767233, 0x924, 0x855A2500, 0x928, 0x4AB0E4E4,
1431 0x92C, 0xFFFEB200, 0x930, 0xFFFFFFFE, 0x934, 0x001FFFFF,
1432 0x938, 0x00008480, 0x93C, 0xE41C0642, 0x940, 0x0E470430,
1433 0x944, 0x00000000, 0x948, 0xAC000000, 0x94C, 0x10000083,
1434 0x950, 0x32010080, 0x954, 0x84510080, 0x958, 0x00000001,
1435 0x95C, 0x04248000, 0x960, 0x00000000, 0x964, 0x00000000,
1436 0x968, 0x00000000, 0x96C, 0x00000000, 0x970, 0x00001FFF,
1437 0x974, 0x44000FFF, 0x978, 0x00000000, 0x97C, 0x00000000,
1438 0x980, 0x00000000, 0x984, 0x00000000, 0x988, 0x00000000,
1439 0x98C, 0x23440000, 0x990, 0x27100000, 0x994, 0xFFFF0100,
1440 0x998, 0xFFFFFF5C, 0x99C, 0xFFFFFFFF, 0x9A0, 0x000000FF,
1441 0x9A4, 0x80000088, 0x9A8, 0x0C2F0000, 0x9AC, 0x01560000,
1442 0x9B0, 0x70000000, 0x9B4, 0x00000000, 0x9B8, 0x00000000,
1443 0x9BC, 0x00000000, 0x9C0, 0x00000000, 0x9C4, 0x00000000,
1444 0x9C8, 0x00000000, 0x9CC, 0x00000000, 0x9D0, 0x00000000,
1445 0x9D4, 0x00000000, 0x9D8, 0x00000000, 0x9DC, 0x00000000,
1446 0x9E0, 0x00000000, 0x9E4, 0x02000402, 0x9E8, 0x000022D4,
1447 0x9EC, 0x00000000, 0x9F0, 0x00010080, 0x9F4, 0x00000000,
1448 0x9F8, 0x00000000, 0x9FC, 0xEFFFF7F7, 0xA00, 0x00D047C8,
1449 0xA04, 0x81FF800C, 0xA08, 0x8C838300, 0xA0C, 0x2E20100F,
1450 0xA10, 0x9500BB78, 0xA14, 0x1114D028, 0xA18, 0x00881117,
1451 0xA1C, 0x89140F00, 0xA20, 0x84880000, 0xA24, 0x384F6577,
1452 0xA28, 0x00001525, 0xA2C, 0x00920000, 0xA70, 0x101FFF00,
1453 0xA74, 0x00000148, 0xA78, 0x00000900, 0xA7C, 0x225B0606,
1454 0xA80, 0x218675B2, 0xA84, 0x80208C00, 0xA88, 0x040C0000,
1455 0xA8C, 0x12345678, 0xA90, 0xABCDEF00, 0xA94, 0x001B1B89,
1456 0xA98, 0x030A0000, 0xA9C, 0x00060000, 0xAA0, 0x00000000,
1457 0xAA4, 0x0004000F, 0xAA8, 0x00000200, 0xB00, 0xE1000440,
1458 0xB04, 0x00800000, 0xB08, 0xFF02030B, 0xB0C, 0x01EAA406,
1459 0xB10, 0x00030690, 0xB14, 0x006000FA, 0xB18, 0x00000002,
1460 0xB1C, 0x00000002, 0xB20, 0x4B00001F, 0xB24, 0x4E8E3E40,
1461 0xB28, 0x03020100, 0xB2C, 0x07060504, 0xB30, 0x0B0A0908,
1462 0xB34, 0x0F0E0D0C, 0xB38, 0x13121110, 0xB3C, 0x0000003A,
1463 0xB40, 0x00000000, 0xB44, 0x80000000, 0xB48, 0x3F0000FA,
1464 0xB4C, 0x88C80020, 0xB50, 0x00000000, 0xB54, 0x00004241,
1465 0xB58, 0xE0008208, 0xB5C, 0x41EFFFF9, 0xB60, 0x00000000,
1466 0xB64, 0x00200063, 0xB68, 0x0000003A, 0xB6C, 0x00000102,
1467 0xB70, 0x4E6D1870, 0xB74, 0x03020100, 0xB78, 0x07060504,
1468 0xB7C, 0x0B0A0908, 0xB80, 0x0F0E0D0C, 0xB84, 0x13121110,
1469 0xB88, 0x00000000, 0xB8C, 0x00000000, 0xC00, 0x00000007,
1470 0xC04, 0x00000020, 0xC08, 0x60403231, 0xC0C, 0x00012345,
1471 0xC10, 0x00000100, 0xC14, 0x01000000, 0xC18, 0x00000000,
1472 0xC1C, 0x40040053, 0xC20, 0x40020103, 0xC24, 0x00000000,
1473 0xC28, 0x00000000, 0xC2C, 0x00000000, 0xC30, 0x00000000,
1474 0xC34, 0x00000000, 0xC38, 0x00000000, 0xC3C, 0x00000000,
1475 0xC40, 0x00000000, 0xC44, 0x00000000, 0xC48, 0x00000000,
1476 0xC4C, 0x00000000, 0xC50, 0x00000020, 0xC54, 0x00000000,
1477 0xC58, 0xD8020402, 0xC5C, 0xDE000120, 0xC68, 0x5979993F,
1478 0xC6C, 0x0000122A, 0xC70, 0x99795979, 0xC74, 0x99795979,
1479 0xC78, 0x99799979, 0xC7C, 0x99791979, 0xC80, 0x19791979,
1480 0xC84, 0x19791979, 0xC88, 0x00000000, 0xC8C, 0x07000000,
1481 0xC94, 0x01000100, 0xC98, 0x201C8000, 0xC9C, 0x00000000,
1482 0xCA0, 0x0000A555, 0xCA4, 0x08040201, 0xCA8, 0x80402010,
1483 0xCAC, 0x00000000, 0xCB0, 0x77777777, 0xCB4, 0x00007777,
1484 0xCB8, 0x00000000, 0xCBC, 0x00000000, 0xCC0, 0x00000000,
1485 0xCC4, 0x00000000, 0xCC8, 0x00000000, 0xCCC, 0x00000000,
1486 0xCD0, 0x00000000, 0xCD4, 0x00000000, 0xCD8, 0x00000000,
1487 0xCDC, 0x00000000, 0xCE0, 0x00000000, 0xCE4, 0x00000000,
1488 0xCE8, 0x00000000, 0xCEC, 0x00000000, 0xE00, 0x00000007,
1489 0xE04, 0x00000020, 0xE08, 0x60403231, 0xE0C, 0x00012345,
1490 0xE10, 0x00000100, 0xE14, 0x01000000, 0xE18, 0x00000000,
1491 0xE1C, 0x40040053, 0xE20, 0x40020103, 0xE24, 0x00000000,
1492 0xE28, 0x00000000, 0xE2C, 0x00000000, 0xE30, 0x00000000,
1493 0xE34, 0x00000000, 0xE38, 0x00000000, 0xE3C, 0x00000000,
1494 0xE40, 0x00000000, 0xE44, 0x00000000, 0xE48, 0x00000000,
1495 0xE4C, 0x00000000, 0xE50, 0x00000020, 0xE54, 0x00000000,
1496 0xE58, 0xD8020402, 0xE5C, 0xDE000120, 0xE68, 0x5979993F,
1497 0xE6C, 0x0000122A, 0xE70, 0x99795979, 0xE74, 0x99795979,
1498 0xE78, 0x99799979, 0xE7C, 0x99791979, 0xE80, 0x19791979,
1499 0xE84, 0x19791979, 0xE88, 0x00000000, 0xE8C, 0x07000000,
1500 0xE94, 0x01000100, 0xE98, 0x201C8000, 0xE9C, 0x00000000,
1501 0xEA0, 0x0000A555, 0xEA4, 0x08040201, 0xEA8, 0x80402010,
1502 0xEAC, 0x00000000, 0xEB0, 0x77777777, 0xEB4, 0x00007777,
1503 0xEB8, 0x00000000, 0xEBC, 0x00000000, 0xEC0, 0x00000000,
1504 0xEC4, 0x00000000, 0xEC8, 0x00000000, 0xECC, 0x00000000,
1505 0xED0, 0x00000000, 0xED4, 0x00000000, 0xED8, 0x00000000,
1506 0xEDC, 0x00000000, 0xEE0, 0x00000000, 0xEE4, 0x00000000,
1507 0xEE8, 0x00000000, 0xEEC, 0x00000000, 0x1900, 0x00000000,
1508 0x1904, 0x00238000, 0x1908, 0x00000000, 0x190C, 0x00000000,
1509 0x1910, 0x00000000, 0x1914, 0x00000000, 0x1918, 0x00000000,
1510 0x191C, 0x00000000, 0x1920, 0x00000000, 0x1924, 0x00000000,
1511 0x1928, 0x00000000, 0x192C, 0x00000000, 0x1930, 0x00000000,
1512 0x1934, 0x00000000, 0x1938, 0x00000000, 0x193C, 0x00000000,
1513 0x1940, 0x00000000, 0x1944, 0x00000000, 0x1948, 0x00000000,
1514 0x194C, 0x00000000, 0x1950, 0x00000000, 0x1954, 0x00000000,
1515 0x1958, 0x00000000, 0x195C, 0x00000000, 0x1960, 0x00000000,
1516 0x1964, 0x00000000, 0x1968, 0x00000000, 0x196C, 0x00000000,
1517 0x1970, 0x00000000, 0x1974, 0x00000000, 0x1978, 0x00000000,
1518 0x197C, 0x00000000, 0x1980, 0x00000000, 0x1984, 0x03000000,
1519 0x1988, 0x21401E88, 0x198C, 0x00004000, 0x1990, 0x00000000,
1520 0x1994, 0x00000000, 0x1998, 0x00000053, 0x199C, 0x00000000,
1521 0x19A0, 0x00000000, 0x19A4, 0x00000000, 0x19A8, 0x00000000,
1522 0x19AC, 0x0E47E47F, 0x19B0, 0x00000000, 0x19B4, 0x0E47E47F,
1523 0x19B8, 0x00000000, 0x19BC, 0x00000000, 0x19C0, 0x00000000,
1524 0x19C4, 0x00000000, 0x19C8, 0x00000000, 0x19CC, 0x00000000,
1525 0x19D0, 0x00000000, 0x19D4, 0xAAAAAAAA, 0x19D8, 0x00000AAA,
1526 0x19DC, 0x133E0F37, 0x19E0, 0x00000000, 0x19E4, 0x00000000,
1527 0x19E8, 0x00000000, 0x19EC, 0x00000000, 0x19F0, 0x00000000,
1528 0x19F4, 0x00000000, 0x19F8, 0x01A00000, 0x19FC, 0x00000000,
1529 0x1C00, 0x00000100, 0x1C04, 0x01000000, 0x1C08, 0x00000100,
1530 0x1C0C, 0x01000000, 0x1C10, 0x00000100, 0x1C14, 0x01000000,
1531 0x1C18, 0x00000100, 0x1C1C, 0x01000000, 0x1C20, 0x00000100,
1532 0x1C24, 0x01000000, 0x1C28, 0x00000100, 0x1C2C, 0x01000000,
1533 0x1C30, 0x00000100, 0x1C34, 0x01000000, 0x1C38, 0x00000000,
1534 0x1C3C, 0x00000000, 0x1C40, 0x000C0100, 0x1C44, 0x000000F3,
1535 0x1C48, 0x1A8249A8, 0x1C4C, 0x1461C826, 0x1C50, 0x0001469E,
1536 0x1C54, 0x58D158D1, 0x1C58, 0x04490088, 0x1C5C, 0x04004400,
1537 0x1C60, 0x00000000, 0x1C64, 0x04004400, 0x1C68, 0x00000100,
1538 0x1C6C, 0x01000000, 0x1C70, 0x00000100, 0x1C74, 0x01000000,
1539 0x1C78, 0x00000000, 0x1C7C, 0x00000010, 0x1C80, 0x5FFF5FFF,
1540 0x1C84, 0x5FFF5FFF, 0x1C88, 0x5FFF5FFF, 0x1C8C, 0x5FFF5FFF,
1541 0x1C90, 0x5FFF5FFF, 0x1C94, 0x5FFF5FFF, 0x1C98, 0x5FFF5FFF,
1542 0x1C9C, 0x5FFF5FFF, 0x1CA0, 0x00000100, 0x1CA4, 0x01000000,
1543 0x1CA8, 0x00000100, 0x1CAC, 0x5FFF5FFF, 0x1CB0, 0x00000100,
1544 0x1CB4, 0x01000000, 0x1CB8, 0x00000000, 0x1CBC, 0x00000000,
1545 0x1CC0, 0x00000100, 0x1CC4, 0x01000000, 0x1CC8, 0x00000100,
1546 0x1CCC, 0x01000000, 0x1CD0, 0x00000100, 0x1CD4, 0x01000000,
1547 0x1CD8, 0x00000100, 0x1CDC, 0x01000000, 0x1CE0, 0x00000100,
1548 0x1CE4, 0x01000000, 0x1CE8, 0x00000100, 0x1CEC, 0x01000000,
1549 0x1CF0, 0x00000100, 0x1CF4, 0x01000000, 0x1CF8, 0x00000000,
1550 0x1CFC, 0x00000000, 0xC60, 0x70038040, 0xC60, 0x70038040,
1551 0xC60, 0x70146040, 0xC60, 0x70246040, 0xC60, 0x70346040,
1552 0xC60, 0x70446040, 0xC60, 0x70532040, 0xC60, 0x70646040,
1553 0xC60, 0x70738040, 0xC60, 0x70838040, 0xC60, 0x70938040,
1554 0xC60, 0x70A38040, 0xC60, 0x70B36040, 0xC60, 0x70C06040,
1555 0xC60, 0x70D06040, 0xC60, 0x70E76040, 0xC60, 0x70F06040,
1556 0xE60, 0x70038040, 0xE60, 0x70038040, 0xE60, 0x70146040,
1557 0xE60, 0x70246040, 0xE60, 0x70346040, 0xE60, 0x70446040,
1558 0xE60, 0x70532040, 0xE60, 0x70646040, 0xE60, 0x70738040,
1559 0xE60, 0x70838040, 0xE60, 0x70938040, 0xE60, 0x70A38040,
1560 0xE60, 0x70B36040, 0xE60, 0x70C06040, 0xE60, 0x70D06040,
1561 0xE60, 0x70E76040, 0xE60, 0x70F06040, 0xC64, 0x00800000,
1562 0xC64, 0x08800001, 0xC64, 0x00800002, 0xC64, 0x00800003,
1563 0xC64, 0x00800004, 0xC64, 0x00800005, 0xC64, 0x00800006,
1564 0xC64, 0x08800007, 0xC64, 0x00004000, 0xE64, 0x00800000,
1565 0xE64, 0x08800001, 0xE64, 0x00800002, 0xE64, 0x00800003,
1566 0xE64, 0x00800004, 0xE64, 0x00800005, 0xE64, 0x00800006,
1567 0xE64, 0x08800007, 0xE64, 0x00004000, 0x1B00, 0xF8000008,
1568 0x1B00, 0xF80A7008, 0x1B00, 0xF8015008, 0x1B00, 0xF8000008,
1569 0x1B04, 0xE24629D2, 0x1B08, 0x00000080, 0x1B0C, 0x00000000,
1570 0x1B10, 0x00010C00, 0x1B14, 0x00000000, 0x1B18, 0x00292903,
1571 0x1B1C, 0xA2193C32, 0x1B20, 0x01840008, 0x1B24, 0x01860008,
1572 0x1B28, 0x80060300, 0x1B2C, 0x00000003, 0x1B30, 0x20000000,
1573 0x1B34, 0x00000800, 0x1B3C, 0x20000000, 0x1BC0, 0x01000000,
1574 0x1BCC, 0x00000000, 0x1B00, 0xF800000A, 0x1B1C, 0xA2193C32,
1575 0x1B20, 0x01840008, 0x1B24, 0x01860008, 0x1B28, 0x80060300,
1576 0x1B2C, 0x00000003, 0x1B30, 0x20000000, 0x1B34, 0x00000800,
1577 0x1B3C, 0x20000000, 0x1BC0, 0x01000000, 0x1BCC, 0x00000000,
1578 0x1B00, 0xF8000000, 0x1B80, 0x00000007, 0x1B80, 0x090A0005,
1579 0x1B80, 0x090A0007, 0x1B80, 0x0FFE0015, 0x1B80, 0x0FFE0017,
1580 0x1B80, 0x00220025, 0x1B80, 0x00220027, 0x1B80, 0x00040035,
1581 0x1B80, 0x00040037, 0x1B80, 0x05C00045, 0x1B80, 0x05C00047,
1582 0x1B80, 0x00070055, 0x1B80, 0x00070057, 0x1B80, 0x64000065,
1583 0x1B80, 0x64000067, 0x1B80, 0x00020075, 0x1B80, 0x00020077,
1584 0x1B80, 0x00080085, 0x1B80, 0x00080087, 0x1B80, 0x80000095,
1585 0x1B80, 0x80000097, 0x1B80, 0x090800A5, 0x1B80, 0x090800A7,
1586 0x1B80, 0x0F0200B5, 0x1B80, 0x0F0200B7, 0x1B80, 0x002200C5,
1587 0x1B80, 0x002200C7, 0x1B80, 0x000400D5, 0x1B80, 0x000400D7,
1588 0x1B80, 0x05C000E5, 0x1B80, 0x05C000E7, 0x1B80, 0x000700F5,
1589 0x1B80, 0x000700F7, 0x1B80, 0x64020105, 0x1B80, 0x64020107,
1590 0x1B80, 0x00020115, 0x1B80, 0x00020117, 0x1B80, 0x00040125,
1591 0x1B80, 0x00040127, 0x1B80, 0x4A000135, 0x1B80, 0x4A000137,
1592 0x1B80, 0x4B040145, 0x1B80, 0x4B040147, 0x1B80, 0x85030155,
1593 0x1B80, 0x85030157, 0x1B80, 0x40090165, 0x1B80, 0x40090167,
1594 0x1B80, 0xE0210175, 0x1B80, 0xE0210177, 0x1B80, 0x4B050185,
1595 0x1B80, 0x4B050187, 0x1B80, 0x86030195, 0x1B80, 0x86030197,
1596 0x1B80, 0x400B01A5, 0x1B80, 0x400B01A7, 0x1B80, 0xE02101B5,
1597 0x1B80, 0xE02101B7, 0x1B80, 0x4B0001C5, 0x1B80, 0x4B0001C7,
1598 0x1B80, 0x000701D5, 0x1B80, 0x000701D7, 0x1B80, 0x4C0001E5,
1599 0x1B80, 0x4C0001E7, 0x1B80, 0x000401F5, 0x1B80, 0x000401F7,
1600 0x1B80, 0x30000205, 0x1B80, 0x30000207, 0x1B80, 0xFE000215,
1601 0x1B80, 0xFE000217, 0x1B80, 0xFF000225, 0x1B80, 0xFF000227,
1602 0x1B80, 0xE1750235, 0x1B80, 0xE1750237, 0x1B80, 0xF00D0245,
1603 0x1B80, 0xF00D0247, 0x1B80, 0xF10D0255, 0x1B80, 0xF10D0257,
1604 0x1B80, 0xF20D0265, 0x1B80, 0xF20D0267, 0x1B80, 0xF30D0275,
1605 0x1B80, 0xF30D0277, 0x1B80, 0xF40D0285, 0x1B80, 0xF40D0287,
1606 0x1B80, 0xF50D0295, 0x1B80, 0xF50D0297, 0x1B80, 0xF60D02A5,
1607 0x1B80, 0xF60D02A7, 0x1B80, 0xF70D02B5, 0x1B80, 0xF70D02B7,
1608 0x1B80, 0xF80D02C5, 0x1B80, 0xF80D02C7, 0x1B80, 0xF90D02D5,
1609 0x1B80, 0xF90D02D7, 0x1B80, 0xFA0D02E5, 0x1B80, 0xFA0D02E7,
1610 0x1B80, 0xFB0D02F5, 0x1B80, 0xFB0D02F7, 0x1B80, 0x00010305,
1611 0x1B80, 0x00010307, 0x1B80, 0x303D0315, 0x1B80, 0x303D0317,
1612 0x1B80, 0x30550325, 0x1B80, 0x30550327, 0x1B80, 0x30A00335,
1613 0x1B80, 0x30A00337, 0x1B80, 0x30A30345, 0x1B80, 0x30A30347,
1614 0x1B80, 0x30570355, 0x1B80, 0x30570357, 0x1B80, 0x30620365,
1615 0x1B80, 0x30620367, 0x1B80, 0x306D0375, 0x1B80, 0x306D0377,
1616 0x1B80, 0x30AD0385, 0x1B80, 0x30AD0387, 0x1B80, 0x30A70395,
1617 0x1B80, 0x30A70397, 0x1B80, 0x30BB03A5, 0x1B80, 0x30BB03A7,
1618 0x1B80, 0x30C603B5, 0x1B80, 0x30C603B7, 0x1B80, 0x30D103C5,
1619 0x1B80, 0x30D103C7, 0x1B80, 0xE11403D5, 0x1B80, 0xE11403D7,
1620 0x1B80, 0x4D0403E5, 0x1B80, 0x4D0403E7, 0x1B80, 0x208003F5,
1621 0x1B80, 0x208003F7, 0x1B80, 0x00000405, 0x1B80, 0x00000407,
1622 0x1B80, 0x4D000415, 0x1B80, 0x4D000417, 0x1B80, 0x55070425,
1623 0x1B80, 0x55070427, 0x1B80, 0xE10C0435, 0x1B80, 0xE10C0437,
1624 0x1B80, 0xE10C0445, 0x1B80, 0xE10C0447, 0x1B80, 0x4D040455,
1625 0x1B80, 0x4D040457, 0x1B80, 0x20880465, 0x1B80, 0x20880467,
1626 0x1B80, 0x02000475, 0x1B80, 0x02000477, 0x1B80, 0x4D000485,
1627 0x1B80, 0x4D000487, 0x1B80, 0x550F0495, 0x1B80, 0x550F0497,
1628 0x1B80, 0xE10C04A5, 0x1B80, 0xE10C04A7, 0x1B80, 0x4F0204B5,
1629 0x1B80, 0x4F0204B7, 0x1B80, 0x4E0004C5, 0x1B80, 0x4E0004C7,
1630 0x1B80, 0x530204D5, 0x1B80, 0x530204D7, 0x1B80, 0x520104E5,
1631 0x1B80, 0x520104E7, 0x1B80, 0xE11004F5, 0x1B80, 0xE11004F7,
1632 0x1B80, 0x4D080505, 0x1B80, 0x4D080507, 0x1B80, 0x57100515,
1633 0x1B80, 0x57100517, 0x1B80, 0x57000525, 0x1B80, 0x57000527,
1634 0x1B80, 0x4D000535, 0x1B80, 0x4D000537, 0x1B80, 0x00010545,
1635 0x1B80, 0x00010547, 0x1B80, 0xE1140555, 0x1B80, 0xE1140557,
1636 0x1B80, 0x00010565, 0x1B80, 0x00010567, 0x1B80, 0x30770575,
1637 0x1B80, 0x30770577, 0x1B80, 0x00230585, 0x1B80, 0x00230587,
1638 0x1B80, 0xE1680595, 0x1B80, 0xE1680597, 0x1B80, 0x000205A5,
1639 0x1B80, 0x000205A7, 0x1B80, 0x54E905B5, 0x1B80, 0x54E905B7,
1640 0x1B80, 0x0BA605C5, 0x1B80, 0x0BA605C7, 0x1B80, 0x002305D5,
1641 0x1B80, 0x002305D7, 0x1B80, 0xE16805E5, 0x1B80, 0xE16805E7,
1642 0x1B80, 0x000205F5, 0x1B80, 0x000205F7, 0x1B80, 0x4D300605,
1643 0x1B80, 0x4D300607, 0x1B80, 0x30900615, 0x1B80, 0x30900617,
1644 0x1B80, 0x30730625, 0x1B80, 0x30730627, 0x1B80, 0x00220635,
1645 0x1B80, 0x00220637, 0x1B80, 0xE1680645, 0x1B80, 0xE1680647,
1646 0x1B80, 0x00020655, 0x1B80, 0x00020657, 0x1B80, 0x54E80665,
1647 0x1B80, 0x54E80667, 0x1B80, 0x0BA60675, 0x1B80, 0x0BA60677,
1648 0x1B80, 0x00220685, 0x1B80, 0x00220687, 0x1B80, 0xE1680695,
1649 0x1B80, 0xE1680697, 0x1B80, 0x000206A5, 0x1B80, 0x000206A7,
1650 0x1B80, 0x4D3006B5, 0x1B80, 0x4D3006B7, 0x1B80, 0x309006C5,
1651 0x1B80, 0x309006C7, 0x1B80, 0x63F106D5, 0x1B80, 0x63F106D7,
1652 0x1B80, 0xE11406E5, 0x1B80, 0xE11406E7, 0x1B80, 0xE16806F5,
1653 0x1B80, 0xE16806F7, 0x1B80, 0x63F40705, 0x1B80, 0x63F40707,
1654 0x1B80, 0xE1140715, 0x1B80, 0xE1140717, 0x1B80, 0xE1680725,
1655 0x1B80, 0xE1680727, 0x1B80, 0x0BA80735, 0x1B80, 0x0BA80737,
1656 0x1B80, 0x63F80745, 0x1B80, 0x63F80747, 0x1B80, 0xE1140755,
1657 0x1B80, 0xE1140757, 0x1B80, 0xE1680765, 0x1B80, 0xE1680767,
1658 0x1B80, 0x0BA90775, 0x1B80, 0x0BA90777, 0x1B80, 0x63FC0785,
1659 0x1B80, 0x63FC0787, 0x1B80, 0xE1140795, 0x1B80, 0xE1140797,
1660 0x1B80, 0xE16807A5, 0x1B80, 0xE16807A7, 0x1B80, 0x63FF07B5,
1661 0x1B80, 0x63FF07B7, 0x1B80, 0xE11407C5, 0x1B80, 0xE11407C7,
1662 0x1B80, 0xE16807D5, 0x1B80, 0xE16807D7, 0x1B80, 0x630007E5,
1663 0x1B80, 0x630007E7, 0x1B80, 0xE11407F5, 0x1B80, 0xE11407F7,
1664 0x1B80, 0xE1680805, 0x1B80, 0xE1680807, 0x1B80, 0x63030815,
1665 0x1B80, 0x63030817, 0x1B80, 0xE1140825, 0x1B80, 0xE1140827,
1666 0x1B80, 0xE1680835, 0x1B80, 0xE1680837, 0x1B80, 0xF4D40845,
1667 0x1B80, 0xF4D40847, 0x1B80, 0x63070855, 0x1B80, 0x63070857,
1668 0x1B80, 0xE1140865, 0x1B80, 0xE1140867, 0x1B80, 0xE1680875,
1669 0x1B80, 0xE1680877, 0x1B80, 0xF5DB0885, 0x1B80, 0xF5DB0887,
1670 0x1B80, 0x630B0895, 0x1B80, 0x630B0897, 0x1B80, 0xE11408A5,
1671 0x1B80, 0xE11408A7, 0x1B80, 0xE16808B5, 0x1B80, 0xE16808B7,
1672 0x1B80, 0x630E08C5, 0x1B80, 0x630E08C7, 0x1B80, 0xE11408D5,
1673 0x1B80, 0xE11408D7, 0x1B80, 0xE16808E5, 0x1B80, 0xE16808E7,
1674 0x1B80, 0x4D3008F5, 0x1B80, 0x4D3008F7, 0x1B80, 0x55010905,
1675 0x1B80, 0x55010907, 0x1B80, 0x57040915, 0x1B80, 0x57040917,
1676 0x1B80, 0x57000925, 0x1B80, 0x57000927, 0x1B80, 0x96000935,
1677 0x1B80, 0x96000937, 0x1B80, 0x57080945, 0x1B80, 0x57080947,
1678 0x1B80, 0x57000955, 0x1B80, 0x57000957, 0x1B80, 0x95000965,
1679 0x1B80, 0x95000967, 0x1B80, 0x4D000975, 0x1B80, 0x4D000977,
1680 0x1B80, 0x6C070985, 0x1B80, 0x6C070987, 0x1B80, 0x7B200995,
1681 0x1B80, 0x7B200997, 0x1B80, 0x7A0009A5, 0x1B80, 0x7A0009A7,
1682 0x1B80, 0x790009B5, 0x1B80, 0x790009B7, 0x1B80, 0x7F2009C5,
1683 0x1B80, 0x7F2009C7, 0x1B80, 0x7E0009D5, 0x1B80, 0x7E0009D7,
1684 0x1B80, 0x7D0009E5, 0x1B80, 0x7D0009E7, 0x1B80, 0x000109F5,
1685 0x1B80, 0x000109F7, 0x1B80, 0x62850A05, 0x1B80, 0x62850A07,
1686 0x1B80, 0xE1140A15, 0x1B80, 0xE1140A17, 0x1B80, 0x00010A25,
1687 0x1B80, 0x00010A27, 0x1B80, 0x5C320A35, 0x1B80, 0x5C320A37,
1688 0x1B80, 0xE1640A45, 0x1B80, 0xE1640A47, 0x1B80, 0xE1420A55,
1689 0x1B80, 0xE1420A57, 0x1B80, 0x00010A65, 0x1B80, 0x00010A67,
1690 0x1B80, 0x5C320A75, 0x1B80, 0x5C320A77, 0x1B80, 0x63F40A85,
1691 0x1B80, 0x63F40A87, 0x1B80, 0x62850A95, 0x1B80, 0x62850A97,
1692 0x1B80, 0x0BB00AA5, 0x1B80, 0x0BB00AA7, 0x1B80, 0xE1140AB5,
1693 0x1B80, 0xE1140AB7, 0x1B80, 0xE1680AC5, 0x1B80, 0xE1680AC7,
1694 0x1B80, 0x5C320AD5, 0x1B80, 0x5C320AD7, 0x1B80, 0x63FC0AE5,
1695 0x1B80, 0x63FC0AE7, 0x1B80, 0x62850AF5, 0x1B80, 0x62850AF7,
1696 0x1B80, 0x0BB10B05, 0x1B80, 0x0BB10B07, 0x1B80, 0xE1140B15,
1697 0x1B80, 0xE1140B17, 0x1B80, 0xE1680B25, 0x1B80, 0xE1680B27,
1698 0x1B80, 0x63030B35, 0x1B80, 0x63030B37, 0x1B80, 0xE1140B45,
1699 0x1B80, 0xE1140B47, 0x1B80, 0xE1680B55, 0x1B80, 0xE1680B57,
1700 0x1B80, 0xF7040B65, 0x1B80, 0xF7040B67, 0x1B80, 0x630B0B75,
1701 0x1B80, 0x630B0B77, 0x1B80, 0xE1140B85, 0x1B80, 0xE1140B87,
1702 0x1B80, 0xE1680B95, 0x1B80, 0xE1680B97, 0x1B80, 0x00010BA5,
1703 0x1B80, 0x00010BA7, 0x1B80, 0x30DF0BB5, 0x1B80, 0x30DF0BB7,
1704 0x1B80, 0x00230BC5, 0x1B80, 0x00230BC7, 0x1B80, 0xE16D0BD5,
1705 0x1B80, 0xE16D0BD7, 0x1B80, 0x00020BE5, 0x1B80, 0x00020BE7,
1706 0x1B80, 0x54E90BF5, 0x1B80, 0x54E90BF7, 0x1B80, 0x0BA60C05,
1707 0x1B80, 0x0BA60C07, 0x1B80, 0x00230C15, 0x1B80, 0x00230C17,
1708 0x1B80, 0xE16D0C25, 0x1B80, 0xE16D0C27, 0x1B80, 0x00020C35,
1709 0x1B80, 0x00020C37, 0x1B80, 0x4D100C45, 0x1B80, 0x4D100C47,
1710 0x1B80, 0x30900C55, 0x1B80, 0x30900C57, 0x1B80, 0x30D90C65,
1711 0x1B80, 0x30D90C67, 0x1B80, 0x00220C75, 0x1B80, 0x00220C77,
1712 0x1B80, 0xE16D0C85, 0x1B80, 0xE16D0C87, 0x1B80, 0x00020C95,
1713 0x1B80, 0x00020C97, 0x1B80, 0x54E80CA5, 0x1B80, 0x54E80CA7,
1714 0x1B80, 0x0BA60CB5, 0x1B80, 0x0BA60CB7, 0x1B80, 0x00220CC5,
1715 0x1B80, 0x00220CC7, 0x1B80, 0xE16D0CD5, 0x1B80, 0xE16D0CD7,
1716 0x1B80, 0x00020CE5, 0x1B80, 0x00020CE7, 0x1B80, 0x4D100CF5,
1717 0x1B80, 0x4D100CF7, 0x1B80, 0x30900D05, 0x1B80, 0x30900D07,
1718 0x1B80, 0x5C320D15, 0x1B80, 0x5C320D17, 0x1B80, 0x54F00D25,
1719 0x1B80, 0x54F00D27, 0x1B80, 0x67F10D35, 0x1B80, 0x67F10D37,
1720 0x1B80, 0xE1420D45, 0x1B80, 0xE1420D47, 0x1B80, 0xE16D0D55,
1721 0x1B80, 0xE16D0D57, 0x1B80, 0x67F40D65, 0x1B80, 0x67F40D67,
1722 0x1B80, 0xE1420D75, 0x1B80, 0xE1420D77, 0x1B80, 0xE16D0D85,
1723 0x1B80, 0xE16D0D87, 0x1B80, 0x5C320D95, 0x1B80, 0x5C320D97,
1724 0x1B80, 0x54F10DA5, 0x1B80, 0x54F10DA7, 0x1B80, 0x0BA80DB5,
1725 0x1B80, 0x0BA80DB7, 0x1B80, 0x67F80DC5, 0x1B80, 0x67F80DC7,
1726 0x1B80, 0xE1420DD5, 0x1B80, 0xE1420DD7, 0x1B80, 0xE16D0DE5,
1727 0x1B80, 0xE16D0DE7, 0x1B80, 0x5C320DF5, 0x1B80, 0x5C320DF7,
1728 0x1B80, 0x54F10E05, 0x1B80, 0x54F10E07, 0x1B80, 0x0BA90E15,
1729 0x1B80, 0x0BA90E17, 0x1B80, 0x67FC0E25, 0x1B80, 0x67FC0E27,
1730 0x1B80, 0xE1420E35, 0x1B80, 0xE1420E37, 0x1B80, 0xE16D0E45,
1731 0x1B80, 0xE16D0E47, 0x1B80, 0x67FF0E55, 0x1B80, 0x67FF0E57,
1732 0x1B80, 0xE1420E65, 0x1B80, 0xE1420E67, 0x1B80, 0xE16D0E75,
1733 0x1B80, 0xE16D0E77, 0x1B80, 0x5C320E85, 0x1B80, 0x5C320E87,
1734 0x1B80, 0x54F20E95, 0x1B80, 0x54F20E97, 0x1B80, 0x67000EA5,
1735 0x1B80, 0x67000EA7, 0x1B80, 0xE1420EB5, 0x1B80, 0xE1420EB7,
1736 0x1B80, 0xE16D0EC5, 0x1B80, 0xE16D0EC7, 0x1B80, 0x67030ED5,
1737 0x1B80, 0x67030ED7, 0x1B80, 0xE1420EE5, 0x1B80, 0xE1420EE7,
1738 0x1B80, 0xE16D0EF5, 0x1B80, 0xE16D0EF7, 0x1B80, 0xF9CC0F05,
1739 0x1B80, 0xF9CC0F07, 0x1B80, 0x67070F15, 0x1B80, 0x67070F17,
1740 0x1B80, 0xE1420F25, 0x1B80, 0xE1420F27, 0x1B80, 0xE16D0F35,
1741 0x1B80, 0xE16D0F37, 0x1B80, 0xFAD30F45, 0x1B80, 0xFAD30F47,
1742 0x1B80, 0x5C320F55, 0x1B80, 0x5C320F57, 0x1B80, 0x54F30F65,
1743 0x1B80, 0x54F30F67, 0x1B80, 0x670B0F75, 0x1B80, 0x670B0F77,
1744 0x1B80, 0xE1420F85, 0x1B80, 0xE1420F87, 0x1B80, 0xE16D0F95,
1745 0x1B80, 0xE16D0F97, 0x1B80, 0x670E0FA5, 0x1B80, 0x670E0FA7,
1746 0x1B80, 0xE1420FB5, 0x1B80, 0xE1420FB7, 0x1B80, 0xE16D0FC5,
1747 0x1B80, 0xE16D0FC7, 0x1B80, 0x4D100FD5, 0x1B80, 0x4D100FD7,
1748 0x1B80, 0x30900FE5, 0x1B80, 0x30900FE7, 0x1B80, 0x00010FF5,
1749 0x1B80, 0x00010FF7, 0x1B80, 0x7B241005, 0x1B80, 0x7B241007,
1750 0x1B80, 0x7A401015, 0x1B80, 0x7A401017, 0x1B80, 0x79001025,
1751 0x1B80, 0x79001027, 0x1B80, 0x55031035, 0x1B80, 0x55031037,
1752 0x1B80, 0x310C1045, 0x1B80, 0x310C1047, 0x1B80, 0x7B1C1055,
1753 0x1B80, 0x7B1C1057, 0x1B80, 0x7A401065, 0x1B80, 0x7A401067,
1754 0x1B80, 0x550B1075, 0x1B80, 0x550B1077, 0x1B80, 0x310C1085,
1755 0x1B80, 0x310C1087, 0x1B80, 0x7B201095, 0x1B80, 0x7B201097,
1756 0x1B80, 0x7A0010A5, 0x1B80, 0x7A0010A7, 0x1B80, 0x551310B5,
1757 0x1B80, 0x551310B7, 0x1B80, 0x740110C5, 0x1B80, 0x740110C7,
1758 0x1B80, 0x740010D5, 0x1B80, 0x740010D7, 0x1B80, 0x8E0010E5,
1759 0x1B80, 0x8E0010E7, 0x1B80, 0x000110F5, 0x1B80, 0x000110F7,
1760 0x1B80, 0x57021105, 0x1B80, 0x57021107, 0x1B80, 0x57001115,
1761 0x1B80, 0x57001117, 0x1B80, 0x97001125, 0x1B80, 0x97001127,
1762 0x1B80, 0x00011135, 0x1B80, 0x00011137, 0x1B80, 0x4F781145,
1763 0x1B80, 0x4F781147, 0x1B80, 0x53881155, 0x1B80, 0x53881157,
1764 0x1B80, 0xE1221165, 0x1B80, 0xE1221167, 0x1B80, 0x54801175,
1765 0x1B80, 0x54801177, 0x1B80, 0x54001185, 0x1B80, 0x54001187,
1766 0x1B80, 0xE1221195, 0x1B80, 0xE1221197, 0x1B80, 0x548111A5,
1767 0x1B80, 0x548111A7, 0x1B80, 0x540011B5, 0x1B80, 0x540011B7,
1768 0x1B80, 0xE12211C5, 0x1B80, 0xE12211C7, 0x1B80, 0x548211D5,
1769 0x1B80, 0x548211D7, 0x1B80, 0x540011E5, 0x1B80, 0x540011E7,
1770 0x1B80, 0xE12D11F5, 0x1B80, 0xE12D11F7, 0x1B80, 0xBF1D1205,
1771 0x1B80, 0xBF1D1207, 0x1B80, 0x301D1215, 0x1B80, 0x301D1217,
1772 0x1B80, 0xE1001225, 0x1B80, 0xE1001227, 0x1B80, 0xE1051235,
1773 0x1B80, 0xE1051237, 0x1B80, 0xE1091245, 0x1B80, 0xE1091247,
1774 0x1B80, 0xE1101255, 0x1B80, 0xE1101257, 0x1B80, 0xE1641265,
1775 0x1B80, 0xE1641267, 0x1B80, 0x55131275, 0x1B80, 0x55131277,
1776 0x1B80, 0xE10C1285, 0x1B80, 0xE10C1287, 0x1B80, 0x55151295,
1777 0x1B80, 0x55151297, 0x1B80, 0xE11012A5, 0x1B80, 0xE11012A7,
1778 0x1B80, 0xE16412B5, 0x1B80, 0xE16412B7, 0x1B80, 0x000112C5,
1779 0x1B80, 0x000112C7, 0x1B80, 0x54BF12D5, 0x1B80, 0x54BF12D7,
1780 0x1B80, 0x54C012E5, 0x1B80, 0x54C012E7, 0x1B80, 0x54A312F5,
1781 0x1B80, 0x54A312F7, 0x1B80, 0x54C11305, 0x1B80, 0x54C11307,
1782 0x1B80, 0x54A41315, 0x1B80, 0x54A41317, 0x1B80, 0x4C181325,
1783 0x1B80, 0x4C181327, 0x1B80, 0xBF071335, 0x1B80, 0xBF071337,
1784 0x1B80, 0x54C21345, 0x1B80, 0x54C21347, 0x1B80, 0x54A41355,
1785 0x1B80, 0x54A41357, 0x1B80, 0xBF041365, 0x1B80, 0xBF041367,
1786 0x1B80, 0x54C11375, 0x1B80, 0x54C11377, 0x1B80, 0x54A31385,
1787 0x1B80, 0x54A31387, 0x1B80, 0xBF011395, 0x1B80, 0xBF011397,
1788 0x1B80, 0xE17213A5, 0x1B80, 0xE17213A7, 0x1B80, 0x54DF13B5,
1789 0x1B80, 0x54DF13B7, 0x1B80, 0x000113C5, 0x1B80, 0x000113C7,
1790 0x1B80, 0x54BF13D5, 0x1B80, 0x54BF13D7, 0x1B80, 0x54E513E5,
1791 0x1B80, 0x54E513E7, 0x1B80, 0x050A13F5, 0x1B80, 0x050A13F7,
1792 0x1B80, 0x54DF1405, 0x1B80, 0x54DF1407, 0x1B80, 0x00011415,
1793 0x1B80, 0x00011417, 0x1B80, 0x7F201425, 0x1B80, 0x7F201427,
1794 0x1B80, 0x7E001435, 0x1B80, 0x7E001437, 0x1B80, 0x7D001445,
1795 0x1B80, 0x7D001447, 0x1B80, 0x55011455, 0x1B80, 0x55011457,
1796 0x1B80, 0x5C311465, 0x1B80, 0x5C311467, 0x1B80, 0xE10C1475,
1797 0x1B80, 0xE10C1477, 0x1B80, 0xE1101485, 0x1B80, 0xE1101487,
1798 0x1B80, 0x54801495, 0x1B80, 0x54801497, 0x1B80, 0x540014A5,
1799 0x1B80, 0x540014A7, 0x1B80, 0xE10C14B5, 0x1B80, 0xE10C14B7,
1800 0x1B80, 0xE11014C5, 0x1B80, 0xE11014C7, 0x1B80, 0x548114D5,
1801 0x1B80, 0x548114D7, 0x1B80, 0x540014E5, 0x1B80, 0x540014E7,
1802 0x1B80, 0xE10C14F5, 0x1B80, 0xE10C14F7, 0x1B80, 0xE1101505,
1803 0x1B80, 0xE1101507, 0x1B80, 0x54821515, 0x1B80, 0x54821517,
1804 0x1B80, 0x54001525, 0x1B80, 0x54001527, 0x1B80, 0xE12D1535,
1805 0x1B80, 0xE12D1537, 0x1B80, 0xBFE91545, 0x1B80, 0xBFE91547,
1806 0x1B80, 0x301D1555, 0x1B80, 0x301D1557, 0x1B80, 0x00231565,
1807 0x1B80, 0x00231567, 0x1B80, 0x7B201575, 0x1B80, 0x7B201577,
1808 0x1B80, 0x7A001585, 0x1B80, 0x7A001587, 0x1B80, 0x79001595,
1809 0x1B80, 0x79001597, 0x1B80, 0xE16815A5, 0x1B80, 0xE16815A7,
1810 0x1B80, 0x000215B5, 0x1B80, 0x000215B7, 0x1B80, 0x000115C5,
1811 0x1B80, 0x000115C7, 0x1B80, 0x002215D5, 0x1B80, 0x002215D7,
1812 0x1B80, 0x7B2015E5, 0x1B80, 0x7B2015E7, 0x1B80, 0x7A0015F5,
1813 0x1B80, 0x7A0015F7, 0x1B80, 0x79001605, 0x1B80, 0x79001607,
1814 0x1B80, 0xE1681615, 0x1B80, 0xE1681617, 0x1B80, 0x00021625,
1815 0x1B80, 0x00021627, 0x1B80, 0x00011635, 0x1B80, 0x00011637,
1816 0x1B80, 0x549F1645, 0x1B80, 0x549F1647, 0x1B80, 0x54FF1655,
1817 0x1B80, 0x54FF1657, 0x1B80, 0x54001665, 0x1B80, 0x54001667,
1818 0x1B80, 0x00011675, 0x1B80, 0x00011677, 0x1B80, 0x5C311685,
1819 0x1B80, 0x5C311687, 0x1B80, 0x07141695, 0x1B80, 0x07141697,
1820 0x1B80, 0x540016A5, 0x1B80, 0x540016A7, 0x1B80, 0x5C3216B5,
1821 0x1B80, 0x5C3216B7, 0x1B80, 0x000116C5, 0x1B80, 0x000116C7,
1822 0x1B80, 0x5C3216D5, 0x1B80, 0x5C3216D7, 0x1B80, 0x071416E5,
1823 0x1B80, 0x071416E7, 0x1B80, 0x540016F5, 0x1B80, 0x540016F7,
1824 0x1B80, 0x5C311705, 0x1B80, 0x5C311707, 0x1B80, 0x00011715,
1825 0x1B80, 0x00011717, 0x1B80, 0x4C981725, 0x1B80, 0x4C981727,
1826 0x1B80, 0x4C181735, 0x1B80, 0x4C181737, 0x1B80, 0x00011745,
1827 0x1B80, 0x00011747, 0x1B80, 0x5C321755, 0x1B80, 0x5C321757,
1828 0x1B80, 0x62841765, 0x1B80, 0x62841767, 0x1B80, 0x66861775,
1829 0x1B80, 0x66861777, 0x1B80, 0x6C031785, 0x1B80, 0x6C031787,
1830 0x1B80, 0x7B201795, 0x1B80, 0x7B201797, 0x1B80, 0x7A0017A5,
1831 0x1B80, 0x7A0017A7, 0x1B80, 0x790017B5, 0x1B80, 0x790017B7,
1832 0x1B80, 0x7F2017C5, 0x1B80, 0x7F2017C7, 0x1B80, 0x7E0017D5,
1833 0x1B80, 0x7E0017D7, 0x1B80, 0x7D0017E5, 0x1B80, 0x7D0017E7,
1834 0x1B80, 0x090117F5, 0x1B80, 0x090117F7, 0x1B80, 0x0C011805,
1835 0x1B80, 0x0C011807, 0x1B80, 0x0BA61815, 0x1B80, 0x0BA61817,
1836 0x1B80, 0x00011825, 0x1B80, 0x00011827, 0x1B80, 0x00000006,
1837 0x1B80, 0x00000002,
1838
1839};
1840
1841void odm_read_and_config_mp_8822b_phy_reg(struct phy_dm_struct *dm)
1842{
1843 u32 i = 0;
1844 u8 c_cond;
1845 bool is_matched = true, is_skipped = false;
1846 u32 array_len = sizeof(array_mp_8822b_phy_reg) / sizeof(u32);
1847 u32 *array = array_mp_8822b_phy_reg;
1848
1849 u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
1850
1851 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1852 "===> %s\n", __func__);
1853
1854 for (; (i + 1) < array_len; i = i + 2) {
1855 v1 = array[i];
1856 v2 = array[i + 1];
1857
1858 if (v1 & BIT(31)) { /* positive condition*/
1859 c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
1860 if (c_cond == COND_ENDIF) { /*end*/
1861 is_matched = true;
1862 is_skipped = false;
1863 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
1864 } else if (c_cond == COND_ELSE) { /*else*/
1865 is_matched = is_skipped ? false : true;
1866 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
1867 } else { /*if , else if*/
1868 pre_v1 = v1;
1869 pre_v2 = v2;
1870 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1871 "IF or ELSE IF\n");
1872 }
1873 } else if (v1 & BIT(30)) { /*negative condition*/
1874 if (is_skipped) {
1875 is_matched = false;
1876 continue;
1877 }
1878
1879 if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
1880 is_matched = true;
1881 is_skipped = true;
1882 } else {
1883 is_matched = false;
1884 is_skipped = false;
1885 }
1886 } else if (is_matched) {
1887 odm_config_bb_phy_8822b(dm, v1, MASKDWORD, v2);
1888 }
1889 }
1890}
1891
1892u32 odm_get_version_mp_8822b_phy_reg(void) { return 67; }
1893
1894/******************************************************************************
1895 * phy_reg_pg.TXT
1896 ******************************************************************************/
1897
1898static u32 array_mp_8822b_phy_reg_pg[] = {
1899 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638,
1900 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042,
1901 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234,
1902 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840,
1903 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032,
1904 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840,
1905 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032,
1906 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840,
1907 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032,
1908 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224,
1909 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436,
1910 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
1911 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638,
1912 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042,
1913 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234,
1914 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840,
1915 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032,
1916 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840,
1917 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032,
1918 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840,
1919 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032,
1920 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224,
1921 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436,
1922 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628,
1923 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840,
1924 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032,
1925 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638,
1926 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830,
1927 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638,
1928 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830,
1929 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638,
1930 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
1931 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022,
1932 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234,
1933 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426,
1934 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840,
1935 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032,
1936 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638,
1937 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830,
1938 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638,
1939 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830,
1940 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638,
1941 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830,
1942 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022,
1943 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234,
1944 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426,
1945};
1946
1947void odm_read_and_config_mp_8822b_phy_reg_pg(struct phy_dm_struct *dm)
1948{
1949 u32 i = 0;
1950 u32 array_len = sizeof(array_mp_8822b_phy_reg_pg) / sizeof(u32);
1951 u32 *array = array_mp_8822b_phy_reg_pg;
1952
1953 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1954 "===> %s\n", __func__);
1955
1956 dm->phy_reg_pg_version = 1;
1957 dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
1958
1959 for (i = 0; i < array_len; i += 6) {
1960 u32 v1 = array[i];
1961 u32 v2 = array[i + 1];
1962 u32 v3 = array[i + 2];
1963 u32 v4 = array[i + 3];
1964 u32 v5 = array[i + 4];
1965 u32 v6 = array[i + 5];
1966
1967 odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6);
1968 }
1969}
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_bb.h b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_bb.h
new file mode 100644
index 000000000000..53431998b47e
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_bb.h
@@ -0,0 +1,54 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/*Image2HeaderVersion: 3.2*/
27#ifndef __INC_MP_BB_HW_IMG_8822B_H
28#define __INC_MP_BB_HW_IMG_8822B_H
29
30/******************************************************************************
31 * agc_tab.TXT
32 ******************************************************************************/
33
34void odm_read_and_config_mp_8822b_agc_tab(/* tc: Test Chip, mp: mp Chip*/
35 struct phy_dm_struct *dm);
36u32 odm_get_version_mp_8822b_agc_tab(void);
37
38/******************************************************************************
39 * phy_reg.TXT
40 ******************************************************************************/
41
42void odm_read_and_config_mp_8822b_phy_reg(/* tc: Test Chip, mp: mp Chip*/
43 struct phy_dm_struct *dm);
44u32 odm_get_version_mp_8822b_phy_reg(void);
45
46/******************************************************************************
47 * phy_reg_pg.TXT
48 ******************************************************************************/
49
50void odm_read_and_config_mp_8822b_phy_reg_pg(/* tc: Test Chip, mp: mp Chip*/
51 struct phy_dm_struct *dm);
52u32 odm_get_version_mp_8822b_phy_reg_pg(void);
53
54#endif
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_mac.c b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_mac.c
new file mode 100644
index 000000000000..1a9daed2e609
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_mac.c
@@ -0,0 +1,222 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/*Image2HeaderVersion: 3.2*/
27#include "../mp_precomp.h"
28#include "../phydm_precomp.h"
29
30static bool check_positive(struct phy_dm_struct *dm, const u32 condition1,
31 const u32 condition2, const u32 condition3,
32 const u32 condition4)
33{
34 u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
35 ((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
36 ((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
37 ((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
38 ((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
39
40 u32 cond1 = condition1, cond2 = condition2, cond3 = condition3,
41 cond4 = condition4;
42
43 u8 cut_version_for_para =
44 (dm->cut_version == ODM_CUT_A) ? 14 : dm->cut_version;
45 u8 pkg_type_for_para = (dm->package_type == 0) ? 14 : dm->package_type;
46
47 u32 driver1 = cut_version_for_para << 24 |
48 (dm->support_interface & 0xF0) << 16 |
49 dm->support_platform << 16 | pkg_type_for_para << 12 |
50 (dm->support_interface & 0x0F) << 8 | _board_type;
51
52 u32 driver2 = (dm->type_glna & 0xFF) << 0 | (dm->type_gpa & 0xFF) << 8 |
53 (dm->type_alna & 0xFF) << 16 |
54 (dm->type_apa & 0xFF) << 24;
55
56 u32 driver3 = 0;
57
58 u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | (dm->type_gpa & 0xFF00) |
59 (dm->type_alna & 0xFF00) << 8 |
60 (dm->type_apa & 0xFF00) << 16;
61
62 ODM_RT_TRACE(
63 dm, ODM_COMP_INIT,
64 "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
65 __func__, cond1, cond2, cond3, cond4);
66 ODM_RT_TRACE(
67 dm, ODM_COMP_INIT,
68 "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
69 __func__, driver1, driver2, driver3, driver4);
70
71 ODM_RT_TRACE(dm, ODM_COMP_INIT,
72 " (Platform, Interface) = (0x%X, 0x%X)\n",
73 dm->support_platform, dm->support_interface);
74 ODM_RT_TRACE(dm, ODM_COMP_INIT,
75 " (Board, Package) = (0x%X, 0x%X)\n",
76 dm->board_type, dm->package_type);
77
78 /*============== value Defined Check ===============*/
79 /*QFN type [15:12] and cut version [27:24] need to do value check*/
80
81 if (((cond1 & 0x0000F000) != 0) &&
82 ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
83 return false;
84 if (((cond1 & 0x0F000000) != 0) &&
85 ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
86 return false;
87
88 /*=============== Bit Defined Check ================*/
89 /* We don't care [31:28] */
90
91 cond1 &= 0x00FF0FFF;
92 driver1 &= 0x00FF0FFF;
93
94 if ((cond1 & driver1) == cond1) {
95 u32 bit_mask = 0;
96
97 if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
98 return true;
99
100 if ((cond1 & BIT(0)) != 0) /*GLNA*/
101 bit_mask |= 0x000000FF;
102 if ((cond1 & BIT(1)) != 0) /*GPA*/
103 bit_mask |= 0x0000FF00;
104 if ((cond1 & BIT(2)) != 0) /*ALNA*/
105 bit_mask |= 0x00FF0000;
106 if ((cond1 & BIT(3)) != 0) /*APA*/
107 bit_mask |= 0xFF000000;
108
109 if (((cond2 & bit_mask) == (driver2 & bit_mask)) &&
110 ((cond4 & bit_mask) ==
111 (driver4 &
112 bit_mask))) /* board_type of each RF path is matched*/
113 return true;
114 else
115 return false;
116 } else {
117 return false;
118 }
119}
120
121/******************************************************************************
122 * mac_reg.TXT
123 ******************************************************************************/
124
125static u32 array_mp_8822b_mac_reg[] = {
126 0x029, 0x000000F9, 0x420, 0x00000080, 0x421, 0x0000000F,
127 0x428, 0x0000000A, 0x429, 0x00000010, 0x430, 0x00000000,
128 0x431, 0x00000000, 0x432, 0x00000000, 0x433, 0x00000001,
129 0x434, 0x00000004, 0x435, 0x00000005, 0x436, 0x00000007,
130 0x437, 0x00000008, 0x43C, 0x00000004, 0x43D, 0x00000005,
131 0x43E, 0x00000007, 0x43F, 0x00000008, 0x440, 0x0000005D,
132 0x441, 0x00000001, 0x442, 0x00000000, 0x444, 0x00000010,
133 0x445, 0x000000F0, 0x446, 0x00000001, 0x447, 0x000000FE,
134 0x448, 0x00000000, 0x449, 0x00000000, 0x44A, 0x00000000,
135 0x44B, 0x00000040, 0x44C, 0x00000010, 0x44D, 0x000000F0,
136 0x44E, 0x0000003F, 0x44F, 0x00000000, 0x450, 0x00000000,
137 0x451, 0x00000000, 0x452, 0x00000000, 0x453, 0x00000040,
138 0x455, 0x00000070, 0x45E, 0x00000004, 0x49C, 0x00000010,
139 0x49D, 0x000000F0, 0x49E, 0x00000000, 0x49F, 0x00000006,
140 0x4A0, 0x000000E0, 0x4A1, 0x00000003, 0x4A2, 0x00000000,
141 0x4A3, 0x00000040, 0x4A4, 0x00000015, 0x4A5, 0x000000F0,
142 0x4A6, 0x00000000, 0x4A7, 0x00000006, 0x4A8, 0x000000E0,
143 0x4A9, 0x00000000, 0x4AA, 0x00000000, 0x4AB, 0x00000000,
144 0x7DA, 0x00000008, 0x1448, 0x00000006, 0x144A, 0x00000006,
145 0x144C, 0x00000006, 0x144E, 0x00000006, 0x4C8, 0x000000FF,
146 0x4C9, 0x00000008, 0x4CA, 0x00000020, 0x4CB, 0x00000020,
147 0x4CC, 0x000000FF, 0x4CD, 0x000000FF, 0x4CE, 0x00000001,
148 0x4CF, 0x00000008, 0x500, 0x00000026, 0x501, 0x000000A2,
149 0x502, 0x0000002F, 0x503, 0x00000000, 0x504, 0x00000028,
150 0x505, 0x000000A3, 0x506, 0x0000005E, 0x507, 0x00000000,
151 0x508, 0x0000002B, 0x509, 0x000000A4, 0x50A, 0x0000005E,
152 0x50B, 0x00000000, 0x50C, 0x0000004F, 0x50D, 0x000000A4,
153 0x50E, 0x00000000, 0x50F, 0x00000000, 0x512, 0x0000001C,
154 0x514, 0x0000000A, 0x516, 0x0000000A, 0x521, 0x0000002F,
155 0x525, 0x0000004F, 0x551, 0x00000010, 0x559, 0x00000002,
156 0x55C, 0x00000050, 0x55D, 0x000000FF, 0x577, 0x0000000B,
157 0x5BE, 0x00000064, 0x605, 0x00000030, 0x608, 0x0000000E,
158 0x609, 0x00000022, 0x60C, 0x00000018, 0x6A0, 0x000000FF,
159 0x6A1, 0x000000FF, 0x6A2, 0x000000FF, 0x6A3, 0x000000FF,
160 0x6A4, 0x000000FF, 0x6A5, 0x000000FF, 0x6DE, 0x00000084,
161 0x620, 0x000000FF, 0x621, 0x000000FF, 0x622, 0x000000FF,
162 0x623, 0x000000FF, 0x624, 0x000000FF, 0x625, 0x000000FF,
163 0x626, 0x000000FF, 0x627, 0x000000FF, 0x638, 0x00000050,
164 0x63C, 0x0000000A, 0x63D, 0x0000000A, 0x63E, 0x0000000E,
165 0x63F, 0x0000000E, 0x640, 0x00000040, 0x642, 0x00000040,
166 0x643, 0x00000000, 0x652, 0x000000C8, 0x66E, 0x00000005,
167 0x718, 0x00000040, 0x7D4, 0x00000098,
168
169};
170
171void odm_read_and_config_mp_8822b_mac_reg(struct phy_dm_struct *dm)
172{
173 u32 i = 0;
174 u8 c_cond;
175 bool is_matched = true, is_skipped = false;
176 u32 array_len = sizeof(array_mp_8822b_mac_reg) / sizeof(u32);
177 u32 *array = array_mp_8822b_mac_reg;
178
179 u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
180
181 ODM_RT_TRACE(dm, ODM_COMP_INIT,
182 "===> %s\n", __func__);
183
184 for (; (i + 1) < array_len; i = i + 2) {
185 v1 = array[i];
186 v2 = array[i + 1];
187
188 if (v1 & BIT(31)) { /* positive condition*/
189 c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
190 if (c_cond == COND_ENDIF) { /*end*/
191 is_matched = true;
192 is_skipped = false;
193 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
194 } else if (c_cond == COND_ELSE) { /*else*/
195 is_matched = is_skipped ? false : true;
196 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
197 } else { /*if , else if*/
198 pre_v1 = v1;
199 pre_v2 = v2;
200 ODM_RT_TRACE(dm, ODM_COMP_INIT,
201 "IF or ELSE IF\n");
202 }
203 } else if (v1 & BIT(30)) { /*negative condition*/
204 if (is_skipped) {
205 is_matched = false;
206 continue;
207 }
208
209 if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
210 is_matched = true;
211 is_skipped = true;
212 } else {
213 is_matched = false;
214 is_skipped = false;
215 }
216 } else if (is_matched) {
217 odm_config_mac_8822b(dm, v1, (u8)v2);
218 }
219 }
220}
221
222u32 odm_get_version_mp_8822b_mac_reg(void) { return 67; }
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_mac.h b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_mac.h
new file mode 100644
index 000000000000..d02fdd7a4a53
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_mac.h
@@ -0,0 +1,38 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/*Image2HeaderVersion: 3.2*/
27#ifndef __INC_MP_MAC_HW_IMG_8822B_H
28#define __INC_MP_MAC_HW_IMG_8822B_H
29
30/******************************************************************************
31 * mac_reg.TXT
32 ******************************************************************************/
33
34void odm_read_and_config_mp_8822b_mac_reg(/* tc: Test Chip, mp: mp Chip*/
35 struct phy_dm_struct *dm);
36u32 odm_get_version_mp_8822b_mac_reg(void);
37
38#endif
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_rf.c b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_rf.c
new file mode 100644
index 000000000000..84cdc0644207
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_rf.c
@@ -0,0 +1,4744 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/*Image2HeaderVersion: 3.2*/
27#include "../mp_precomp.h"
28#include "../phydm_precomp.h"
29
30static bool check_positive(struct phy_dm_struct *dm, const u32 condition1,
31 const u32 condition2, const u32 condition3,
32 const u32 condition4)
33{
34 u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
35 ((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
36 ((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
37 ((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
38 ((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
39
40 u32 cond1 = condition1, cond2 = condition2, cond3 = condition3,
41 cond4 = condition4;
42
43 u8 cut_version_for_para =
44 (dm->cut_version == ODM_CUT_A) ? 14 : dm->cut_version;
45 u8 pkg_type_for_para = (dm->package_type == 0) ? 14 : dm->package_type;
46
47 u32 driver1 = cut_version_for_para << 24 |
48 (dm->support_interface & 0xF0) << 16 |
49 dm->support_platform << 16 | pkg_type_for_para << 12 |
50 (dm->support_interface & 0x0F) << 8 | _board_type;
51
52 u32 driver2 = (dm->type_glna & 0xFF) << 0 | (dm->type_gpa & 0xFF) << 8 |
53 (dm->type_alna & 0xFF) << 16 |
54 (dm->type_apa & 0xFF) << 24;
55
56 u32 driver3 = 0;
57
58 u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | (dm->type_gpa & 0xFF00) |
59 (dm->type_alna & 0xFF00) << 8 |
60 (dm->type_apa & 0xFF00) << 16;
61
62 ODM_RT_TRACE(
63 dm, ODM_COMP_INIT,
64 "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
65 __func__, cond1, cond2, cond3, cond4);
66 ODM_RT_TRACE(
67 dm, ODM_COMP_INIT,
68 "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
69 __func__, driver1, driver2, driver3, driver4);
70
71 ODM_RT_TRACE(dm, ODM_COMP_INIT,
72 " (Platform, Interface) = (0x%X, 0x%X)\n",
73 dm->support_platform, dm->support_interface);
74 ODM_RT_TRACE(dm, ODM_COMP_INIT,
75 " (Board, Package) = (0x%X, 0x%X)\n",
76 dm->board_type, dm->package_type);
77
78 /*============== value Defined Check ===============*/
79 /*QFN type [15:12] and cut version [27:24] need to do value check*/
80
81 if (((cond1 & 0x0000F000) != 0) &&
82 ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
83 return false;
84 if (((cond1 & 0x0F000000) != 0) &&
85 ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
86 return false;
87
88 /*=============== Bit Defined Check ================*/
89 /* We don't care [31:28] */
90
91 cond1 &= 0x00FF0FFF;
92 driver1 &= 0x00FF0FFF;
93
94 if ((cond1 & driver1) == cond1) {
95 u32 bit_mask = 0;
96
97 if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
98 return true;
99
100 if ((cond1 & BIT(0)) != 0) /*GLNA*/
101 bit_mask |= 0x000000FF;
102 if ((cond1 & BIT(1)) != 0) /*GPA*/
103 bit_mask |= 0x0000FF00;
104 if ((cond1 & BIT(2)) != 0) /*ALNA*/
105 bit_mask |= 0x00FF0000;
106 if ((cond1 & BIT(3)) != 0) /*APA*/
107 bit_mask |= 0xFF000000;
108
109 if (((cond2 & bit_mask) == (driver2 & bit_mask)) &&
110 ((cond4 & bit_mask) ==
111 (driver4 &
112 bit_mask))) /* board_type of each RF path is matched*/
113 return true;
114 else
115 return false;
116 } else {
117 return false;
118 }
119}
120
121/******************************************************************************
122 * radioa.TXT
123 ******************************************************************************/
124
125static u32 array_mp_8822b_radioa[] = {
126 0x000, 0x00030000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
127 0x001, 0x0004002D, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
128 0x001, 0x0004002D, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
129 0x001, 0x0004002D, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
130 0x001, 0x0004002D, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
131 0x001, 0x0004002D, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
132 0x001, 0x0004002D, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
133 0x001, 0x0004002D, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
134 0x001, 0x0004002D, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
135 0x001, 0x00040029, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
136 0x001, 0x00040029, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
137 0x001, 0x00040029, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
138 0x001, 0x00040029, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
139 0x001, 0x00040029, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
140 0x001, 0x00040029, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
141 0x001, 0x00040029, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
142 0x001, 0x00040029, 0xA0000000, 0x00000000, 0x001, 0x00040029,
143 0xB0000000, 0x00000000, 0x018, 0x00010D24, 0x0EF, 0x00080000,
144 0x033, 0x00000002, 0x03E, 0x0000003F, 0x03F, 0x000C0F4E,
145 0x033, 0x00000001, 0x03E, 0x00000034, 0x03F, 0x0004080E,
146 0x0EF, 0x00080000, 0x0DF, 0x00002449, 0x033, 0x00000024,
147 0x03E, 0x0000003F, 0x03F, 0x00060FDE, 0x0EF, 0x00000000,
148 0x0EF, 0x00080000, 0x033, 0x00000025, 0x03E, 0x00000037,
149 0x03F, 0x0007EFCE, 0x0EF, 0x00000000, 0x0EF, 0x00080000,
150 0x033, 0x00000026, 0x03E, 0x00000037, 0x03F, 0x000DEFCE,
151 0x0EF, 0x00000000, 0x07F, 0x00000000, 0x8300100f, 0x0a0a0a0a,
152 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9300100f, 0x05050505,
153 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9300100f, 0x00000000,
154 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9300200f, 0x00000000,
155 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x9000100f, 0x0a0a0a0a,
156 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9000100f, 0x05050505,
157 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9000100f, 0x00000000,
158 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9000200f, 0x00000000,
159 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x9300200c, 0x00000000,
160 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x93012100, 0x00000000,
161 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x93002100, 0x00000000,
162 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x93011000, 0x00000000,
163 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9000200c, 0x00000000,
164 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x90001004, 0x00000000,
165 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x93002000, 0x00000000,
166 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x93001000, 0x00000000,
167 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x90002100, 0x00000000,
168 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x90002000, 0x00000000,
169 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0xA0000000, 0x00000000,
170 0x0B0, 0x000FF0F8, 0xB0000000, 0x00000000, 0x0B1, 0x0007DBE4,
171 0x0B2, 0x000225D1, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
172 0x0B3, 0x000FC760, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
173 0x0B3, 0x000FC760, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
174 0x0B3, 0x000FC760, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
175 0x0B3, 0x000FC760, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
176 0x0B3, 0x000FC760, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
177 0x0B3, 0x000FC760, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
178 0x0B3, 0x000FC760, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
179 0x0B3, 0x000FC760, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
180 0x0B3, 0x000FC760, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
181 0x0B3, 0x000FC760, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
182 0x0B3, 0x0007C330, 0xA0000000, 0x00000000, 0x0B3, 0x000FC760,
183 0xB0000000, 0x00000000, 0x0B4, 0x00099DD0, 0x0B5, 0x000400FC,
184 0x0B6, 0x000187F0, 0x0B7, 0x00030018, 0x0B8, 0x00080800,
185 0x0B9, 0x00000000, 0x0BA, 0x00008000, 0x0BB, 0x00000000,
186 0x0BC, 0x00040030, 0x0BD, 0x00000000, 0x0BE, 0x00000000,
187 0x0BF, 0x00000000, 0x0C0, 0x00000000, 0x0C1, 0x00000000,
188 0x0C2, 0x00000000, 0x0C3, 0x00000000, 0x0C4, 0x00002402,
189 0x0C5, 0x00000009, 0x0C6, 0x00040299, 0x0C7, 0x00055555,
190 0x0C8, 0x0000C16C, 0x0C9, 0x0001C140, 0x0CA, 0x00000000,
191 0x0CB, 0x00000000, 0x0CC, 0x00000000, 0x0CD, 0x00000000,
192 0x0CE, 0x00090C00, 0x0CF, 0x0006D200, 0x0DF, 0x00000009,
193 0x018, 0x00010524, 0x089, 0x00000207, 0x8300100f, 0x0a0a0a0a,
194 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9300100f, 0x05050505,
195 0x40000000, 0x00000000, 0x08A, 0x000FE186, 0x9300100f, 0x00000000,
196 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9300200f, 0x00000000,
197 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9000100f, 0x0a0a0a0a,
198 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9000100f, 0x05050505,
199 0x40000000, 0x00000000, 0x08A, 0x000FE186, 0x9000100f, 0x00000000,
200 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9000200f, 0x00000000,
201 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9300200c, 0x00000000,
202 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x93012100, 0x00000000,
203 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x93002100, 0x00000000,
204 0x40000000, 0x00000000, 0x08A, 0x000FE186, 0xA0000000, 0x00000000,
205 0x08A, 0x000FF186, 0xB0000000, 0x00000000, 0x08B, 0x00061E3C,
206 0x08C, 0x000112C7, 0x08D, 0x000F4988, 0x08E, 0x00064D40,
207 0x0EF, 0x00020000, 0x033, 0x00000007, 0x8300100f, 0x0a0a0a0a,
208 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300100f, 0x05050505,
209 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9300100f, 0x00000000,
210 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200f, 0x00000000,
211 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x0a0a0a0a,
212 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x05050505,
213 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x00000000,
214 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000200f, 0x00000000,
215 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200c, 0x00000000,
216 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x93012100, 0x00000000,
217 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93002100, 0x00000000,
218 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93011000, 0x00000000,
219 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x9000200c, 0x00000000,
220 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x90001004, 0x00000000,
221 0x40000000, 0x00000000, 0x03E, 0x00004040, 0xA0000000, 0x00000000,
222 0x03E, 0x00004000, 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a,
223 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x05050505,
224 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x00000000,
225 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200f, 0x00000000,
226 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x0a0a0a0a,
227 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x05050505,
228 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x00000000,
229 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200f, 0x00000000,
230 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200c, 0x00000000,
231 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93012100, 0x00000000,
232 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002100, 0x00000000,
233 0x40000000, 0x00000000, 0x03F, 0x000DFF86, 0x93011000, 0x00000000,
234 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200c, 0x00000000,
235 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x90001004, 0x00000000,
236 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002000, 0x00000000,
237 0x40000000, 0x00000000, 0x03F, 0x000C0006, 0x93001000, 0x00000000,
238 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0xA0000000, 0x00000000,
239 0x03F, 0x000C3186, 0xB0000000, 0x00000000, 0x033, 0x00000006,
240 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004080,
241 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
242 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004080,
243 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004080,
244 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004080,
245 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004040,
246 0xA0000000, 0x00000000, 0x03E, 0x00004080, 0xB0000000, 0x00000000,
247 0x03F, 0x000C3186, 0x033, 0x00000005, 0x8300100f, 0x0a0a0a0a,
248 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9300100f, 0x05050505,
249 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9300100f, 0x00000000,
250 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9300200f, 0x00000000,
251 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9000100f, 0x0a0a0a0a,
252 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9000100f, 0x05050505,
253 0x40000000, 0x00000000, 0x03E, 0x00004084, 0xA0000000, 0x00000000,
254 0x03E, 0x000040C8, 0xB0000000, 0x00000000, 0x03F, 0x000C3186,
255 0x033, 0x00000004, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
256 0x03E, 0x00004190, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
257 0x03E, 0x00004190, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
258 0x03E, 0x00004190, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
259 0x03E, 0x00004190, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
260 0x03E, 0x00004190, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
261 0x03E, 0x00004108, 0xA0000000, 0x00000000, 0x03E, 0x00004190,
262 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000003,
263 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004998,
264 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004998,
265 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004998,
266 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004998,
267 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004998,
268 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x0000490C,
269 0xA0000000, 0x00000000, 0x03E, 0x00004998, 0xB0000000, 0x00000000,
270 0x03F, 0x000C3186, 0x033, 0x00000002, 0x8300100f, 0x0a0a0a0a,
271 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9300100f, 0x05050505,
272 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9300100f, 0x00000000,
273 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9300200f, 0x00000000,
274 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9000100f, 0x0a0a0a0a,
275 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9000100f, 0x05050505,
276 0x40000000, 0x00000000, 0x03E, 0x00005E00, 0xA0000000, 0x00000000,
277 0x03E, 0x00005840, 0xB0000000, 0x00000000, 0x03F, 0x000C3186,
278 0x033, 0x00000001, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
279 0x03E, 0x000058C2, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
280 0x03E, 0x000058C2, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
281 0x03E, 0x000058C2, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
282 0x03E, 0x000058C2, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
283 0x03E, 0x000058C2, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
284 0x03E, 0x00005862, 0xA0000000, 0x00000000, 0x03E, 0x000058C2,
285 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000000,
286 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00005930,
287 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00005930,
288 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00005930,
289 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00005930,
290 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00005930,
291 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00005948,
292 0xA0000000, 0x00000000, 0x03E, 0x00005930, 0xB0000000, 0x00000000,
293 0x03F, 0x000C3186, 0x033, 0x0000000F, 0x8300100f, 0x0a0a0a0a,
294 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300100f, 0x05050505,
295 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9300100f, 0x00000000,
296 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200f, 0x00000000,
297 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x0a0a0a0a,
298 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x05050505,
299 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9000100f, 0x00000000,
300 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000200f, 0x00000000,
301 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200c, 0x00000000,
302 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x93012100, 0x00000000,
303 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93002100, 0x00000000,
304 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93011000, 0x00000000,
305 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x9000200c, 0x00000000,
306 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x90001004, 0x00000000,
307 0x40000000, 0x00000000, 0x03E, 0x00004040, 0xA0000000, 0x00000000,
308 0x03E, 0x00004000, 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a,
309 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x05050505,
310 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x00000000,
311 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200f, 0x00000000,
312 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x0a0a0a0a,
313 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x05050505,
314 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x00000000,
315 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200f, 0x00000000,
316 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200c, 0x00000000,
317 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93012100, 0x00000000,
318 0x40000000, 0x00000000, 0x03F, 0x000DFF86, 0x93002100, 0x00000000,
319 0x40000000, 0x00000000, 0x03F, 0x000DFF86, 0x93011000, 0x00000000,
320 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200c, 0x00000000,
321 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x90001004, 0x00000000,
322 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002000, 0x00000000,
323 0x40000000, 0x00000000, 0x03F, 0x000C0006, 0x93001000, 0x00000000,
324 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0xA0000000, 0x00000000,
325 0x03F, 0x000C3186, 0xB0000000, 0x00000000, 0x033, 0x0000000E,
326 0x03E, 0x00004080, 0x03F, 0x000C3186, 0x033, 0x0000000D,
327 0x03E, 0x000040C8, 0x03F, 0x000C3186, 0x033, 0x0000000C,
328 0x03E, 0x00004190, 0x03F, 0x000C3186, 0x033, 0x0000000B,
329 0x03E, 0x00004998, 0x03F, 0x000C3186, 0x033, 0x0000000A,
330 0x03E, 0x00005840, 0x03F, 0x000C3186, 0x033, 0x00000009,
331 0x03E, 0x000058C2, 0x03F, 0x000C3186, 0x033, 0x00000008,
332 0x03E, 0x00005930, 0x03F, 0x000C3186, 0x033, 0x00000017,
333 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004040,
334 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
335 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
336 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
337 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004040,
338 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
339 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
340 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
341 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
342 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
343 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
344 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
345 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
346 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
347 0xA0000000, 0x00000000, 0x03E, 0x00004000, 0xB0000000, 0x00000000,
348 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
349 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
350 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
351 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
352 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
353 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
354 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
355 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
356 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
357 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
358 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
359 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
360 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
361 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
362 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C0006,
363 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
364 0xA0000000, 0x00000000, 0x03F, 0x000C3186, 0xB0000000, 0x00000000,
365 0x033, 0x00000016, 0x03E, 0x00004080, 0x03F, 0x000C3186,
366 0x033, 0x00000015, 0x03E, 0x000040C8, 0x03F, 0x000C3186,
367 0x033, 0x00000014, 0x03E, 0x00004190, 0x03F, 0x000C3186,
368 0x033, 0x00000013, 0x03E, 0x00004998, 0x03F, 0x000C3186,
369 0x033, 0x00000012, 0x03E, 0x00005840, 0x03F, 0x000C3186,
370 0x033, 0x00000011, 0x03E, 0x000058C2, 0x03F, 0x000C3186,
371 0x033, 0x00000010, 0x03E, 0x00005930, 0x03F, 0x000C3186,
372 0x0EF, 0x00000000, 0x0EF, 0x00004000, 0x033, 0x00000000,
373 0x03F, 0x0000000A, 0x033, 0x00000001, 0x8300100f, 0x0a0a0a0a,
374 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300100f, 0x05050505,
375 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300100f, 0x00000000,
376 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300200f, 0x00000000,
377 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x0a0a0a0a,
378 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x05050505,
379 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x00000000,
380 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000200f, 0x00000000,
381 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300200c, 0x00000000,
382 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93012100, 0x00000000,
383 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x93002100, 0x00000000,
384 0x40000000, 0x00000000, 0x03F, 0x00000006, 0x93011000, 0x00000000,
385 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x9000200c, 0x00000000,
386 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90001004, 0x00000000,
387 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93002000, 0x00000000,
388 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93001000, 0x00000000,
389 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x90002100, 0x00000000,
390 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90002000, 0x00000000,
391 0x40000000, 0x00000000, 0x03F, 0x00000000, 0xA0000000, 0x00000000,
392 0x03F, 0x00000005, 0xB0000000, 0x00000000, 0x033, 0x00000002,
393 0x03F, 0x00000000, 0x0EF, 0x00000000, 0x018, 0x00000401,
394 0x084, 0x00001209, 0x086, 0x000001A0, 0x8300100f, 0x0a0a0a0a,
395 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300100f, 0x05050505,
396 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300100f, 0x00000000,
397 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300200f, 0x00000000,
398 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x0a0a0a0a,
399 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x05050505,
400 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x00000000,
401 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000200f, 0x00000000,
402 0x40000000, 0x00000000, 0x087, 0x00068080, 0xA0000000, 0x00000000,
403 0x087, 0x000E8180, 0xB0000000, 0x00000000, 0x088, 0x00070020,
404 0x0DE, 0x00000010, 0x0EF, 0x00008000, 0x033, 0x0000000F,
405 0x03F, 0x0000003C, 0x033, 0x0000000E, 0x03F, 0x00000038,
406 0x033, 0x0000000D, 0x03F, 0x00000030, 0x033, 0x0000000C,
407 0x03F, 0x00000028, 0x033, 0x0000000B, 0x03F, 0x00000020,
408 0x033, 0x0000000A, 0x03F, 0x00000018, 0x033, 0x00000009,
409 0x03F, 0x00000010, 0x033, 0x00000008, 0x03F, 0x00000008,
410 0x033, 0x00000007, 0x03F, 0x0000003C, 0x033, 0x00000006,
411 0x03F, 0x00000038, 0x033, 0x00000005, 0x03F, 0x00000030,
412 0x033, 0x00000004, 0x03F, 0x00000028, 0x033, 0x00000003,
413 0x03F, 0x00000020, 0x033, 0x00000002, 0x03F, 0x00000018,
414 0x033, 0x00000001, 0x03F, 0x00000010, 0x033, 0x00000000,
415 0x03F, 0x00000008, 0x0EF, 0x00000000, 0x0B8, 0x00080A00,
416 0x0B0, 0x000FF0FA, 0x0FE, 0x00000000, 0x0CA, 0x00080000,
417 0x0C9, 0x0001C141, 0x0FE, 0x00000000, 0x0B0, 0x000FF0F8,
418 0x018, 0x00018D24, 0xFFE, 0x00000000, 0xFFE, 0x00000000,
419 0xFFE, 0x00000000, 0xFFE, 0x00000000, 0x018, 0x00010D24,
420 0x01B, 0x00075A40, 0x0EE, 0x00000002, 0x033, 0x00000000,
421 0x03F, 0x00000004, 0x033, 0x00000001, 0x03F, 0x00000004,
422 0x033, 0x00000002, 0x03F, 0x00000004, 0x033, 0x00000003,
423 0x03F, 0x00000004, 0x033, 0x00000004, 0x03F, 0x00000004,
424 0x033, 0x00000005, 0x03F, 0x00000006, 0x033, 0x00000006,
425 0x03F, 0x00000002, 0x033, 0x00000007, 0x03F, 0x00000000,
426 0x0EE, 0x00000000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
427 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062,
428 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x061, 0x0005D4A0,
429 0x062, 0x0000D203, 0x063, 0x00000062, 0x9300100f, 0x00000000,
430 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203,
431 0x063, 0x00000062, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
432 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000062,
433 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x061, 0x0005D4A0,
434 0x062, 0x0000D203, 0x063, 0x00000062, 0x9000100f, 0x05050505,
435 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203,
436 0x063, 0x00000062, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
437 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062,
438 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1,
439 0x062, 0x0000D3A2, 0x063, 0x00000062, 0x9300200c, 0x00000000,
440 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2,
441 0x063, 0x00000062, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
442 0x061, 0x0005D301, 0x062, 0x0000D303, 0x063, 0x00000002,
443 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D301,
444 0x062, 0x0000D303, 0x063, 0x00000002, 0x93011000, 0x00000000,
445 0x40000000, 0x00000000, 0x061, 0x0005D3D1, 0x062, 0x0000D3A2,
446 0x063, 0x00000002, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
447 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000062,
448 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D3D1,
449 0x062, 0x0000D3A2, 0x063, 0x00000002, 0x93002000, 0x00000000,
450 0x40000000, 0x00000000, 0x061, 0x0005D301, 0x062, 0x0000D303,
451 0x063, 0x00000002, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
452 0x061, 0x0005D3D1, 0x062, 0x0000D3A2, 0x063, 0x00000002,
453 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D301,
454 0x062, 0x0000D303, 0x063, 0x00000002, 0x90002000, 0x00000000,
455 0x40000000, 0x00000000, 0x061, 0x0005D301, 0x062, 0x0000D303,
456 0x063, 0x00000002, 0xA0000000, 0x00000000, 0x061, 0x0005D3D0,
457 0x062, 0x0000D303, 0x063, 0x00000002, 0xB0000000, 0x00000000,
458 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
459 0x030, 0x000004A3, 0x030, 0x000014A3, 0x030, 0x000024A3,
460 0x030, 0x000034A3, 0x030, 0x000044A3, 0x030, 0x000054A3,
461 0x030, 0x000064A3, 0x030, 0x000074A3, 0x030, 0x000084A3,
462 0x030, 0x000094A3, 0x030, 0x0000A4A3, 0x030, 0x0000B4A3,
463 0x0EF, 0x00000000, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
464 0x0EF, 0x00000200, 0x030, 0x000004A3, 0x030, 0x000014A3,
465 0x030, 0x000024A3, 0x030, 0x000034A3, 0x030, 0x000044A3,
466 0x030, 0x000054A3, 0x030, 0x000064A3, 0x030, 0x000074A3,
467 0x030, 0x000084A3, 0x030, 0x000094A3, 0x030, 0x0000A4A3,
468 0x030, 0x0000B4A3, 0x0EF, 0x00000000, 0x9300100f, 0x00000000,
469 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000004A3,
470 0x030, 0x000014A3, 0x030, 0x000024A3, 0x030, 0x000034A3,
471 0x030, 0x000044A3, 0x030, 0x000054A3, 0x030, 0x000064A3,
472 0x030, 0x000074A3, 0x030, 0x000084A3, 0x030, 0x000094A3,
473 0x030, 0x0000A4A3, 0x030, 0x0000B4A3, 0x0EF, 0x00000000,
474 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
475 0x030, 0x000002A6, 0x030, 0x000012A6, 0x030, 0x000022A6,
476 0x030, 0x000032A6, 0x030, 0x000042A6, 0x030, 0x000052A6,
477 0x030, 0x000062A6, 0x030, 0x000072A6, 0x030, 0x000082A6,
478 0x030, 0x000092A6, 0x030, 0x0000A2A6, 0x030, 0x0000B2A6,
479 0x0EF, 0x00000000, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
480 0x0EF, 0x00000200, 0x030, 0x000004A0, 0x030, 0x000014A0,
481 0x030, 0x000024A0, 0x030, 0x000034A0, 0x030, 0x000044A0,
482 0x030, 0x000054A0, 0x030, 0x000064A0, 0x030, 0x000074A0,
483 0x030, 0x000084A0, 0x030, 0x000094A0, 0x030, 0x0000A4A0,
484 0x030, 0x0000B4A0, 0x0EF, 0x00000000, 0x9000100f, 0x05050505,
485 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000004A0,
486 0x030, 0x000014A0, 0x030, 0x000024A0, 0x030, 0x000034A0,
487 0x030, 0x000044A0, 0x030, 0x000054A0, 0x030, 0x000064A0,
488 0x030, 0x000074A0, 0x030, 0x000084A0, 0x030, 0x000094A0,
489 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, 0x0EF, 0x00000000,
490 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
491 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0,
492 0x030, 0x000034A0, 0x030, 0x000044A0, 0x030, 0x000054A0,
493 0x030, 0x000064A0, 0x030, 0x000074A0, 0x030, 0x000084A0,
494 0x030, 0x000094A0, 0x030, 0x0000A4A0, 0x030, 0x0000B4A0,
495 0x0EF, 0x00000000, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
496 0x0EF, 0x00000200, 0x030, 0x000002A1, 0x030, 0x000012A1,
497 0x030, 0x000022A1, 0x030, 0x000032A1, 0x030, 0x000042A1,
498 0x030, 0x000052A1, 0x030, 0x000062A1, 0x030, 0x000072A1,
499 0x030, 0x000082A1, 0x030, 0x000092A1, 0x030, 0x0000A2A1,
500 0x030, 0x0000B2A1, 0x0EF, 0x00000000, 0x9300200c, 0x00000000,
501 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000002A6,
502 0x030, 0x000012A6, 0x030, 0x000022A6, 0x030, 0x000032A6,
503 0x030, 0x000042A6, 0x030, 0x000052A6, 0x030, 0x000062A6,
504 0x030, 0x000072A6, 0x030, 0x000082A6, 0x030, 0x000092A6,
505 0x030, 0x0000A2A6, 0x030, 0x0000B2A6, 0x0EF, 0x00000000,
506 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
507 0x030, 0x00000384, 0x030, 0x00001384, 0x030, 0x00002384,
508 0x030, 0x00003384, 0x030, 0x00004425, 0x030, 0x00005425,
509 0x030, 0x00006425, 0x030, 0x00007425, 0x030, 0x000083A4,
510 0x030, 0x000093A4, 0x030, 0x0000A3A4, 0x030, 0x0000B3A4,
511 0x0EF, 0x00000000, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
512 0x0EF, 0x00000200, 0x030, 0x000003A3, 0x030, 0x000013A3,
513 0x030, 0x000023A3, 0x030, 0x000033A3, 0x030, 0x00004355,
514 0x030, 0x00005355, 0x030, 0x00006355, 0x030, 0x00007355,
515 0x030, 0x00008314, 0x030, 0x00009314, 0x030, 0x0000A314,
516 0x030, 0x0000B314, 0x0EF, 0x00000000, 0x93011000, 0x00000000,
517 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000003A1,
518 0x030, 0x000013A1, 0x030, 0x000023A1, 0x030, 0x000033A1,
519 0x030, 0x000043A3, 0x030, 0x000053A3, 0x030, 0x000063A3,
520 0x030, 0x000073A3, 0x030, 0x000083A5, 0x030, 0x000093A5,
521 0x030, 0x0000A3A5, 0x030, 0x0000B3A5, 0x0EF, 0x00000000,
522 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
523 0x030, 0x000002A1, 0x030, 0x000012A1, 0x030, 0x000022A1,
524 0x030, 0x000032A1, 0x030, 0x000042A1, 0x030, 0x000052A1,
525 0x030, 0x000062A1, 0x030, 0x000072A1, 0x030, 0x000082A1,
526 0x030, 0x000092A1, 0x030, 0x0000A2A1, 0x030, 0x0000B2A1,
527 0x0EF, 0x00000000, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
528 0x0EF, 0x00000200, 0x030, 0x00000463, 0x030, 0x00001463,
529 0x030, 0x00002463, 0x030, 0x00003463, 0x030, 0x00004545,
530 0x030, 0x00005545, 0x030, 0x00006545, 0x030, 0x00007545,
531 0x030, 0x00008565, 0x030, 0x00009565, 0x030, 0x0000A565,
532 0x030, 0x0000B565, 0x0EF, 0x00000000, 0x93002000, 0x00000000,
533 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x00000303,
534 0x030, 0x00001303, 0x030, 0x00002303, 0x030, 0x00003303,
535 0x030, 0x000043A4, 0x030, 0x000053A4, 0x030, 0x000063A4,
536 0x030, 0x000073A4, 0x030, 0x00008365, 0x030, 0x00009365,
537 0x030, 0x0000A365, 0x030, 0x0000B365, 0x0EF, 0x00000000,
538 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
539 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
540 0x030, 0x000033A2, 0x030, 0x00004343, 0x030, 0x00005343,
541 0x030, 0x00006343, 0x030, 0x00007343, 0x030, 0x00008364,
542 0x030, 0x00009364, 0x030, 0x0000A364, 0x030, 0x0000B364,
543 0x0EF, 0x00000000, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
544 0x0EF, 0x00000200, 0x030, 0x000003A0, 0x030, 0x000013A0,
545 0x030, 0x000023A0, 0x030, 0x000033A0, 0x030, 0x00004430,
546 0x030, 0x00005430, 0x030, 0x00006430, 0x030, 0x00007430,
547 0x030, 0x00008372, 0x030, 0x00009372, 0x030, 0x0000A372,
548 0x030, 0x0000B372, 0x0EF, 0x00000000, 0x90002000, 0x00000000,
549 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000003A0,
550 0x030, 0x000013A0, 0x030, 0x000023A0, 0x030, 0x000033A0,
551 0x030, 0x000043A1, 0x030, 0x000053A1, 0x030, 0x000063A1,
552 0x030, 0x000073A1, 0x030, 0x000083A2, 0x030, 0x000093A2,
553 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x0EF, 0x00000000,
554 0xA0000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000003D0,
555 0x030, 0x000013D0, 0x030, 0x000023D0, 0x030, 0x000033D0,
556 0x030, 0x000043D0, 0x030, 0x000053D0, 0x030, 0x000063D0,
557 0x030, 0x000073D0, 0x030, 0x000083D0, 0x030, 0x000093D0,
558 0x030, 0x0000A3D0, 0x030, 0x0000B3D0, 0x0EF, 0x00000000,
559 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
560 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
561 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
562 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
563 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
564 0x030, 0x0000B203, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
565 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
566 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
567 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
568 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
569 0x030, 0x0000B203, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
570 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
571 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
572 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
573 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
574 0x030, 0x0000B203, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
575 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
576 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
577 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
578 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
579 0x030, 0x0000B3A2, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
580 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
581 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
582 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
583 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
584 0x030, 0x0000B203, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
585 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
586 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
587 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
588 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
589 0x030, 0x0000B203, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
590 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
591 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
592 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
593 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
594 0x030, 0x0000B203, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
595 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
596 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
597 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
598 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
599 0x030, 0x0000B3A2, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
600 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
601 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
602 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
603 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
604 0x030, 0x0000B3A2, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
605 0x0EF, 0x00000080, 0x030, 0x000003A3, 0x030, 0x000013A3,
606 0x030, 0x000023A3, 0x030, 0x000033A3, 0x030, 0x000043A3,
607 0x030, 0x000053A3, 0x030, 0x000063A3, 0x030, 0x000073A3,
608 0x030, 0x000083A3, 0x030, 0x000093A3, 0x030, 0x0000A3A3,
609 0x030, 0x0000B3A3, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
610 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
611 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
612 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
613 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
614 0x030, 0x0000B3A2, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
615 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
616 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
617 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
618 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
619 0x030, 0x0000B3A2, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
620 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
621 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
622 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
623 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
624 0x030, 0x0000B3A2, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
625 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
626 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
627 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
628 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
629 0x030, 0x0000B3A2, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
630 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
631 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
632 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
633 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
634 0x030, 0x0000B3A2, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
635 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
636 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
637 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
638 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
639 0x030, 0x0000B3A2, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
640 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
641 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
642 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
643 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
644 0x030, 0x0000B3A2, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
645 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
646 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
647 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
648 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
649 0x030, 0x0000B3A2, 0xA0000000, 0x00000000, 0x0EF, 0x00000080,
650 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
651 0x030, 0x000033A2, 0x030, 0x000043A2, 0x030, 0x000053A2,
652 0x030, 0x000063A2, 0x030, 0x000073A2, 0x030, 0x000083A2,
653 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
654 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x8300100f, 0x0a0a0a0a,
655 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
656 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
657 0x030, 0x00005000, 0x030, 0x00006000, 0x9300100f, 0x05050505,
658 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
659 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
660 0x030, 0x00005000, 0x030, 0x00006000, 0x9300100f, 0x00000000,
661 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
662 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
663 0x030, 0x00005000, 0x030, 0x00006000, 0x9300200f, 0x00000000,
664 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
665 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004777,
666 0x030, 0x00005777, 0x030, 0x00006777, 0x9000100f, 0x0a0a0a0a,
667 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
668 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
669 0x030, 0x00005000, 0x030, 0x00006000, 0x9000100f, 0x05050505,
670 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
671 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
672 0x030, 0x00005000, 0x030, 0x00006000, 0x9000100f, 0x00000000,
673 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
674 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
675 0x030, 0x00005000, 0x030, 0x00006000, 0x9000200f, 0x00000000,
676 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
677 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
678 0x030, 0x00005000, 0x030, 0x00006000, 0x9300200c, 0x00000000,
679 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
680 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004777,
681 0x030, 0x00005777, 0x030, 0x00006777, 0x93012100, 0x00000000,
682 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000660,
683 0x030, 0x00001443, 0x030, 0x00002221, 0x030, 0x00004777,
684 0x030, 0x00005777, 0x030, 0x00006777, 0x93002100, 0x00000000,
685 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000776,
686 0x030, 0x00001455, 0x030, 0x00002325, 0x030, 0x00004777,
687 0x030, 0x00005777, 0x030, 0x00006777, 0x93011000, 0x00000000,
688 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000764,
689 0x030, 0x00001632, 0x030, 0x00002421, 0x030, 0x00004000,
690 0x030, 0x00005000, 0x030, 0x00006000, 0x9000200c, 0x00000000,
691 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
692 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
693 0x030, 0x00005000, 0x030, 0x00006000, 0x90001004, 0x00000000,
694 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000764,
695 0x030, 0x00001632, 0x030, 0x00002421, 0x030, 0x00004000,
696 0x030, 0x00005000, 0x030, 0x00006000, 0x93002000, 0x00000000,
697 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000777,
698 0x030, 0x00001442, 0x030, 0x00002222, 0x030, 0x00004777,
699 0x030, 0x00005777, 0x030, 0x00006777, 0x93001000, 0x00000000,
700 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000764,
701 0x030, 0x00001632, 0x030, 0x00002421, 0x030, 0x00004000,
702 0x030, 0x00005000, 0x030, 0x00006000, 0x90002100, 0x00000000,
703 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000775,
704 0x030, 0x00001343, 0x030, 0x00002210, 0x030, 0x00004000,
705 0x030, 0x00005000, 0x030, 0x00006000, 0x90002000, 0x00000000,
706 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000775,
707 0x030, 0x00001422, 0x030, 0x00002210, 0x030, 0x00004000,
708 0x030, 0x00005000, 0x030, 0x00006000, 0xA0000000, 0x00000000,
709 0x0EF, 0x00000040, 0x030, 0x00000764, 0x030, 0x00001632,
710 0x030, 0x00002421, 0x030, 0x00004000, 0x030, 0x00005000,
711 0x030, 0x00006000, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
712 0x0EF, 0x00000800, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
713 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
714 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
715 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
716 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
717 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
718 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
719 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
720 0x03F, 0x000000F3, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
721 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
722 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
723 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
724 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
725 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
726 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
727 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
728 0x03F, 0x000000F3, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
729 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
730 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
731 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
732 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
733 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
734 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
735 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
736 0x03F, 0x000000F3, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
737 0x033, 0x00000020, 0x03F, 0x00000005, 0x033, 0x00000021,
738 0x03F, 0x00000008, 0x033, 0x00000022, 0x03F, 0x0000000B,
739 0x033, 0x00000023, 0x03F, 0x0000000E, 0x033, 0x00000024,
740 0x03F, 0x0000002B, 0x033, 0x00000025, 0x03F, 0x00000068,
741 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027,
742 0x03F, 0x0000006E, 0x033, 0x00000028, 0x03F, 0x00000071,
743 0x033, 0x00000029, 0x03F, 0x00000074, 0x033, 0x0000002A,
744 0x03F, 0x00000077, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
745 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
746 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
747 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
748 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
749 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
750 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
751 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
752 0x03F, 0x000000F3, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
753 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
754 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
755 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
756 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
757 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
758 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
759 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
760 0x03F, 0x000000F3, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
761 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
762 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
763 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
764 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
765 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
766 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
767 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
768 0x03F, 0x000000F3, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
769 0x033, 0x00000020, 0x03F, 0x00000005, 0x033, 0x00000021,
770 0x03F, 0x00000008, 0x033, 0x00000022, 0x03F, 0x0000000B,
771 0x033, 0x00000023, 0x03F, 0x0000000E, 0x033, 0x00000024,
772 0x03F, 0x0000002B, 0x033, 0x00000025, 0x03F, 0x00000068,
773 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027,
774 0x03F, 0x0000006E, 0x033, 0x00000028, 0x03F, 0x00000071,
775 0x033, 0x00000029, 0x03F, 0x00000074, 0x033, 0x0000002A,
776 0x03F, 0x00000077, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
777 0x033, 0x00000020, 0x03F, 0x00000005, 0x033, 0x00000021,
778 0x03F, 0x00000008, 0x033, 0x00000022, 0x03F, 0x0000000B,
779 0x033, 0x00000023, 0x03F, 0x0000000E, 0x033, 0x00000024,
780 0x03F, 0x0000002B, 0x033, 0x00000025, 0x03F, 0x00000068,
781 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027,
782 0x03F, 0x0000006E, 0x033, 0x00000028, 0x03F, 0x00000071,
783 0x033, 0x00000029, 0x03F, 0x00000074, 0x033, 0x0000002A,
784 0x03F, 0x00000077, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
785 0x033, 0x00000020, 0x03F, 0x00000C0C, 0x033, 0x00000021,
786 0x03F, 0x00000C29, 0x033, 0x00000022, 0x03F, 0x00000C2C,
787 0x033, 0x00000023, 0x03F, 0x00000C69, 0x033, 0x00000024,
788 0x03F, 0x00000CA8, 0x033, 0x00000025, 0x03F, 0x00000CE8,
789 0x033, 0x00000026, 0x03F, 0x00000CEB, 0x033, 0x00000027,
790 0x03F, 0x00000CEE, 0x033, 0x00000028, 0x03F, 0x00000CF1,
791 0x033, 0x00000029, 0x03F, 0x00000CF4, 0x033, 0x0000002A,
792 0x03F, 0x00000CF7, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
793 0x033, 0x00000020, 0x03F, 0x0000042B, 0x033, 0x00000021,
794 0x03F, 0x0000082A, 0x033, 0x00000022, 0x03F, 0x00000849,
795 0x033, 0x00000023, 0x03F, 0x0000084C, 0x033, 0x00000024,
796 0x03F, 0x00000C4C, 0x033, 0x00000025, 0x03F, 0x00000CA9,
797 0x033, 0x00000026, 0x03F, 0x00000CEA, 0x033, 0x00000027,
798 0x03F, 0x00000CED, 0x033, 0x00000028, 0x03F, 0x00000CF0,
799 0x033, 0x00000029, 0x03F, 0x00000CF3, 0x033, 0x0000002A,
800 0x03F, 0x00000CF6, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
801 0x033, 0x00000020, 0x03F, 0x00000C09, 0x033, 0x00000021,
802 0x03F, 0x00000C0C, 0x033, 0x00000022, 0x03F, 0x00000C0F,
803 0x033, 0x00000023, 0x03F, 0x00000C2C, 0x033, 0x00000024,
804 0x03F, 0x00000C2F, 0x033, 0x00000025, 0x03F, 0x00000C8A,
805 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
806 0x03F, 0x00000C90, 0x033, 0x00000028, 0x03F, 0x00000CD0,
807 0x033, 0x00000029, 0x03F, 0x00000CF2, 0x033, 0x0000002A,
808 0x03F, 0x00000CF5, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
809 0x033, 0x00000020, 0x03F, 0x00000005, 0x033, 0x00000021,
810 0x03F, 0x00000008, 0x033, 0x00000022, 0x03F, 0x0000000B,
811 0x033, 0x00000023, 0x03F, 0x0000000E, 0x033, 0x00000024,
812 0x03F, 0x0000002B, 0x033, 0x00000025, 0x03F, 0x00000068,
813 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027,
814 0x03F, 0x0000006E, 0x033, 0x00000028, 0x03F, 0x00000071,
815 0x033, 0x00000029, 0x03F, 0x00000074, 0x033, 0x0000002A,
816 0x03F, 0x00000077, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
817 0x033, 0x00000020, 0x03F, 0x00000C09, 0x033, 0x00000021,
818 0x03F, 0x00000C0C, 0x033, 0x00000022, 0x03F, 0x00000C0F,
819 0x033, 0x00000023, 0x03F, 0x00000C2C, 0x033, 0x00000024,
820 0x03F, 0x00000C2F, 0x033, 0x00000025, 0x03F, 0x00000C8A,
821 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
822 0x03F, 0x00000C90, 0x033, 0x00000028, 0x03F, 0x00000CD0,
823 0x033, 0x00000029, 0x03F, 0x00000CF2, 0x033, 0x0000002A,
824 0x03F, 0x00000CF5, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
825 0x033, 0x00000020, 0x03F, 0x00000429, 0x033, 0x00000021,
826 0x03F, 0x00000828, 0x033, 0x00000022, 0x03F, 0x00000847,
827 0x033, 0x00000023, 0x03F, 0x0000084A, 0x033, 0x00000024,
828 0x03F, 0x00000C4B, 0x033, 0x00000025, 0x03F, 0x00000C8A,
829 0x033, 0x00000026, 0x03F, 0x00000CEA, 0x033, 0x00000027,
830 0x03F, 0x00000CED, 0x033, 0x00000028, 0x03F, 0x00000CF0,
831 0x033, 0x00000029, 0x03F, 0x00000CF3, 0x033, 0x0000002A,
832 0x03F, 0x00000CF6, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
833 0x033, 0x00000020, 0x03F, 0x00000C09, 0x033, 0x00000021,
834 0x03F, 0x00000C0C, 0x033, 0x00000022, 0x03F, 0x00000C0F,
835 0x033, 0x00000023, 0x03F, 0x00000C2C, 0x033, 0x00000024,
836 0x03F, 0x00000C2F, 0x033, 0x00000025, 0x03F, 0x00000C8A,
837 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
838 0x03F, 0x00000C90, 0x033, 0x00000028, 0x03F, 0x00000CD0,
839 0x033, 0x00000029, 0x03F, 0x00000CF2, 0x033, 0x0000002A,
840 0x03F, 0x00000CF5, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
841 0x033, 0x00000020, 0x03F, 0x0000042B, 0x033, 0x00000021,
842 0x03F, 0x0000082A, 0x033, 0x00000022, 0x03F, 0x00000849,
843 0x033, 0x00000023, 0x03F, 0x0000084C, 0x033, 0x00000024,
844 0x03F, 0x00000C4C, 0x033, 0x00000025, 0x03F, 0x00000C8A,
845 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
846 0x03F, 0x00000CEB, 0x033, 0x00000028, 0x03F, 0x00000CEE,
847 0x033, 0x00000029, 0x03F, 0x00000CF1, 0x033, 0x0000002A,
848 0x03F, 0x00000CF4, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
849 0x033, 0x00000020, 0x03F, 0x0000042B, 0x033, 0x00000021,
850 0x03F, 0x0000082A, 0x033, 0x00000022, 0x03F, 0x00000849,
851 0x033, 0x00000023, 0x03F, 0x0000084C, 0x033, 0x00000024,
852 0x03F, 0x00000C4C, 0x033, 0x00000025, 0x03F, 0x00000C8A,
853 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
854 0x03F, 0x00000CEB, 0x033, 0x00000028, 0x03F, 0x00000CEE,
855 0x033, 0x00000029, 0x03F, 0x00000CF1, 0x033, 0x0000002A,
856 0x03F, 0x00000CF4, 0xA0000000, 0x00000000, 0x033, 0x00000020,
857 0x03F, 0x00000C09, 0x033, 0x00000021, 0x03F, 0x00000C0C,
858 0x033, 0x00000022, 0x03F, 0x00000C0F, 0x033, 0x00000023,
859 0x03F, 0x00000C2C, 0x033, 0x00000024, 0x03F, 0x00000C2F,
860 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
861 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000C90,
862 0x033, 0x00000028, 0x03F, 0x00000CD0, 0x033, 0x00000029,
863 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5,
864 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
865 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
866 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
867 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
868 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
869 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
870 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
871 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
872 0x03F, 0x000000F3, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
873 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
874 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
875 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
876 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
877 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
878 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
879 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
880 0x03F, 0x000000F3, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
881 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
882 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
883 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
884 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
885 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
886 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
887 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
888 0x03F, 0x000000F3, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
889 0x033, 0x00000060, 0x03F, 0x00000005, 0x033, 0x00000061,
890 0x03F, 0x00000008, 0x033, 0x00000062, 0x03F, 0x0000000B,
891 0x033, 0x00000063, 0x03F, 0x0000000E, 0x033, 0x00000064,
892 0x03F, 0x0000002B, 0x033, 0x00000065, 0x03F, 0x00000068,
893 0x033, 0x00000066, 0x03F, 0x0000006B, 0x033, 0x00000067,
894 0x03F, 0x0000006E, 0x033, 0x00000068, 0x03F, 0x00000071,
895 0x033, 0x00000069, 0x03F, 0x00000074, 0x033, 0x0000006A,
896 0x03F, 0x00000077, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
897 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
898 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
899 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
900 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
901 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
902 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
903 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
904 0x03F, 0x000000F3, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
905 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
906 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
907 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
908 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
909 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
910 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
911 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
912 0x03F, 0x000000F3, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
913 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
914 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
915 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
916 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
917 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
918 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
919 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
920 0x03F, 0x000000F3, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
921 0x033, 0x00000060, 0x03F, 0x00000005, 0x033, 0x00000061,
922 0x03F, 0x00000008, 0x033, 0x00000062, 0x03F, 0x0000000B,
923 0x033, 0x00000063, 0x03F, 0x0000000E, 0x033, 0x00000064,
924 0x03F, 0x0000002B, 0x033, 0x00000065, 0x03F, 0x00000068,
925 0x033, 0x00000066, 0x03F, 0x0000006B, 0x033, 0x00000067,
926 0x03F, 0x0000006E, 0x033, 0x00000068, 0x03F, 0x00000071,
927 0x033, 0x00000069, 0x03F, 0x00000074, 0x033, 0x0000006A,
928 0x03F, 0x00000077, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
929 0x033, 0x00000060, 0x03F, 0x00000005, 0x033, 0x00000061,
930 0x03F, 0x00000008, 0x033, 0x00000062, 0x03F, 0x0000000B,
931 0x033, 0x00000063, 0x03F, 0x0000000E, 0x033, 0x00000064,
932 0x03F, 0x0000002B, 0x033, 0x00000065, 0x03F, 0x00000068,
933 0x033, 0x00000066, 0x03F, 0x0000006B, 0x033, 0x00000067,
934 0x03F, 0x0000006E, 0x033, 0x00000068, 0x03F, 0x00000071,
935 0x033, 0x00000069, 0x03F, 0x00000074, 0x033, 0x0000006A,
936 0x03F, 0x00000077, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
937 0x033, 0x00000060, 0x03F, 0x0000080B, 0x033, 0x00000061,
938 0x03F, 0x0000080E, 0x033, 0x00000062, 0x03F, 0x00000848,
939 0x033, 0x00000063, 0x03F, 0x00000869, 0x033, 0x00000064,
940 0x03F, 0x000008A9, 0x033, 0x00000065, 0x03F, 0x00000CE8,
941 0x033, 0x00000066, 0x03F, 0x00000CEB, 0x033, 0x00000067,
942 0x03F, 0x00000CEE, 0x033, 0x00000068, 0x03F, 0x00000CF1,
943 0x033, 0x00000069, 0x03F, 0x00000CF4, 0x033, 0x0000006A,
944 0x03F, 0x00000CF7, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
945 0x033, 0x00000060, 0x03F, 0x0000042B, 0x033, 0x00000061,
946 0x03F, 0x0000082A, 0x033, 0x00000062, 0x03F, 0x00000849,
947 0x033, 0x00000063, 0x03F, 0x0000084C, 0x033, 0x00000064,
948 0x03F, 0x00000C4C, 0x033, 0x00000065, 0x03F, 0x00000CA9,
949 0x033, 0x00000066, 0x03F, 0x00000CEA, 0x033, 0x00000067,
950 0x03F, 0x00000CED, 0x033, 0x00000068, 0x03F, 0x00000CF0,
951 0x033, 0x00000069, 0x03F, 0x00000CF3, 0x033, 0x0000006A,
952 0x03F, 0x00000CF6, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
953 0x033, 0x00000060, 0x03F, 0x00000C0A, 0x033, 0x00000061,
954 0x03F, 0x00000C0D, 0x033, 0x00000062, 0x03F, 0x00000C2A,
955 0x033, 0x00000063, 0x03F, 0x00000C2D, 0x033, 0x00000064,
956 0x03F, 0x00000C6A, 0x033, 0x00000065, 0x03F, 0x00000CAA,
957 0x033, 0x00000066, 0x03F, 0x00000CAD, 0x033, 0x00000067,
958 0x03F, 0x00000CB0, 0x033, 0x00000068, 0x03F, 0x00000CF1,
959 0x033, 0x00000069, 0x03F, 0x00000CF4, 0x033, 0x0000006A,
960 0x03F, 0x00000CF7, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
961 0x033, 0x00000060, 0x03F, 0x00000005, 0x033, 0x00000061,
962 0x03F, 0x00000008, 0x033, 0x00000062, 0x03F, 0x0000000B,
963 0x033, 0x00000063, 0x03F, 0x0000000E, 0x033, 0x00000064,
964 0x03F, 0x0000002B, 0x033, 0x00000065, 0x03F, 0x00000068,
965 0x033, 0x00000066, 0x03F, 0x0000006B, 0x033, 0x00000067,
966 0x03F, 0x0000006E, 0x033, 0x00000068, 0x03F, 0x00000071,
967 0x033, 0x00000069, 0x03F, 0x00000074, 0x033, 0x0000006A,
968 0x03F, 0x00000077, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
969 0x033, 0x00000060, 0x03F, 0x00000C0A, 0x033, 0x00000061,
970 0x03F, 0x00000C0D, 0x033, 0x00000062, 0x03F, 0x00000C2A,
971 0x033, 0x00000063, 0x03F, 0x00000C2D, 0x033, 0x00000064,
972 0x03F, 0x00000C6A, 0x033, 0x00000065, 0x03F, 0x00000CAA,
973 0x033, 0x00000066, 0x03F, 0x00000CAD, 0x033, 0x00000067,
974 0x03F, 0x00000CB0, 0x033, 0x00000068, 0x03F, 0x00000CF1,
975 0x033, 0x00000069, 0x03F, 0x00000CF4, 0x033, 0x0000006A,
976 0x03F, 0x00000CF7, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
977 0x033, 0x00000060, 0x03F, 0x00000429, 0x033, 0x00000061,
978 0x03F, 0x00000828, 0x033, 0x00000062, 0x03F, 0x00000847,
979 0x033, 0x00000063, 0x03F, 0x0000084A, 0x033, 0x00000064,
980 0x03F, 0x00000C4B, 0x033, 0x00000065, 0x03F, 0x00000C8A,
981 0x033, 0x00000066, 0x03F, 0x00000CEA, 0x033, 0x00000067,
982 0x03F, 0x00000CED, 0x033, 0x00000068, 0x03F, 0x00000CF0,
983 0x033, 0x00000069, 0x03F, 0x00000CF3, 0x033, 0x0000006A,
984 0x03F, 0x00000CF6, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
985 0x033, 0x00000060, 0x03F, 0x00000C0A, 0x033, 0x00000061,
986 0x03F, 0x00000C0D, 0x033, 0x00000062, 0x03F, 0x00000C2A,
987 0x033, 0x00000063, 0x03F, 0x00000C2D, 0x033, 0x00000064,
988 0x03F, 0x00000C6A, 0x033, 0x00000065, 0x03F, 0x00000CAA,
989 0x033, 0x00000066, 0x03F, 0x00000CAD, 0x033, 0x00000067,
990 0x03F, 0x00000CB0, 0x033, 0x00000068, 0x03F, 0x00000CF1,
991 0x033, 0x00000069, 0x03F, 0x00000CF4, 0x033, 0x0000006A,
992 0x03F, 0x00000CF7, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
993 0x033, 0x00000060, 0x03F, 0x0000042C, 0x033, 0x00000061,
994 0x03F, 0x0000082B, 0x033, 0x00000062, 0x03F, 0x0000084A,
995 0x033, 0x00000063, 0x03F, 0x0000084D, 0x033, 0x00000064,
996 0x03F, 0x00000C4D, 0x033, 0x00000065, 0x03F, 0x00000C8B,
997 0x033, 0x00000066, 0x03F, 0x00000C8E, 0x033, 0x00000067,
998 0x03F, 0x00000CEC, 0x033, 0x00000068, 0x03F, 0x00000CEF,
999 0x033, 0x00000069, 0x03F, 0x00000CF2, 0x033, 0x0000006A,
1000 0x03F, 0x00000CF5, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
1001 0x033, 0x00000060, 0x03F, 0x0000042C, 0x033, 0x00000061,
1002 0x03F, 0x0000082B, 0x033, 0x00000062, 0x03F, 0x0000084A,
1003 0x033, 0x00000063, 0x03F, 0x0000084D, 0x033, 0x00000064,
1004 0x03F, 0x00000C4D, 0x033, 0x00000065, 0x03F, 0x00000C8B,
1005 0x033, 0x00000066, 0x03F, 0x00000C8E, 0x033, 0x00000067,
1006 0x03F, 0x00000CEC, 0x033, 0x00000068, 0x03F, 0x00000CEF,
1007 0x033, 0x00000069, 0x03F, 0x00000CF2, 0x033, 0x0000006A,
1008 0x03F, 0x00000CF5, 0xA0000000, 0x00000000, 0x033, 0x00000060,
1009 0x03F, 0x00000C0A, 0x033, 0x00000061, 0x03F, 0x00000C0D,
1010 0x033, 0x00000062, 0x03F, 0x00000C2A, 0x033, 0x00000063,
1011 0x03F, 0x00000C2D, 0x033, 0x00000064, 0x03F, 0x00000C6A,
1012 0x033, 0x00000065, 0x03F, 0x00000CAA, 0x033, 0x00000066,
1013 0x03F, 0x00000CAD, 0x033, 0x00000067, 0x03F, 0x00000CB0,
1014 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069,
1015 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7,
1016 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1017 0x033, 0x000000A0, 0x03F, 0x00000007, 0x033, 0x000000A1,
1018 0x03F, 0x0000000A, 0x033, 0x000000A2, 0x03F, 0x0000000D,
1019 0x033, 0x000000A3, 0x03F, 0x0000002A, 0x033, 0x000000A4,
1020 0x03F, 0x0000002D, 0x033, 0x000000A5, 0x03F, 0x00000030,
1021 0x033, 0x000000A6, 0x03F, 0x0000006D, 0x033, 0x000000A7,
1022 0x03F, 0x00000070, 0x033, 0x000000A8, 0x03F, 0x000000ED,
1023 0x033, 0x000000A9, 0x03F, 0x000000F0, 0x033, 0x000000AA,
1024 0x03F, 0x000000F3, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
1025 0x033, 0x000000A0, 0x03F, 0x00000007, 0x033, 0x000000A1,
1026 0x03F, 0x0000000A, 0x033, 0x000000A2, 0x03F, 0x0000000D,
1027 0x033, 0x000000A3, 0x03F, 0x0000002A, 0x033, 0x000000A4,
1028 0x03F, 0x0000002D, 0x033, 0x000000A5, 0x03F, 0x00000030,
1029 0x033, 0x000000A6, 0x03F, 0x0000006D, 0x033, 0x000000A7,
1030 0x03F, 0x00000070, 0x033, 0x000000A8, 0x03F, 0x000000ED,
1031 0x033, 0x000000A9, 0x03F, 0x000000F0, 0x033, 0x000000AA,
1032 0x03F, 0x000000F3, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
1033 0x033, 0x000000A0, 0x03F, 0x00000007, 0x033, 0x000000A1,
1034 0x03F, 0x0000000A, 0x033, 0x000000A2, 0x03F, 0x0000000D,
1035 0x033, 0x000000A3, 0x03F, 0x0000002A, 0x033, 0x000000A4,
1036 0x03F, 0x0000002D, 0x033, 0x000000A5, 0x03F, 0x00000030,
1037 0x033, 0x000000A6, 0x03F, 0x0000006D, 0x033, 0x000000A7,
1038 0x03F, 0x00000070, 0x033, 0x000000A8, 0x03F, 0x000000ED,
1039 0x033, 0x000000A9, 0x03F, 0x000000F0, 0x033, 0x000000AA,
1040 0x03F, 0x000000F3, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
1041 0x033, 0x000000A0, 0x03F, 0x00000005, 0x033, 0x000000A1,
1042 0x03F, 0x00000008, 0x033, 0x000000A2, 0x03F, 0x0000000B,
1043 0x033, 0x000000A3, 0x03F, 0x0000000E, 0x033, 0x000000A4,
1044 0x03F, 0x00000047, 0x033, 0x000000A5, 0x03F, 0x0000004A,
1045 0x033, 0x000000A6, 0x03F, 0x0000004D, 0x033, 0x000000A7,
1046 0x03F, 0x00000050, 0x033, 0x000000A8, 0x03F, 0x00000053,
1047 0x033, 0x000000A9, 0x03F, 0x00000056, 0x033, 0x000000AA,
1048 0x03F, 0x00000094, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1049 0x033, 0x000000A0, 0x03F, 0x00000007, 0x033, 0x000000A1,
1050 0x03F, 0x0000000A, 0x033, 0x000000A2, 0x03F, 0x0000000D,
1051 0x033, 0x000000A3, 0x03F, 0x0000002A, 0x033, 0x000000A4,
1052 0x03F, 0x0000002D, 0x033, 0x000000A5, 0x03F, 0x00000030,
1053 0x033, 0x000000A6, 0x03F, 0x0000006D, 0x033, 0x000000A7,
1054 0x03F, 0x00000070, 0x033, 0x000000A8, 0x03F, 0x000000ED,
1055 0x033, 0x000000A9, 0x03F, 0x000000F0, 0x033, 0x000000AA,
1056 0x03F, 0x000000F3, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
1057 0x033, 0x000000A0, 0x03F, 0x00000007, 0x033, 0x000000A1,
1058 0x03F, 0x0000000A, 0x033, 0x000000A2, 0x03F, 0x0000000D,
1059 0x033, 0x000000A3, 0x03F, 0x0000002A, 0x033, 0x000000A4,
1060 0x03F, 0x0000002D, 0x033, 0x000000A5, 0x03F, 0x00000030,
1061 0x033, 0x000000A6, 0x03F, 0x0000006D, 0x033, 0x000000A7,
1062 0x03F, 0x00000070, 0x033, 0x000000A8, 0x03F, 0x000000ED,
1063 0x033, 0x000000A9, 0x03F, 0x000000F0, 0x033, 0x000000AA,
1064 0x03F, 0x000000F3, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
1065 0x033, 0x000000A0, 0x03F, 0x00000007, 0x033, 0x000000A1,
1066 0x03F, 0x0000000A, 0x033, 0x000000A2, 0x03F, 0x0000000D,
1067 0x033, 0x000000A3, 0x03F, 0x0000002A, 0x033, 0x000000A4,
1068 0x03F, 0x0000002D, 0x033, 0x000000A5, 0x03F, 0x00000030,
1069 0x033, 0x000000A6, 0x03F, 0x0000006D, 0x033, 0x000000A7,
1070 0x03F, 0x00000070, 0x033, 0x000000A8, 0x03F, 0x000000ED,
1071 0x033, 0x000000A9, 0x03F, 0x000000F0, 0x033, 0x000000AA,
1072 0x03F, 0x000000F3, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
1073 0x033, 0x000000A0, 0x03F, 0x00000005, 0x033, 0x000000A1,
1074 0x03F, 0x00000008, 0x033, 0x000000A2, 0x03F, 0x0000000B,
1075 0x033, 0x000000A3, 0x03F, 0x0000000E, 0x033, 0x000000A4,
1076 0x03F, 0x00000047, 0x033, 0x000000A5, 0x03F, 0x0000004A,
1077 0x033, 0x000000A6, 0x03F, 0x0000004D, 0x033, 0x000000A7,
1078 0x03F, 0x00000050, 0x033, 0x000000A8, 0x03F, 0x00000053,
1079 0x033, 0x000000A9, 0x03F, 0x00000056, 0x033, 0x000000AA,
1080 0x03F, 0x00000094, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
1081 0x033, 0x000000A0, 0x03F, 0x00000005, 0x033, 0x000000A1,
1082 0x03F, 0x00000008, 0x033, 0x000000A2, 0x03F, 0x0000000B,
1083 0x033, 0x000000A3, 0x03F, 0x0000000E, 0x033, 0x000000A4,
1084 0x03F, 0x00000047, 0x033, 0x000000A5, 0x03F, 0x0000004A,
1085 0x033, 0x000000A6, 0x03F, 0x0000004D, 0x033, 0x000000A7,
1086 0x03F, 0x00000050, 0x033, 0x000000A8, 0x03F, 0x00000053,
1087 0x033, 0x000000A9, 0x03F, 0x00000056, 0x033, 0x000000AA,
1088 0x03F, 0x00000094, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
1089 0x033, 0x000000A0, 0x03F, 0x00000C0A, 0x033, 0x000000A1,
1090 0x03F, 0x00000C0D, 0x033, 0x000000A2, 0x03F, 0x00000C2A,
1091 0x033, 0x000000A3, 0x03F, 0x00000C2D, 0x033, 0x000000A4,
1092 0x03F, 0x00000C6A, 0x033, 0x000000A5, 0x03F, 0x00000CE8,
1093 0x033, 0x000000A6, 0x03F, 0x00000CEB, 0x033, 0x000000A7,
1094 0x03F, 0x00000CEE, 0x033, 0x000000A8, 0x03F, 0x00000CF1,
1095 0x033, 0x000000A9, 0x03F, 0x00000CF4, 0x033, 0x000000AA,
1096 0x03F, 0x00000CF7, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
1097 0x033, 0x000000A0, 0x03F, 0x0000042A, 0x033, 0x000000A1,
1098 0x03F, 0x00000829, 0x033, 0x000000A2, 0x03F, 0x00000848,
1099 0x033, 0x000000A3, 0x03F, 0x0000084B, 0x033, 0x000000A4,
1100 0x03F, 0x00000C4C, 0x033, 0x000000A5, 0x03F, 0x00000CA9,
1101 0x033, 0x000000A6, 0x03F, 0x00000CEA, 0x033, 0x000000A7,
1102 0x03F, 0x00000CED, 0x033, 0x000000A8, 0x03F, 0x00000CF0,
1103 0x033, 0x000000A9, 0x03F, 0x00000CF3, 0x033, 0x000000AA,
1104 0x03F, 0x00000CF6, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
1105 0x033, 0x000000A0, 0x03F, 0x00000C09, 0x033, 0x000000A1,
1106 0x03F, 0x00000C0C, 0x033, 0x000000A2, 0x03F, 0x00000C0F,
1107 0x033, 0x000000A3, 0x03F, 0x00000C2C, 0x033, 0x000000A4,
1108 0x03F, 0x00000C2F, 0x033, 0x000000A5, 0x03F, 0x00000C8A,
1109 0x033, 0x000000A6, 0x03F, 0x00000C8D, 0x033, 0x000000A7,
1110 0x03F, 0x00000C90, 0x033, 0x000000A8, 0x03F, 0x00000CEF,
1111 0x033, 0x000000A9, 0x03F, 0x00000CF2, 0x033, 0x000000AA,
1112 0x03F, 0x00000CF5, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
1113 0x033, 0x000000A0, 0x03F, 0x00000005, 0x033, 0x000000A1,
1114 0x03F, 0x00000008, 0x033, 0x000000A2, 0x03F, 0x0000000B,
1115 0x033, 0x000000A3, 0x03F, 0x0000000E, 0x033, 0x000000A4,
1116 0x03F, 0x00000047, 0x033, 0x000000A5, 0x03F, 0x0000004A,
1117 0x033, 0x000000A6, 0x03F, 0x0000004D, 0x033, 0x000000A7,
1118 0x03F, 0x00000050, 0x033, 0x000000A8, 0x03F, 0x00000053,
1119 0x033, 0x000000A9, 0x03F, 0x00000056, 0x033, 0x000000AA,
1120 0x03F, 0x00000094, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
1121 0x033, 0x000000A0, 0x03F, 0x00000C09, 0x033, 0x000000A1,
1122 0x03F, 0x00000C0C, 0x033, 0x000000A2, 0x03F, 0x00000C0F,
1123 0x033, 0x000000A3, 0x03F, 0x00000C2C, 0x033, 0x000000A4,
1124 0x03F, 0x00000C2F, 0x033, 0x000000A5, 0x03F, 0x00000C8A,
1125 0x033, 0x000000A6, 0x03F, 0x00000C8D, 0x033, 0x000000A7,
1126 0x03F, 0x00000C90, 0x033, 0x000000A8, 0x03F, 0x00000CEF,
1127 0x033, 0x000000A9, 0x03F, 0x00000CF2, 0x033, 0x000000AA,
1128 0x03F, 0x00000CF5, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
1129 0x033, 0x000000A0, 0x03F, 0x00000429, 0x033, 0x000000A1,
1130 0x03F, 0x00000828, 0x033, 0x000000A2, 0x03F, 0x00000847,
1131 0x033, 0x000000A3, 0x03F, 0x0000084A, 0x033, 0x000000A4,
1132 0x03F, 0x00000C4B, 0x033, 0x000000A5, 0x03F, 0x00000C8A,
1133 0x033, 0x000000A6, 0x03F, 0x00000CEA, 0x033, 0x000000A7,
1134 0x03F, 0x00000CED, 0x033, 0x000000A8, 0x03F, 0x00000CF0,
1135 0x033, 0x000000A9, 0x03F, 0x00000CF3, 0x033, 0x000000AA,
1136 0x03F, 0x00000CF6, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
1137 0x033, 0x000000A0, 0x03F, 0x00000C09, 0x033, 0x000000A1,
1138 0x03F, 0x00000C0C, 0x033, 0x000000A2, 0x03F, 0x00000C0F,
1139 0x033, 0x000000A3, 0x03F, 0x00000C2C, 0x033, 0x000000A4,
1140 0x03F, 0x00000C2F, 0x033, 0x000000A5, 0x03F, 0x00000C8A,
1141 0x033, 0x000000A6, 0x03F, 0x00000C8D, 0x033, 0x000000A7,
1142 0x03F, 0x00000C90, 0x033, 0x000000A8, 0x03F, 0x00000CEF,
1143 0x033, 0x000000A9, 0x03F, 0x00000CF2, 0x033, 0x000000AA,
1144 0x03F, 0x00000CF5, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
1145 0x033, 0x000000A0, 0x03F, 0x0000042A, 0x033, 0x000000A1,
1146 0x03F, 0x00000829, 0x033, 0x000000A2, 0x03F, 0x00000848,
1147 0x033, 0x000000A3, 0x03F, 0x0000084B, 0x033, 0x000000A4,
1148 0x03F, 0x00000C4C, 0x033, 0x000000A5, 0x03F, 0x00000C8A,
1149 0x033, 0x000000A6, 0x03F, 0x00000C8D, 0x033, 0x000000A7,
1150 0x03F, 0x00000CEB, 0x033, 0x000000A8, 0x03F, 0x00000CEE,
1151 0x033, 0x000000A9, 0x03F, 0x00000CF1, 0x033, 0x000000AA,
1152 0x03F, 0x00000CF4, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
1153 0x033, 0x000000A0, 0x03F, 0x0000042A, 0x033, 0x000000A1,
1154 0x03F, 0x00000829, 0x033, 0x000000A2, 0x03F, 0x00000848,
1155 0x033, 0x000000A3, 0x03F, 0x0000084B, 0x033, 0x000000A4,
1156 0x03F, 0x00000C4C, 0x033, 0x000000A5, 0x03F, 0x00000C8A,
1157 0x033, 0x000000A6, 0x03F, 0x00000C8D, 0x033, 0x000000A7,
1158 0x03F, 0x00000CEB, 0x033, 0x000000A8, 0x03F, 0x00000CEE,
1159 0x033, 0x000000A9, 0x03F, 0x00000CF1, 0x033, 0x000000AA,
1160 0x03F, 0x00000CF4, 0xA0000000, 0x00000000, 0x033, 0x000000A0,
1161 0x03F, 0x00000C09, 0x033, 0x000000A1, 0x03F, 0x00000C0C,
1162 0x033, 0x000000A2, 0x03F, 0x00000C0F, 0x033, 0x000000A3,
1163 0x03F, 0x00000C2C, 0x033, 0x000000A4, 0x03F, 0x00000C2F,
1164 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
1165 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000C90,
1166 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
1167 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
1168 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x0EF, 0x00000400,
1169 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
1170 0x03F, 0x0000047C, 0x033, 0x00000001, 0x03F, 0x0000047C,
1171 0x033, 0x00000002, 0x03F, 0x0000047C, 0x033, 0x00000003,
1172 0x03F, 0x0000047C, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
1173 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001,
1174 0x03F, 0x0000047C, 0x033, 0x00000002, 0x03F, 0x0000047C,
1175 0x033, 0x00000003, 0x03F, 0x0000047C, 0x9300100f, 0x00000000,
1176 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000047C,
1177 0x033, 0x00000001, 0x03F, 0x0000047C, 0x033, 0x00000002,
1178 0x03F, 0x0000047C, 0x033, 0x00000003, 0x03F, 0x0000047C,
1179 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
1180 0x03F, 0x0000047C, 0x033, 0x00000001, 0x03F, 0x0000047C,
1181 0x033, 0x00000002, 0x03F, 0x0000047C, 0x033, 0x00000003,
1182 0x03F, 0x0000047C, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1183 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001,
1184 0x03F, 0x0000047C, 0x033, 0x00000002, 0x03F, 0x0000047C,
1185 0x033, 0x00000003, 0x03F, 0x0000047C, 0x9000100f, 0x05050505,
1186 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000047C,
1187 0x033, 0x00000001, 0x03F, 0x0000047C, 0x033, 0x00000002,
1188 0x03F, 0x0000047C, 0x033, 0x00000003, 0x03F, 0x0000047C,
1189 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
1190 0x03F, 0x0000047C, 0x033, 0x00000001, 0x03F, 0x0000047C,
1191 0x033, 0x00000002, 0x03F, 0x0000047C, 0x033, 0x00000003,
1192 0x03F, 0x0000047C, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
1193 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001,
1194 0x03F, 0x0000047C, 0x033, 0x00000002, 0x03F, 0x0000047C,
1195 0x033, 0x00000003, 0x03F, 0x0000047C, 0xA0000000, 0x00000000,
1196 0x033, 0x00000000, 0x03F, 0x000004BB, 0x033, 0x00000001,
1197 0x03F, 0x000004BB, 0x033, 0x00000002, 0x03F, 0x000004BB,
1198 0x033, 0x00000003, 0x03F, 0x000004BB, 0xB0000000, 0x00000000,
1199 0x0EF, 0x00000000, 0x0EF, 0x00000100, 0x8300100f, 0x0a0a0a0a,
1200 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726,
1201 0x033, 0x00000001, 0x03F, 0x00001726, 0x033, 0x00000002,
1202 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726,
1203 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
1204 0x03F, 0x00001726, 0x033, 0x00000001, 0x03F, 0x00001726,
1205 0x033, 0x00000002, 0x03F, 0x00001726, 0x033, 0x00000003,
1206 0x03F, 0x00001726, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
1207 0x033, 0x00000000, 0x03F, 0x00001726, 0x033, 0x00000001,
1208 0x03F, 0x00001726, 0x033, 0x00000002, 0x03F, 0x00001726,
1209 0x033, 0x00000003, 0x03F, 0x00001726, 0x9300200f, 0x00000000,
1210 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726,
1211 0x033, 0x00000001, 0x03F, 0x00001726, 0x033, 0x00000002,
1212 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726,
1213 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
1214 0x03F, 0x00001726, 0x033, 0x00000001, 0x03F, 0x00001726,
1215 0x033, 0x00000002, 0x03F, 0x00001726, 0x033, 0x00000003,
1216 0x03F, 0x00001726, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
1217 0x033, 0x00000000, 0x03F, 0x00001726, 0x033, 0x00000001,
1218 0x03F, 0x00001726, 0x033, 0x00000002, 0x03F, 0x00001726,
1219 0x033, 0x00000003, 0x03F, 0x00001726, 0x9000100f, 0x00000000,
1220 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726,
1221 0x033, 0x00000001, 0x03F, 0x00001726, 0x033, 0x00000002,
1222 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726,
1223 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
1224 0x03F, 0x00001726, 0x033, 0x00000001, 0x03F, 0x00001726,
1225 0x033, 0x00000002, 0x03F, 0x00001726, 0x033, 0x00000003,
1226 0x03F, 0x00001726, 0xA0000000, 0x00000000, 0x033, 0x00000000,
1227 0x03F, 0x00000F34, 0x033, 0x00000001, 0x03F, 0x00000F34,
1228 0x033, 0x00000002, 0x03F, 0x00000F34, 0x033, 0x00000003,
1229 0x03F, 0x00000F34, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
1230 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x081, 0x0000F400,
1231 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
1232 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
1233 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9300100f, 0x05050505,
1234 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
1235 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
1236 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
1237 0x058, 0x00082030, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
1238 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
1239 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
1240 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
1241 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400,
1242 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
1243 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
1244 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9000100f, 0x0a0a0a0a,
1245 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
1246 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
1247 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
1248 0x058, 0x00082030, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
1249 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
1250 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
1251 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
1252 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400,
1253 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
1254 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
1255 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9000200f, 0x00000000,
1256 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
1257 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
1258 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
1259 0x058, 0x00082030, 0xA0000000, 0x00000000, 0x081, 0x0000F000,
1260 0x087, 0x00016040, 0x051, 0x00000C00, 0x052, 0x0007C241,
1261 0x053, 0x0001C069, 0x054, 0x00078032, 0x057, 0x0000CE0A,
1262 0x058, 0x00058750, 0xB0000000, 0x00000000, 0x0EF, 0x00000800,
1263 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
1264 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
1265 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
1266 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
1267 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
1268 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
1269 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
1270 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
1271 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
1272 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
1273 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
1274 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
1275 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
1276 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
1277 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
1278 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
1279 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
1280 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
1281 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
1282 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
1283 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
1284 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
1285 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
1286 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
1287 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
1288 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
1289 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
1290 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
1291 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
1292 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
1293 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
1294 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
1295 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
1296 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
1297 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
1298 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
1299 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
1300 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
1301 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
1302 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
1303 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
1304 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
1305 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
1306 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
1307 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
1308 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
1309 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
1310 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
1311 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
1312 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
1313 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
1314 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
1315 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
1316 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
1317 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
1318 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
1319 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
1320 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
1321 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
1322 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
1323 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
1324 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
1325 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
1326 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
1327 0xA0000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0005142C,
1328 0x033, 0x00000001, 0x03F, 0x0005144B, 0x033, 0x00000002,
1329 0x03F, 0x0005144E, 0x033, 0x00000003, 0x03F, 0x00051C69,
1330 0x033, 0x00000004, 0x03F, 0x00051C6C, 0x033, 0x00000005,
1331 0x03F, 0x00051C6F, 0x033, 0x00000006, 0x03F, 0x00051CEB,
1332 0x033, 0x00000007, 0x03F, 0x00051CEE, 0x033, 0x00000008,
1333 0x03F, 0x00051CF1, 0x033, 0x00000009, 0x03F, 0x00051CF4,
1334 0x033, 0x0000000A, 0x03F, 0x00051CF7, 0xB0000000, 0x00000000,
1335 0x0EF, 0x00000000, 0x0EF, 0x00000010, 0x033, 0x00000000,
1336 0x008, 0x0009C060, 0x033, 0x00000001, 0x008, 0x0009C060,
1337 0x0EF, 0x00000000, 0x033, 0x000000A2, 0x0EF, 0x00080000,
1338 0x03E, 0x0000593F, 0x03F, 0x000C0F4F, 0x0EF, 0x00000000,
1339 0x033, 0x000000A3, 0x0EF, 0x00080000, 0x03E, 0x00005934,
1340 0x03F, 0x0005AFCF, 0x0EF, 0x00000000,
1341
1342};
1343
1344void odm_read_and_config_mp_8822b_radioa(struct phy_dm_struct *dm)
1345{
1346 u32 i = 0;
1347 u8 c_cond;
1348 bool is_matched = true, is_skipped = false;
1349 u32 array_len = sizeof(array_mp_8822b_radioa) / sizeof(u32);
1350 u32 *array = array_mp_8822b_radioa;
1351
1352 u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
1353
1354 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1355 "===> %s\n", __func__);
1356
1357 for (; (i + 1) < array_len; i = i + 2) {
1358 v1 = array[i];
1359 v2 = array[i + 1];
1360
1361 if (v1 & BIT(31)) { /* positive condition*/
1362 c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
1363 if (c_cond == COND_ENDIF) { /*end*/
1364 is_matched = true;
1365 is_skipped = false;
1366 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
1367 } else if (c_cond == COND_ELSE) { /*else*/
1368 is_matched = is_skipped ? false : true;
1369 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
1370 } else { /*if , else if*/
1371 pre_v1 = v1;
1372 pre_v2 = v2;
1373 ODM_RT_TRACE(dm, ODM_COMP_INIT,
1374 "IF or ELSE IF\n");
1375 }
1376 } else if (v1 & BIT(30)) { /*negative condition*/
1377 if (is_skipped) {
1378 is_matched = false;
1379 continue;
1380 }
1381
1382 if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
1383 is_matched = true;
1384 is_skipped = true;
1385 } else {
1386 is_matched = false;
1387 is_skipped = false;
1388 }
1389 } else if (is_matched) {
1390 odm_config_rf_radio_a_8822b(dm, v1, v2);
1391 }
1392 }
1393}
1394
1395u32 odm_get_version_mp_8822b_radioa(void) { return 67; }
1396
1397/******************************************************************************
1398 * radiob.TXT
1399 ******************************************************************************/
1400
1401static u32 array_mp_8822b_radiob[] = {
1402 0x000, 0x00030000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1403 0x001, 0x0004002D, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
1404 0x001, 0x0004002D, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
1405 0x001, 0x0004002D, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
1406 0x001, 0x0004002D, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1407 0x001, 0x0004002D, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
1408 0x001, 0x0004002D, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
1409 0x001, 0x0004002D, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
1410 0x001, 0x0004002D, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
1411 0x001, 0x00040029, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
1412 0x001, 0x00040029, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
1413 0x001, 0x00040029, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
1414 0x001, 0x00040029, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
1415 0x001, 0x00040029, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
1416 0x001, 0x00040029, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
1417 0x001, 0x00040029, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
1418 0x001, 0x00040029, 0xA0000000, 0x00000000, 0x001, 0x00040029,
1419 0xB0000000, 0x00000000, 0x018, 0x00010D24, 0x0EF, 0x00080000,
1420 0x033, 0x00000002, 0x03E, 0x0000003F, 0x03F, 0x000C0F4E,
1421 0x033, 0x00000001, 0x03E, 0x00000034, 0x03F, 0x0004080E,
1422 0x0EF, 0x00080000, 0x0DF, 0x00002449, 0x033, 0x00000024,
1423 0x03E, 0x0000003F, 0x03F, 0x00060FDE, 0x0EF, 0x00000000,
1424 0x0EF, 0x00080000, 0x033, 0x00000025, 0x03E, 0x00000037,
1425 0x03F, 0x0007EFCE, 0x0EF, 0x00000000, 0x0EF, 0x00080000,
1426 0x033, 0x00000026, 0x03E, 0x00000037, 0x03F, 0x000DEFCE,
1427 0x0EF, 0x00000000, 0x0DF, 0x00000009, 0x018, 0x00010524,
1428 0x089, 0x00000207, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1429 0x08A, 0x000FF186, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
1430 0x08A, 0x000FE186, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
1431 0x08A, 0x000FF186, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
1432 0x08A, 0x000FF186, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1433 0x08A, 0x000FF186, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
1434 0x08A, 0x000FE186, 0xA0000000, 0x00000000, 0x08A, 0x000FF186,
1435 0xB0000000, 0x00000000, 0x08B, 0x00061E3C, 0x08C, 0x000112C7,
1436 0x08D, 0x000F4988, 0x08E, 0x00064D40, 0x0EF, 0x00020000,
1437 0x033, 0x00000007, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1438 0x03E, 0x00004040, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
1439 0x03E, 0x00004080, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
1440 0x03E, 0x00004040, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
1441 0x03E, 0x00004040, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1442 0x03E, 0x00004040, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
1443 0x03E, 0x00004080, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
1444 0x03E, 0x00004040, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
1445 0x03E, 0x00004040, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
1446 0x03E, 0x00004040, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
1447 0x03E, 0x00004000, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
1448 0x03E, 0x00004000, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
1449 0x03E, 0x00004000, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
1450 0x03E, 0x00004040, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
1451 0x03E, 0x00004040, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
1452 0x03E, 0x00004000, 0xA0000000, 0x00000000, 0x03E, 0x00004000,
1453 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1454 0x03F, 0x000C3186, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
1455 0x03F, 0x000C3186, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
1456 0x03F, 0x000C3186, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
1457 0x03F, 0x000C3186, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1458 0x03F, 0x000C3186, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
1459 0x03F, 0x000C3186, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
1460 0x03F, 0x000C3186, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
1461 0x03F, 0x000C3186, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
1462 0x03F, 0x000C3186, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
1463 0x03F, 0x000C3186, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
1464 0x03F, 0x000C0006, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
1465 0x03F, 0x000C3186, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
1466 0x03F, 0x000C3186, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
1467 0x03F, 0x000C3186, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
1468 0x03F, 0x000C0006, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
1469 0x03F, 0x000C3186, 0xA0000000, 0x00000000, 0x03F, 0x000C3186,
1470 0xB0000000, 0x00000000, 0x033, 0x00000006, 0x03E, 0x00004080,
1471 0x03F, 0x000C3186, 0x033, 0x00000005, 0x03E, 0x000040C8,
1472 0x03F, 0x000C3186, 0x033, 0x00000004, 0x03E, 0x00004190,
1473 0x03F, 0x000C3186, 0x033, 0x00000003, 0x03E, 0x00004998,
1474 0x03F, 0x000C3186, 0x033, 0x00000002, 0x03E, 0x00005840,
1475 0x03F, 0x000C3186, 0x033, 0x00000001, 0x03E, 0x000058C2,
1476 0x03F, 0x000C3186, 0x033, 0x00000000, 0x03E, 0x00005930,
1477 0x03F, 0x000C3186, 0x033, 0x0000000F, 0x8300100f, 0x0a0a0a0a,
1478 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300100f, 0x05050505,
1479 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9300100f, 0x00000000,
1480 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200f, 0x00000000,
1481 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x0a0a0a0a,
1482 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x05050505,
1483 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9000100f, 0x00000000,
1484 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000200f, 0x00000000,
1485 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200c, 0x00000000,
1486 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x93012100, 0x00000000,
1487 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93002100, 0x00000000,
1488 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93011000, 0x00000000,
1489 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x9000200c, 0x00000000,
1490 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x90001004, 0x00000000,
1491 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x93002000, 0x00000000,
1492 0x40000000, 0x00000000, 0x03E, 0x00004000, 0xA0000000, 0x00000000,
1493 0x03E, 0x00004000, 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a,
1494 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x05050505,
1495 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x00000000,
1496 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200f, 0x00000000,
1497 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x0a0a0a0a,
1498 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x05050505,
1499 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x00000000,
1500 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200f, 0x00000000,
1501 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200c, 0x00000000,
1502 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93012100, 0x00000000,
1503 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002100, 0x00000000,
1504 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93011000, 0x00000000,
1505 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200c, 0x00000000,
1506 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x90001004, 0x00000000,
1507 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002000, 0x00000000,
1508 0x40000000, 0x00000000, 0x03F, 0x000C0006, 0x93001000, 0x00000000,
1509 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0xA0000000, 0x00000000,
1510 0x03F, 0x000C3186, 0xB0000000, 0x00000000, 0x033, 0x0000000E,
1511 0x03E, 0x00004080, 0x03F, 0x000C3186, 0x033, 0x0000000D,
1512 0x03E, 0x000040C8, 0x03F, 0x000C3186, 0x033, 0x0000000C,
1513 0x03E, 0x00004190, 0x03F, 0x000C3186, 0x033, 0x0000000B,
1514 0x03E, 0x00004998, 0x03F, 0x000C3186, 0x033, 0x0000000A,
1515 0x03E, 0x00005840, 0x03F, 0x000C3186, 0x033, 0x00000009,
1516 0x03E, 0x000058C2, 0x03F, 0x000C3186, 0x033, 0x00000008,
1517 0x03E, 0x00005930, 0x03F, 0x000C3186, 0x033, 0x00000017,
1518 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004040,
1519 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
1520 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
1521 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
1522 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004040,
1523 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
1524 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
1525 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
1526 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
1527 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
1528 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
1529 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
1530 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
1531 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
1532 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
1533 0xA0000000, 0x00000000, 0x03E, 0x00004000, 0xB0000000, 0x00000000,
1534 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1535 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1536 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1537 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1538 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1539 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1540 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1541 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1542 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1543 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1544 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000DFF86,
1545 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1546 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1547 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1548 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C0006,
1549 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
1550 0xA0000000, 0x00000000, 0x03F, 0x000C3186, 0xB0000000, 0x00000000,
1551 0x033, 0x00000016, 0x03E, 0x00004080, 0x03F, 0x000C3186,
1552 0x033, 0x00000015, 0x03E, 0x000040C8, 0x03F, 0x000C3186,
1553 0x033, 0x00000014, 0x03E, 0x00004190, 0x03F, 0x000C3186,
1554 0x033, 0x00000013, 0x03E, 0x00004998, 0x03F, 0x000C3186,
1555 0x033, 0x00000012, 0x03E, 0x00005840, 0x03F, 0x000C3186,
1556 0x033, 0x00000011, 0x03E, 0x000058C2, 0x03F, 0x000C3186,
1557 0x033, 0x00000010, 0x03E, 0x00005930, 0x03F, 0x000C3186,
1558 0x0EF, 0x00000000, 0x0EF, 0x00004000, 0x033, 0x00000000,
1559 0x03F, 0x0000000A, 0x033, 0x00000001, 0x8300100f, 0x0a0a0a0a,
1560 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300100f, 0x05050505,
1561 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300100f, 0x00000000,
1562 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300200f, 0x00000000,
1563 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x0a0a0a0a,
1564 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x05050505,
1565 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x00000000,
1566 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000200f, 0x00000000,
1567 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300200c, 0x00000000,
1568 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93012100, 0x00000000,
1569 0x40000000, 0x00000000, 0x03F, 0x00000002, 0x93002100, 0x00000000,
1570 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93011000, 0x00000000,
1571 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x9000200c, 0x00000000,
1572 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90001004, 0x00000000,
1573 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93002000, 0x00000000,
1574 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93001000, 0x00000000,
1575 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x90002100, 0x00000000,
1576 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90002000, 0x00000000,
1577 0x40000000, 0x00000000, 0x03F, 0x00000000, 0xA0000000, 0x00000000,
1578 0x03F, 0x00000005, 0xB0000000, 0x00000000, 0x033, 0x00000002,
1579 0x03F, 0x00000000, 0x0EF, 0x00000000, 0x018, 0x00000401,
1580 0x084, 0x00001209, 0x086, 0x000001A0, 0x8300100f, 0x0a0a0a0a,
1581 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300100f, 0x05050505,
1582 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300100f, 0x00000000,
1583 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300200f, 0x00000000,
1584 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x0a0a0a0a,
1585 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x05050505,
1586 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x00000000,
1587 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000200f, 0x00000000,
1588 0x40000000, 0x00000000, 0x087, 0x00068080, 0xA0000000, 0x00000000,
1589 0x087, 0x000E8180, 0xB0000000, 0x00000000, 0x088, 0x00070020,
1590 0x0DE, 0x00000010, 0x0EF, 0x00008000, 0x033, 0x0000000F,
1591 0x03F, 0x0000003C, 0x033, 0x0000000E, 0x03F, 0x00000038,
1592 0x033, 0x0000000D, 0x03F, 0x00000030, 0x033, 0x0000000C,
1593 0x03F, 0x00000028, 0x033, 0x0000000B, 0x03F, 0x00000020,
1594 0x033, 0x0000000A, 0x03F, 0x00000018, 0x033, 0x00000009,
1595 0x03F, 0x00000010, 0x033, 0x00000008, 0x03F, 0x00000008,
1596 0x033, 0x00000007, 0x03F, 0x0000003C, 0x033, 0x00000006,
1597 0x03F, 0x00000038, 0x033, 0x00000005, 0x03F, 0x00000030,
1598 0x033, 0x00000004, 0x03F, 0x00000028, 0x033, 0x00000003,
1599 0x03F, 0x00000020, 0x033, 0x00000002, 0x03F, 0x00000018,
1600 0x033, 0x00000001, 0x03F, 0x00000010, 0x033, 0x00000000,
1601 0x03F, 0x00000008, 0x0EF, 0x00000000, 0x018, 0x00018D24,
1602 0xFFE, 0x00000000, 0xFFE, 0x00000000, 0xFFE, 0x00000000,
1603 0xFFE, 0x00000000, 0x018, 0x00010D24, 0x01B, 0x00075A40,
1604 0x0EE, 0x00000002, 0x033, 0x00000000, 0x03F, 0x00000004,
1605 0x033, 0x00000001, 0x03F, 0x00000004, 0x033, 0x00000002,
1606 0x03F, 0x00000004, 0x033, 0x00000003, 0x03F, 0x00000004,
1607 0x033, 0x00000004, 0x03F, 0x00000004, 0x033, 0x00000005,
1608 0x03F, 0x00000006, 0x033, 0x00000006, 0x03F, 0x00000002,
1609 0x033, 0x00000007, 0x03F, 0x00000000, 0x0EE, 0x00000000,
1610 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x061, 0x0005D4A0,
1611 0x062, 0x0000D203, 0x063, 0x00000062, 0x9300100f, 0x05050505,
1612 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203,
1613 0x063, 0x00000062, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
1614 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062,
1615 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1,
1616 0x062, 0x0000D3A2, 0x063, 0x00000062, 0x9000100f, 0x0a0a0a0a,
1617 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203,
1618 0x063, 0x00000062, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
1619 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062,
1620 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0,
1621 0x062, 0x0000D203, 0x063, 0x00000062, 0x9000200f, 0x00000000,
1622 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2,
1623 0x063, 0x00000062, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
1624 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000062,
1625 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1,
1626 0x062, 0x0000D3A2, 0x063, 0x00000002, 0x93002100, 0x00000000,
1627 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2,
1628 0x063, 0x00000002, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
1629 0x061, 0x0005D3D1, 0x062, 0x0000D3A2, 0x063, 0x00000002,
1630 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1,
1631 0x062, 0x0000D3A2, 0x063, 0x00000062, 0x90001004, 0x00000000,
1632 0x40000000, 0x00000000, 0x061, 0x0005D3D1, 0x062, 0x0000D3A2,
1633 0x063, 0x00000002, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
1634 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000002,
1635 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D3D1,
1636 0x062, 0x0000D3A2, 0x063, 0x00000002, 0x90002100, 0x00000000,
1637 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2,
1638 0x063, 0x00000002, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
1639 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000002,
1640 0xA0000000, 0x00000000, 0x061, 0x0005D3D0, 0x062, 0x0000D303,
1641 0x063, 0x00000002, 0xB0000000, 0x00000000, 0x0EF, 0x00000200,
1642 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x030, 0x000004A3,
1643 0x030, 0x000014A3, 0x030, 0x000024A3, 0x030, 0x000034A3,
1644 0x030, 0x000044A3, 0x030, 0x000054A3, 0x030, 0x000064A3,
1645 0x030, 0x000074A3, 0x030, 0x000084A3, 0x030, 0x000094A3,
1646 0x030, 0x0000A4A3, 0x030, 0x0000B4A3, 0x9300100f, 0x05050505,
1647 0x40000000, 0x00000000, 0x030, 0x000004A3, 0x030, 0x000014A3,
1648 0x030, 0x000024A3, 0x030, 0x000034A3, 0x030, 0x000044A3,
1649 0x030, 0x000054A3, 0x030, 0x000064A3, 0x030, 0x000074A3,
1650 0x030, 0x000084A3, 0x030, 0x000094A3, 0x030, 0x0000A4A3,
1651 0x030, 0x0000B4A3, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
1652 0x030, 0x000004A3, 0x030, 0x000014A3, 0x030, 0x000024A3,
1653 0x030, 0x000034A3, 0x030, 0x000044A3, 0x030, 0x000054A3,
1654 0x030, 0x000064A3, 0x030, 0x000074A3, 0x030, 0x000084A3,
1655 0x030, 0x000094A3, 0x030, 0x0000A4A3, 0x030, 0x0000B4A3,
1656 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000002A6,
1657 0x030, 0x000012A6, 0x030, 0x000022A6, 0x030, 0x000032A6,
1658 0x030, 0x000042A6, 0x030, 0x000052A6, 0x030, 0x000062A6,
1659 0x030, 0x000072A6, 0x030, 0x000082A6, 0x030, 0x000092A6,
1660 0x030, 0x0000A2A6, 0x030, 0x0000B2A6, 0x9000100f, 0x0a0a0a0a,
1661 0x40000000, 0x00000000, 0x030, 0x000004A0, 0x030, 0x000014A0,
1662 0x030, 0x000024A0, 0x030, 0x000034A0, 0x030, 0x000044A0,
1663 0x030, 0x000054A0, 0x030, 0x000064A0, 0x030, 0x000074A0,
1664 0x030, 0x000084A0, 0x030, 0x000094A0, 0x030, 0x0000A4A0,
1665 0x030, 0x0000B4A0, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
1666 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0,
1667 0x030, 0x000034A0, 0x030, 0x000044A0, 0x030, 0x000054A0,
1668 0x030, 0x000064A0, 0x030, 0x000074A0, 0x030, 0x000084A0,
1669 0x030, 0x000094A0, 0x030, 0x0000A4A0, 0x030, 0x0000B4A0,
1670 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000004A0,
1671 0x030, 0x000014A0, 0x030, 0x000024A0, 0x030, 0x000034A0,
1672 0x030, 0x000044A0, 0x030, 0x000054A0, 0x030, 0x000064A0,
1673 0x030, 0x000074A0, 0x030, 0x000084A0, 0x030, 0x000094A0,
1674 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, 0x9000200f, 0x00000000,
1675 0x40000000, 0x00000000, 0x030, 0x000002A1, 0x030, 0x000012A1,
1676 0x030, 0x000022A1, 0x030, 0x000032A1, 0x030, 0x000042A1,
1677 0x030, 0x000052A1, 0x030, 0x000062A1, 0x030, 0x000072A1,
1678 0x030, 0x000082A1, 0x030, 0x000092A1, 0x030, 0x0000A2A1,
1679 0x030, 0x0000B2A1, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
1680 0x030, 0x000002A6, 0x030, 0x000012A6, 0x030, 0x000022A6,
1681 0x030, 0x000032A6, 0x030, 0x000042A6, 0x030, 0x000052A6,
1682 0x030, 0x000062A6, 0x030, 0x000072A6, 0x030, 0x000082A6,
1683 0x030, 0x000092A6, 0x030, 0x0000A2A6, 0x030, 0x0000B2A6,
1684 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000002F4,
1685 0x030, 0x000012F4, 0x030, 0x000022F4, 0x030, 0x000032F4,
1686 0x030, 0x00004365, 0x030, 0x00005365, 0x030, 0x00006365,
1687 0x030, 0x00007365, 0x030, 0x000082A4, 0x030, 0x000092A4,
1688 0x030, 0x0000A2A4, 0x030, 0x0000B2A4, 0x93002100, 0x00000000,
1689 0x40000000, 0x00000000, 0x030, 0x000004A4, 0x030, 0x000014A4,
1690 0x030, 0x000024A4, 0x030, 0x000034A4, 0x030, 0x000043A4,
1691 0x030, 0x000053A4, 0x030, 0x000063A4, 0x030, 0x000073A4,
1692 0x030, 0x000083A5, 0x030, 0x000093A5, 0x030, 0x0000A3A5,
1693 0x030, 0x0000B3A5, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
1694 0x030, 0x000003A1, 0x030, 0x000013A1, 0x030, 0x000023A1,
1695 0x030, 0x000033A1, 0x030, 0x000043A4, 0x030, 0x000053A4,
1696 0x030, 0x000063A4, 0x030, 0x000073A4, 0x030, 0x000083A6,
1697 0x030, 0x000093A6, 0x030, 0x0000A3A6, 0x030, 0x0000B3A6,
1698 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000002A1,
1699 0x030, 0x000012A1, 0x030, 0x000022A1, 0x030, 0x000032A1,
1700 0x030, 0x000042A1, 0x030, 0x000052A1, 0x030, 0x000062A1,
1701 0x030, 0x000072A1, 0x030, 0x000082A1, 0x030, 0x000092A1,
1702 0x030, 0x0000A2A1, 0x030, 0x0000B2A1, 0x90001004, 0x00000000,
1703 0x40000000, 0x00000000, 0x030, 0x00000382, 0x030, 0x00001382,
1704 0x030, 0x00002382, 0x030, 0x00003382, 0x030, 0x00004445,
1705 0x030, 0x00005445, 0x030, 0x00006445, 0x030, 0x00007445,
1706 0x030, 0x00008425, 0x030, 0x00009425, 0x030, 0x0000A425,
1707 0x030, 0x0000B425, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
1708 0x030, 0x00000303, 0x030, 0x00001303, 0x030, 0x00002303,
1709 0x030, 0x00003303, 0x030, 0x000043A4, 0x030, 0x000053A4,
1710 0x030, 0x000063A4, 0x030, 0x000073A4, 0x030, 0x00008365,
1711 0x030, 0x00009365, 0x030, 0x0000A365, 0x030, 0x0000B365,
1712 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A1,
1713 0x030, 0x000013A1, 0x030, 0x000023A1, 0x030, 0x000033A1,
1714 0x030, 0x00004364, 0x030, 0x00005364, 0x030, 0x00006364,
1715 0x030, 0x00007364, 0x030, 0x00008564, 0x030, 0x00009564,
1716 0x030, 0x0000A564, 0x030, 0x0000B564, 0x90002100, 0x00000000,
1717 0x40000000, 0x00000000, 0x030, 0x000004A1, 0x030, 0x000014A1,
1718 0x030, 0x000024A1, 0x030, 0x000034A1, 0x030, 0x000043A1,
1719 0x030, 0x000053A1, 0x030, 0x000063A1, 0x030, 0x000073A1,
1720 0x030, 0x000083A1, 0x030, 0x000093A1, 0x030, 0x0000A3A1,
1721 0x030, 0x0000B3A1, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
1722 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0,
1723 0x030, 0x000034A0, 0x030, 0x000043A1, 0x030, 0x000053A1,
1724 0x030, 0x000063A1, 0x030, 0x000073A1, 0x030, 0x000083A2,
1725 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
1726 0xA0000000, 0x00000000, 0x030, 0x000002D0, 0x030, 0x000012D0,
1727 0x030, 0x000022D0, 0x030, 0x000032D0, 0x030, 0x000042D0,
1728 0x030, 0x000052D0, 0x030, 0x000062D0, 0x030, 0x000072D0,
1729 0x030, 0x000082D0, 0x030, 0x000092D0, 0x030, 0x0000A2D0,
1730 0x030, 0x0000B2D0, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
1731 0x0EF, 0x00000080, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1732 0x030, 0x00000203, 0x030, 0x00001203, 0x030, 0x00002203,
1733 0x030, 0x00003203, 0x030, 0x00004203, 0x030, 0x00005203,
1734 0x030, 0x00006203, 0x030, 0x00007203, 0x030, 0x00008203,
1735 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203,
1736 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x030, 0x00000203,
1737 0x030, 0x00001203, 0x030, 0x00002203, 0x030, 0x00003203,
1738 0x030, 0x00004203, 0x030, 0x00005203, 0x030, 0x00006203,
1739 0x030, 0x00007203, 0x030, 0x00008203, 0x030, 0x00009203,
1740 0x030, 0x0000A203, 0x030, 0x0000B203, 0x9300100f, 0x00000000,
1741 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203,
1742 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
1743 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
1744 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
1745 0x030, 0x0000B203, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
1746 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
1747 0x030, 0x000033A2, 0x030, 0x000043A2, 0x030, 0x000053A2,
1748 0x030, 0x000063A2, 0x030, 0x000073A2, 0x030, 0x000083A2,
1749 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
1750 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x030, 0x00000203,
1751 0x030, 0x00001203, 0x030, 0x00002203, 0x030, 0x00003203,
1752 0x030, 0x00004203, 0x030, 0x00005203, 0x030, 0x00006203,
1753 0x030, 0x00007203, 0x030, 0x00008203, 0x030, 0x00009203,
1754 0x030, 0x0000A203, 0x030, 0x0000B203, 0x9000100f, 0x05050505,
1755 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203,
1756 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
1757 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
1758 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
1759 0x030, 0x0000B203, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
1760 0x030, 0x00000203, 0x030, 0x00001203, 0x030, 0x00002203,
1761 0x030, 0x00003203, 0x030, 0x00004203, 0x030, 0x00005203,
1762 0x030, 0x00006203, 0x030, 0x00007203, 0x030, 0x00008203,
1763 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203,
1764 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2,
1765 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
1766 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
1767 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
1768 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x9300200c, 0x00000000,
1769 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2,
1770 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
1771 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
1772 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
1773 0x030, 0x0000B3A2, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
1774 0x030, 0x000003A3, 0x030, 0x000013A3, 0x030, 0x000023A3,
1775 0x030, 0x000033A3, 0x030, 0x000043A4, 0x030, 0x000053A4,
1776 0x030, 0x000063A4, 0x030, 0x000073A4, 0x030, 0x000083A3,
1777 0x030, 0x000093A3, 0x030, 0x0000A3A3, 0x030, 0x0000B3A3,
1778 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2,
1779 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
1780 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
1781 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
1782 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x93011000, 0x00000000,
1783 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2,
1784 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
1785 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
1786 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
1787 0x030, 0x0000B3A2, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
1788 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
1789 0x030, 0x000033A2, 0x030, 0x000043A2, 0x030, 0x000053A2,
1790 0x030, 0x000063A2, 0x030, 0x000073A2, 0x030, 0x000083A2,
1791 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
1792 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2,
1793 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
1794 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
1795 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
1796 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x93002000, 0x00000000,
1797 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2,
1798 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
1799 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
1800 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
1801 0x030, 0x0000B3A2, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
1802 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
1803 0x030, 0x000033A2, 0x030, 0x000043A2, 0x030, 0x000053A2,
1804 0x030, 0x000063A2, 0x030, 0x000073A2, 0x030, 0x000083A2,
1805 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
1806 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2,
1807 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
1808 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
1809 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
1810 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x90002000, 0x00000000,
1811 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2,
1812 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
1813 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
1814 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
1815 0x030, 0x0000B3A2, 0xA0000000, 0x00000000, 0x030, 0x000003A2,
1816 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
1817 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
1818 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
1819 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0xB0000000, 0x00000000,
1820 0x0EF, 0x00000000, 0x0EF, 0x00000040, 0x8300100f, 0x0a0a0a0a,
1821 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333,
1822 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000,
1823 0x030, 0x00006000, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
1824 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011,
1825 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
1826 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645,
1827 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
1828 0x030, 0x00005000, 0x030, 0x00006000, 0x9300200f, 0x00000000,
1829 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333,
1830 0x030, 0x00002011, 0x030, 0x00004777, 0x030, 0x00005777,
1831 0x030, 0x00006777, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
1832 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011,
1833 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
1834 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x030, 0x00000645,
1835 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
1836 0x030, 0x00005000, 0x030, 0x00006000, 0x9000100f, 0x00000000,
1837 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333,
1838 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000,
1839 0x030, 0x00006000, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
1840 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011,
1841 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
1842 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645,
1843 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004777,
1844 0x030, 0x00005777, 0x030, 0x00006777, 0x93012100, 0x00000000,
1845 0x40000000, 0x00000000, 0x030, 0x00000660, 0x030, 0x00001341,
1846 0x030, 0x00002220, 0x030, 0x00004777, 0x030, 0x00005777,
1847 0x030, 0x00006777, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
1848 0x030, 0x00000764, 0x030, 0x00001452, 0x030, 0x00002220,
1849 0x030, 0x00004777, 0x030, 0x00005777, 0x030, 0x00006777,
1850 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000764,
1851 0x030, 0x00001632, 0x030, 0x00002421, 0x030, 0x00004000,
1852 0x030, 0x00005000, 0x030, 0x00006000, 0x9000200c, 0x00000000,
1853 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333,
1854 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000,
1855 0x030, 0x00006000, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
1856 0x030, 0x00000764, 0x030, 0x00001632, 0x030, 0x00002421,
1857 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
1858 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000777,
1859 0x030, 0x00001442, 0x030, 0x00002222, 0x030, 0x00004777,
1860 0x030, 0x00005777, 0x030, 0x00006777, 0x93001000, 0x00000000,
1861 0x40000000, 0x00000000, 0x030, 0x00000764, 0x030, 0x00001632,
1862 0x030, 0x00002421, 0x030, 0x00004000, 0x030, 0x00005000,
1863 0x030, 0x00006000, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
1864 0x030, 0x00000775, 0x030, 0x00001222, 0x030, 0x00002210,
1865 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
1866 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000775,
1867 0x030, 0x00001422, 0x030, 0x00002210, 0x030, 0x00004000,
1868 0x030, 0x00005000, 0x030, 0x00006000, 0xA0000000, 0x00000000,
1869 0x030, 0x00000764, 0x030, 0x00001632, 0x030, 0x00002421,
1870 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
1871 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x0EF, 0x00000800,
1872 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000020,
1873 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
1874 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
1875 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
1876 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
1877 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
1878 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
1879 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
1880 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000020,
1881 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
1882 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
1883 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
1884 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
1885 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
1886 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
1887 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
1888 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1889 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
1890 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
1891 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
1892 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
1893 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
1894 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
1895 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
1896 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1897 0x03F, 0x00000005, 0x033, 0x00000021, 0x03F, 0x00000008,
1898 0x033, 0x00000022, 0x03F, 0x0000000B, 0x033, 0x00000023,
1899 0x03F, 0x0000000E, 0x033, 0x00000024, 0x03F, 0x0000002B,
1900 0x033, 0x00000025, 0x03F, 0x00000068, 0x033, 0x00000026,
1901 0x03F, 0x0000006B, 0x033, 0x00000027, 0x03F, 0x0000006E,
1902 0x033, 0x00000028, 0x03F, 0x00000071, 0x033, 0x00000029,
1903 0x03F, 0x00000074, 0x033, 0x0000002A, 0x03F, 0x00000077,
1904 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000020,
1905 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
1906 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
1907 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
1908 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
1909 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
1910 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
1911 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
1912 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000020,
1913 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
1914 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
1915 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
1916 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
1917 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
1918 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
1919 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
1920 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1921 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
1922 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
1923 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
1924 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
1925 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
1926 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
1927 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
1928 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1929 0x03F, 0x00000005, 0x033, 0x00000021, 0x03F, 0x00000008,
1930 0x033, 0x00000022, 0x03F, 0x0000000B, 0x033, 0x00000023,
1931 0x03F, 0x0000000E, 0x033, 0x00000024, 0x03F, 0x0000002B,
1932 0x033, 0x00000025, 0x03F, 0x00000068, 0x033, 0x00000026,
1933 0x03F, 0x0000006B, 0x033, 0x00000027, 0x03F, 0x0000006E,
1934 0x033, 0x00000028, 0x03F, 0x00000071, 0x033, 0x00000029,
1935 0x03F, 0x00000074, 0x033, 0x0000002A, 0x03F, 0x00000077,
1936 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1937 0x03F, 0x00000005, 0x033, 0x00000021, 0x03F, 0x00000008,
1938 0x033, 0x00000022, 0x03F, 0x0000000B, 0x033, 0x00000023,
1939 0x03F, 0x0000000E, 0x033, 0x00000024, 0x03F, 0x0000002B,
1940 0x033, 0x00000025, 0x03F, 0x00000068, 0x033, 0x00000026,
1941 0x03F, 0x0000006B, 0x033, 0x00000027, 0x03F, 0x0000006E,
1942 0x033, 0x00000028, 0x03F, 0x00000071, 0x033, 0x00000029,
1943 0x03F, 0x00000074, 0x033, 0x0000002A, 0x03F, 0x00000077,
1944 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1945 0x03F, 0x00000828, 0x033, 0x00000021, 0x03F, 0x0000082B,
1946 0x033, 0x00000022, 0x03F, 0x00000868, 0x033, 0x00000023,
1947 0x03F, 0x00000889, 0x033, 0x00000024, 0x03F, 0x000008AA,
1948 0x033, 0x00000025, 0x03F, 0x00000CE8, 0x033, 0x00000026,
1949 0x03F, 0x00000CEB, 0x033, 0x00000027, 0x03F, 0x00000CEE,
1950 0x033, 0x00000028, 0x03F, 0x00000CF1, 0x033, 0x00000029,
1951 0x03F, 0x00000CF4, 0x033, 0x0000002A, 0x03F, 0x00000CF7,
1952 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1953 0x03F, 0x0000042A, 0x033, 0x00000021, 0x03F, 0x00000829,
1954 0x033, 0x00000022, 0x03F, 0x00000848, 0x033, 0x00000023,
1955 0x03F, 0x0000084B, 0x033, 0x00000024, 0x03F, 0x00000C4C,
1956 0x033, 0x00000025, 0x03F, 0x00000C8B, 0x033, 0x00000026,
1957 0x03F, 0x00000CEA, 0x033, 0x00000027, 0x03F, 0x00000CED,
1958 0x033, 0x00000028, 0x03F, 0x00000CF0, 0x033, 0x00000029,
1959 0x03F, 0x00000CF3, 0x033, 0x0000002A, 0x03F, 0x00000CF6,
1960 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1961 0x03F, 0x00000C09, 0x033, 0x00000021, 0x03F, 0x00000C0C,
1962 0x033, 0x00000022, 0x03F, 0x00000C0F, 0x033, 0x00000023,
1963 0x03F, 0x00000C2C, 0x033, 0x00000024, 0x03F, 0x00000C2F,
1964 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
1965 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000C90,
1966 0x033, 0x00000028, 0x03F, 0x00000CD0, 0x033, 0x00000029,
1967 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5,
1968 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1969 0x03F, 0x00000005, 0x033, 0x00000021, 0x03F, 0x00000008,
1970 0x033, 0x00000022, 0x03F, 0x0000000B, 0x033, 0x00000023,
1971 0x03F, 0x0000000E, 0x033, 0x00000024, 0x03F, 0x0000002B,
1972 0x033, 0x00000025, 0x03F, 0x00000068, 0x033, 0x00000026,
1973 0x03F, 0x0000006B, 0x033, 0x00000027, 0x03F, 0x0000006E,
1974 0x033, 0x00000028, 0x03F, 0x00000071, 0x033, 0x00000029,
1975 0x03F, 0x00000074, 0x033, 0x0000002A, 0x03F, 0x00000077,
1976 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1977 0x03F, 0x00000C09, 0x033, 0x00000021, 0x03F, 0x00000C0C,
1978 0x033, 0x00000022, 0x03F, 0x00000C0F, 0x033, 0x00000023,
1979 0x03F, 0x00000C2C, 0x033, 0x00000024, 0x03F, 0x00000C2F,
1980 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
1981 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000C90,
1982 0x033, 0x00000028, 0x03F, 0x00000CD0, 0x033, 0x00000029,
1983 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5,
1984 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1985 0x03F, 0x00000429, 0x033, 0x00000021, 0x03F, 0x00000828,
1986 0x033, 0x00000022, 0x03F, 0x00000847, 0x033, 0x00000023,
1987 0x03F, 0x0000084A, 0x033, 0x00000024, 0x03F, 0x00000C4B,
1988 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
1989 0x03F, 0x00000CEA, 0x033, 0x00000027, 0x03F, 0x00000CED,
1990 0x033, 0x00000028, 0x03F, 0x00000CF0, 0x033, 0x00000029,
1991 0x03F, 0x00000CF3, 0x033, 0x0000002A, 0x03F, 0x00000CF6,
1992 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
1993 0x03F, 0x00000C09, 0x033, 0x00000021, 0x03F, 0x00000C0C,
1994 0x033, 0x00000022, 0x03F, 0x00000C0F, 0x033, 0x00000023,
1995 0x03F, 0x00000C2C, 0x033, 0x00000024, 0x03F, 0x00000C2F,
1996 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
1997 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000C90,
1998 0x033, 0x00000028, 0x03F, 0x00000CD0, 0x033, 0x00000029,
1999 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5,
2000 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
2001 0x03F, 0x0000042B, 0x033, 0x00000021, 0x03F, 0x0000082A,
2002 0x033, 0x00000022, 0x03F, 0x00000849, 0x033, 0x00000023,
2003 0x03F, 0x0000084C, 0x033, 0x00000024, 0x03F, 0x00000C4C,
2004 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
2005 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000CEB,
2006 0x033, 0x00000028, 0x03F, 0x00000CEE, 0x033, 0x00000029,
2007 0x03F, 0x00000CF1, 0x033, 0x0000002A, 0x03F, 0x00000CF4,
2008 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
2009 0x03F, 0x0000042B, 0x033, 0x00000021, 0x03F, 0x0000082A,
2010 0x033, 0x00000022, 0x03F, 0x00000849, 0x033, 0x00000023,
2011 0x03F, 0x0000084C, 0x033, 0x00000024, 0x03F, 0x00000C4C,
2012 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
2013 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000CEB,
2014 0x033, 0x00000028, 0x03F, 0x00000CEE, 0x033, 0x00000029,
2015 0x03F, 0x00000CF1, 0x033, 0x0000002A, 0x03F, 0x00000CF4,
2016 0xA0000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x00000C09,
2017 0x033, 0x00000021, 0x03F, 0x00000C0C, 0x033, 0x00000022,
2018 0x03F, 0x00000C0F, 0x033, 0x00000023, 0x03F, 0x00000C2C,
2019 0x033, 0x00000024, 0x03F, 0x00000C2F, 0x033, 0x00000025,
2020 0x03F, 0x00000C8A, 0x033, 0x00000026, 0x03F, 0x00000C8D,
2021 0x033, 0x00000027, 0x03F, 0x00000C90, 0x033, 0x00000028,
2022 0x03F, 0x00000CD0, 0x033, 0x00000029, 0x03F, 0x00000CF2,
2023 0x033, 0x0000002A, 0x03F, 0x00000CF5, 0xB0000000, 0x00000000,
2024 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000060,
2025 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
2026 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
2027 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
2028 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
2029 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
2030 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
2031 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
2032 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000060,
2033 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
2034 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
2035 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
2036 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
2037 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
2038 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
2039 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
2040 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2041 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
2042 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
2043 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
2044 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
2045 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
2046 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
2047 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
2048 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2049 0x03F, 0x00000005, 0x033, 0x00000061, 0x03F, 0x00000008,
2050 0x033, 0x00000062, 0x03F, 0x0000000B, 0x033, 0x00000063,
2051 0x03F, 0x0000000E, 0x033, 0x00000064, 0x03F, 0x0000002B,
2052 0x033, 0x00000065, 0x03F, 0x00000068, 0x033, 0x00000066,
2053 0x03F, 0x0000006B, 0x033, 0x00000067, 0x03F, 0x0000006E,
2054 0x033, 0x00000068, 0x03F, 0x00000071, 0x033, 0x00000069,
2055 0x03F, 0x00000074, 0x033, 0x0000006A, 0x03F, 0x00000077,
2056 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000060,
2057 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
2058 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
2059 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
2060 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
2061 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
2062 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
2063 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
2064 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000060,
2065 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
2066 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
2067 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
2068 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
2069 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
2070 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
2071 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
2072 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2073 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
2074 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
2075 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
2076 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
2077 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
2078 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
2079 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
2080 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2081 0x03F, 0x00000005, 0x033, 0x00000061, 0x03F, 0x00000008,
2082 0x033, 0x00000062, 0x03F, 0x0000000B, 0x033, 0x00000063,
2083 0x03F, 0x0000000E, 0x033, 0x00000064, 0x03F, 0x0000002B,
2084 0x033, 0x00000065, 0x03F, 0x00000068, 0x033, 0x00000066,
2085 0x03F, 0x0000006B, 0x033, 0x00000067, 0x03F, 0x0000006E,
2086 0x033, 0x00000068, 0x03F, 0x00000071, 0x033, 0x00000069,
2087 0x03F, 0x00000074, 0x033, 0x0000006A, 0x03F, 0x00000077,
2088 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2089 0x03F, 0x00000005, 0x033, 0x00000061, 0x03F, 0x00000008,
2090 0x033, 0x00000062, 0x03F, 0x0000000B, 0x033, 0x00000063,
2091 0x03F, 0x0000000E, 0x033, 0x00000064, 0x03F, 0x0000002B,
2092 0x033, 0x00000065, 0x03F, 0x00000068, 0x033, 0x00000066,
2093 0x03F, 0x0000006B, 0x033, 0x00000067, 0x03F, 0x0000006E,
2094 0x033, 0x00000068, 0x03F, 0x00000071, 0x033, 0x00000069,
2095 0x03F, 0x00000074, 0x033, 0x0000006A, 0x03F, 0x00000077,
2096 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2097 0x03F, 0x00000842, 0x033, 0x00000061, 0x03F, 0x00000845,
2098 0x033, 0x00000062, 0x03F, 0x00000866, 0x033, 0x00000063,
2099 0x03F, 0x000008A6, 0x033, 0x00000064, 0x03F, 0x000008C8,
2100 0x033, 0x00000065, 0x03F, 0x00000CE8, 0x033, 0x00000066,
2101 0x03F, 0x00000CEB, 0x033, 0x00000067, 0x03F, 0x00000CEE,
2102 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069,
2103 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7,
2104 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2105 0x03F, 0x0000042A, 0x033, 0x00000061, 0x03F, 0x00000829,
2106 0x033, 0x00000062, 0x03F, 0x00000848, 0x033, 0x00000063,
2107 0x03F, 0x0000084B, 0x033, 0x00000064, 0x03F, 0x00000C69,
2108 0x033, 0x00000065, 0x03F, 0x00000CA9, 0x033, 0x00000066,
2109 0x03F, 0x00000CEA, 0x033, 0x00000067, 0x03F, 0x00000CED,
2110 0x033, 0x00000068, 0x03F, 0x00000CF0, 0x033, 0x00000069,
2111 0x03F, 0x00000CF3, 0x033, 0x0000006A, 0x03F, 0x00000CF6,
2112 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2113 0x03F, 0x00000C0A, 0x033, 0x00000061, 0x03F, 0x00000C0D,
2114 0x033, 0x00000062, 0x03F, 0x00000C2A, 0x033, 0x00000063,
2115 0x03F, 0x00000C2D, 0x033, 0x00000064, 0x03F, 0x00000C6A,
2116 0x033, 0x00000065, 0x03F, 0x00000CAA, 0x033, 0x00000066,
2117 0x03F, 0x00000CAD, 0x033, 0x00000067, 0x03F, 0x00000CB0,
2118 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069,
2119 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7,
2120 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2121 0x03F, 0x00000005, 0x033, 0x00000061, 0x03F, 0x00000008,
2122 0x033, 0x00000062, 0x03F, 0x0000000B, 0x033, 0x00000063,
2123 0x03F, 0x0000000E, 0x033, 0x00000064, 0x03F, 0x0000002B,
2124 0x033, 0x00000065, 0x03F, 0x00000068, 0x033, 0x00000066,
2125 0x03F, 0x0000006B, 0x033, 0x00000067, 0x03F, 0x0000006E,
2126 0x033, 0x00000068, 0x03F, 0x00000071, 0x033, 0x00000069,
2127 0x03F, 0x00000074, 0x033, 0x0000006A, 0x03F, 0x00000077,
2128 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2129 0x03F, 0x00000C0A, 0x033, 0x00000061, 0x03F, 0x00000C0D,
2130 0x033, 0x00000062, 0x03F, 0x00000C2A, 0x033, 0x00000063,
2131 0x03F, 0x00000C2D, 0x033, 0x00000064, 0x03F, 0x00000C6A,
2132 0x033, 0x00000065, 0x03F, 0x00000CAA, 0x033, 0x00000066,
2133 0x03F, 0x00000CAD, 0x033, 0x00000067, 0x03F, 0x00000CB0,
2134 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069,
2135 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7,
2136 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2137 0x03F, 0x00000429, 0x033, 0x00000061, 0x03F, 0x00000828,
2138 0x033, 0x00000062, 0x03F, 0x00000847, 0x033, 0x00000063,
2139 0x03F, 0x0000084A, 0x033, 0x00000064, 0x03F, 0x00000C4B,
2140 0x033, 0x00000065, 0x03F, 0x00000C8A, 0x033, 0x00000066,
2141 0x03F, 0x00000CEA, 0x033, 0x00000067, 0x03F, 0x00000CED,
2142 0x033, 0x00000068, 0x03F, 0x00000CF0, 0x033, 0x00000069,
2143 0x03F, 0x00000CF3, 0x033, 0x0000006A, 0x03F, 0x00000CF6,
2144 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2145 0x03F, 0x00000C0A, 0x033, 0x00000061, 0x03F, 0x00000C0D,
2146 0x033, 0x00000062, 0x03F, 0x00000C2A, 0x033, 0x00000063,
2147 0x03F, 0x00000C2D, 0x033, 0x00000064, 0x03F, 0x00000C6A,
2148 0x033, 0x00000065, 0x03F, 0x00000CAA, 0x033, 0x00000066,
2149 0x03F, 0x00000CAD, 0x033, 0x00000067, 0x03F, 0x00000CB0,
2150 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069,
2151 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7,
2152 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2153 0x03F, 0x0000042C, 0x033, 0x00000061, 0x03F, 0x0000082B,
2154 0x033, 0x00000062, 0x03F, 0x0000084A, 0x033, 0x00000063,
2155 0x03F, 0x0000084D, 0x033, 0x00000064, 0x03F, 0x00000C4E,
2156 0x033, 0x00000065, 0x03F, 0x00000C8C, 0x033, 0x00000066,
2157 0x03F, 0x00000C8F, 0x033, 0x00000067, 0x03F, 0x00000CEC,
2158 0x033, 0x00000068, 0x03F, 0x00000CEF, 0x033, 0x00000069,
2159 0x03F, 0x00000CF2, 0x033, 0x0000006A, 0x03F, 0x00000CF5,
2160 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
2161 0x03F, 0x0000042C, 0x033, 0x00000061, 0x03F, 0x0000082B,
2162 0x033, 0x00000062, 0x03F, 0x0000084A, 0x033, 0x00000063,
2163 0x03F, 0x0000084D, 0x033, 0x00000064, 0x03F, 0x00000C4E,
2164 0x033, 0x00000065, 0x03F, 0x00000C8C, 0x033, 0x00000066,
2165 0x03F, 0x00000C8F, 0x033, 0x00000067, 0x03F, 0x00000CEC,
2166 0x033, 0x00000068, 0x03F, 0x00000CEF, 0x033, 0x00000069,
2167 0x03F, 0x00000CF2, 0x033, 0x0000006A, 0x03F, 0x00000CF5,
2168 0xA0000000, 0x00000000, 0x033, 0x00000060, 0x03F, 0x00000C0A,
2169 0x033, 0x00000061, 0x03F, 0x00000C0D, 0x033, 0x00000062,
2170 0x03F, 0x00000C2A, 0x033, 0x00000063, 0x03F, 0x00000C2D,
2171 0x033, 0x00000064, 0x03F, 0x00000C6A, 0x033, 0x00000065,
2172 0x03F, 0x00000CAA, 0x033, 0x00000066, 0x03F, 0x00000CAD,
2173 0x033, 0x00000067, 0x03F, 0x00000CB0, 0x033, 0x00000068,
2174 0x03F, 0x00000CF1, 0x033, 0x00000069, 0x03F, 0x00000CF4,
2175 0x033, 0x0000006A, 0x03F, 0x00000CF7, 0xB0000000, 0x00000000,
2176 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2177 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
2178 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
2179 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
2180 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
2181 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
2182 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
2183 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
2184 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2185 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
2186 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
2187 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
2188 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
2189 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
2190 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
2191 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
2192 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2193 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
2194 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
2195 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
2196 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
2197 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
2198 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
2199 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
2200 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2201 0x03F, 0x00000005, 0x033, 0x000000A1, 0x03F, 0x00000008,
2202 0x033, 0x000000A2, 0x03F, 0x0000000B, 0x033, 0x000000A3,
2203 0x03F, 0x0000000E, 0x033, 0x000000A4, 0x03F, 0x00000047,
2204 0x033, 0x000000A5, 0x03F, 0x0000004A, 0x033, 0x000000A6,
2205 0x03F, 0x0000004D, 0x033, 0x000000A7, 0x03F, 0x00000050,
2206 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9,
2207 0x03F, 0x00000056, 0x033, 0x000000AA, 0x03F, 0x00000094,
2208 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2209 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
2210 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
2211 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
2212 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
2213 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
2214 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
2215 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
2216 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2217 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
2218 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
2219 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
2220 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
2221 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
2222 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
2223 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
2224 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2225 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
2226 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
2227 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
2228 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
2229 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
2230 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
2231 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
2232 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2233 0x03F, 0x00000005, 0x033, 0x000000A1, 0x03F, 0x00000008,
2234 0x033, 0x000000A2, 0x03F, 0x0000000B, 0x033, 0x000000A3,
2235 0x03F, 0x0000000E, 0x033, 0x000000A4, 0x03F, 0x00000047,
2236 0x033, 0x000000A5, 0x03F, 0x0000004A, 0x033, 0x000000A6,
2237 0x03F, 0x0000004D, 0x033, 0x000000A7, 0x03F, 0x00000050,
2238 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9,
2239 0x03F, 0x00000056, 0x033, 0x000000AA, 0x03F, 0x00000094,
2240 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2241 0x03F, 0x00000005, 0x033, 0x000000A1, 0x03F, 0x00000008,
2242 0x033, 0x000000A2, 0x03F, 0x0000000B, 0x033, 0x000000A3,
2243 0x03F, 0x0000000E, 0x033, 0x000000A4, 0x03F, 0x00000047,
2244 0x033, 0x000000A5, 0x03F, 0x0000004A, 0x033, 0x000000A6,
2245 0x03F, 0x0000004D, 0x033, 0x000000A7, 0x03F, 0x00000050,
2246 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9,
2247 0x03F, 0x00000056, 0x033, 0x000000AA, 0x03F, 0x00000094,
2248 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2249 0x03F, 0x00000826, 0x033, 0x000000A1, 0x03F, 0x00000829,
2250 0x033, 0x000000A2, 0x03F, 0x0000082C, 0x033, 0x000000A3,
2251 0x03F, 0x0000082F, 0x033, 0x000000A4, 0x03F, 0x0000086C,
2252 0x033, 0x000000A5, 0x03F, 0x00000CE8, 0x033, 0x000000A6,
2253 0x03F, 0x00000CEB, 0x033, 0x000000A7, 0x03F, 0x00000CEE,
2254 0x033, 0x000000A8, 0x03F, 0x00000CF1, 0x033, 0x000000A9,
2255 0x03F, 0x00000CF4, 0x033, 0x000000AA, 0x03F, 0x00000CF7,
2256 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2257 0x03F, 0x0000042A, 0x033, 0x000000A1, 0x03F, 0x00000829,
2258 0x033, 0x000000A2, 0x03F, 0x00000848, 0x033, 0x000000A3,
2259 0x03F, 0x0000084B, 0x033, 0x000000A4, 0x03F, 0x00000C4C,
2260 0x033, 0x000000A5, 0x03F, 0x00000CA9, 0x033, 0x000000A6,
2261 0x03F, 0x00000CEA, 0x033, 0x000000A7, 0x03F, 0x00000CED,
2262 0x033, 0x000000A8, 0x03F, 0x00000CF0, 0x033, 0x000000A9,
2263 0x03F, 0x00000CF3, 0x033, 0x000000AA, 0x03F, 0x00000CF6,
2264 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2265 0x03F, 0x00000C09, 0x033, 0x000000A1, 0x03F, 0x00000C0C,
2266 0x033, 0x000000A2, 0x03F, 0x00000C0F, 0x033, 0x000000A3,
2267 0x03F, 0x00000C2C, 0x033, 0x000000A4, 0x03F, 0x00000C2F,
2268 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
2269 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000C90,
2270 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
2271 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
2272 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2273 0x03F, 0x00000005, 0x033, 0x000000A1, 0x03F, 0x00000008,
2274 0x033, 0x000000A2, 0x03F, 0x0000000B, 0x033, 0x000000A3,
2275 0x03F, 0x0000000E, 0x033, 0x000000A4, 0x03F, 0x00000047,
2276 0x033, 0x000000A5, 0x03F, 0x0000004A, 0x033, 0x000000A6,
2277 0x03F, 0x0000004D, 0x033, 0x000000A7, 0x03F, 0x00000050,
2278 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9,
2279 0x03F, 0x00000056, 0x033, 0x000000AA, 0x03F, 0x00000094,
2280 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2281 0x03F, 0x00000C09, 0x033, 0x000000A1, 0x03F, 0x00000C0C,
2282 0x033, 0x000000A2, 0x03F, 0x00000C0F, 0x033, 0x000000A3,
2283 0x03F, 0x00000C2C, 0x033, 0x000000A4, 0x03F, 0x00000C2F,
2284 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
2285 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000C90,
2286 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
2287 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
2288 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2289 0x03F, 0x00000429, 0x033, 0x000000A1, 0x03F, 0x00000828,
2290 0x033, 0x000000A2, 0x03F, 0x00000847, 0x033, 0x000000A3,
2291 0x03F, 0x0000084A, 0x033, 0x000000A4, 0x03F, 0x00000C4B,
2292 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
2293 0x03F, 0x00000CEA, 0x033, 0x000000A7, 0x03F, 0x00000CED,
2294 0x033, 0x000000A8, 0x03F, 0x00000CF0, 0x033, 0x000000A9,
2295 0x03F, 0x00000CF3, 0x033, 0x000000AA, 0x03F, 0x00000CF6,
2296 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2297 0x03F, 0x00000C09, 0x033, 0x000000A1, 0x03F, 0x00000C0C,
2298 0x033, 0x000000A2, 0x03F, 0x00000C0F, 0x033, 0x000000A3,
2299 0x03F, 0x00000C2C, 0x033, 0x000000A4, 0x03F, 0x00000C2F,
2300 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
2301 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000C90,
2302 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
2303 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
2304 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2305 0x03F, 0x0000042A, 0x033, 0x000000A1, 0x03F, 0x00000829,
2306 0x033, 0x000000A2, 0x03F, 0x00000848, 0x033, 0x000000A3,
2307 0x03F, 0x0000084B, 0x033, 0x000000A4, 0x03F, 0x00000C4C,
2308 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
2309 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000CEC,
2310 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
2311 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
2312 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
2313 0x03F, 0x0000042A, 0x033, 0x000000A1, 0x03F, 0x00000829,
2314 0x033, 0x000000A2, 0x03F, 0x00000848, 0x033, 0x000000A3,
2315 0x03F, 0x0000084B, 0x033, 0x000000A4, 0x03F, 0x00000C4C,
2316 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
2317 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000CEC,
2318 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
2319 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
2320 0xA0000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000C09,
2321 0x033, 0x000000A1, 0x03F, 0x00000C0C, 0x033, 0x000000A2,
2322 0x03F, 0x00000C0F, 0x033, 0x000000A3, 0x03F, 0x00000C2C,
2323 0x033, 0x000000A4, 0x03F, 0x00000C2F, 0x033, 0x000000A5,
2324 0x03F, 0x00000C8A, 0x033, 0x000000A6, 0x03F, 0x00000C8D,
2325 0x033, 0x000000A7, 0x03F, 0x00000C90, 0x033, 0x000000A8,
2326 0x03F, 0x00000CEF, 0x033, 0x000000A9, 0x03F, 0x00000CF2,
2327 0x033, 0x000000AA, 0x03F, 0x00000CF5, 0xB0000000, 0x00000000,
2328 0x0EF, 0x00000000, 0x0EF, 0x00000400, 0x8300100f, 0x0a0a0a0a,
2329 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A,
2330 0x033, 0x00000001, 0x03F, 0x0000265A, 0x033, 0x00000002,
2331 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A,
2332 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
2333 0x03F, 0x0000265A, 0x033, 0x00000001, 0x03F, 0x0000265A,
2334 0x033, 0x00000002, 0x03F, 0x0000265A, 0x033, 0x00000003,
2335 0x03F, 0x0000265A, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
2336 0x033, 0x00000000, 0x03F, 0x0000265A, 0x033, 0x00000001,
2337 0x03F, 0x0000265A, 0x033, 0x00000002, 0x03F, 0x0000265A,
2338 0x033, 0x00000003, 0x03F, 0x0000265A, 0x9300200f, 0x00000000,
2339 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A,
2340 0x033, 0x00000001, 0x03F, 0x0000265A, 0x033, 0x00000002,
2341 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A,
2342 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
2343 0x03F, 0x0000265A, 0x033, 0x00000001, 0x03F, 0x0000265A,
2344 0x033, 0x00000002, 0x03F, 0x0000265A, 0x033, 0x00000003,
2345 0x03F, 0x0000265A, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
2346 0x033, 0x00000000, 0x03F, 0x0000265A, 0x033, 0x00000001,
2347 0x03F, 0x0000265A, 0x033, 0x00000002, 0x03F, 0x0000265A,
2348 0x033, 0x00000003, 0x03F, 0x0000265A, 0x9000100f, 0x00000000,
2349 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A,
2350 0x033, 0x00000001, 0x03F, 0x0000265A, 0x033, 0x00000002,
2351 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A,
2352 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
2353 0x03F, 0x0000265A, 0x033, 0x00000001, 0x03F, 0x0000265A,
2354 0x033, 0x00000002, 0x03F, 0x0000265A, 0x033, 0x00000003,
2355 0x03F, 0x0000265A, 0xA0000000, 0x00000000, 0x033, 0x00000000,
2356 0x03F, 0x000004BB, 0x033, 0x00000001, 0x03F, 0x000004BB,
2357 0x033, 0x00000002, 0x03F, 0x000004BB, 0x033, 0x00000003,
2358 0x03F, 0x000004BB, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
2359 0x0EF, 0x00000100, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
2360 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001,
2361 0x03F, 0x00000745, 0x033, 0x00000002, 0x03F, 0x00000745,
2362 0x033, 0x00000003, 0x03F, 0x00000745, 0x9300100f, 0x05050505,
2363 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745,
2364 0x033, 0x00000001, 0x03F, 0x00000745, 0x033, 0x00000002,
2365 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745,
2366 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
2367 0x03F, 0x00000745, 0x033, 0x00000001, 0x03F, 0x00000745,
2368 0x033, 0x00000002, 0x03F, 0x00000745, 0x033, 0x00000003,
2369 0x03F, 0x00000745, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
2370 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001,
2371 0x03F, 0x00000745, 0x033, 0x00000002, 0x03F, 0x00000745,
2372 0x033, 0x00000003, 0x03F, 0x00000745, 0x9000100f, 0x0a0a0a0a,
2373 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745,
2374 0x033, 0x00000001, 0x03F, 0x00000745, 0x033, 0x00000002,
2375 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745,
2376 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
2377 0x03F, 0x00000745, 0x033, 0x00000001, 0x03F, 0x00000745,
2378 0x033, 0x00000002, 0x03F, 0x00000745, 0x033, 0x00000003,
2379 0x03F, 0x00000745, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
2380 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001,
2381 0x03F, 0x00000745, 0x033, 0x00000002, 0x03F, 0x00000745,
2382 0x033, 0x00000003, 0x03F, 0x00000745, 0x9000200f, 0x00000000,
2383 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745,
2384 0x033, 0x00000001, 0x03F, 0x00000745, 0x033, 0x00000002,
2385 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745,
2386 0xA0000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000F34,
2387 0x033, 0x00000001, 0x03F, 0x00000F34, 0x033, 0x00000002,
2388 0x03F, 0x00000F34, 0x033, 0x00000003, 0x03F, 0x00000F34,
2389 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x8300100f, 0x0a0a0a0a,
2390 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
2391 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
2392 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
2393 0x058, 0x00082030, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
2394 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
2395 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
2396 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
2397 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400,
2398 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
2399 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
2400 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9300200f, 0x00000000,
2401 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
2402 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
2403 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
2404 0x058, 0x00082030, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
2405 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
2406 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
2407 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
2408 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x081, 0x0000F400,
2409 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
2410 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
2411 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9000100f, 0x00000000,
2412 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
2413 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
2414 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
2415 0x058, 0x00082030, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
2416 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
2417 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
2418 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
2419 0xA0000000, 0x00000000, 0x081, 0x0000F000, 0x087, 0x00016040,
2420 0x051, 0x00000C00, 0x052, 0x0007C241, 0x053, 0x0001C069,
2421 0x054, 0x00078032, 0x057, 0x0000CE0A, 0x058, 0x00058750,
2422 0xB0000000, 0x00000000, 0x0EF, 0x00000800, 0x8300100f, 0x0a0a0a0a,
2423 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
2424 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
2425 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
2426 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
2427 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
2428 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
2429 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
2430 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9300100f, 0x05050505,
2431 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
2432 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
2433 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
2434 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
2435 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
2436 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
2437 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
2438 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9300100f, 0x00000000,
2439 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
2440 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
2441 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
2442 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
2443 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
2444 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
2445 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
2446 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9300200f, 0x00000000,
2447 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
2448 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
2449 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
2450 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
2451 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
2452 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
2453 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
2454 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9000100f, 0x0a0a0a0a,
2455 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
2456 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
2457 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
2458 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
2459 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
2460 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
2461 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
2462 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9000100f, 0x05050505,
2463 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
2464 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
2465 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
2466 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
2467 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
2468 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
2469 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
2470 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9000100f, 0x00000000,
2471 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
2472 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
2473 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
2474 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
2475 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
2476 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
2477 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
2478 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9000200f, 0x00000000,
2479 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
2480 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
2481 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
2482 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
2483 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
2484 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
2485 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
2486 0x033, 0x0000000A, 0x03F, 0x0000003C, 0xA0000000, 0x00000000,
2487 0x033, 0x00000000, 0x03F, 0x0005142C, 0x033, 0x00000001,
2488 0x03F, 0x0005142F, 0x033, 0x00000002, 0x03F, 0x00051432,
2489 0x033, 0x00000003, 0x03F, 0x00051C87, 0x033, 0x00000004,
2490 0x03F, 0x00051C8A, 0x033, 0x00000005, 0x03F, 0x00051C8D,
2491 0x033, 0x00000006, 0x03F, 0x00051CEB, 0x033, 0x00000007,
2492 0x03F, 0x00051CEE, 0x033, 0x00000008, 0x03F, 0x00051CF1,
2493 0x033, 0x00000009, 0x03F, 0x00051CF4, 0x033, 0x0000000A,
2494 0x03F, 0x00051CF7, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
2495 0x0EF, 0x00000010, 0x033, 0x00000000, 0x008, 0x0009C060,
2496 0x033, 0x00000001, 0x008, 0x0009C060, 0x0EF, 0x00000000,
2497 0x033, 0x000000A2, 0x0EF, 0x00080000, 0x03E, 0x0000593F,
2498 0x03F, 0x000C0F4F, 0x0EF, 0x00000000, 0x033, 0x000000A3,
2499 0x0EF, 0x00080000, 0x03E, 0x00005934, 0x03F, 0x0005AFCF,
2500 0x0EF, 0x00000000,
2501
2502};
2503
2504void odm_read_and_config_mp_8822b_radiob(struct phy_dm_struct *dm)
2505{
2506 u32 i = 0;
2507 u8 c_cond;
2508 bool is_matched = true, is_skipped = false;
2509 u32 array_len = sizeof(array_mp_8822b_radiob) / sizeof(u32);
2510 u32 *array = array_mp_8822b_radiob;
2511
2512 u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
2513
2514 ODM_RT_TRACE(dm, ODM_COMP_INIT,
2515 "===> %s\n", __func__);
2516
2517 for (; (i + 1) < array_len; i = i + 2) {
2518 v1 = array[i];
2519 v2 = array[i + 1];
2520
2521 if (v1 & BIT(31)) { /* positive condition*/
2522 c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
2523 if (c_cond == COND_ENDIF) { /*end*/
2524 is_matched = true;
2525 is_skipped = false;
2526 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
2527 } else if (c_cond == COND_ELSE) { /*else*/
2528 is_matched = is_skipped ? false : true;
2529 ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
2530 } else { /*if , else if*/
2531 pre_v1 = v1;
2532 pre_v2 = v2;
2533 ODM_RT_TRACE(dm, ODM_COMP_INIT,
2534 "IF or ELSE IF\n");
2535 }
2536 } else if (v1 & BIT(30)) { /*negative condition*/
2537 if (is_skipped) {
2538 is_matched = false;
2539 continue;
2540 }
2541
2542 if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
2543 is_matched = true;
2544 is_skipped = true;
2545 } else {
2546 is_matched = false;
2547 is_skipped = false;
2548 }
2549 } else if (is_matched) {
2550 odm_config_rf_radio_b_8822b(dm, v1, v2);
2551 }
2552 }
2553}
2554
2555u32 odm_get_version_mp_8822b_radiob(void) { return 67; }
2556
2557/******************************************************************************
2558 * txpowertrack.TXT
2559 ******************************************************************************/
2560
2561static u8 delta_swing_index_mp_5gb_n_txpwrtrack_8822b[][DELTA_SWINGIDX_SIZE] = {
2562 {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10,
2563 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
2564 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8,
2565 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
2566 {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9,
2567 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
2568};
2569
2570static u8 delta_swing_index_mp_5gb_p_txpwrtrack_8822b[][DELTA_SWINGIDX_SIZE] = {
2571 {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11,
2572 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19},
2573 {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10,
2574 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18},
2575 {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10,
2576 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17},
2577};
2578
2579static u8 delta_swing_index_mp_5ga_n_txpwrtrack_8822b[][DELTA_SWINGIDX_SIZE] = {
2580 {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10,
2581 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
2582 {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9,
2583 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
2584 {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9,
2585 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
2586};
2587
2588static u8 delta_swing_index_mp_5ga_p_txpwrtrack_8822b[][DELTA_SWINGIDX_SIZE] = {
2589 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
2590 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20},
2591 {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9,
2592 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18},
2593 {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10,
2594 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18},
2595};
2596
2597static u8 delta_swing_index_mp_2gb_n_txpwrtrack_8822b[] = {
2598 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2599 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
2600
2601static u8 delta_swing_index_mp_2gb_p_txpwrtrack_8822b[] = {
2602 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
2603 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
2604
2605static u8 delta_swing_index_mp_2ga_n_txpwrtrack_8822b[] = {
2606 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
2607 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
2608
2609static u8 delta_swing_index_mp_2ga_p_txpwrtrack_8822b[] = {
2610 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
2611 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
2612
2613static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_8822b[] = {
2614 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2615 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
2616
2617static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_8822b[] = {
2618 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
2619 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
2620
2621static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_8822b[] = {
2622 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2623 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
2624
2625static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_8822b[] = {
2626 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
2627 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
2628
2629void odm_read_and_config_mp_8822b_txpowertrack(struct phy_dm_struct *dm)
2630{
2631 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
2632
2633 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
2634
2635 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
2636 delta_swing_index_mp_2ga_p_txpwrtrack_8822b,
2637 DELTA_SWINGIDX_SIZE);
2638 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
2639 delta_swing_index_mp_2ga_n_txpwrtrack_8822b,
2640 DELTA_SWINGIDX_SIZE);
2641 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
2642 delta_swing_index_mp_2gb_p_txpwrtrack_8822b,
2643 DELTA_SWINGIDX_SIZE);
2644 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
2645 delta_swing_index_mp_2gb_n_txpwrtrack_8822b,
2646 DELTA_SWINGIDX_SIZE);
2647
2648 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
2649 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_8822b,
2650 DELTA_SWINGIDX_SIZE);
2651 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
2652 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_8822b,
2653 DELTA_SWINGIDX_SIZE);
2654 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
2655 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_8822b,
2656 DELTA_SWINGIDX_SIZE);
2657 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
2658 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_8822b,
2659 DELTA_SWINGIDX_SIZE);
2660
2661 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
2662 delta_swing_index_mp_5ga_p_txpwrtrack_8822b,
2663 DELTA_SWINGIDX_SIZE * 3);
2664 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
2665 delta_swing_index_mp_5ga_n_txpwrtrack_8822b,
2666 DELTA_SWINGIDX_SIZE * 3);
2667 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
2668 delta_swing_index_mp_5gb_p_txpwrtrack_8822b,
2669 DELTA_SWINGIDX_SIZE * 3);
2670 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
2671 delta_swing_index_mp_5gb_n_txpwrtrack_8822b,
2672 DELTA_SWINGIDX_SIZE * 3);
2673}
2674
2675/******************************************************************************
2676 * txpowertrack_type0.TXT
2677 ******************************************************************************/
2678
2679static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type0_8822b
2680 [][DELTA_SWINGIDX_SIZE] = {
2681 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2682 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
2683 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8,
2684 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14},
2685 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8,
2686 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15},
2687};
2688
2689static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type0_8822b
2690 [][DELTA_SWINGIDX_SIZE] = {
2691 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2692 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15},
2693 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2694 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15},
2695 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2696 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16},
2697};
2698
2699static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type0_8822b
2700 [][DELTA_SWINGIDX_SIZE] = {
2701 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2702 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14},
2703 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2704 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14},
2705 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2706 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14},
2707};
2708
2709static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type0_8822b
2710 [][DELTA_SWINGIDX_SIZE] = {
2711 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2712 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15},
2713 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2714 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15},
2715 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
2716 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15},
2717};
2718
2719static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type0_8822b[] = {
2720 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2721 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
2722
2723static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type0_8822b[] = {
2724 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
2725 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
2726
2727static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type0_8822b[] = {
2728 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
2729 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
2730
2731static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type0_8822b[] = {
2732 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
2733 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
2734
2735static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type0_8822b[] = {
2736 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2737 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
2738
2739static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type0_8822b[] = {
2740 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
2741 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
2742
2743static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type0_8822b[] = {
2744 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2745 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
2746
2747static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type0_8822b[] = {
2748 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
2749 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
2750
2751void odm_read_and_config_mp_8822b_txpowertrack_type0(struct phy_dm_struct *dm)
2752{
2753 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
2754
2755 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
2756
2757 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
2758 delta_swing_index_mp_2ga_p_txpwrtrack_type0_8822b,
2759 DELTA_SWINGIDX_SIZE);
2760 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
2761 delta_swing_index_mp_2ga_n_txpwrtrack_type0_8822b,
2762 DELTA_SWINGIDX_SIZE);
2763 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
2764 delta_swing_index_mp_2gb_p_txpwrtrack_type0_8822b,
2765 DELTA_SWINGIDX_SIZE);
2766 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
2767 delta_swing_index_mp_2gb_n_txpwrtrack_type0_8822b,
2768 DELTA_SWINGIDX_SIZE);
2769
2770 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
2771 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type0_8822b,
2772 DELTA_SWINGIDX_SIZE);
2773 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
2774 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type0_8822b,
2775 DELTA_SWINGIDX_SIZE);
2776 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
2777 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type0_8822b,
2778 DELTA_SWINGIDX_SIZE);
2779 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
2780 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type0_8822b,
2781 DELTA_SWINGIDX_SIZE);
2782
2783 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
2784 delta_swing_index_mp_5ga_p_txpwrtrack_type0_8822b,
2785 DELTA_SWINGIDX_SIZE * 3);
2786 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
2787 delta_swing_index_mp_5ga_n_txpwrtrack_type0_8822b,
2788 DELTA_SWINGIDX_SIZE * 3);
2789 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
2790 delta_swing_index_mp_5gb_p_txpwrtrack_type0_8822b,
2791 DELTA_SWINGIDX_SIZE * 3);
2792 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
2793 delta_swing_index_mp_5gb_n_txpwrtrack_type0_8822b,
2794 DELTA_SWINGIDX_SIZE * 3);
2795}
2796
2797/******************************************************************************
2798 * txpowertrack_type1.TXT
2799 ******************************************************************************/
2800
2801static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type1_8822b
2802 [][DELTA_SWINGIDX_SIZE] = {
2803 {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10,
2804 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
2805 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8,
2806 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
2807 {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9,
2808 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
2809};
2810
2811static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type1_8822b
2812 [][DELTA_SWINGIDX_SIZE] = {
2813 {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11,
2814 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19},
2815 {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10,
2816 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18},
2817 {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10,
2818 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17},
2819};
2820
2821static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type1_8822b
2822 [][DELTA_SWINGIDX_SIZE] = {
2823 {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10,
2824 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
2825 {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9,
2826 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
2827 {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9,
2828 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
2829};
2830
2831static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type1_8822b
2832 [][DELTA_SWINGIDX_SIZE] = {
2833 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
2834 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20},
2835 {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9,
2836 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18},
2837 {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10,
2838 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18},
2839};
2840
2841static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type1_8822b[] = {
2842 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2843 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
2844
2845static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type1_8822b[] = {
2846 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
2847 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
2848
2849static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type1_8822b[] = {
2850 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
2851 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
2852
2853static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type1_8822b[] = {
2854 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
2855 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
2856
2857static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type1_8822b[] = {
2858 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2859 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
2860
2861static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type1_8822b[] = {
2862 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
2863 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
2864
2865static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type1_8822b[] = {
2866 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2867 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
2868
2869static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type1_8822b[] = {
2870 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
2871 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
2872
2873void odm_read_and_config_mp_8822b_txpowertrack_type1(struct phy_dm_struct *dm)
2874{
2875 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
2876
2877 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
2878
2879 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
2880 delta_swing_index_mp_2ga_p_txpwrtrack_type1_8822b,
2881 DELTA_SWINGIDX_SIZE);
2882 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
2883 delta_swing_index_mp_2ga_n_txpwrtrack_type1_8822b,
2884 DELTA_SWINGIDX_SIZE);
2885 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
2886 delta_swing_index_mp_2gb_p_txpwrtrack_type1_8822b,
2887 DELTA_SWINGIDX_SIZE);
2888 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
2889 delta_swing_index_mp_2gb_n_txpwrtrack_type1_8822b,
2890 DELTA_SWINGIDX_SIZE);
2891
2892 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
2893 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type1_8822b,
2894 DELTA_SWINGIDX_SIZE);
2895 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
2896 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type1_8822b,
2897 DELTA_SWINGIDX_SIZE);
2898 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
2899 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type1_8822b,
2900 DELTA_SWINGIDX_SIZE);
2901 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
2902 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type1_8822b,
2903 DELTA_SWINGIDX_SIZE);
2904
2905 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
2906 delta_swing_index_mp_5ga_p_txpwrtrack_type1_8822b,
2907 DELTA_SWINGIDX_SIZE * 3);
2908 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
2909 delta_swing_index_mp_5ga_n_txpwrtrack_type1_8822b,
2910 DELTA_SWINGIDX_SIZE * 3);
2911 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
2912 delta_swing_index_mp_5gb_p_txpwrtrack_type1_8822b,
2913 DELTA_SWINGIDX_SIZE * 3);
2914 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
2915 delta_swing_index_mp_5gb_n_txpwrtrack_type1_8822b,
2916 DELTA_SWINGIDX_SIZE * 3);
2917}
2918
2919/******************************************************************************
2920 * txpowertrack_type2.TXT
2921 ******************************************************************************/
2922
2923static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type2_8822b
2924 [][DELTA_SWINGIDX_SIZE] = {
2925 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
2926 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
2927 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
2928 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
2929 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
2930 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
2931};
2932
2933static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type2_8822b
2934 [][DELTA_SWINGIDX_SIZE] = {
2935 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
2936 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2937 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
2938 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2939 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
2940 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2941};
2942
2943static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type2_8822b
2944 [][DELTA_SWINGIDX_SIZE] = {
2945 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
2946 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
2947 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
2948 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
2949 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
2950 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
2951};
2952
2953static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type2_8822b
2954 [][DELTA_SWINGIDX_SIZE] = {
2955 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
2956 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2957 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
2958 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2959 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
2960 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2961};
2962
2963static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type2_8822b[] = {
2964 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
2965 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
2966
2967static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type2_8822b[] = {
2968 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
2969 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
2970
2971static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type2_8822b[] = {
2972 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
2973 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
2974
2975static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type2_8822b[] = {
2976 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
2977 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
2978
2979static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type2_8822b[] = {
2980 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
2981 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
2982
2983static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type2_8822b[] = {
2984 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
2985 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
2986
2987static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type2_8822b[] = {
2988 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
2989 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
2990
2991static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type2_8822b[] = {
2992 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
2993 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
2994
2995void odm_read_and_config_mp_8822b_txpowertrack_type2(struct phy_dm_struct *dm)
2996{
2997 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
2998
2999 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
3000
3001 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
3002 delta_swing_index_mp_2ga_p_txpwrtrack_type2_8822b,
3003 DELTA_SWINGIDX_SIZE);
3004 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
3005 delta_swing_index_mp_2ga_n_txpwrtrack_type2_8822b,
3006 DELTA_SWINGIDX_SIZE);
3007 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
3008 delta_swing_index_mp_2gb_p_txpwrtrack_type2_8822b,
3009 DELTA_SWINGIDX_SIZE);
3010 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
3011 delta_swing_index_mp_2gb_n_txpwrtrack_type2_8822b,
3012 DELTA_SWINGIDX_SIZE);
3013
3014 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
3015 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type2_8822b,
3016 DELTA_SWINGIDX_SIZE);
3017 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
3018 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type2_8822b,
3019 DELTA_SWINGIDX_SIZE);
3020 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
3021 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type2_8822b,
3022 DELTA_SWINGIDX_SIZE);
3023 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
3024 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type2_8822b,
3025 DELTA_SWINGIDX_SIZE);
3026
3027 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
3028 delta_swing_index_mp_5ga_p_txpwrtrack_type2_8822b,
3029 DELTA_SWINGIDX_SIZE * 3);
3030 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
3031 delta_swing_index_mp_5ga_n_txpwrtrack_type2_8822b,
3032 DELTA_SWINGIDX_SIZE * 3);
3033 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
3034 delta_swing_index_mp_5gb_p_txpwrtrack_type2_8822b,
3035 DELTA_SWINGIDX_SIZE * 3);
3036 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
3037 delta_swing_index_mp_5gb_n_txpwrtrack_type2_8822b,
3038 DELTA_SWINGIDX_SIZE * 3);
3039}
3040
3041/******************************************************************************
3042 * txpowertrack_type3_type5.TXT
3043 ******************************************************************************/
3044
3045static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type3_type5_8822b
3046 [][DELTA_SWINGIDX_SIZE] = {
3047 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3048 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3049 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3050 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3051 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3052 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3053};
3054
3055static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type3_type5_8822b
3056 [][DELTA_SWINGIDX_SIZE] = {
3057 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3058 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3059 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3060 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3061 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3062 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3063};
3064
3065static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type3_type5_8822b
3066 [][DELTA_SWINGIDX_SIZE] = {
3067 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3068 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3069 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3070 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3071 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3072 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3073};
3074
3075static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type3_type5_8822b
3076 [][DELTA_SWINGIDX_SIZE] = {
3077 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3078 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3079 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3080 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3081 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3082 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3083};
3084
3085static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type3_type5_8822b[] = {
3086 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3087 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3088
3089static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type3_type5_8822b[] = {
3090 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3091 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3092
3093static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type3_type5_8822b[] = {
3094 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3095 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3096
3097static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type3_type5_8822b[] = {
3098 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3099 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3100
3101static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type3_type5_8822b[] = {
3102 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3103 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3104
3105static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type3_type5_8822b[] = {
3106 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3107 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3108
3109static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type3_type5_8822b[] = {
3110 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3111 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3112
3113static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type3_type5_8822b[] = {
3114 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3115 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3116
3117void odm_read_and_config_mp_8822b_txpowertrack_type3_type5(
3118 struct phy_dm_struct *dm)
3119{
3120 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
3121
3122 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
3123
3124 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
3125 delta_swing_index_mp_2ga_p_txpwrtrack_type3_type5_8822b,
3126 DELTA_SWINGIDX_SIZE);
3127 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
3128 delta_swing_index_mp_2ga_n_txpwrtrack_type3_type5_8822b,
3129 DELTA_SWINGIDX_SIZE);
3130 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
3131 delta_swing_index_mp_2gb_p_txpwrtrack_type3_type5_8822b,
3132 DELTA_SWINGIDX_SIZE);
3133 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
3134 delta_swing_index_mp_2gb_n_txpwrtrack_type3_type5_8822b,
3135 DELTA_SWINGIDX_SIZE);
3136
3137 odm_move_memory(
3138 dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
3139 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type3_type5_8822b,
3140 DELTA_SWINGIDX_SIZE);
3141 odm_move_memory(
3142 dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
3143 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type3_type5_8822b,
3144 DELTA_SWINGIDX_SIZE);
3145 odm_move_memory(
3146 dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
3147 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type3_type5_8822b,
3148 DELTA_SWINGIDX_SIZE);
3149 odm_move_memory(
3150 dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
3151 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type3_type5_8822b,
3152 DELTA_SWINGIDX_SIZE);
3153
3154 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
3155 delta_swing_index_mp_5ga_p_txpwrtrack_type3_type5_8822b,
3156 DELTA_SWINGIDX_SIZE * 3);
3157 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
3158 delta_swing_index_mp_5ga_n_txpwrtrack_type3_type5_8822b,
3159 DELTA_SWINGIDX_SIZE * 3);
3160 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
3161 delta_swing_index_mp_5gb_p_txpwrtrack_type3_type5_8822b,
3162 DELTA_SWINGIDX_SIZE * 3);
3163 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
3164 delta_swing_index_mp_5gb_n_txpwrtrack_type3_type5_8822b,
3165 DELTA_SWINGIDX_SIZE * 3);
3166}
3167
3168/******************************************************************************
3169 * txpowertrack_type4.TXT
3170 ******************************************************************************/
3171
3172static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type4_8822b
3173 [][DELTA_SWINGIDX_SIZE] = {
3174 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
3175 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
3176 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
3177 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
3178 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
3179 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
3180};
3181
3182static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type4_8822b
3183 [][DELTA_SWINGIDX_SIZE] = {
3184 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
3185 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
3186 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
3187 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
3188 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
3189 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
3190};
3191
3192static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type4_8822b
3193 [][DELTA_SWINGIDX_SIZE] = {
3194 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
3195 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
3196 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
3197 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
3198 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
3199 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
3200};
3201
3202static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type4_8822b
3203 [][DELTA_SWINGIDX_SIZE] = {
3204 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
3205 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
3206 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
3207 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
3208 {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
3209 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
3210};
3211
3212static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type4_8822b[] = {
3213 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3214 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3215
3216static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type4_8822b[] = {
3217 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3218 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3219
3220static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type4_8822b[] = {
3221 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3222 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3223
3224static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type4_8822b[] = {
3225 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3226 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3227
3228static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type4_8822b[] = {
3229 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3230 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3231
3232static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type4_8822b[] = {
3233 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3234 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3235
3236static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type4_8822b[] = {
3237 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3238 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3239
3240static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type4_8822b[] = {
3241 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3242 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3243
3244void odm_read_and_config_mp_8822b_txpowertrack_type4(struct phy_dm_struct *dm)
3245{
3246 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
3247
3248 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
3249
3250 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
3251 delta_swing_index_mp_2ga_p_txpwrtrack_type4_8822b,
3252 DELTA_SWINGIDX_SIZE);
3253 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
3254 delta_swing_index_mp_2ga_n_txpwrtrack_type4_8822b,
3255 DELTA_SWINGIDX_SIZE);
3256 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
3257 delta_swing_index_mp_2gb_p_txpwrtrack_type4_8822b,
3258 DELTA_SWINGIDX_SIZE);
3259 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
3260 delta_swing_index_mp_2gb_n_txpwrtrack_type4_8822b,
3261 DELTA_SWINGIDX_SIZE);
3262
3263 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
3264 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type4_8822b,
3265 DELTA_SWINGIDX_SIZE);
3266 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
3267 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type4_8822b,
3268 DELTA_SWINGIDX_SIZE);
3269 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
3270 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type4_8822b,
3271 DELTA_SWINGIDX_SIZE);
3272 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
3273 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type4_8822b,
3274 DELTA_SWINGIDX_SIZE);
3275
3276 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
3277 delta_swing_index_mp_5ga_p_txpwrtrack_type4_8822b,
3278 DELTA_SWINGIDX_SIZE * 3);
3279 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
3280 delta_swing_index_mp_5ga_n_txpwrtrack_type4_8822b,
3281 DELTA_SWINGIDX_SIZE * 3);
3282 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
3283 delta_swing_index_mp_5gb_p_txpwrtrack_type4_8822b,
3284 DELTA_SWINGIDX_SIZE * 3);
3285 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
3286 delta_swing_index_mp_5gb_n_txpwrtrack_type4_8822b,
3287 DELTA_SWINGIDX_SIZE * 3);
3288}
3289
3290/******************************************************************************
3291 * txpowertrack_type6.TXT
3292 ******************************************************************************/
3293
3294static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type6_8822b
3295 [][DELTA_SWINGIDX_SIZE] = {
3296 {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10,
3297 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
3298 {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10,
3299 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16},
3300 {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12,
3301 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17},
3302};
3303
3304static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type6_8822b
3305 [][DELTA_SWINGIDX_SIZE] = {
3306 {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11,
3307 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19},
3308 {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12,
3309 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21},
3310 {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12,
3311 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21},
3312};
3313
3314static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type6_8822b
3315 [][DELTA_SWINGIDX_SIZE] = {
3316 {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11,
3317 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17},
3318 {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10,
3319 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15},
3320 {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10,
3321 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16},
3322};
3323
3324static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type6_8822b
3325 [][DELTA_SWINGIDX_SIZE] = {
3326 {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12,
3327 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21},
3328 {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11,
3329 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21},
3330 {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12,
3331 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20},
3332};
3333
3334static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type6_8822b[] = {
3335 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
3336 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
3337
3338static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type6_8822b[] = {
3339 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
3340 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
3341
3342static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type6_8822b[] = {
3343 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
3344 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
3345
3346static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type6_8822b[] = {
3347 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
3348 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
3349
3350static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type6_8822b[] = {
3351 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
3352 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
3353
3354static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type6_8822b[] = {
3355 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
3356 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
3357
3358static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type6_8822b[] = {
3359 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
3360 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
3361
3362static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type6_8822b[] = {
3363 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
3364 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
3365
3366void odm_read_and_config_mp_8822b_txpowertrack_type6(struct phy_dm_struct *dm)
3367{
3368 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
3369
3370 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
3371
3372 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
3373 delta_swing_index_mp_2ga_p_txpwrtrack_type6_8822b,
3374 DELTA_SWINGIDX_SIZE);
3375 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
3376 delta_swing_index_mp_2ga_n_txpwrtrack_type6_8822b,
3377 DELTA_SWINGIDX_SIZE);
3378 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
3379 delta_swing_index_mp_2gb_p_txpwrtrack_type6_8822b,
3380 DELTA_SWINGIDX_SIZE);
3381 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
3382 delta_swing_index_mp_2gb_n_txpwrtrack_type6_8822b,
3383 DELTA_SWINGIDX_SIZE);
3384
3385 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
3386 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type6_8822b,
3387 DELTA_SWINGIDX_SIZE);
3388 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
3389 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type6_8822b,
3390 DELTA_SWINGIDX_SIZE);
3391 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
3392 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type6_8822b,
3393 DELTA_SWINGIDX_SIZE);
3394 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
3395 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type6_8822b,
3396 DELTA_SWINGIDX_SIZE);
3397
3398 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
3399 delta_swing_index_mp_5ga_p_txpwrtrack_type6_8822b,
3400 DELTA_SWINGIDX_SIZE * 3);
3401 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
3402 delta_swing_index_mp_5ga_n_txpwrtrack_type6_8822b,
3403 DELTA_SWINGIDX_SIZE * 3);
3404 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
3405 delta_swing_index_mp_5gb_p_txpwrtrack_type6_8822b,
3406 DELTA_SWINGIDX_SIZE * 3);
3407 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
3408 delta_swing_index_mp_5gb_n_txpwrtrack_type6_8822b,
3409 DELTA_SWINGIDX_SIZE * 3);
3410}
3411
3412/******************************************************************************
3413 * txpowertrack_type7.TXT
3414 ******************************************************************************/
3415
3416static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type7_8822b
3417 [][DELTA_SWINGIDX_SIZE] = {
3418 {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10,
3419 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
3420 {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10,
3421 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16},
3422 {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12,
3423 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17},
3424};
3425
3426static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type7_8822b
3427 [][DELTA_SWINGIDX_SIZE] = {
3428 {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11,
3429 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19},
3430 {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12,
3431 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21},
3432 {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12,
3433 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21},
3434};
3435
3436static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type7_8822b
3437 [][DELTA_SWINGIDX_SIZE] = {
3438 {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11,
3439 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17},
3440 {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10,
3441 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15},
3442 {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10,
3443 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16},
3444};
3445
3446static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type7_8822b
3447 [][DELTA_SWINGIDX_SIZE] = {
3448 {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12,
3449 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21},
3450 {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11,
3451 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21},
3452 {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12,
3453 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20},
3454};
3455
3456static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type7_8822b[] = {
3457 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
3458 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
3459
3460static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type7_8822b[] = {
3461 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
3462 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
3463
3464static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type7_8822b[] = {
3465 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
3466 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
3467
3468static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type7_8822b[] = {
3469 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
3470 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
3471
3472static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type7_8822b[] = {
3473 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
3474 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
3475
3476static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type7_8822b[] = {
3477 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
3478 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
3479
3480static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type7_8822b[] = {
3481 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
3482 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
3483
3484static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type7_8822b[] = {
3485 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
3486 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
3487
3488void odm_read_and_config_mp_8822b_txpowertrack_type7(struct phy_dm_struct *dm)
3489{
3490 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
3491
3492 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
3493
3494 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
3495 delta_swing_index_mp_2ga_p_txpwrtrack_type7_8822b,
3496 DELTA_SWINGIDX_SIZE);
3497 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
3498 delta_swing_index_mp_2ga_n_txpwrtrack_type7_8822b,
3499 DELTA_SWINGIDX_SIZE);
3500 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
3501 delta_swing_index_mp_2gb_p_txpwrtrack_type7_8822b,
3502 DELTA_SWINGIDX_SIZE);
3503 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
3504 delta_swing_index_mp_2gb_n_txpwrtrack_type7_8822b,
3505 DELTA_SWINGIDX_SIZE);
3506
3507 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
3508 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type7_8822b,
3509 DELTA_SWINGIDX_SIZE);
3510 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
3511 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type7_8822b,
3512 DELTA_SWINGIDX_SIZE);
3513 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
3514 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type7_8822b,
3515 DELTA_SWINGIDX_SIZE);
3516 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
3517 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type7_8822b,
3518 DELTA_SWINGIDX_SIZE);
3519
3520 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
3521 delta_swing_index_mp_5ga_p_txpwrtrack_type7_8822b,
3522 DELTA_SWINGIDX_SIZE * 3);
3523 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
3524 delta_swing_index_mp_5ga_n_txpwrtrack_type7_8822b,
3525 DELTA_SWINGIDX_SIZE * 3);
3526 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
3527 delta_swing_index_mp_5gb_p_txpwrtrack_type7_8822b,
3528 DELTA_SWINGIDX_SIZE * 3);
3529 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
3530 delta_swing_index_mp_5gb_n_txpwrtrack_type7_8822b,
3531 DELTA_SWINGIDX_SIZE * 3);
3532}
3533
3534/******************************************************************************
3535 * txpowertrack_type8.TXT
3536 ******************************************************************************/
3537
3538static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type8_8822b
3539 [][DELTA_SWINGIDX_SIZE] = {
3540 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3541 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3542 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3543 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3544 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3545 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3546};
3547
3548static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type8_8822b
3549 [][DELTA_SWINGIDX_SIZE] = {
3550 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3551 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3552 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3553 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3554 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3555 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3556};
3557
3558static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type8_8822b
3559 [][DELTA_SWINGIDX_SIZE] = {
3560 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3561 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3562 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3563 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3564 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3565 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3566};
3567
3568static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type8_8822b
3569 [][DELTA_SWINGIDX_SIZE] = {
3570 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3571 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3572 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3573 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3574 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
3575 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
3576};
3577
3578static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type8_8822b[] = {
3579 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3580 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3581
3582static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type8_8822b[] = {
3583 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3584 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3585
3586static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type8_8822b[] = {
3587 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3588 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3589
3590static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type8_8822b[] = {
3591 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3592 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3593
3594static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type8_8822b[] = {
3595 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3596 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3597
3598static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type8_8822b[] = {
3599 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3600 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3601
3602static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type8_8822b[] = {
3603 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
3604 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
3605
3606static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type8_8822b[] = {
3607 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
3608 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
3609
3610void odm_read_and_config_mp_8822b_txpowertrack_type8(struct phy_dm_struct *dm)
3611{
3612 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
3613
3614 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
3615
3616 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
3617 delta_swing_index_mp_2ga_p_txpwrtrack_type8_8822b,
3618 DELTA_SWINGIDX_SIZE);
3619 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
3620 delta_swing_index_mp_2ga_n_txpwrtrack_type8_8822b,
3621 DELTA_SWINGIDX_SIZE);
3622 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
3623 delta_swing_index_mp_2gb_p_txpwrtrack_type8_8822b,
3624 DELTA_SWINGIDX_SIZE);
3625 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
3626 delta_swing_index_mp_2gb_n_txpwrtrack_type8_8822b,
3627 DELTA_SWINGIDX_SIZE);
3628
3629 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
3630 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type8_8822b,
3631 DELTA_SWINGIDX_SIZE);
3632 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
3633 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type8_8822b,
3634 DELTA_SWINGIDX_SIZE);
3635 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
3636 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type8_8822b,
3637 DELTA_SWINGIDX_SIZE);
3638 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
3639 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type8_8822b,
3640 DELTA_SWINGIDX_SIZE);
3641
3642 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
3643 delta_swing_index_mp_5ga_p_txpwrtrack_type8_8822b,
3644 DELTA_SWINGIDX_SIZE * 3);
3645 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
3646 delta_swing_index_mp_5ga_n_txpwrtrack_type8_8822b,
3647 DELTA_SWINGIDX_SIZE * 3);
3648 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
3649 delta_swing_index_mp_5gb_p_txpwrtrack_type8_8822b,
3650 DELTA_SWINGIDX_SIZE * 3);
3651 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
3652 delta_swing_index_mp_5gb_n_txpwrtrack_type8_8822b,
3653 DELTA_SWINGIDX_SIZE * 3);
3654}
3655
3656/******************************************************************************
3657 * txpowertrack_type9.TXT
3658 ******************************************************************************/
3659
3660static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type9_8822b
3661 [][DELTA_SWINGIDX_SIZE] = {
3662 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3663 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3664 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8,
3665 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14},
3666 {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8,
3667 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15},
3668};
3669
3670static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type9_8822b
3671 [][DELTA_SWINGIDX_SIZE] = {
3672 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3673 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3674 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3675 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15},
3676 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3677 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16},
3678};
3679
3680static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type9_8822b
3681 [][DELTA_SWINGIDX_SIZE] = {
3682 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3683 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14},
3684 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3685 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14},
3686 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3687 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14},
3688};
3689
3690static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type9_8822b
3691 [][DELTA_SWINGIDX_SIZE] = {
3692 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3693 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15},
3694 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3695 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15},
3696 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
3697 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15},
3698};
3699
3700static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type9_8822b[] = {
3701 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
3702 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
3703
3704static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type9_8822b[] = {
3705 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
3706 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
3707
3708static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type9_8822b[] = {
3709 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
3710 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
3711
3712static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type9_8822b[] = {
3713 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
3714 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
3715
3716static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type9_8822b[] = {
3717 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
3718 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
3719
3720static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type9_8822b[] = {
3721 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
3722 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
3723
3724static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type9_8822b[] = {
3725 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
3726 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
3727
3728static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type9_8822b[] = {
3729 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
3730 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
3731
3732void odm_read_and_config_mp_8822b_txpowertrack_type9(struct phy_dm_struct *dm)
3733{
3734 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
3735
3736 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
3737
3738 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
3739 delta_swing_index_mp_2ga_p_txpwrtrack_type9_8822b,
3740 DELTA_SWINGIDX_SIZE);
3741 odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
3742 delta_swing_index_mp_2ga_n_txpwrtrack_type9_8822b,
3743 DELTA_SWINGIDX_SIZE);
3744 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
3745 delta_swing_index_mp_2gb_p_txpwrtrack_type9_8822b,
3746 DELTA_SWINGIDX_SIZE);
3747 odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
3748 delta_swing_index_mp_2gb_n_txpwrtrack_type9_8822b,
3749 DELTA_SWINGIDX_SIZE);
3750
3751 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
3752 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type9_8822b,
3753 DELTA_SWINGIDX_SIZE);
3754 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
3755 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type9_8822b,
3756 DELTA_SWINGIDX_SIZE);
3757 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
3758 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type9_8822b,
3759 DELTA_SWINGIDX_SIZE);
3760 odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
3761 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type9_8822b,
3762 DELTA_SWINGIDX_SIZE);
3763
3764 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
3765 delta_swing_index_mp_5ga_p_txpwrtrack_type9_8822b,
3766 DELTA_SWINGIDX_SIZE * 3);
3767 odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
3768 delta_swing_index_mp_5ga_n_txpwrtrack_type9_8822b,
3769 DELTA_SWINGIDX_SIZE * 3);
3770 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
3771 delta_swing_index_mp_5gb_p_txpwrtrack_type9_8822b,
3772 DELTA_SWINGIDX_SIZE * 3);
3773 odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
3774 delta_swing_index_mp_5gb_n_txpwrtrack_type9_8822b,
3775 DELTA_SWINGIDX_SIZE * 3);
3776}
3777
3778/******************************************************************************
3779 * txpwr_lmt.TXT
3780 ******************************************************************************/
3781
3782static const char *const array_mp_8822b_txpwr_lmt[] = {
3783 "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", "ETSI", "2.4G",
3784 "20M", "CCK", "1T", "01", "28", "MKK", "2.4G", "20M", "CCK",
3785 "1T", "01", "30", "FCC", "2.4G", "20M", "CCK", "1T", "02",
3786 "32", "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", "MKK",
3787 "2.4G", "20M", "CCK", "1T", "02", "30", "FCC", "2.4G", "20M",
3788 "CCK", "1T", "03", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
3789 "03", "28", "MKK", "2.4G", "20M", "CCK", "1T", "03", "30",
3790 "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", "ETSI", "2.4G",
3791 "20M", "CCK", "1T", "04", "28", "MKK", "2.4G", "20M", "CCK",
3792 "1T", "04", "30", "FCC", "2.4G", "20M", "CCK", "1T", "05",
3793 "32", "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", "MKK",
3794 "2.4G", "20M", "CCK", "1T", "05", "30", "FCC", "2.4G", "20M",
3795 "CCK", "1T", "06", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
3796 "06", "28", "MKK", "2.4G", "20M", "CCK", "1T", "06", "30",
3797 "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", "ETSI", "2.4G",
3798 "20M", "CCK", "1T", "07", "28", "MKK", "2.4G", "20M", "CCK",
3799 "1T", "07", "30", "FCC", "2.4G", "20M", "CCK", "1T", "08",
3800 "32", "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", "MKK",
3801 "2.4G", "20M", "CCK", "1T", "08", "30", "FCC", "2.4G", "20M",
3802 "CCK", "1T", "09", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
3803 "09", "28", "MKK", "2.4G", "20M", "CCK", "1T", "09", "30",
3804 "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", "ETSI", "2.4G",
3805 "20M", "CCK", "1T", "10", "28", "MKK", "2.4G", "20M", "CCK",
3806 "1T", "10", "30", "FCC", "2.4G", "20M", "CCK", "1T", "11",
3807 "32", "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", "MKK",
3808 "2.4G", "20M", "CCK", "1T", "11", "30", "FCC", "2.4G", "20M",
3809 "CCK", "1T", "12", "26", "ETSI", "2.4G", "20M", "CCK", "1T",
3810 "12", "28", "MKK", "2.4G", "20M", "CCK", "1T", "12", "30",
3811 "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", "ETSI", "2.4G",
3812 "20M", "CCK", "1T", "13", "28", "MKK", "2.4G", "20M", "CCK",
3813 "1T", "13", "28", "FCC", "2.4G", "20M", "CCK", "1T", "14",
3814 "63", "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", "MKK",
3815 "2.4G", "20M", "CCK", "1T", "14", "32", "FCC", "2.4G", "20M",
3816 "OFDM", "1T", "01", "26", "ETSI", "2.4G", "20M", "OFDM", "1T",
3817 "01", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34",
3818 "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", "ETSI", "2.4G",
3819 "20M", "OFDM", "1T", "02", "30", "MKK", "2.4G", "20M", "OFDM",
3820 "1T", "02", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "03",
3821 "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", "MKK",
3822 "2.4G", "20M", "OFDM", "1T", "03", "34", "FCC", "2.4G", "20M",
3823 "OFDM", "1T", "04", "34", "ETSI", "2.4G", "20M", "OFDM", "1T",
3824 "04", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34",
3825 "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", "ETSI", "2.4G",
3826 "20M", "OFDM", "1T", "05", "30", "MKK", "2.4G", "20M", "OFDM",
3827 "1T", "05", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "06",
3828 "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", "MKK",
3829 "2.4G", "20M", "OFDM", "1T", "06", "34", "FCC", "2.4G", "20M",
3830 "OFDM", "1T", "07", "34", "ETSI", "2.4G", "20M", "OFDM", "1T",
3831 "07", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34",
3832 "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", "ETSI", "2.4G",
3833 "20M", "OFDM", "1T", "08", "30", "MKK", "2.4G", "20M", "OFDM",
3834 "1T", "08", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "09",
3835 "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", "MKK",
3836 "2.4G", "20M", "OFDM", "1T", "09", "34", "FCC", "2.4G", "20M",
3837 "OFDM", "1T", "10", "30", "ETSI", "2.4G", "20M", "OFDM", "1T",
3838 "10", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34",
3839 "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", "ETSI", "2.4G",
3840 "20M", "OFDM", "1T", "11", "30", "MKK", "2.4G", "20M", "OFDM",
3841 "1T", "11", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "12",
3842 "22", "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", "MKK",
3843 "2.4G", "20M", "OFDM", "1T", "12", "34", "FCC", "2.4G", "20M",
3844 "OFDM", "1T", "13", "14", "ETSI", "2.4G", "20M", "OFDM", "1T",
3845 "13", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34",
3846 "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", "ETSI", "2.4G",
3847 "20M", "OFDM", "1T", "14", "63", "MKK", "2.4G", "20M", "OFDM",
3848 "1T", "14", "63", "FCC", "2.4G", "20M", "HT", "1T", "01",
3849 "26", "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", "MKK",
3850 "2.4G", "20M", "HT", "1T", "01", "34", "FCC", "2.4G", "20M",
3851 "HT", "1T", "02", "30", "ETSI", "2.4G", "20M", "HT", "1T",
3852 "02", "30", "MKK", "2.4G", "20M", "HT", "1T", "02", "34",
3853 "FCC", "2.4G", "20M", "HT", "1T", "03", "32", "ETSI", "2.4G",
3854 "20M", "HT", "1T", "03", "30", "MKK", "2.4G", "20M", "HT",
3855 "1T", "03", "34", "FCC", "2.4G", "20M", "HT", "1T", "04",
3856 "34", "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", "MKK",
3857 "2.4G", "20M", "HT", "1T", "04", "34", "FCC", "2.4G", "20M",
3858 "HT", "1T", "05", "34", "ETSI", "2.4G", "20M", "HT", "1T",
3859 "05", "30", "MKK", "2.4G", "20M", "HT", "1T", "05", "34",
3860 "FCC", "2.4G", "20M", "HT", "1T", "06", "34", "ETSI", "2.4G",
3861 "20M", "HT", "1T", "06", "30", "MKK", "2.4G", "20M", "HT",
3862 "1T", "06", "34", "FCC", "2.4G", "20M", "HT", "1T", "07",
3863 "34", "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", "MKK",
3864 "2.4G", "20M", "HT", "1T", "07", "34", "FCC", "2.4G", "20M",
3865 "HT", "1T", "08", "34", "ETSI", "2.4G", "20M", "HT", "1T",
3866 "08", "30", "MKK", "2.4G", "20M", "HT", "1T", "08", "34",
3867 "FCC", "2.4G", "20M", "HT", "1T", "09", "32", "ETSI", "2.4G",
3868 "20M", "HT", "1T", "09", "30", "MKK", "2.4G", "20M", "HT",
3869 "1T", "09", "34", "FCC", "2.4G", "20M", "HT", "1T", "10",
3870 "30", "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", "MKK",
3871 "2.4G", "20M", "HT", "1T", "10", "34", "FCC", "2.4G", "20M",
3872 "HT", "1T", "11", "26", "ETSI", "2.4G", "20M", "HT", "1T",
3873 "11", "30", "MKK", "2.4G", "20M", "HT", "1T", "11", "34",
3874 "FCC", "2.4G", "20M", "HT", "1T", "12", "20", "ETSI", "2.4G",
3875 "20M", "HT", "1T", "12", "30", "MKK", "2.4G", "20M", "HT",
3876 "1T", "12", "34", "FCC", "2.4G", "20M", "HT", "1T", "13",
3877 "14", "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", "MKK",
3878 "2.4G", "20M", "HT", "1T", "13", "34", "FCC", "2.4G", "20M",
3879 "HT", "1T", "14", "63", "ETSI", "2.4G", "20M", "HT", "1T",
3880 "14", "63", "MKK", "2.4G", "20M", "HT", "1T", "14", "63",
3881 "FCC", "2.4G", "20M", "HT", "2T", "01", "26", "ETSI", "2.4G",
3882 "20M", "HT", "2T", "01", "18", "MKK", "2.4G", "20M", "HT",
3883 "2T", "01", "30", "FCC", "2.4G", "20M", "HT", "2T", "02",
3884 "28", "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", "MKK",
3885 "2.4G", "20M", "HT", "2T", "02", "30", "FCC", "2.4G", "20M",
3886 "HT", "2T", "03", "30", "ETSI", "2.4G", "20M", "HT", "2T",
3887 "03", "18", "MKK", "2.4G", "20M", "HT", "2T", "03", "30",
3888 "FCC", "2.4G", "20M", "HT", "2T", "04", "30", "ETSI", "2.4G",
3889 "20M", "HT", "2T", "04", "18", "MKK", "2.4G", "20M", "HT",
3890 "2T", "04", "30", "FCC", "2.4G", "20M", "HT", "2T", "05",
3891 "32", "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", "MKK",
3892 "2.4G", "20M", "HT", "2T", "05", "30", "FCC", "2.4G", "20M",
3893 "HT", "2T", "06", "32", "ETSI", "2.4G", "20M", "HT", "2T",
3894 "06", "18", "MKK", "2.4G", "20M", "HT", "2T", "06", "30",
3895 "FCC", "2.4G", "20M", "HT", "2T", "07", "32", "ETSI", "2.4G",
3896 "20M", "HT", "2T", "07", "18", "MKK", "2.4G", "20M", "HT",
3897 "2T", "07", "30", "FCC", "2.4G", "20M", "HT", "2T", "08",
3898 "30", "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", "MKK",
3899 "2.4G", "20M", "HT", "2T", "08", "30", "FCC", "2.4G", "20M",
3900 "HT", "2T", "09", "30", "ETSI", "2.4G", "20M", "HT", "2T",
3901 "09", "18", "MKK", "2.4G", "20M", "HT", "2T", "09", "30",
3902 "FCC", "2.4G", "20M", "HT", "2T", "10", "28", "ETSI", "2.4G",
3903 "20M", "HT", "2T", "10", "18", "MKK", "2.4G", "20M", "HT",
3904 "2T", "10", "30", "FCC", "2.4G", "20M", "HT", "2T", "11",
3905 "26", "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", "MKK",
3906 "2.4G", "20M", "HT", "2T", "11", "30", "FCC", "2.4G", "20M",
3907 "HT", "2T", "12", "20", "ETSI", "2.4G", "20M", "HT", "2T",
3908 "12", "18", "MKK", "2.4G", "20M", "HT", "2T", "12", "30",
3909 "FCC", "2.4G", "20M", "HT", "2T", "13", "14", "ETSI", "2.4G",
3910 "20M", "HT", "2T", "13", "18", "MKK", "2.4G", "20M", "HT",
3911 "2T", "13", "30", "FCC", "2.4G", "20M", "HT", "2T", "14",
3912 "63", "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", "MKK",
3913 "2.4G", "20M", "HT", "2T", "14", "63", "FCC", "2.4G", "40M",
3914 "HT", "1T", "01", "63", "ETSI", "2.4G", "40M", "HT", "1T",
3915 "01", "63", "MKK", "2.4G", "40M", "HT", "1T", "01", "63",
3916 "FCC", "2.4G", "40M", "HT", "1T", "02", "63", "ETSI", "2.4G",
3917 "40M", "HT", "1T", "02", "63", "MKK", "2.4G", "40M", "HT",
3918 "1T", "02", "63", "FCC", "2.4G", "40M", "HT", "1T", "03",
3919 "26", "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", "MKK",
3920 "2.4G", "40M", "HT", "1T", "03", "34", "FCC", "2.4G", "40M",
3921 "HT", "1T", "04", "26", "ETSI", "2.4G", "40M", "HT", "1T",
3922 "04", "30", "MKK", "2.4G", "40M", "HT", "1T", "04", "34",
3923 "FCC", "2.4G", "40M", "HT", "1T", "05", "30", "ETSI", "2.4G",
3924 "40M", "HT", "1T", "05", "30", "MKK", "2.4G", "40M", "HT",
3925 "1T", "05", "34", "FCC", "2.4G", "40M", "HT", "1T", "06",
3926 "32", "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", "MKK",
3927 "2.4G", "40M", "HT", "1T", "06", "34", "FCC", "2.4G", "40M",
3928 "HT", "1T", "07", "30", "ETSI", "2.4G", "40M", "HT", "1T",
3929 "07", "30", "MKK", "2.4G", "40M", "HT", "1T", "07", "34",
3930 "FCC", "2.4G", "40M", "HT", "1T", "08", "26", "ETSI", "2.4G",
3931 "40M", "HT", "1T", "08", "30", "MKK", "2.4G", "40M", "HT",
3932 "1T", "08", "34", "FCC", "2.4G", "40M", "HT", "1T", "09",
3933 "26", "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", "MKK",
3934 "2.4G", "40M", "HT", "1T", "09", "34", "FCC", "2.4G", "40M",
3935 "HT", "1T", "10", "20", "ETSI", "2.4G", "40M", "HT", "1T",
3936 "10", "30", "MKK", "2.4G", "40M", "HT", "1T", "10", "34",
3937 "FCC", "2.4G", "40M", "HT", "1T", "11", "14", "ETSI", "2.4G",
3938 "40M", "HT", "1T", "11", "30", "MKK", "2.4G", "40M", "HT",
3939 "1T", "11", "34", "FCC", "2.4G", "40M", "HT", "1T", "12",
3940 "63", "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", "MKK",
3941 "2.4G", "40M", "HT", "1T", "12", "63", "FCC", "2.4G", "40M",
3942 "HT", "1T", "13", "63", "ETSI", "2.4G", "40M", "HT", "1T",
3943 "13", "63", "MKK", "2.4G", "40M", "HT", "1T", "13", "63",
3944 "FCC", "2.4G", "40M", "HT", "1T", "14", "63", "ETSI", "2.4G",
3945 "40M", "HT", "1T", "14", "63", "MKK", "2.4G", "40M", "HT",
3946 "1T", "14", "63", "FCC", "2.4G", "40M", "HT", "2T", "01",
3947 "63", "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", "MKK",
3948 "2.4G", "40M", "HT", "2T", "01", "63", "FCC", "2.4G", "40M",
3949 "HT", "2T", "02", "63", "ETSI", "2.4G", "40M", "HT", "2T",
3950 "02", "63", "MKK", "2.4G", "40M", "HT", "2T", "02", "63",
3951 "FCC", "2.4G", "40M", "HT", "2T", "03", "24", "ETSI", "2.4G",
3952 "40M", "HT", "2T", "03", "18", "MKK", "2.4G", "40M", "HT",
3953 "2T", "03", "30", "FCC", "2.4G", "40M", "HT", "2T", "04",
3954 "24", "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", "MKK",
3955 "2.4G", "40M", "HT", "2T", "04", "30", "FCC", "2.4G", "40M",
3956 "HT", "2T", "05", "26", "ETSI", "2.4G", "40M", "HT", "2T",
3957 "05", "18", "MKK", "2.4G", "40M", "HT", "2T", "05", "30",
3958 "FCC", "2.4G", "40M", "HT", "2T", "06", "28", "ETSI", "2.4G",
3959 "40M", "HT", "2T", "06", "18", "MKK", "2.4G", "40M", "HT",
3960 "2T", "06", "30", "FCC", "2.4G", "40M", "HT", "2T", "07",
3961 "26", "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", "MKK",
3962 "2.4G", "40M", "HT", "2T", "07", "30", "FCC", "2.4G", "40M",
3963 "HT", "2T", "08", "26", "ETSI", "2.4G", "40M", "HT", "2T",
3964 "08", "18", "MKK", "2.4G", "40M", "HT", "2T", "08", "30",
3965 "FCC", "2.4G", "40M", "HT", "2T", "09", "26", "ETSI", "2.4G",
3966 "40M", "HT", "2T", "09", "18", "MKK", "2.4G", "40M", "HT",
3967 "2T", "09", "30", "FCC", "2.4G", "40M", "HT", "2T", "10",
3968 "20", "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", "MKK",
3969 "2.4G", "40M", "HT", "2T", "10", "30", "FCC", "2.4G", "40M",
3970 "HT", "2T", "11", "14", "ETSI", "2.4G", "40M", "HT", "2T",
3971 "11", "18", "MKK", "2.4G", "40M", "HT", "2T", "11", "30",
3972 "FCC", "2.4G", "40M", "HT", "2T", "12", "63", "ETSI", "2.4G",
3973 "40M", "HT", "2T", "12", "63", "MKK", "2.4G", "40M", "HT",
3974 "2T", "12", "63", "FCC", "2.4G", "40M", "HT", "2T", "13",
3975 "63", "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", "MKK",
3976 "2.4G", "40M", "HT", "2T", "13", "63", "FCC", "2.4G", "40M",
3977 "HT", "2T", "14", "63", "ETSI", "2.4G", "40M", "HT", "2T",
3978 "14", "63", "MKK", "2.4G", "40M", "HT", "2T", "14", "63",
3979 "FCC", "5G", "20M", "OFDM", "1T", "36", "30", "ETSI", "5G",
3980 "20M", "OFDM", "1T", "36", "32", "MKK", "5G", "20M", "OFDM",
3981 "1T", "36", "30", "FCC", "5G", "20M", "OFDM", "1T", "40",
3982 "32", "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", "MKK",
3983 "5G", "20M", "OFDM", "1T", "40", "30", "FCC", "5G", "20M",
3984 "OFDM", "1T", "44", "32", "ETSI", "5G", "20M", "OFDM", "1T",
3985 "44", "32", "MKK", "5G", "20M", "OFDM", "1T", "44", "30",
3986 "FCC", "5G", "20M", "OFDM", "1T", "48", "32", "ETSI", "5G",
3987 "20M", "OFDM", "1T", "48", "32", "MKK", "5G", "20M", "OFDM",
3988 "1T", "48", "30", "FCC", "5G", "20M", "OFDM", "1T", "52",
3989 "32", "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", "MKK",
3990 "5G", "20M", "OFDM", "1T", "52", "28", "FCC", "5G", "20M",
3991 "OFDM", "1T", "56", "32", "ETSI", "5G", "20M", "OFDM", "1T",
3992 "56", "32", "MKK", "5G", "20M", "OFDM", "1T", "56", "28",
3993 "FCC", "5G", "20M", "OFDM", "1T", "60", "32", "ETSI", "5G",
3994 "20M", "OFDM", "1T", "60", "32", "MKK", "5G", "20M", "OFDM",
3995 "1T", "60", "28", "FCC", "5G", "20M", "OFDM", "1T", "64",
3996 "28", "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", "MKK",
3997 "5G", "20M", "OFDM", "1T", "64", "28", "FCC", "5G", "20M",
3998 "OFDM", "1T", "100", "26", "ETSI", "5G", "20M", "OFDM", "1T",
3999 "100", "32", "MKK", "5G", "20M", "OFDM", "1T", "100", "32",
4000 "FCC", "5G", "20M", "OFDM", "1T", "104", "32", "ETSI", "5G",
4001 "20M", "OFDM", "1T", "104", "32", "MKK", "5G", "20M", "OFDM",
4002 "1T", "104", "32", "FCC", "5G", "20M", "OFDM", "1T", "108",
4003 "32", "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", "MKK",
4004 "5G", "20M", "OFDM", "1T", "108", "32", "FCC", "5G", "20M",
4005 "OFDM", "1T", "112", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4006 "112", "32", "MKK", "5G", "20M", "OFDM", "1T", "112", "32",
4007 "FCC", "5G", "20M", "OFDM", "1T", "116", "32", "ETSI", "5G",
4008 "20M", "OFDM", "1T", "116", "32", "MKK", "5G", "20M", "OFDM",
4009 "1T", "116", "32", "FCC", "5G", "20M", "OFDM", "1T", "120",
4010 "32", "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", "MKK",
4011 "5G", "20M", "OFDM", "1T", "120", "32", "FCC", "5G", "20M",
4012 "OFDM", "1T", "124", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4013 "124", "32", "MKK", "5G", "20M", "OFDM", "1T", "124", "32",
4014 "FCC", "5G", "20M", "OFDM", "1T", "128", "32", "ETSI", "5G",
4015 "20M", "OFDM", "1T", "128", "32", "MKK", "5G", "20M", "OFDM",
4016 "1T", "128", "32", "FCC", "5G", "20M", "OFDM", "1T", "132",
4017 "32", "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", "MKK",
4018 "5G", "20M", "OFDM", "1T", "132", "32", "FCC", "5G", "20M",
4019 "OFDM", "1T", "136", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4020 "136", "32", "MKK", "5G", "20M", "OFDM", "1T", "136", "32",
4021 "FCC", "5G", "20M", "OFDM", "1T", "140", "28", "ETSI", "5G",
4022 "20M", "OFDM", "1T", "140", "32", "MKK", "5G", "20M", "OFDM",
4023 "1T", "140", "32", "FCC", "5G", "20M", "OFDM", "1T", "144",
4024 "28", "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", "MKK",
4025 "5G", "20M", "OFDM", "1T", "144", "63", "FCC", "5G", "20M",
4026 "OFDM", "1T", "149", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4027 "149", "63", "MKK", "5G", "20M", "OFDM", "1T", "149", "63",
4028 "FCC", "5G", "20M", "OFDM", "1T", "153", "32", "ETSI", "5G",
4029 "20M", "OFDM", "1T", "153", "63", "MKK", "5G", "20M", "OFDM",
4030 "1T", "153", "63", "FCC", "5G", "20M", "OFDM", "1T", "157",
4031 "32", "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", "MKK",
4032 "5G", "20M", "OFDM", "1T", "157", "63", "FCC", "5G", "20M",
4033 "OFDM", "1T", "161", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4034 "161", "63", "MKK", "5G", "20M", "OFDM", "1T", "161", "63",
4035 "FCC", "5G", "20M", "OFDM", "1T", "165", "32", "ETSI", "5G",
4036 "20M", "OFDM", "1T", "165", "63", "MKK", "5G", "20M", "OFDM",
4037 "1T", "165", "63", "FCC", "5G", "20M", "HT", "1T", "36",
4038 "30", "ETSI", "5G", "20M", "HT", "1T", "36", "32", "MKK",
4039 "5G", "20M", "HT", "1T", "36", "28", "FCC", "5G", "20M",
4040 "HT", "1T", "40", "32", "ETSI", "5G", "20M", "HT", "1T",
4041 "40", "32", "MKK", "5G", "20M", "HT", "1T", "40", "28",
4042 "FCC", "5G", "20M", "HT", "1T", "44", "32", "ETSI", "5G",
4043 "20M", "HT", "1T", "44", "32", "MKK", "5G", "20M", "HT",
4044 "1T", "44", "28", "FCC", "5G", "20M", "HT", "1T", "48",
4045 "32", "ETSI", "5G", "20M", "HT", "1T", "48", "32", "MKK",
4046 "5G", "20M", "HT", "1T", "48", "28", "FCC", "5G", "20M",
4047 "HT", "1T", "52", "32", "ETSI", "5G", "20M", "HT", "1T",
4048 "52", "32", "MKK", "5G", "20M", "HT", "1T", "52", "28",
4049 "FCC", "5G", "20M", "HT", "1T", "56", "32", "ETSI", "5G",
4050 "20M", "HT", "1T", "56", "32", "MKK", "5G", "20M", "HT",
4051 "1T", "56", "28", "FCC", "5G", "20M", "HT", "1T", "60",
4052 "32", "ETSI", "5G", "20M", "HT", "1T", "60", "32", "MKK",
4053 "5G", "20M", "HT", "1T", "60", "28", "FCC", "5G", "20M",
4054 "HT", "1T", "64", "28", "ETSI", "5G", "20M", "HT", "1T",
4055 "64", "32", "MKK", "5G", "20M", "HT", "1T", "64", "28",
4056 "FCC", "5G", "20M", "HT", "1T", "100", "26", "ETSI", "5G",
4057 "20M", "HT", "1T", "100", "32", "MKK", "5G", "20M", "HT",
4058 "1T", "100", "32", "FCC", "5G", "20M", "HT", "1T", "104",
4059 "32", "ETSI", "5G", "20M", "HT", "1T", "104", "32", "MKK",
4060 "5G", "20M", "HT", "1T", "104", "32", "FCC", "5G", "20M",
4061 "HT", "1T", "108", "32", "ETSI", "5G", "20M", "HT", "1T",
4062 "108", "32", "MKK", "5G", "20M", "HT", "1T", "108", "32",
4063 "FCC", "5G", "20M", "HT", "1T", "112", "32", "ETSI", "5G",
4064 "20M", "HT", "1T", "112", "32", "MKK", "5G", "20M", "HT",
4065 "1T", "112", "32", "FCC", "5G", "20M", "HT", "1T", "116",
4066 "32", "ETSI", "5G", "20M", "HT", "1T", "116", "32", "MKK",
4067 "5G", "20M", "HT", "1T", "116", "32", "FCC", "5G", "20M",
4068 "HT", "1T", "120", "32", "ETSI", "5G", "20M", "HT", "1T",
4069 "120", "32", "MKK", "5G", "20M", "HT", "1T", "120", "32",
4070 "FCC", "5G", "20M", "HT", "1T", "124", "32", "ETSI", "5G",
4071 "20M", "HT", "1T", "124", "32", "MKK", "5G", "20M", "HT",
4072 "1T", "124", "32", "FCC", "5G", "20M", "HT", "1T", "128",
4073 "32", "ETSI", "5G", "20M", "HT", "1T", "128", "32", "MKK",
4074 "5G", "20M", "HT", "1T", "128", "32", "FCC", "5G", "20M",
4075 "HT", "1T", "132", "32", "ETSI", "5G", "20M", "HT", "1T",
4076 "132", "32", "MKK", "5G", "20M", "HT", "1T", "132", "32",
4077 "FCC", "5G", "20M", "HT", "1T", "136", "32", "ETSI", "5G",
4078 "20M", "HT", "1T", "136", "32", "MKK", "5G", "20M", "HT",
4079 "1T", "136", "32", "FCC", "5G", "20M", "HT", "1T", "140",
4080 "26", "ETSI", "5G", "20M", "HT", "1T", "140", "32", "MKK",
4081 "5G", "20M", "HT", "1T", "140", "32", "FCC", "5G", "20M",
4082 "HT", "1T", "144", "26", "ETSI", "5G", "20M", "HT", "1T",
4083 "144", "63", "MKK", "5G", "20M", "HT", "1T", "144", "63",
4084 "FCC", "5G", "20M", "HT", "1T", "149", "32", "ETSI", "5G",
4085 "20M", "HT", "1T", "149", "63", "MKK", "5G", "20M", "HT",
4086 "1T", "149", "63", "FCC", "5G", "20M", "HT", "1T", "153",
4087 "32", "ETSI", "5G", "20M", "HT", "1T", "153", "63", "MKK",
4088 "5G", "20M", "HT", "1T", "153", "63", "FCC", "5G", "20M",
4089 "HT", "1T", "157", "32", "ETSI", "5G", "20M", "HT", "1T",
4090 "157", "63", "MKK", "5G", "20M", "HT", "1T", "157", "63",
4091 "FCC", "5G", "20M", "HT", "1T", "161", "32", "ETSI", "5G",
4092 "20M", "HT", "1T", "161", "63", "MKK", "5G", "20M", "HT",
4093 "1T", "161", "63", "FCC", "5G", "20M", "HT", "1T", "165",
4094 "32", "ETSI", "5G", "20M", "HT", "1T", "165", "63", "MKK",
4095 "5G", "20M", "HT", "1T", "165", "63", "FCC", "5G", "20M",
4096 "HT", "2T", "36", "28", "ETSI", "5G", "20M", "HT", "2T",
4097 "36", "20", "MKK", "5G", "20M", "HT", "2T", "36", "22",
4098 "FCC", "5G", "20M", "HT", "2T", "40", "30", "ETSI", "5G",
4099 "20M", "HT", "2T", "40", "20", "MKK", "5G", "20M", "HT",
4100 "2T", "40", "22", "FCC", "5G", "20M", "HT", "2T", "44",
4101 "30", "ETSI", "5G", "20M", "HT", "2T", "44", "20", "MKK",
4102 "5G", "20M", "HT", "2T", "44", "22", "FCC", "5G", "20M",
4103 "HT", "2T", "48", "30", "ETSI", "5G", "20M", "HT", "2T",
4104 "48", "20", "MKK", "5G", "20M", "HT", "2T", "48", "22",
4105 "FCC", "5G", "20M", "HT", "2T", "52", "30", "ETSI", "5G",
4106 "20M", "HT", "2T", "52", "20", "MKK", "5G", "20M", "HT",
4107 "2T", "52", "22", "FCC", "5G", "20M", "HT", "2T", "56",
4108 "30", "ETSI", "5G", "20M", "HT", "2T", "56", "20", "MKK",
4109 "5G", "20M", "HT", "2T", "56", "22", "FCC", "5G", "20M",
4110 "HT", "2T", "60", "30", "ETSI", "5G", "20M", "HT", "2T",
4111 "60", "20", "MKK", "5G", "20M", "HT", "2T", "60", "22",
4112 "FCC", "5G", "20M", "HT", "2T", "64", "28", "ETSI", "5G",
4113 "20M", "HT", "2T", "64", "20", "MKK", "5G", "20M", "HT",
4114 "2T", "64", "22", "FCC", "5G", "20M", "HT", "2T", "100",
4115 "26", "ETSI", "5G", "20M", "HT", "2T", "100", "20", "MKK",
4116 "5G", "20M", "HT", "2T", "100", "30", "FCC", "5G", "20M",
4117 "HT", "2T", "104", "30", "ETSI", "5G", "20M", "HT", "2T",
4118 "104", "20", "MKK", "5G", "20M", "HT", "2T", "104", "30",
4119 "FCC", "5G", "20M", "HT", "2T", "108", "32", "ETSI", "5G",
4120 "20M", "HT", "2T", "108", "20", "MKK", "5G", "20M", "HT",
4121 "2T", "108", "30", "FCC", "5G", "20M", "HT", "2T", "112",
4122 "32", "ETSI", "5G", "20M", "HT", "2T", "112", "20", "MKK",
4123 "5G", "20M", "HT", "2T", "112", "30", "FCC", "5G", "20M",
4124 "HT", "2T", "116", "32", "ETSI", "5G", "20M", "HT", "2T",
4125 "116", "20", "MKK", "5G", "20M", "HT", "2T", "116", "30",
4126 "FCC", "5G", "20M", "HT", "2T", "120", "32", "ETSI", "5G",
4127 "20M", "HT", "2T", "120", "20", "MKK", "5G", "20M", "HT",
4128 "2T", "120", "30", "FCC", "5G", "20M", "HT", "2T", "124",
4129 "32", "ETSI", "5G", "20M", "HT", "2T", "124", "20", "MKK",
4130 "5G", "20M", "HT", "2T", "124", "30", "FCC", "5G", "20M",
4131 "HT", "2T", "128", "32", "ETSI", "5G", "20M", "HT", "2T",
4132 "128", "20", "MKK", "5G", "20M", "HT", "2T", "128", "30",
4133 "FCC", "5G", "20M", "HT", "2T", "132", "32", "ETSI", "5G",
4134 "20M", "HT", "2T", "132", "20", "MKK", "5G", "20M", "HT",
4135 "2T", "132", "30", "FCC", "5G", "20M", "HT", "2T", "136",
4136 "30", "ETSI", "5G", "20M", "HT", "2T", "136", "20", "MKK",
4137 "5G", "20M", "HT", "2T", "136", "30", "FCC", "5G", "20M",
4138 "HT", "2T", "140", "26", "ETSI", "5G", "20M", "HT", "2T",
4139 "140", "20", "MKK", "5G", "20M", "HT", "2T", "140", "30",
4140 "FCC", "5G", "20M", "HT", "2T", "144", "26", "ETSI", "5G",
4141 "20M", "HT", "2T", "144", "63", "MKK", "5G", "20M", "HT",
4142 "2T", "144", "63", "FCC", "5G", "20M", "HT", "2T", "149",
4143 "32", "ETSI", "5G", "20M", "HT", "2T", "149", "63", "MKK",
4144 "5G", "20M", "HT", "2T", "149", "63", "FCC", "5G", "20M",
4145 "HT", "2T", "153", "32", "ETSI", "5G", "20M", "HT", "2T",
4146 "153", "63", "MKK", "5G", "20M", "HT", "2T", "153", "63",
4147 "FCC", "5G", "20M", "HT", "2T", "157", "32", "ETSI", "5G",
4148 "20M", "HT", "2T", "157", "63", "MKK", "5G", "20M", "HT",
4149 "2T", "157", "63", "FCC", "5G", "20M", "HT", "2T", "161",
4150 "32", "ETSI", "5G", "20M", "HT", "2T", "161", "63", "MKK",
4151 "5G", "20M", "HT", "2T", "161", "63", "FCC", "5G", "20M",
4152 "HT", "2T", "165", "32", "ETSI", "5G", "20M", "HT", "2T",
4153 "165", "63", "MKK", "5G", "20M", "HT", "2T", "165", "63",
4154 "FCC", "5G", "40M", "HT", "1T", "38", "22", "ETSI", "5G",
4155 "40M", "HT", "1T", "38", "30", "MKK", "5G", "40M", "HT",
4156 "1T", "38", "30", "FCC", "5G", "40M", "HT", "1T", "46",
4157 "30", "ETSI", "5G", "40M", "HT", "1T", "46", "30", "MKK",
4158 "5G", "40M", "HT", "1T", "46", "30", "FCC", "5G", "40M",
4159 "HT", "1T", "54", "30", "ETSI", "5G", "40M", "HT", "1T",
4160 "54", "30", "MKK", "5G", "40M", "HT", "1T", "54", "30",
4161 "FCC", "5G", "40M", "HT", "1T", "62", "24", "ETSI", "5G",
4162 "40M", "HT", "1T", "62", "30", "MKK", "5G", "40M", "HT",
4163 "1T", "62", "30", "FCC", "5G", "40M", "HT", "1T", "102",
4164 "24", "ETSI", "5G", "40M", "HT", "1T", "102", "30", "MKK",
4165 "5G", "40M", "HT", "1T", "102", "30", "FCC", "5G", "40M",
4166 "HT", "1T", "110", "30", "ETSI", "5G", "40M", "HT", "1T",
4167 "110", "30", "MKK", "5G", "40M", "HT", "1T", "110", "30",
4168 "FCC", "5G", "40M", "HT", "1T", "118", "30", "ETSI", "5G",
4169 "40M", "HT", "1T", "118", "30", "MKK", "5G", "40M", "HT",
4170 "1T", "118", "30", "FCC", "5G", "40M", "HT", "1T", "126",
4171 "30", "ETSI", "5G", "40M", "HT", "1T", "126", "30", "MKK",
4172 "5G", "40M", "HT", "1T", "126", "30", "FCC", "5G", "40M",
4173 "HT", "1T", "134", "30", "ETSI", "5G", "40M", "HT", "1T",
4174 "134", "30", "MKK", "5G", "40M", "HT", "1T", "134", "30",
4175 "FCC", "5G", "40M", "HT", "1T", "142", "30", "ETSI", "5G",
4176 "40M", "HT", "1T", "142", "63", "MKK", "5G", "40M", "HT",
4177 "1T", "142", "63", "FCC", "5G", "40M", "HT", "1T", "151",
4178 "30", "ETSI", "5G", "40M", "HT", "1T", "151", "63", "MKK",
4179 "5G", "40M", "HT", "1T", "151", "63", "FCC", "5G", "40M",
4180 "HT", "1T", "159", "30", "ETSI", "5G", "40M", "HT", "1T",
4181 "159", "63", "MKK", "5G", "40M", "HT", "1T", "159", "63",
4182 "FCC", "5G", "40M", "HT", "2T", "38", "20", "ETSI", "5G",
4183 "40M", "HT", "2T", "38", "20", "MKK", "5G", "40M", "HT",
4184 "2T", "38", "22", "FCC", "5G", "40M", "HT", "2T", "46",
4185 "30", "ETSI", "5G", "40M", "HT", "2T", "46", "20", "MKK",
4186 "5G", "40M", "HT", "2T", "46", "22", "FCC", "5G", "40M",
4187 "HT", "2T", "54", "30", "ETSI", "5G", "40M", "HT", "2T",
4188 "54", "20", "MKK", "5G", "40M", "HT", "2T", "54", "22",
4189 "FCC", "5G", "40M", "HT", "2T", "62", "22", "ETSI", "5G",
4190 "40M", "HT", "2T", "62", "20", "MKK", "5G", "40M", "HT",
4191 "2T", "62", "22", "FCC", "5G", "40M", "HT", "2T", "102",
4192 "22", "ETSI", "5G", "40M", "HT", "2T", "102", "20", "MKK",
4193 "5G", "40M", "HT", "2T", "102", "30", "FCC", "5G", "40M",
4194 "HT", "2T", "110", "30", "ETSI", "5G", "40M", "HT", "2T",
4195 "110", "20", "MKK", "5G", "40M", "HT", "2T", "110", "30",
4196 "FCC", "5G", "40M", "HT", "2T", "118", "30", "ETSI", "5G",
4197 "40M", "HT", "2T", "118", "20", "MKK", "5G", "40M", "HT",
4198 "2T", "118", "30", "FCC", "5G", "40M", "HT", "2T", "126",
4199 "30", "ETSI", "5G", "40M", "HT", "2T", "126", "20", "MKK",
4200 "5G", "40M", "HT", "2T", "126", "30", "FCC", "5G", "40M",
4201 "HT", "2T", "134", "30", "ETSI", "5G", "40M", "HT", "2T",
4202 "134", "20", "MKK", "5G", "40M", "HT", "2T", "134", "30",
4203 "FCC", "5G", "40M", "HT", "2T", "142", "30", "ETSI", "5G",
4204 "40M", "HT", "2T", "142", "63", "MKK", "5G", "40M", "HT",
4205 "2T", "142", "63", "FCC", "5G", "40M", "HT", "2T", "151",
4206 "30", "ETSI", "5G", "40M", "HT", "2T", "151", "63", "MKK",
4207 "5G", "40M", "HT", "2T", "151", "63", "FCC", "5G", "40M",
4208 "HT", "2T", "159", "30", "ETSI", "5G", "40M", "HT", "2T",
4209 "159", "63", "MKK", "5G", "40M", "HT", "2T", "159", "63",
4210 "FCC", "5G", "80M", "VHT", "1T", "42", "20", "ETSI", "5G",
4211 "80M", "VHT", "1T", "42", "30", "MKK", "5G", "80M", "VHT",
4212 "1T", "42", "28", "FCC", "5G", "80M", "VHT", "1T", "58",
4213 "20", "ETSI", "5G", "80M", "VHT", "1T", "58", "30", "MKK",
4214 "5G", "80M", "VHT", "1T", "58", "28", "FCC", "5G", "80M",
4215 "VHT", "1T", "106", "20", "ETSI", "5G", "80M", "VHT", "1T",
4216 "106", "30", "MKK", "5G", "80M", "VHT", "1T", "106", "30",
4217 "FCC", "5G", "80M", "VHT", "1T", "122", "30", "ETSI", "5G",
4218 "80M", "VHT", "1T", "122", "30", "MKK", "5G", "80M", "VHT",
4219 "1T", "122", "30", "FCC", "5G", "80M", "VHT", "1T", "138",
4220 "30", "ETSI", "5G", "80M", "VHT", "1T", "138", "63", "MKK",
4221 "5G", "80M", "VHT", "1T", "138", "63", "FCC", "5G", "80M",
4222 "VHT", "1T", "155", "30", "ETSI", "5G", "80M", "VHT", "1T",
4223 "155", "63", "MKK", "5G", "80M", "VHT", "1T", "155", "63",
4224 "FCC", "5G", "80M", "VHT", "2T", "42", "18", "ETSI", "5G",
4225 "80M", "VHT", "2T", "42", "20", "MKK", "5G", "80M", "VHT",
4226 "2T", "42", "22", "FCC", "5G", "80M", "VHT", "2T", "58",
4227 "18", "ETSI", "5G", "80M", "VHT", "2T", "58", "20", "MKK",
4228 "5G", "80M", "VHT", "2T", "58", "22", "FCC", "5G", "80M",
4229 "VHT", "2T", "106", "20", "ETSI", "5G", "80M", "VHT", "2T",
4230 "106", "20", "MKK", "5G", "80M", "VHT", "2T", "106", "30",
4231 "FCC", "5G", "80M", "VHT", "2T", "122", "30", "ETSI", "5G",
4232 "80M", "VHT", "2T", "122", "20", "MKK", "5G", "80M", "VHT",
4233 "2T", "122", "30", "FCC", "5G", "80M", "VHT", "2T", "138",
4234 "30", "ETSI", "5G", "80M", "VHT", "2T", "138", "63", "MKK",
4235 "5G", "80M", "VHT", "2T", "138", "63", "FCC", "5G", "80M",
4236 "VHT", "2T", "155", "30", "ETSI", "5G", "80M", "VHT", "2T",
4237 "155", "63", "MKK", "5G", "80M", "VHT", "2T", "155", "63"};
4238
4239void odm_read_and_config_mp_8822b_txpwr_lmt(struct phy_dm_struct *dm)
4240{
4241 u32 i = 0;
4242 u32 array_len = sizeof(array_mp_8822b_txpwr_lmt) / sizeof(u8 *);
4243 u8 **array = (u8 **)array_mp_8822b_txpwr_lmt;
4244
4245 ODM_RT_TRACE(dm, ODM_COMP_INIT,
4246 "===> %s\n", __func__);
4247
4248 for (i = 0; i < array_len; i += 7) {
4249 u8 *regulation = array[i];
4250 u8 *band = array[i + 1];
4251 u8 *bandwidth = array[i + 2];
4252 u8 *rate = array[i + 3];
4253 u8 *rf_path = array[i + 4];
4254 u8 *chnl = array[i + 5];
4255 u8 *val = array[i + 6];
4256
4257 odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth,
4258 rate, rf_path, chnl, val);
4259 }
4260}
4261
4262/******************************************************************************
4263* txpwr_lmt_type5.TXT
4264******************************************************************************/
4265
4266static const char *const array_mp_8822b_txpwr_lmt_type5[] = {
4267 "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", "ETSI", "2.4G",
4268 "20M", "CCK", "1T", "01", "28", "MKK", "2.4G", "20M", "CCK",
4269 "1T", "01", "30", "FCC", "2.4G", "20M", "CCK", "1T", "02",
4270 "32", "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", "MKK",
4271 "2.4G", "20M", "CCK", "1T", "02", "30", "FCC", "2.4G", "20M",
4272 "CCK", "1T", "03", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
4273 "03", "28", "MKK", "2.4G", "20M", "CCK", "1T", "03", "30",
4274 "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", "ETSI", "2.4G",
4275 "20M", "CCK", "1T", "04", "28", "MKK", "2.4G", "20M", "CCK",
4276 "1T", "04", "30", "FCC", "2.4G", "20M", "CCK", "1T", "05",
4277 "32", "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", "MKK",
4278 "2.4G", "20M", "CCK", "1T", "05", "30", "FCC", "2.4G", "20M",
4279 "CCK", "1T", "06", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
4280 "06", "28", "MKK", "2.4G", "20M", "CCK", "1T", "06", "30",
4281 "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", "ETSI", "2.4G",
4282 "20M", "CCK", "1T", "07", "28", "MKK", "2.4G", "20M", "CCK",
4283 "1T", "07", "30", "FCC", "2.4G", "20M", "CCK", "1T", "08",
4284 "32", "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", "MKK",
4285 "2.4G", "20M", "CCK", "1T", "08", "30", "FCC", "2.4G", "20M",
4286 "CCK", "1T", "09", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
4287 "09", "28", "MKK", "2.4G", "20M", "CCK", "1T", "09", "30",
4288 "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", "ETSI", "2.4G",
4289 "20M", "CCK", "1T", "10", "28", "MKK", "2.4G", "20M", "CCK",
4290 "1T", "10", "30", "FCC", "2.4G", "20M", "CCK", "1T", "11",
4291 "32", "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", "MKK",
4292 "2.4G", "20M", "CCK", "1T", "11", "30", "FCC", "2.4G", "20M",
4293 "CCK", "1T", "12", "26", "ETSI", "2.4G", "20M", "CCK", "1T",
4294 "12", "28", "MKK", "2.4G", "20M", "CCK", "1T", "12", "30",
4295 "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", "ETSI", "2.4G",
4296 "20M", "CCK", "1T", "13", "28", "MKK", "2.4G", "20M", "CCK",
4297 "1T", "13", "28", "FCC", "2.4G", "20M", "CCK", "1T", "14",
4298 "63", "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", "MKK",
4299 "2.4G", "20M", "CCK", "1T", "14", "32", "FCC", "2.4G", "20M",
4300 "OFDM", "1T", "01", "26", "ETSI", "2.4G", "20M", "OFDM", "1T",
4301 "01", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34",
4302 "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", "ETSI", "2.4G",
4303 "20M", "OFDM", "1T", "02", "30", "MKK", "2.4G", "20M", "OFDM",
4304 "1T", "02", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "03",
4305 "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", "MKK",
4306 "2.4G", "20M", "OFDM", "1T", "03", "34", "FCC", "2.4G", "20M",
4307 "OFDM", "1T", "04", "34", "ETSI", "2.4G", "20M", "OFDM", "1T",
4308 "04", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34",
4309 "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", "ETSI", "2.4G",
4310 "20M", "OFDM", "1T", "05", "30", "MKK", "2.4G", "20M", "OFDM",
4311 "1T", "05", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "06",
4312 "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", "MKK",
4313 "2.4G", "20M", "OFDM", "1T", "06", "34", "FCC", "2.4G", "20M",
4314 "OFDM", "1T", "07", "34", "ETSI", "2.4G", "20M", "OFDM", "1T",
4315 "07", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34",
4316 "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", "ETSI", "2.4G",
4317 "20M", "OFDM", "1T", "08", "30", "MKK", "2.4G", "20M", "OFDM",
4318 "1T", "08", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "09",
4319 "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", "MKK",
4320 "2.4G", "20M", "OFDM", "1T", "09", "34", "FCC", "2.4G", "20M",
4321 "OFDM", "1T", "10", "30", "ETSI", "2.4G", "20M", "OFDM", "1T",
4322 "10", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34",
4323 "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", "ETSI", "2.4G",
4324 "20M", "OFDM", "1T", "11", "30", "MKK", "2.4G", "20M", "OFDM",
4325 "1T", "11", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "12",
4326 "22", "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", "MKK",
4327 "2.4G", "20M", "OFDM", "1T", "12", "34", "FCC", "2.4G", "20M",
4328 "OFDM", "1T", "13", "14", "ETSI", "2.4G", "20M", "OFDM", "1T",
4329 "13", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34",
4330 "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", "ETSI", "2.4G",
4331 "20M", "OFDM", "1T", "14", "63", "MKK", "2.4G", "20M", "OFDM",
4332 "1T", "14", "63", "FCC", "2.4G", "20M", "HT", "1T", "01",
4333 "26", "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", "MKK",
4334 "2.4G", "20M", "HT", "1T", "01", "34", "FCC", "2.4G", "20M",
4335 "HT", "1T", "02", "30", "ETSI", "2.4G", "20M", "HT", "1T",
4336 "02", "30", "MKK", "2.4G", "20M", "HT", "1T", "02", "34",
4337 "FCC", "2.4G", "20M", "HT", "1T", "03", "32", "ETSI", "2.4G",
4338 "20M", "HT", "1T", "03", "30", "MKK", "2.4G", "20M", "HT",
4339 "1T", "03", "34", "FCC", "2.4G", "20M", "HT", "1T", "04",
4340 "34", "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", "MKK",
4341 "2.4G", "20M", "HT", "1T", "04", "34", "FCC", "2.4G", "20M",
4342 "HT", "1T", "05", "34", "ETSI", "2.4G", "20M", "HT", "1T",
4343 "05", "30", "MKK", "2.4G", "20M", "HT", "1T", "05", "34",
4344 "FCC", "2.4G", "20M", "HT", "1T", "06", "34", "ETSI", "2.4G",
4345 "20M", "HT", "1T", "06", "30", "MKK", "2.4G", "20M", "HT",
4346 "1T", "06", "34", "FCC", "2.4G", "20M", "HT", "1T", "07",
4347 "34", "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", "MKK",
4348 "2.4G", "20M", "HT", "1T", "07", "34", "FCC", "2.4G", "20M",
4349 "HT", "1T", "08", "34", "ETSI", "2.4G", "20M", "HT", "1T",
4350 "08", "30", "MKK", "2.4G", "20M", "HT", "1T", "08", "34",
4351 "FCC", "2.4G", "20M", "HT", "1T", "09", "32", "ETSI", "2.4G",
4352 "20M", "HT", "1T", "09", "30", "MKK", "2.4G", "20M", "HT",
4353 "1T", "09", "34", "FCC", "2.4G", "20M", "HT", "1T", "10",
4354 "30", "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", "MKK",
4355 "2.4G", "20M", "HT", "1T", "10", "34", "FCC", "2.4G", "20M",
4356 "HT", "1T", "11", "26", "ETSI", "2.4G", "20M", "HT", "1T",
4357 "11", "30", "MKK", "2.4G", "20M", "HT", "1T", "11", "34",
4358 "FCC", "2.4G", "20M", "HT", "1T", "12", "20", "ETSI", "2.4G",
4359 "20M", "HT", "1T", "12", "30", "MKK", "2.4G", "20M", "HT",
4360 "1T", "12", "34", "FCC", "2.4G", "20M", "HT", "1T", "13",
4361 "14", "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", "MKK",
4362 "2.4G", "20M", "HT", "1T", "13", "34", "FCC", "2.4G", "20M",
4363 "HT", "1T", "14", "63", "ETSI", "2.4G", "20M", "HT", "1T",
4364 "14", "63", "MKK", "2.4G", "20M", "HT", "1T", "14", "63",
4365 "FCC", "2.4G", "20M", "HT", "2T", "01", "26", "ETSI", "2.4G",
4366 "20M", "HT", "2T", "01", "18", "MKK", "2.4G", "20M", "HT",
4367 "2T", "01", "30", "FCC", "2.4G", "20M", "HT", "2T", "02",
4368 "28", "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", "MKK",
4369 "2.4G", "20M", "HT", "2T", "02", "30", "FCC", "2.4G", "20M",
4370 "HT", "2T", "03", "30", "ETSI", "2.4G", "20M", "HT", "2T",
4371 "03", "18", "MKK", "2.4G", "20M", "HT", "2T", "03", "30",
4372 "FCC", "2.4G", "20M", "HT", "2T", "04", "30", "ETSI", "2.4G",
4373 "20M", "HT", "2T", "04", "18", "MKK", "2.4G", "20M", "HT",
4374 "2T", "04", "30", "FCC", "2.4G", "20M", "HT", "2T", "05",
4375 "32", "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", "MKK",
4376 "2.4G", "20M", "HT", "2T", "05", "30", "FCC", "2.4G", "20M",
4377 "HT", "2T", "06", "32", "ETSI", "2.4G", "20M", "HT", "2T",
4378 "06", "18", "MKK", "2.4G", "20M", "HT", "2T", "06", "30",
4379 "FCC", "2.4G", "20M", "HT", "2T", "07", "32", "ETSI", "2.4G",
4380 "20M", "HT", "2T", "07", "18", "MKK", "2.4G", "20M", "HT",
4381 "2T", "07", "30", "FCC", "2.4G", "20M", "HT", "2T", "08",
4382 "30", "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", "MKK",
4383 "2.4G", "20M", "HT", "2T", "08", "30", "FCC", "2.4G", "20M",
4384 "HT", "2T", "09", "30", "ETSI", "2.4G", "20M", "HT", "2T",
4385 "09", "18", "MKK", "2.4G", "20M", "HT", "2T", "09", "30",
4386 "FCC", "2.4G", "20M", "HT", "2T", "10", "28", "ETSI", "2.4G",
4387 "20M", "HT", "2T", "10", "18", "MKK", "2.4G", "20M", "HT",
4388 "2T", "10", "30", "FCC", "2.4G", "20M", "HT", "2T", "11",
4389 "26", "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", "MKK",
4390 "2.4G", "20M", "HT", "2T", "11", "30", "FCC", "2.4G", "20M",
4391 "HT", "2T", "12", "20", "ETSI", "2.4G", "20M", "HT", "2T",
4392 "12", "18", "MKK", "2.4G", "20M", "HT", "2T", "12", "30",
4393 "FCC", "2.4G", "20M", "HT", "2T", "13", "14", "ETSI", "2.4G",
4394 "20M", "HT", "2T", "13", "18", "MKK", "2.4G", "20M", "HT",
4395 "2T", "13", "30", "FCC", "2.4G", "20M", "HT", "2T", "14",
4396 "63", "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", "MKK",
4397 "2.4G", "20M", "HT", "2T", "14", "63", "FCC", "2.4G", "40M",
4398 "HT", "1T", "01", "63", "ETSI", "2.4G", "40M", "HT", "1T",
4399 "01", "63", "MKK", "2.4G", "40M", "HT", "1T", "01", "63",
4400 "FCC", "2.4G", "40M", "HT", "1T", "02", "63", "ETSI", "2.4G",
4401 "40M", "HT", "1T", "02", "63", "MKK", "2.4G", "40M", "HT",
4402 "1T", "02", "63", "FCC", "2.4G", "40M", "HT", "1T", "03",
4403 "26", "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", "MKK",
4404 "2.4G", "40M", "HT", "1T", "03", "34", "FCC", "2.4G", "40M",
4405 "HT", "1T", "04", "26", "ETSI", "2.4G", "40M", "HT", "1T",
4406 "04", "30", "MKK", "2.4G", "40M", "HT", "1T", "04", "34",
4407 "FCC", "2.4G", "40M", "HT", "1T", "05", "30", "ETSI", "2.4G",
4408 "40M", "HT", "1T", "05", "30", "MKK", "2.4G", "40M", "HT",
4409 "1T", "05", "34", "FCC", "2.4G", "40M", "HT", "1T", "06",
4410 "32", "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", "MKK",
4411 "2.4G", "40M", "HT", "1T", "06", "34", "FCC", "2.4G", "40M",
4412 "HT", "1T", "07", "30", "ETSI", "2.4G", "40M", "HT", "1T",
4413 "07", "30", "MKK", "2.4G", "40M", "HT", "1T", "07", "34",
4414 "FCC", "2.4G", "40M", "HT", "1T", "08", "26", "ETSI", "2.4G",
4415 "40M", "HT", "1T", "08", "30", "MKK", "2.4G", "40M", "HT",
4416 "1T", "08", "34", "FCC", "2.4G", "40M", "HT", "1T", "09",
4417 "26", "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", "MKK",
4418 "2.4G", "40M", "HT", "1T", "09", "34", "FCC", "2.4G", "40M",
4419 "HT", "1T", "10", "20", "ETSI", "2.4G", "40M", "HT", "1T",
4420 "10", "30", "MKK", "2.4G", "40M", "HT", "1T", "10", "34",
4421 "FCC", "2.4G", "40M", "HT", "1T", "11", "14", "ETSI", "2.4G",
4422 "40M", "HT", "1T", "11", "30", "MKK", "2.4G", "40M", "HT",
4423 "1T", "11", "34", "FCC", "2.4G", "40M", "HT", "1T", "12",
4424 "63", "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", "MKK",
4425 "2.4G", "40M", "HT", "1T", "12", "63", "FCC", "2.4G", "40M",
4426 "HT", "1T", "13", "63", "ETSI", "2.4G", "40M", "HT", "1T",
4427 "13", "63", "MKK", "2.4G", "40M", "HT", "1T", "13", "63",
4428 "FCC", "2.4G", "40M", "HT", "1T", "14", "63", "ETSI", "2.4G",
4429 "40M", "HT", "1T", "14", "63", "MKK", "2.4G", "40M", "HT",
4430 "1T", "14", "63", "FCC", "2.4G", "40M", "HT", "2T", "01",
4431 "63", "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", "MKK",
4432 "2.4G", "40M", "HT", "2T", "01", "63", "FCC", "2.4G", "40M",
4433 "HT", "2T", "02", "63", "ETSI", "2.4G", "40M", "HT", "2T",
4434 "02", "63", "MKK", "2.4G", "40M", "HT", "2T", "02", "63",
4435 "FCC", "2.4G", "40M", "HT", "2T", "03", "24", "ETSI", "2.4G",
4436 "40M", "HT", "2T", "03", "18", "MKK", "2.4G", "40M", "HT",
4437 "2T", "03", "30", "FCC", "2.4G", "40M", "HT", "2T", "04",
4438 "24", "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", "MKK",
4439 "2.4G", "40M", "HT", "2T", "04", "30", "FCC", "2.4G", "40M",
4440 "HT", "2T", "05", "26", "ETSI", "2.4G", "40M", "HT", "2T",
4441 "05", "18", "MKK", "2.4G", "40M", "HT", "2T", "05", "30",
4442 "FCC", "2.4G", "40M", "HT", "2T", "06", "28", "ETSI", "2.4G",
4443 "40M", "HT", "2T", "06", "18", "MKK", "2.4G", "40M", "HT",
4444 "2T", "06", "30", "FCC", "2.4G", "40M", "HT", "2T", "07",
4445 "26", "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", "MKK",
4446 "2.4G", "40M", "HT", "2T", "07", "30", "FCC", "2.4G", "40M",
4447 "HT", "2T", "08", "26", "ETSI", "2.4G", "40M", "HT", "2T",
4448 "08", "18", "MKK", "2.4G", "40M", "HT", "2T", "08", "30",
4449 "FCC", "2.4G", "40M", "HT", "2T", "09", "26", "ETSI", "2.4G",
4450 "40M", "HT", "2T", "09", "18", "MKK", "2.4G", "40M", "HT",
4451 "2T", "09", "30", "FCC", "2.4G", "40M", "HT", "2T", "10",
4452 "20", "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", "MKK",
4453 "2.4G", "40M", "HT", "2T", "10", "30", "FCC", "2.4G", "40M",
4454 "HT", "2T", "11", "14", "ETSI", "2.4G", "40M", "HT", "2T",
4455 "11", "18", "MKK", "2.4G", "40M", "HT", "2T", "11", "30",
4456 "FCC", "2.4G", "40M", "HT", "2T", "12", "63", "ETSI", "2.4G",
4457 "40M", "HT", "2T", "12", "63", "MKK", "2.4G", "40M", "HT",
4458 "2T", "12", "63", "FCC", "2.4G", "40M", "HT", "2T", "13",
4459 "63", "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", "MKK",
4460 "2.4G", "40M", "HT", "2T", "13", "63", "FCC", "2.4G", "40M",
4461 "HT", "2T", "14", "63", "ETSI", "2.4G", "40M", "HT", "2T",
4462 "14", "63", "MKK", "2.4G", "40M", "HT", "2T", "14", "63",
4463 "FCC", "5G", "20M", "OFDM", "1T", "36", "30", "ETSI", "5G",
4464 "20M", "OFDM", "1T", "36", "32", "MKK", "5G", "20M", "OFDM",
4465 "1T", "36", "30", "FCC", "5G", "20M", "OFDM", "1T", "40",
4466 "32", "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", "MKK",
4467 "5G", "20M", "OFDM", "1T", "40", "30", "FCC", "5G", "20M",
4468 "OFDM", "1T", "44", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4469 "44", "32", "MKK", "5G", "20M", "OFDM", "1T", "44", "30",
4470 "FCC", "5G", "20M", "OFDM", "1T", "48", "32", "ETSI", "5G",
4471 "20M", "OFDM", "1T", "48", "32", "MKK", "5G", "20M", "OFDM",
4472 "1T", "48", "30", "FCC", "5G", "20M", "OFDM", "1T", "52",
4473 "32", "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", "MKK",
4474 "5G", "20M", "OFDM", "1T", "52", "28", "FCC", "5G", "20M",
4475 "OFDM", "1T", "56", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4476 "56", "32", "MKK", "5G", "20M", "OFDM", "1T", "56", "28",
4477 "FCC", "5G", "20M", "OFDM", "1T", "60", "32", "ETSI", "5G",
4478 "20M", "OFDM", "1T", "60", "32", "MKK", "5G", "20M", "OFDM",
4479 "1T", "60", "28", "FCC", "5G", "20M", "OFDM", "1T", "64",
4480 "28", "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", "MKK",
4481 "5G", "20M", "OFDM", "1T", "64", "28", "FCC", "5G", "20M",
4482 "OFDM", "1T", "100", "26", "ETSI", "5G", "20M", "OFDM", "1T",
4483 "100", "32", "MKK", "5G", "20M", "OFDM", "1T", "100", "32",
4484 "FCC", "5G", "20M", "OFDM", "1T", "104", "32", "ETSI", "5G",
4485 "20M", "OFDM", "1T", "104", "32", "MKK", "5G", "20M", "OFDM",
4486 "1T", "104", "32", "FCC", "5G", "20M", "OFDM", "1T", "108",
4487 "32", "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", "MKK",
4488 "5G", "20M", "OFDM", "1T", "108", "32", "FCC", "5G", "20M",
4489 "OFDM", "1T", "112", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4490 "112", "32", "MKK", "5G", "20M", "OFDM", "1T", "112", "32",
4491 "FCC", "5G", "20M", "OFDM", "1T", "116", "32", "ETSI", "5G",
4492 "20M", "OFDM", "1T", "116", "32", "MKK", "5G", "20M", "OFDM",
4493 "1T", "116", "32", "FCC", "5G", "20M", "OFDM", "1T", "120",
4494 "32", "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", "MKK",
4495 "5G", "20M", "OFDM", "1T", "120", "32", "FCC", "5G", "20M",
4496 "OFDM", "1T", "124", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4497 "124", "32", "MKK", "5G", "20M", "OFDM", "1T", "124", "32",
4498 "FCC", "5G", "20M", "OFDM", "1T", "128", "32", "ETSI", "5G",
4499 "20M", "OFDM", "1T", "128", "32", "MKK", "5G", "20M", "OFDM",
4500 "1T", "128", "32", "FCC", "5G", "20M", "OFDM", "1T", "132",
4501 "32", "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", "MKK",
4502 "5G", "20M", "OFDM", "1T", "132", "32", "FCC", "5G", "20M",
4503 "OFDM", "1T", "136", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4504 "136", "32", "MKK", "5G", "20M", "OFDM", "1T", "136", "32",
4505 "FCC", "5G", "20M", "OFDM", "1T", "140", "28", "ETSI", "5G",
4506 "20M", "OFDM", "1T", "140", "32", "MKK", "5G", "20M", "OFDM",
4507 "1T", "140", "32", "FCC", "5G", "20M", "OFDM", "1T", "144",
4508 "28", "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", "MKK",
4509 "5G", "20M", "OFDM", "1T", "144", "63", "FCC", "5G", "20M",
4510 "OFDM", "1T", "149", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4511 "149", "63", "MKK", "5G", "20M", "OFDM", "1T", "149", "63",
4512 "FCC", "5G", "20M", "OFDM", "1T", "153", "32", "ETSI", "5G",
4513 "20M", "OFDM", "1T", "153", "63", "MKK", "5G", "20M", "OFDM",
4514 "1T", "153", "63", "FCC", "5G", "20M", "OFDM", "1T", "157",
4515 "32", "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", "MKK",
4516 "5G", "20M", "OFDM", "1T", "157", "63", "FCC", "5G", "20M",
4517 "OFDM", "1T", "161", "32", "ETSI", "5G", "20M", "OFDM", "1T",
4518 "161", "63", "MKK", "5G", "20M", "OFDM", "1T", "161", "63",
4519 "FCC", "5G", "20M", "OFDM", "1T", "165", "32", "ETSI", "5G",
4520 "20M", "OFDM", "1T", "165", "63", "MKK", "5G", "20M", "OFDM",
4521 "1T", "165", "63", "FCC", "5G", "20M", "HT", "1T", "36",
4522 "30", "ETSI", "5G", "20M", "HT", "1T", "36", "32", "MKK",
4523 "5G", "20M", "HT", "1T", "36", "28", "FCC", "5G", "20M",
4524 "HT", "1T", "40", "32", "ETSI", "5G", "20M", "HT", "1T",
4525 "40", "32", "MKK", "5G", "20M", "HT", "1T", "40", "28",
4526 "FCC", "5G", "20M", "HT", "1T", "44", "32", "ETSI", "5G",
4527 "20M", "HT", "1T", "44", "32", "MKK", "5G", "20M", "HT",
4528 "1T", "44", "28", "FCC", "5G", "20M", "HT", "1T", "48",
4529 "32", "ETSI", "5G", "20M", "HT", "1T", "48", "32", "MKK",
4530 "5G", "20M", "HT", "1T", "48", "28", "FCC", "5G", "20M",
4531 "HT", "1T", "52", "32", "ETSI", "5G", "20M", "HT", "1T",
4532 "52", "32", "MKK", "5G", "20M", "HT", "1T", "52", "28",
4533 "FCC", "5G", "20M", "HT", "1T", "56", "32", "ETSI", "5G",
4534 "20M", "HT", "1T", "56", "32", "MKK", "5G", "20M", "HT",
4535 "1T", "56", "28", "FCC", "5G", "20M", "HT", "1T", "60",
4536 "32", "ETSI", "5G", "20M", "HT", "1T", "60", "32", "MKK",
4537 "5G", "20M", "HT", "1T", "60", "28", "FCC", "5G", "20M",
4538 "HT", "1T", "64", "28", "ETSI", "5G", "20M", "HT", "1T",
4539 "64", "32", "MKK", "5G", "20M", "HT", "1T", "64", "28",
4540 "FCC", "5G", "20M", "HT", "1T", "100", "26", "ETSI", "5G",
4541 "20M", "HT", "1T", "100", "32", "MKK", "5G", "20M", "HT",
4542 "1T", "100", "32", "FCC", "5G", "20M", "HT", "1T", "104",
4543 "32", "ETSI", "5G", "20M", "HT", "1T", "104", "32", "MKK",
4544 "5G", "20M", "HT", "1T", "104", "32", "FCC", "5G", "20M",
4545 "HT", "1T", "108", "32", "ETSI", "5G", "20M", "HT", "1T",
4546 "108", "32", "MKK", "5G", "20M", "HT", "1T", "108", "32",
4547 "FCC", "5G", "20M", "HT", "1T", "112", "32", "ETSI", "5G",
4548 "20M", "HT", "1T", "112", "32", "MKK", "5G", "20M", "HT",
4549 "1T", "112", "32", "FCC", "5G", "20M", "HT", "1T", "116",
4550 "32", "ETSI", "5G", "20M", "HT", "1T", "116", "32", "MKK",
4551 "5G", "20M", "HT", "1T", "116", "32", "FCC", "5G", "20M",
4552 "HT", "1T", "120", "32", "ETSI", "5G", "20M", "HT", "1T",
4553 "120", "32", "MKK", "5G", "20M", "HT", "1T", "120", "32",
4554 "FCC", "5G", "20M", "HT", "1T", "124", "32", "ETSI", "5G",
4555 "20M", "HT", "1T", "124", "32", "MKK", "5G", "20M", "HT",
4556 "1T", "124", "32", "FCC", "5G", "20M", "HT", "1T", "128",
4557 "32", "ETSI", "5G", "20M", "HT", "1T", "128", "32", "MKK",
4558 "5G", "20M", "HT", "1T", "128", "32", "FCC", "5G", "20M",
4559 "HT", "1T", "132", "32", "ETSI", "5G", "20M", "HT", "1T",
4560 "132", "32", "MKK", "5G", "20M", "HT", "1T", "132", "32",
4561 "FCC", "5G", "20M", "HT", "1T", "136", "32", "ETSI", "5G",
4562 "20M", "HT", "1T", "136", "32", "MKK", "5G", "20M", "HT",
4563 "1T", "136", "32", "FCC", "5G", "20M", "HT", "1T", "140",
4564 "26", "ETSI", "5G", "20M", "HT", "1T", "140", "32", "MKK",
4565 "5G", "20M", "HT", "1T", "140", "32", "FCC", "5G", "20M",
4566 "HT", "1T", "144", "26", "ETSI", "5G", "20M", "HT", "1T",
4567 "144", "63", "MKK", "5G", "20M", "HT", "1T", "144", "63",
4568 "FCC", "5G", "20M", "HT", "1T", "149", "32", "ETSI", "5G",
4569 "20M", "HT", "1T", "149", "63", "MKK", "5G", "20M", "HT",
4570 "1T", "149", "63", "FCC", "5G", "20M", "HT", "1T", "153",
4571 "32", "ETSI", "5G", "20M", "HT", "1T", "153", "63", "MKK",
4572 "5G", "20M", "HT", "1T", "153", "63", "FCC", "5G", "20M",
4573 "HT", "1T", "157", "32", "ETSI", "5G", "20M", "HT", "1T",
4574 "157", "63", "MKK", "5G", "20M", "HT", "1T", "157", "63",
4575 "FCC", "5G", "20M", "HT", "1T", "161", "32", "ETSI", "5G",
4576 "20M", "HT", "1T", "161", "63", "MKK", "5G", "20M", "HT",
4577 "1T", "161", "63", "FCC", "5G", "20M", "HT", "1T", "165",
4578 "32", "ETSI", "5G", "20M", "HT", "1T", "165", "63", "MKK",
4579 "5G", "20M", "HT", "1T", "165", "63", "FCC", "5G", "20M",
4580 "HT", "2T", "36", "28", "ETSI", "5G", "20M", "HT", "2T",
4581 "36", "20", "MKK", "5G", "20M", "HT", "2T", "36", "22",
4582 "FCC", "5G", "20M", "HT", "2T", "40", "30", "ETSI", "5G",
4583 "20M", "HT", "2T", "40", "20", "MKK", "5G", "20M", "HT",
4584 "2T", "40", "22", "FCC", "5G", "20M", "HT", "2T", "44",
4585 "30", "ETSI", "5G", "20M", "HT", "2T", "44", "20", "MKK",
4586 "5G", "20M", "HT", "2T", "44", "22", "FCC", "5G", "20M",
4587 "HT", "2T", "48", "30", "ETSI", "5G", "20M", "HT", "2T",
4588 "48", "20", "MKK", "5G", "20M", "HT", "2T", "48", "22",
4589 "FCC", "5G", "20M", "HT", "2T", "52", "30", "ETSI", "5G",
4590 "20M", "HT", "2T", "52", "20", "MKK", "5G", "20M", "HT",
4591 "2T", "52", "22", "FCC", "5G", "20M", "HT", "2T", "56",
4592 "30", "ETSI", "5G", "20M", "HT", "2T", "56", "20", "MKK",
4593 "5G", "20M", "HT", "2T", "56", "22", "FCC", "5G", "20M",
4594 "HT", "2T", "60", "30", "ETSI", "5G", "20M", "HT", "2T",
4595 "60", "20", "MKK", "5G", "20M", "HT", "2T", "60", "22",
4596 "FCC", "5G", "20M", "HT", "2T", "64", "28", "ETSI", "5G",
4597 "20M", "HT", "2T", "64", "20", "MKK", "5G", "20M", "HT",
4598 "2T", "64", "22", "FCC", "5G", "20M", "HT", "2T", "100",
4599 "26", "ETSI", "5G", "20M", "HT", "2T", "100", "20", "MKK",
4600 "5G", "20M", "HT", "2T", "100", "30", "FCC", "5G", "20M",
4601 "HT", "2T", "104", "30", "ETSI", "5G", "20M", "HT", "2T",
4602 "104", "20", "MKK", "5G", "20M", "HT", "2T", "104", "30",
4603 "FCC", "5G", "20M", "HT", "2T", "108", "32", "ETSI", "5G",
4604 "20M", "HT", "2T", "108", "20", "MKK", "5G", "20M", "HT",
4605 "2T", "108", "30", "FCC", "5G", "20M", "HT", "2T", "112",
4606 "32", "ETSI", "5G", "20M", "HT", "2T", "112", "20", "MKK",
4607 "5G", "20M", "HT", "2T", "112", "30", "FCC", "5G", "20M",
4608 "HT", "2T", "116", "32", "ETSI", "5G", "20M", "HT", "2T",
4609 "116", "20", "MKK", "5G", "20M", "HT", "2T", "116", "30",
4610 "FCC", "5G", "20M", "HT", "2T", "120", "32", "ETSI", "5G",
4611 "20M", "HT", "2T", "120", "20", "MKK", "5G", "20M", "HT",
4612 "2T", "120", "30", "FCC", "5G", "20M", "HT", "2T", "124",
4613 "32", "ETSI", "5G", "20M", "HT", "2T", "124", "20", "MKK",
4614 "5G", "20M", "HT", "2T", "124", "30", "FCC", "5G", "20M",
4615 "HT", "2T", "128", "32", "ETSI", "5G", "20M", "HT", "2T",
4616 "128", "20", "MKK", "5G", "20M", "HT", "2T", "128", "30",
4617 "FCC", "5G", "20M", "HT", "2T", "132", "32", "ETSI", "5G",
4618 "20M", "HT", "2T", "132", "20", "MKK", "5G", "20M", "HT",
4619 "2T", "132", "30", "FCC", "5G", "20M", "HT", "2T", "136",
4620 "30", "ETSI", "5G", "20M", "HT", "2T", "136", "20", "MKK",
4621 "5G", "20M", "HT", "2T", "136", "30", "FCC", "5G", "20M",
4622 "HT", "2T", "140", "26", "ETSI", "5G", "20M", "HT", "2T",
4623 "140", "20", "MKK", "5G", "20M", "HT", "2T", "140", "30",
4624 "FCC", "5G", "20M", "HT", "2T", "144", "26", "ETSI", "5G",
4625 "20M", "HT", "2T", "144", "63", "MKK", "5G", "20M", "HT",
4626 "2T", "144", "63", "FCC", "5G", "20M", "HT", "2T", "149",
4627 "32", "ETSI", "5G", "20M", "HT", "2T", "149", "63", "MKK",
4628 "5G", "20M", "HT", "2T", "149", "63", "FCC", "5G", "20M",
4629 "HT", "2T", "153", "32", "ETSI", "5G", "20M", "HT", "2T",
4630 "153", "63", "MKK", "5G", "20M", "HT", "2T", "153", "63",
4631 "FCC", "5G", "20M", "HT", "2T", "157", "32", "ETSI", "5G",
4632 "20M", "HT", "2T", "157", "63", "MKK", "5G", "20M", "HT",
4633 "2T", "157", "63", "FCC", "5G", "20M", "HT", "2T", "161",
4634 "32", "ETSI", "5G", "20M", "HT", "2T", "161", "63", "MKK",
4635 "5G", "20M", "HT", "2T", "161", "63", "FCC", "5G", "20M",
4636 "HT", "2T", "165", "32", "ETSI", "5G", "20M", "HT", "2T",
4637 "165", "63", "MKK", "5G", "20M", "HT", "2T", "165", "63",
4638 "FCC", "5G", "40M", "HT", "1T", "38", "22", "ETSI", "5G",
4639 "40M", "HT", "1T", "38", "30", "MKK", "5G", "40M", "HT",
4640 "1T", "38", "30", "FCC", "5G", "40M", "HT", "1T", "46",
4641 "30", "ETSI", "5G", "40M", "HT", "1T", "46", "30", "MKK",
4642 "5G", "40M", "HT", "1T", "46", "30", "FCC", "5G", "40M",
4643 "HT", "1T", "54", "30", "ETSI", "5G", "40M", "HT", "1T",
4644 "54", "30", "MKK", "5G", "40M", "HT", "1T", "54", "30",
4645 "FCC", "5G", "40M", "HT", "1T", "62", "24", "ETSI", "5G",
4646 "40M", "HT", "1T", "62", "30", "MKK", "5G", "40M", "HT",
4647 "1T", "62", "30", "FCC", "5G", "40M", "HT", "1T", "102",
4648 "24", "ETSI", "5G", "40M", "HT", "1T", "102", "30", "MKK",
4649 "5G", "40M", "HT", "1T", "102", "30", "FCC", "5G", "40M",
4650 "HT", "1T", "110", "30", "ETSI", "5G", "40M", "HT", "1T",
4651 "110", "30", "MKK", "5G", "40M", "HT", "1T", "110", "30",
4652 "FCC", "5G", "40M", "HT", "1T", "118", "30", "ETSI", "5G",
4653 "40M", "HT", "1T", "118", "30", "MKK", "5G", "40M", "HT",
4654 "1T", "118", "30", "FCC", "5G", "40M", "HT", "1T", "126",
4655 "30", "ETSI", "5G", "40M", "HT", "1T", "126", "30", "MKK",
4656 "5G", "40M", "HT", "1T", "126", "30", "FCC", "5G", "40M",
4657 "HT", "1T", "134", "30", "ETSI", "5G", "40M", "HT", "1T",
4658 "134", "30", "MKK", "5G", "40M", "HT", "1T", "134", "30",
4659 "FCC", "5G", "40M", "HT", "1T", "142", "30", "ETSI", "5G",
4660 "40M", "HT", "1T", "142", "63", "MKK", "5G", "40M", "HT",
4661 "1T", "142", "63", "FCC", "5G", "40M", "HT", "1T", "151",
4662 "30", "ETSI", "5G", "40M", "HT", "1T", "151", "63", "MKK",
4663 "5G", "40M", "HT", "1T", "151", "63", "FCC", "5G", "40M",
4664 "HT", "1T", "159", "30", "ETSI", "5G", "40M", "HT", "1T",
4665 "159", "63", "MKK", "5G", "40M", "HT", "1T", "159", "63",
4666 "FCC", "5G", "40M", "HT", "2T", "38", "20", "ETSI", "5G",
4667 "40M", "HT", "2T", "38", "20", "MKK", "5G", "40M", "HT",
4668 "2T", "38", "22", "FCC", "5G", "40M", "HT", "2T", "46",
4669 "30", "ETSI", "5G", "40M", "HT", "2T", "46", "20", "MKK",
4670 "5G", "40M", "HT", "2T", "46", "22", "FCC", "5G", "40M",
4671 "HT", "2T", "54", "30", "ETSI", "5G", "40M", "HT", "2T",
4672 "54", "20", "MKK", "5G", "40M", "HT", "2T", "54", "22",
4673 "FCC", "5G", "40M", "HT", "2T", "62", "22", "ETSI", "5G",
4674 "40M", "HT", "2T", "62", "20", "MKK", "5G", "40M", "HT",
4675 "2T", "62", "22", "FCC", "5G", "40M", "HT", "2T", "102",
4676 "22", "ETSI", "5G", "40M", "HT", "2T", "102", "20", "MKK",
4677 "5G", "40M", "HT", "2T", "102", "30", "FCC", "5G", "40M",
4678 "HT", "2T", "110", "30", "ETSI", "5G", "40M", "HT", "2T",
4679 "110", "20", "MKK", "5G", "40M", "HT", "2T", "110", "30",
4680 "FCC", "5G", "40M", "HT", "2T", "118", "30", "ETSI", "5G",
4681 "40M", "HT", "2T", "118", "20", "MKK", "5G", "40M", "HT",
4682 "2T", "118", "30", "FCC", "5G", "40M", "HT", "2T", "126",
4683 "30", "ETSI", "5G", "40M", "HT", "2T", "126", "20", "MKK",
4684 "5G", "40M", "HT", "2T", "126", "30", "FCC", "5G", "40M",
4685 "HT", "2T", "134", "30", "ETSI", "5G", "40M", "HT", "2T",
4686 "134", "20", "MKK", "5G", "40M", "HT", "2T", "134", "30",
4687 "FCC", "5G", "40M", "HT", "2T", "142", "30", "ETSI", "5G",
4688 "40M", "HT", "2T", "142", "63", "MKK", "5G", "40M", "HT",
4689 "2T", "142", "63", "FCC", "5G", "40M", "HT", "2T", "151",
4690 "30", "ETSI", "5G", "40M", "HT", "2T", "151", "63", "MKK",
4691 "5G", "40M", "HT", "2T", "151", "63", "FCC", "5G", "40M",
4692 "HT", "2T", "159", "30", "ETSI", "5G", "40M", "HT", "2T",
4693 "159", "63", "MKK", "5G", "40M", "HT", "2T", "159", "63",
4694 "FCC", "5G", "80M", "VHT", "1T", "42", "20", "ETSI", "5G",
4695 "80M", "VHT", "1T", "42", "30", "MKK", "5G", "80M", "VHT",
4696 "1T", "42", "28", "FCC", "5G", "80M", "VHT", "1T", "58",
4697 "20", "ETSI", "5G", "80M", "VHT", "1T", "58", "30", "MKK",
4698 "5G", "80M", "VHT", "1T", "58", "28", "FCC", "5G", "80M",
4699 "VHT", "1T", "106", "20", "ETSI", "5G", "80M", "VHT", "1T",
4700 "106", "30", "MKK", "5G", "80M", "VHT", "1T", "106", "30",
4701 "FCC", "5G", "80M", "VHT", "1T", "122", "30", "ETSI", "5G",
4702 "80M", "VHT", "1T", "122", "30", "MKK", "5G", "80M", "VHT",
4703 "1T", "122", "30", "FCC", "5G", "80M", "VHT", "1T", "138",
4704 "30", "ETSI", "5G", "80M", "VHT", "1T", "138", "63", "MKK",
4705 "5G", "80M", "VHT", "1T", "138", "63", "FCC", "5G", "80M",
4706 "VHT", "1T", "155", "30", "ETSI", "5G", "80M", "VHT", "1T",
4707 "155", "63", "MKK", "5G", "80M", "VHT", "1T", "155", "63",
4708 "FCC", "5G", "80M", "VHT", "2T", "42", "18", "ETSI", "5G",
4709 "80M", "VHT", "2T", "42", "20", "MKK", "5G", "80M", "VHT",
4710 "2T", "42", "22", "FCC", "5G", "80M", "VHT", "2T", "58",
4711 "18", "ETSI", "5G", "80M", "VHT", "2T", "58", "20", "MKK",
4712 "5G", "80M", "VHT", "2T", "58", "22", "FCC", "5G", "80M",
4713 "VHT", "2T", "106", "20", "ETSI", "5G", "80M", "VHT", "2T",
4714 "106", "20", "MKK", "5G", "80M", "VHT", "2T", "106", "30",
4715 "FCC", "5G", "80M", "VHT", "2T", "122", "30", "ETSI", "5G",
4716 "80M", "VHT", "2T", "122", "20", "MKK", "5G", "80M", "VHT",
4717 "2T", "122", "30", "FCC", "5G", "80M", "VHT", "2T", "138",
4718 "30", "ETSI", "5G", "80M", "VHT", "2T", "138", "63", "MKK",
4719 "5G", "80M", "VHT", "2T", "138", "63", "FCC", "5G", "80M",
4720 "VHT", "2T", "155", "30", "ETSI", "5G", "80M", "VHT", "2T",
4721 "155", "63", "MKK", "5G", "80M", "VHT", "2T", "155", "63"};
4722
4723void odm_read_and_config_mp_8822b_txpwr_lmt_type5(struct phy_dm_struct *dm)
4724{
4725 u32 i = 0;
4726 u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type5) / sizeof(u8 *);
4727 u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type5;
4728
4729 ODM_RT_TRACE(dm, ODM_COMP_INIT,
4730 "===> odm_read_and_config_mp_8822b_txpwr_lmt_type5\n");
4731
4732 for (i = 0; i < array_len; i += 7) {
4733 u8 *regulation = array[i];
4734 u8 *band = array[i + 1];
4735 u8 *bandwidth = array[i + 2];
4736 u8 *rate = array[i + 3];
4737 u8 *rf_path = array[i + 4];
4738 u8 *chnl = array[i + 5];
4739 u8 *val = array[i + 6];
4740
4741 odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth,
4742 rate, rf_path, chnl, val);
4743 }
4744}
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_rf.h b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_rf.h
new file mode 100644
index 000000000000..1340fa9f369b
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/halhwimg8822b_rf.h
@@ -0,0 +1,129 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26/*Image2HeaderVersion: 3.2*/
27#ifndef __INC_MP_RF_HW_IMG_8822B_H
28#define __INC_MP_RF_HW_IMG_8822B_H
29
30/******************************************************************************
31 * radioa.TXT
32 ******************************************************************************/
33
34void odm_read_and_config_mp_8822b_radioa(struct phy_dm_struct *dm);
35u32 odm_get_version_mp_8822b_radioa(void);
36
37/******************************************************************************
38 * radiob.TXT
39 ******************************************************************************/
40
41void odm_read_and_config_mp_8822b_radiob(struct phy_dm_struct *dm);
42u32 odm_get_version_mp_8822b_radiob(void);
43
44/******************************************************************************
45 * txpowertrack.TXT
46 ******************************************************************************/
47
48void odm_read_and_config_mp_8822b_txpowertrack(struct phy_dm_struct *dm);
49u32 odm_get_version_mp_8822b_txpowertrack(void);
50
51/******************************************************************************
52 * txpowertrack_type0.TXT
53 ******************************************************************************/
54
55void odm_read_and_config_mp_8822b_txpowertrack_type0(struct phy_dm_struct *dm);
56u32 odm_get_version_mp_8822b_txpowertrack_type0(void);
57
58/******************************************************************************
59 * txpowertrack_type1.TXT
60 ******************************************************************************/
61
62void odm_read_and_config_mp_8822b_txpowertrack_type1(struct phy_dm_struct *dm);
63u32 odm_get_version_mp_8822b_txpowertrack_type1(void);
64
65/******************************************************************************
66 * txpowertrack_type2.TXT
67 ******************************************************************************/
68
69void odm_read_and_config_mp_8822b_txpowertrack_type2(struct phy_dm_struct *dm);
70u32 odm_get_version_mp_8822b_txpowertrack_type2(void);
71
72/******************************************************************************
73 * txpowertrack_type3_type5.TXT
74 ******************************************************************************/
75
76void odm_read_and_config_mp_8822b_txpowertrack_type3_type5(
77 struct phy_dm_struct *dm);
78u32 odm_get_version_mp_8822b_txpowertrack_type3_type5(void);
79
80/******************************************************************************
81 * txpowertrack_type4.TXT
82 ******************************************************************************/
83
84void odm_read_and_config_mp_8822b_txpowertrack_type4(struct phy_dm_struct *dm);
85u32 odm_get_version_mp_8822b_txpowertrack_type4(void);
86
87/******************************************************************************
88 * txpowertrack_type6.TXT
89 ******************************************************************************/
90
91void odm_read_and_config_mp_8822b_txpowertrack_type6(struct phy_dm_struct *dm);
92u32 odm_get_version_mp_8822b_txpowertrack_type6(void);
93
94/******************************************************************************
95 * txpowertrack_type7.TXT
96 ******************************************************************************/
97
98void odm_read_and_config_mp_8822b_txpowertrack_type7(struct phy_dm_struct *dm);
99u32 odm_get_version_mp_8822b_txpowertrack_type7(void);
100
101/******************************************************************************
102 * txpowertrack_type8.TXT
103 *****************************************************************************/
104
105void odm_read_and_config_mp_8822b_txpowertrack_type8(struct phy_dm_struct *dm);
106u32 odm_get_version_mp_8822b_txpowertrack_type8(void);
107
108/******************************************************************************
109 * txpowertrack_type9.TXT
110 ******************************************************************************/
111
112void odm_read_and_config_mp_8822b_txpowertrack_type9(struct phy_dm_struct *dm);
113u32 odm_get_version_mp_8822b_txpowertrack_type9(void);
114
115/******************************************************************************
116 * txpwr_lmt.TXT
117 ******************************************************************************/
118
119void odm_read_and_config_mp_8822b_txpwr_lmt(struct phy_dm_struct *dm);
120u32 odm_get_version_mp_8822b_txpwr_lmt(void);
121
122/******************************************************************************
123 * txpwr_lmt_type5.TXT
124 ******************************************************************************/
125
126void odm_read_and_config_mp_8822b_txpwr_lmt_type5(struct phy_dm_struct *dm);
127u32 odm_get_version_mp_8822b_txpwr_lmt_type5(void);
128
129#endif
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/halphyrf_8822b.c b/drivers/staging/rtlwifi/phydm/rtl8822b/halphyrf_8822b.c
new file mode 100644
index 000000000000..ae3e2278fefd
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/halphyrf_8822b.c
@@ -0,0 +1,351 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../mp_precomp.h"
27#include "../phydm_precomp.h"
28
29static bool
30get_mix_mode_tx_agc_bb_swing_offset_8822b(void *dm_void,
31 enum pwrtrack_method method,
32 u8 rf_path, u8 tx_power_index_offest)
33{
34 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
35 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
36
37 u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
38 u8 bb_swing_lower_bound = 0;
39
40 s8 tx_agc_index = 0;
41 u8 tx_bb_swing_index = cali_info->default_ofdm_index;
42
43 ODM_RT_TRACE(
44 dm, ODM_COMP_TX_PWR_TRACK,
45 "Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest=%d\n",
46 rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
47 tx_power_index_offest);
48
49 if (tx_power_index_offest > 0XF)
50 tx_power_index_offest = 0XF;
51
52 if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 &&
53 cali_info->absolute_ofdm_swing_idx[rf_path] <=
54 tx_power_index_offest) {
55 tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
56 tx_bb_swing_index = cali_info->default_ofdm_index;
57 } else if (cali_info->absolute_ofdm_swing_idx[rf_path] >
58 tx_power_index_offest) {
59 tx_agc_index = tx_power_index_offest;
60 cali_info->remnant_ofdm_swing_idx[rf_path] =
61 cali_info->absolute_ofdm_swing_idx[rf_path] -
62 tx_power_index_offest;
63 tx_bb_swing_index = cali_info->default_ofdm_index +
64 cali_info->remnant_ofdm_swing_idx[rf_path];
65
66 if (tx_bb_swing_index > bb_swing_upper_bound)
67 tx_bb_swing_index = bb_swing_upper_bound;
68 } else {
69 tx_agc_index = 0;
70
71 if (cali_info->default_ofdm_index >
72 (cali_info->absolute_ofdm_swing_idx[rf_path] * (-1)))
73 tx_bb_swing_index =
74 cali_info->default_ofdm_index +
75 cali_info->absolute_ofdm_swing_idx[rf_path];
76 else
77 tx_bb_swing_index = bb_swing_lower_bound;
78
79 if (tx_bb_swing_index < bb_swing_lower_bound)
80 tx_bb_swing_index = bb_swing_lower_bound;
81 }
82
83 cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
84 cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
85
86 ODM_RT_TRACE(
87 dm, ODM_COMP_TX_PWR_TRACK,
88 "MixMode Offset Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d cali_info->bb_swing_idx_ofdm[rf_path]=%d tx_power_index_offest=%d\n",
89 rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
90 cali_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest);
91
92 return true;
93}
94
95void odm_tx_pwr_track_set_pwr8822b(void *dm_void, enum pwrtrack_method method,
96 u8 rf_path, u8 channel_mapped_index)
97{
98 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
99 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
100 u8 tx_power_index_offest = 0;
101 u8 tx_power_index = 0;
102
103 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
104 struct rtl_phy *rtlphy = &rtlpriv->phy;
105 u8 channel = rtlphy->current_channel;
106 u8 band_width = rtlphy->current_chan_bw;
107 u8 tx_rate = 0xFF;
108
109 if (!dm->mp_mode) {
110 u16 rate = *dm->forced_data_rate;
111
112 if (!rate) /*auto rate*/
113 tx_rate = dm->tx_rate;
114 else /*force rate*/
115 tx_rate = (u8)rate;
116 }
117
118 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n",
119 __func__, tx_rate);
120
121 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
122 "pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n",
123 cali_info->default_ofdm_index,
124 cali_info->default_cck_index);
125
126 ODM_RT_TRACE(
127 dm, ODM_COMP_TX_PWR_TRACK,
128 "pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n",
129 cali_info->absolute_ofdm_swing_idx[rf_path],
130 cali_info->remnant_ofdm_swing_idx[rf_path],
131 cali_info->absolute_cck_swing_idx[rf_path],
132 cali_info->remnant_cck_swing_idx, rf_path);
133
134 if (dm->number_linked_client != 0)
135 tx_power_index = odm_get_tx_power_index(
136 dm, (enum odm_rf_radio_path)rf_path, tx_rate,
137 band_width, channel);
138
139 if (tx_power_index >= 63)
140 tx_power_index = 63;
141
142 tx_power_index_offest = 63 - tx_power_index;
143
144 ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
145 "tx_power_index=%d tx_power_index_offest=%d rf_path=%d\n",
146 tx_power_index, tx_power_index_offest, rf_path);
147
148 if (method ==
149 BBSWING) { /*use for mp driver clean power tracking status*/
150 switch (rf_path) {
151 case ODM_RF_PATH_A:
152 odm_set_bb_reg(
153 dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) |
154 BIT(26) | BIT(25)),
155 cali_info->absolute_ofdm_swing_idx[rf_path]);
156 odm_set_bb_reg(
157 dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000,
158 tx_scaling_table_jaguar
159 [cali_info
160 ->bb_swing_idx_ofdm[rf_path]]);
161 break;
162 case ODM_RF_PATH_B:
163 odm_set_bb_reg(
164 dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) |
165 BIT(26) | BIT(25)),
166 cali_info->absolute_ofdm_swing_idx[rf_path]);
167 odm_set_bb_reg(
168 dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000,
169 tx_scaling_table_jaguar
170 [cali_info
171 ->bb_swing_idx_ofdm[rf_path]]);
172 break;
173
174 default:
175 break;
176 }
177 } else if (method == MIX_MODE) {
178 switch (rf_path) {
179 case ODM_RF_PATH_A:
180 get_mix_mode_tx_agc_bb_swing_offset_8822b(
181 dm, method, rf_path, tx_power_index_offest);
182 odm_set_bb_reg(
183 dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) |
184 BIT(26) | BIT(25)),
185 cali_info->absolute_ofdm_swing_idx[rf_path]);
186 odm_set_bb_reg(
187 dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000,
188 tx_scaling_table_jaguar
189 [cali_info
190 ->bb_swing_idx_ofdm[rf_path]]);
191
192 ODM_RT_TRACE(
193 dm, ODM_COMP_TX_PWR_TRACK,
194 "TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
195 odm_get_bb_reg(dm, 0xC94,
196 (BIT(29) | BIT(28) | BIT(27) |
197 BIT(26) | BIT(25))),
198 odm_get_bb_reg(dm, 0xc1c, 0xFFE00000),
199 cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
200 break;
201
202 case ODM_RF_PATH_B:
203 get_mix_mode_tx_agc_bb_swing_offset_8822b(
204 dm, method, rf_path, tx_power_index_offest);
205 odm_set_bb_reg(
206 dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) |
207 BIT(26) | BIT(25)),
208 cali_info->absolute_ofdm_swing_idx[rf_path]);
209 odm_set_bb_reg(
210 dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000,
211 tx_scaling_table_jaguar
212 [cali_info
213 ->bb_swing_idx_ofdm[rf_path]]);
214
215 ODM_RT_TRACE(
216 dm, ODM_COMP_TX_PWR_TRACK,
217 "TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
218 odm_get_bb_reg(dm, 0xE94,
219 (BIT(29) | BIT(28) | BIT(27) |
220 BIT(26) | BIT(25))),
221 odm_get_bb_reg(dm, 0xe1c, 0xFFE00000),
222 cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
223 break;
224
225 default:
226 break;
227 }
228 }
229}
230
231void get_delta_swing_table_8822b(void *dm_void, u8 **temperature_up_a,
232 u8 **temperature_down_a, u8 **temperature_up_b,
233 u8 **temperature_down_b)
234{
235 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
236 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
237
238 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
239 struct rtl_phy *rtlphy = &rtlpriv->phy;
240 u8 channel = rtlphy->current_channel;
241
242 *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
243 *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
244 *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
245 *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
246
247 if (channel >= 36 && channel <= 64) {
248 *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
249 *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
250 *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
251 *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
252 } else if (channel >= 100 && channel <= 144) {
253 *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
254 *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
255 *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
256 *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
257 } else if (channel >= 149 && channel <= 177) {
258 *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
259 *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
260 *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
261 *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
262 }
263}
264
265static void _phy_lc_calibrate_8822b(struct phy_dm_struct *dm)
266{
267 u32 lc_cal = 0, cnt = 0;
268
269 /*backup RF0x18*/
270 lc_cal = odm_get_rf_reg(dm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
271
272 /*Start LCK*/
273 odm_set_rf_reg(dm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK,
274 lc_cal | 0x08000);
275
276 ODM_delay_ms(100);
277
278 for (cnt = 0; cnt < 100; cnt++) {
279 if (odm_get_rf_reg(dm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
280 break;
281 ODM_delay_ms(10);
282 }
283
284 /*Recover channel number*/
285 odm_set_rf_reg(dm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
286}
287
288void phy_lc_calibrate_8822b(void *dm_void)
289{
290 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
291 bool is_start_cont_tx = false, is_single_tone = false,
292 is_carrier_suppression = false;
293 u64 start_time;
294 u64 progressing_time;
295
296 if (is_start_cont_tx || is_single_tone || is_carrier_suppression) {
297 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
298 "[LCK]continues TX ing !!! LCK return\n");
299 return;
300 }
301
302 start_time = odm_get_current_time(dm);
303 _phy_lc_calibrate_8822b(dm);
304 progressing_time = odm_get_progressing_time(dm, start_time);
305 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
306 "[LCK]LCK progressing_time = %lld\n", progressing_time);
307}
308
309void configure_txpower_track_8822b(struct txpwrtrack_cfg *config)
310{
311 config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
312 config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
313 config->threshold_iqk = IQK_THRESHOLD;
314 config->threshold_dpk = DPK_THRESHOLD;
315 config->average_thermal_num = AVG_THERMAL_NUM_8822B;
316 config->rf_path_count = MAX_PATH_NUM_8822B;
317 config->thermal_reg_addr = RF_T_METER_8822B;
318
319 config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8822b;
320 config->do_iqk = do_iqk_8822b;
321 config->phy_lc_calibrate = phy_lc_calibrate_8822b;
322
323 config->get_delta_swing_table = get_delta_swing_table_8822b;
324}
325
326void phy_set_rf_path_switch_8822b(struct phy_dm_struct *dm, bool is_main)
327{
328 /*BY SY Request */
329 odm_set_bb_reg(dm, 0x4C, (BIT(24) | BIT(23)), 0x2);
330 odm_set_bb_reg(dm, 0x974, 0xff, 0xff);
331
332 /*odm_set_bb_reg(dm, 0x1991, 0x3, 0x0);*/
333 odm_set_bb_reg(dm, 0x1990, (BIT(9) | BIT(8)), 0x0);
334
335 /*odm_set_bb_reg(dm, 0xCBE, 0x8, 0x0);*/
336 odm_set_bb_reg(dm, 0xCBC, BIT(19), 0x0);
337
338 odm_set_bb_reg(dm, 0xCB4, 0xff, 0x77);
339
340 odm_set_bb_reg(dm, 0x70, MASKBYTE3, 0x0e);
341 odm_set_bb_reg(dm, 0x1704, MASKDWORD, 0x0000ff00);
342 odm_set_bb_reg(dm, 0x1700, MASKDWORD, 0xc00f0038);
343
344 if (is_main) {
345 /*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x2); WiFi */
346 odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x2); /*WiFi */
347 } else {
348 /*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x1); BT*/
349 odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x1); /*BT*/
350 }
351}
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/halphyrf_8822b.h b/drivers/staging/rtlwifi/phydm/rtl8822b/halphyrf_8822b.h
new file mode 100644
index 000000000000..4f3bfe316ee9
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/halphyrf_8822b.h
@@ -0,0 +1,45 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __HAL_PHY_RF_8822B_H__
27#define __HAL_PHY_RF_8822B_H__
28
29#define AVG_THERMAL_NUM_8822B 4
30#define RF_T_METER_8822B 0x42
31
32void configure_txpower_track_8822b(struct txpwrtrack_cfg *config);
33
34void odm_tx_pwr_track_set_pwr8822b(void *dm_void, enum pwrtrack_method method,
35 u8 rf_path, u8 channel_mapped_index);
36
37void get_delta_swing_table_8822b(void *dm_void, u8 **temperature_up_a,
38 u8 **temperature_down_a, u8 **temperature_up_b,
39 u8 **temperature_down_b);
40
41void phy_lc_calibrate_8822b(void *dm_void);
42
43void phy_set_rf_path_switch_8822b(struct phy_dm_struct *dm, bool is_main);
44
45#endif /* #ifndef __HAL_PHY_RF_8822B_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_hal_api8822b.c b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_hal_api8822b.c
new file mode 100644
index 000000000000..26d1022e851c
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_hal_api8822b.c
@@ -0,0 +1,1815 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../mp_precomp.h"
27#include "../phydm_precomp.h"
28
29/* ======================================================================== */
30/* These following functions can be used for PHY DM only*/
31
32static u32 reg82c_8822b;
33static u32 reg838_8822b;
34static u32 reg830_8822b;
35static u32 reg83c_8822b;
36static u32 rega20_8822b;
37static u32 rega24_8822b;
38static u32 rega28_8822b;
39static enum odm_bw bw_8822b;
40static u8 central_ch_8822b;
41
42static u32 cca_ifem_ccut[12][4] = {
43 /*20M*/
44 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
45 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
46 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/
47 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
48 /*40M*/
49 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
50 {0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
51 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
52 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
53 /*80M*/
54 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
55 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
56 {0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/
57 {0x00000000, 0x00000000, 0x00000000, 0x00000000},
58}; /*Reg83C*/
59static u32 cca_efem_ccut[12][4] = {
60 /*20M*/
61 {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/
62 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
63 {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
64 {0x9194b2b9, 0x9194b2b9, 0x9194b2b9, 0x9194b2b9}, /*Reg83C*/
65 /*40M*/
66 {0x75A85010, 0x75A75010, 0x75A85010, 0x75A75010}, /*Reg82C*/
67 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
68 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
69 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
70 /*80M*/
71 {0x76BA7010, 0x75BA7010, 0x76BA7010, 0x75BA7010}, /*Reg82C*/
72 {0x79a0ea28, 0x00000000, 0x79a0ea28, 0x00000000}, /*Reg830*/
73 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
74 {0x00000000, 0x00000000, 0x00000000, 0x00000000},
75}; /*Reg83C*/
76static u32 cca_ifem_ccut_rfetype5[12][4] = {
77 /*20M*/
78 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
79 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
80 {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
81 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
82 /*40M*/
83 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
84 {0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
85 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
86 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
87 /*80M*/
88 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
89 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
90 {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
91 {0x00000000, 0x00000000, 0x00000000, 0x00000000},
92}; /*Reg83C*/
93static u32 cca_ifem_ccut_rfetype3[12][4] = {
94 /*20M*/
95 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
96 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
97 {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
98 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
99 /*40M*/
100 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
101 {0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
102 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
103 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
104 /*80M*/
105 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
106 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
107 {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
108 {0x00000000, 0x00000000, 0x00000000, 0x00000000},
109}; /*Reg83C*/
110
111static inline u32 phydm_check_bit_mask(u32 bit_mask, u32 data_original,
112 u32 data)
113{
114 u8 bit_shift;
115
116 if (bit_mask != 0xfffff) {
117 for (bit_shift = 0; bit_shift <= 19; bit_shift++) {
118 if (((bit_mask >> bit_shift) & 0x1) == 1)
119 break;
120 }
121 return ((data_original) & (~bit_mask)) | (data << bit_shift);
122 }
123 return data;
124}
125
126static bool phydm_rfe_8822b(struct phy_dm_struct *dm, u8 channel)
127{
128 if (dm->rfe_type == 4) {
129 /* Default setting is in PHY parameters */
130
131 if (channel <= 14) {
132 /* signal source */
133 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
134 0x745774);
135 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
136 0x745774);
137 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
138 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
139
140 /* inverse or not */
141 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
142 BIT(2) | BIT(1) | BIT(0)),
143 0x8);
144 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x2);
145 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
146 BIT(2) | BIT(1) | BIT(0)),
147 0x8);
148 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x2);
149
150 /* antenna switch table */
151 if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
152 (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
153 /* 2TX or 2RX */
154 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf050);
155 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf050);
156 } else if (dm->rx_ant_status == dm->tx_ant_status) {
157 /* TXA+RXA or TXB+RXB */
158 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf055);
159 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf055);
160 } else {
161 /* TXB+RXA or TXA+RXB */
162 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf550);
163 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf550);
164 }
165
166 } else if (channel > 35) {
167 /* signal source */
168 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
169 0x477547);
170 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
171 0x477547);
172 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
173 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
174
175 /* inverse or not */
176 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
177 BIT(2) | BIT(1) | BIT(0)),
178 0x0);
179 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
180 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
181 BIT(2) | BIT(1) | BIT(0)),
182 0x0);
183 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
184
185 /* antenna switch table */
186 if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
187 (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
188 /* 2TX or 2RX */
189 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
190 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
191 } else if (dm->rx_ant_status == dm->tx_ant_status) {
192 /* TXA+RXA or TXB+RXB */
193 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
194 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
195 } else {
196 /* TXB+RXA or TXA+RXB */
197 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
198 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
199 }
200 } else {
201 return false;
202 }
203
204 } else if ((dm->rfe_type == 1) || (dm->rfe_type == 2) ||
205 (dm->rfe_type == 7) || (dm->rfe_type == 9)) {
206 /* eFem */
207 if (((dm->cut_version == ODM_CUT_A) ||
208 (dm->cut_version == ODM_CUT_B)) &&
209 (dm->rfe_type < 2)) {
210 if (channel <= 14) {
211 /* signal source */
212 odm_set_bb_reg(dm, 0xcb0,
213 (MASKBYTE2 | MASKLWORD),
214 0x704570);
215 odm_set_bb_reg(dm, 0xeb0,
216 (MASKBYTE2 | MASKLWORD),
217 0x704570);
218 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45);
219 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45);
220 } else if (channel > 35) {
221 odm_set_bb_reg(dm, 0xcb0,
222 (MASKBYTE2 | MASKLWORD),
223 0x174517);
224 odm_set_bb_reg(dm, 0xeb0,
225 (MASKBYTE2 | MASKLWORD),
226 0x174517);
227 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45);
228 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45);
229 } else {
230 return false;
231 }
232
233 /* delay 400ns for PAPE */
234 odm_set_bb_reg(dm, 0x810,
235 MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) |
236 BIT(23),
237 0x211);
238
239 /* antenna switch table */
240 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa555);
241 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa555);
242
243 /* inverse or not */
244 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
245 BIT(2) | BIT(1) | BIT(0)),
246 0x0);
247 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
248 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
249 BIT(2) | BIT(1) | BIT(0)),
250 0x0);
251 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
252
253 ODM_RT_TRACE(
254 dm, ODM_PHY_CONFIG,
255 "%s: Using old RFE control pin setting for A-cut and B-cut\n",
256 __func__);
257 } else {
258 if (channel <= 14) {
259 /* signal source */
260 odm_set_bb_reg(dm, 0xcb0,
261 (MASKBYTE2 | MASKLWORD),
262 0x705770);
263 odm_set_bb_reg(dm, 0xeb0,
264 (MASKBYTE2 | MASKLWORD),
265 0x705770);
266 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
267 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
268 odm_set_bb_reg(dm, 0xcb8, BIT(4), 0);
269 odm_set_bb_reg(dm, 0xeb8, BIT(4), 0);
270 } else if (channel > 35) {
271 /* signal source */
272 odm_set_bb_reg(dm, 0xcb0,
273 (MASKBYTE2 | MASKLWORD),
274 0x177517);
275 odm_set_bb_reg(dm, 0xeb0,
276 (MASKBYTE2 | MASKLWORD),
277 0x177517);
278 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
279 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
280 odm_set_bb_reg(dm, 0xcb8, BIT(5), 0);
281 odm_set_bb_reg(dm, 0xeb8, BIT(5), 0);
282 } else {
283 return false;
284 }
285
286 /* inverse or not */
287 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
288 BIT(2) | BIT(1) | BIT(0)),
289 0x0);
290 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
291 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
292 BIT(2) | BIT(1) | BIT(0)),
293 0x0);
294 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
295
296 /* antenna switch table */
297 if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
298 (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
299 /* 2TX or 2RX */
300 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
301 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
302 } else if (dm->rx_ant_status == dm->tx_ant_status) {
303 /* TXA+RXA or TXB+RXB */
304 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
305 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
306 } else {
307 /* TXB+RXA or TXA+RXB */
308 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
309 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
310 }
311 }
312 } else if ((dm->rfe_type == 0) || (dm->rfe_type == 3) ||
313 (dm->rfe_type == 5) || (dm->rfe_type == 6) ||
314 (dm->rfe_type == 8) || (dm->rfe_type == 10)) {
315 /* iFEM */
316 if (channel <= 14) {
317 /* signal source */
318
319 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
320 0x745774);
321 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
322 0x745774);
323 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
324 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
325
326 } else if (channel > 35) {
327 /* signal source */
328
329 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
330 0x477547);
331 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
332 0x477547);
333 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
334 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
335
336 } else {
337 return false;
338 }
339
340 /* inverse or not */
341 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) |
342 BIT(1) | BIT(0)),
343 0x0);
344 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
345 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) |
346 BIT(1) | BIT(0)),
347 0x0);
348 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
349
350 /* antenna switch table */
351 if (channel <= 14) {
352 if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
353 (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
354 /* 2TX or 2RX */
355 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
356 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
357 } else if (dm->rx_ant_status == dm->tx_ant_status) {
358 /* TXA+RXA or TXB+RXB */
359 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
360 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
361 } else {
362 /* TXB+RXA or TXA+RXB */
363 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
364 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
365 }
366 } else if (channel > 35) {
367 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa5a5);
368 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa5a5);
369 }
370 }
371
372 /* chip top mux */
373 odm_set_bb_reg(dm, 0x64, BIT(29) | BIT(28), 0x3);
374 odm_set_bb_reg(dm, 0x4c, BIT(26) | BIT(25), 0x0);
375 odm_set_bb_reg(dm, 0x40, BIT(2), 0x1);
376
377 /* from s0 or s1 */
378 odm_set_bb_reg(dm, 0x1990,
379 (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
380 0x30);
381 odm_set_bb_reg(dm, 0x1990, (BIT(11) | BIT(10)), 0x3);
382
383 /* input or output */
384 odm_set_bb_reg(dm, 0x974,
385 (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
386 0x3f);
387 odm_set_bb_reg(dm, 0x974, (BIT(11) | BIT(10)), 0x3);
388
389 ODM_RT_TRACE(
390 dm, ODM_PHY_CONFIG,
391 "%s: Update RFE control pin setting (ch%d, tx_path 0x%x, rx_path 0x%x)\n",
392 __func__, channel, dm->tx_ant_status, dm->rx_ant_status);
393
394 return true;
395}
396
397static void phydm_ccapar_by_rfe_8822b(struct phy_dm_struct *dm)
398{
399 u32 cca_ifem[12][4], cca_efem[12][4];
400 u8 row, col;
401 u32 reg82c, reg830, reg838, reg83c;
402
403 if (dm->cut_version == ODM_CUT_A)
404 return;
405 {
406 odm_move_memory(dm, cca_efem, cca_efem_ccut, 48 * 4);
407 if (dm->rfe_type == 5)
408 odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfetype5,
409 48 * 4);
410 else if (dm->rfe_type == 3)
411 odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfetype3,
412 48 * 4);
413 else
414 odm_move_memory(dm, cca_ifem, cca_ifem_ccut, 48 * 4);
415
416 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
417 "%s: Update CCA parameters for Ccut\n", __func__);
418 }
419
420 if (bw_8822b == ODM_BW20M)
421 row = 0;
422 else if (bw_8822b == ODM_BW40M)
423 row = 4;
424 else
425 row = 8;
426
427 if (central_ch_8822b <= 14) {
428 if ((dm->rx_ant_status == ODM_RF_A) ||
429 (dm->rx_ant_status == ODM_RF_B))
430 col = 0;
431 else
432 col = 1;
433 } else {
434 if ((dm->rx_ant_status == ODM_RF_A) ||
435 (dm->rx_ant_status == ODM_RF_B))
436 col = 2;
437 else
438 col = 3;
439 }
440
441 if ((dm->rfe_type == 1) || (dm->rfe_type == 4) || (dm->rfe_type == 6) ||
442 (dm->rfe_type == 7)) {
443 /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7*/
444 reg82c = (cca_efem[row][col] != 0) ? cca_efem[row][col] :
445 reg82c_8822b;
446 reg830 = (cca_efem[row + 1][col] != 0) ?
447 cca_efem[row + 1][col] :
448 reg830_8822b;
449 reg838 = (cca_efem[row + 2][col] != 0) ?
450 cca_efem[row + 2][col] :
451 reg838_8822b;
452 reg83c = (cca_efem[row + 3][col] != 0) ?
453 cca_efem[row + 3][col] :
454 reg83c_8822b;
455 } else if ((dm->rfe_type == 2) || (dm->rfe_type == 9)) {
456 /*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */
457 if (central_ch_8822b <= 14) {
458 reg82c = (cca_ifem[row][col] != 0) ?
459 cca_ifem[row][col] :
460 reg82c_8822b;
461 reg830 = (cca_ifem[row + 1][col] != 0) ?
462 cca_ifem[row + 1][col] :
463 reg830_8822b;
464 reg838 = (cca_ifem[row + 2][col] != 0) ?
465 cca_ifem[row + 2][col] :
466 reg838_8822b;
467 reg83c = (cca_ifem[row + 3][col] != 0) ?
468 cca_ifem[row + 3][col] :
469 reg83c_8822b;
470 } else {
471 reg82c = (cca_efem[row][col] != 0) ?
472 cca_efem[row][col] :
473 reg82c_8822b;
474 reg830 = (cca_efem[row + 1][col] != 0) ?
475 cca_efem[row + 1][col] :
476 reg830_8822b;
477 reg838 = (cca_efem[row + 2][col] != 0) ?
478 cca_efem[row + 2][col] :
479 reg838_8822b;
480 reg83c = (cca_efem[row + 3][col] != 0) ?
481 cca_efem[row + 3][col] :
482 reg83c_8822b;
483 }
484 } else {
485 /* iFEM =>RFE type 3 & RFE type 5 & RFE type 0 & RFE type 8 &
486 * RFE type 10
487 */
488 reg82c = (cca_ifem[row][col] != 0) ? cca_ifem[row][col] :
489 reg82c_8822b;
490 reg830 = (cca_ifem[row + 1][col] != 0) ?
491 cca_ifem[row + 1][col] :
492 reg830_8822b;
493 reg838 = (cca_ifem[row + 2][col] != 0) ?
494 cca_ifem[row + 2][col] :
495 reg838_8822b;
496 reg83c = (cca_ifem[row + 3][col] != 0) ?
497 cca_ifem[row + 3][col] :
498 reg83c_8822b;
499 }
500
501 odm_set_bb_reg(dm, 0x82c, MASKDWORD, reg82c);
502 odm_set_bb_reg(dm, 0x830, MASKDWORD, reg830);
503 odm_set_bb_reg(dm, 0x838, MASKDWORD, reg838);
504 odm_set_bb_reg(dm, 0x83c, MASKDWORD, reg83c);
505 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
506 "%s: (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n",
507 __func__, dm->package_type, dm->support_interface,
508 dm->rfe_type, row, col);
509}
510
511static void phydm_ccapar_by_bw_8822b(struct phy_dm_struct *dm,
512 enum odm_bw bandwidth)
513{
514 u32 reg82c;
515
516 if (dm->cut_version != ODM_CUT_A)
517 return;
518
519 /* A-cut */
520 reg82c = odm_get_bb_reg(dm, 0x82c, MASKDWORD);
521
522 if (bandwidth == ODM_BW20M) {
523 /* 82c[15:12] = 4 */
524 /* 82c[27:24] = 6 */
525
526 reg82c &= (~(0x0f00f000));
527 reg82c |= ((0x4) << 12);
528 reg82c |= ((0x6) << 24);
529 } else if (bandwidth == ODM_BW40M) {
530 /* 82c[19:16] = 9 */
531 /* 82c[27:24] = 6 */
532
533 reg82c &= (~(0x0f0f0000));
534 reg82c |= ((0x9) << 16);
535 reg82c |= ((0x6) << 24);
536 } else if (bandwidth == ODM_BW80M) {
537 /* 82c[15:12] 7 */
538 /* 82c[19:16] b */
539 /* 82c[23:20] d */
540 /* 82c[27:24] 3 */
541
542 reg82c &= (~(0x0ffff000));
543 reg82c |= ((0xdb7) << 12);
544 reg82c |= ((0x3) << 24);
545 }
546
547 odm_set_bb_reg(dm, 0x82c, MASKDWORD, reg82c);
548 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
549 "%s(): Update CCA parameters for Acut\n", __func__);
550}
551
552static void phydm_ccapar_by_rxpath_8822b(struct phy_dm_struct *dm)
553{
554 if (dm->cut_version != ODM_CUT_A)
555 return;
556
557 if ((dm->rx_ant_status == ODM_RF_A) ||
558 (dm->rx_ant_status == ODM_RF_B)) {
559 /* 838[7:4] = 8 */
560 /* 838[11:8] = 7 */
561 /* 838[15:12] = 6 */
562 /* 838[19:16] = 7 */
563 /* 838[23:20] = 7 */
564 /* 838[27:24] = 7 */
565 odm_set_bb_reg(dm, 0x838, 0x0ffffff0, 0x777678);
566 } else {
567 /* 838[7:4] = 3 */
568 /* 838[11:8] = 3 */
569 /* 838[15:12] = 6 */
570 /* 838[19:16] = 6 */
571 /* 838[23:20] = 7 */
572 /* 838[27:24] = 7 */
573 odm_set_bb_reg(dm, 0x838, 0x0ffffff0, 0x776633);
574 }
575 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
576 "%s(): Update CCA parameters for Acut\n", __func__);
577}
578
579static void phydm_rxdfirpar_by_bw_8822b(struct phy_dm_struct *dm,
580 enum odm_bw bandwidth)
581{
582 if (bandwidth == ODM_BW40M) {
583 /* RX DFIR for BW40 */
584 odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x1);
585 odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x0);
586 odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0);
587 odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0);
588 } else if (bandwidth == ODM_BW80M) {
589 /* RX DFIR for BW80 */
590 odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2);
591 odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x1);
592 odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0);
593 odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0);
594 } else {
595 /* RX DFIR for BW20, BW10 and BW5*/
596 odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2);
597 odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x2);
598 odm_set_bb_reg(dm, 0xc20, BIT(31), 0x1);
599 odm_set_bb_reg(dm, 0xe20, BIT(31), 0x1);
600 }
601}
602
603bool phydm_write_txagc_1byte_8822b(struct phy_dm_struct *dm, u32 power_index,
604 enum odm_rf_radio_path path, u8 hw_rate)
605{
606 u32 offset_txagc[2] = {0x1d00, 0x1d80};
607 u8 rate_idx = (hw_rate & 0xfc), i;
608 u8 rate_offset = (hw_rate & 0x3);
609 u32 txagc_content = 0x0;
610
611 /* For debug command only!!!! */
612
613 /* Error handling */
614 if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
615 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
616 "%s(): unsupported path (%d)\n", __func__, path);
617 return false;
618 }
619
620 /* For HW limitation, We can't write TXAGC once a byte. */
621 for (i = 0; i < 4; i++) {
622 if (i != rate_offset)
623 txagc_content =
624 txagc_content | (config_phydm_read_txagc_8822b(
625 dm, path, rate_idx + i)
626 << (i << 3));
627 else
628 txagc_content = txagc_content |
629 ((power_index & 0x3f) << (i << 3));
630 }
631 odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD,
632 txagc_content);
633
634 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
635 "%s(): path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
636 path, hw_rate, (offset_txagc[path] + hw_rate),
637 power_index);
638 return true;
639}
640
641void phydm_init_hw_info_by_rfe_type_8822b(struct phy_dm_struct *dm)
642{
643 u16 mask_path_a = 0x0303;
644 u16 mask_path_b = 0x0c0c;
645 /*u16 mask_path_c = 0x3030;*/
646 /*u16 mask_path_d = 0xc0c0;*/
647
648 dm->is_init_hw_info_by_rfe = false;
649
650 if ((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7)) {
651 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
652 (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G |
653 ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G));
654
655 if (dm->rfe_type == 6) {
656 odm_cmn_info_init(
657 dm, ODM_CMNINFO_GPA,
658 (TYPE_GPA1 & (mask_path_a | mask_path_b)));
659 odm_cmn_info_init(
660 dm, ODM_CMNINFO_APA,
661 (TYPE_APA1 & (mask_path_a | mask_path_b)));
662 odm_cmn_info_init(
663 dm, ODM_CMNINFO_GLNA,
664 (TYPE_GLNA1 & (mask_path_a | mask_path_b)));
665 odm_cmn_info_init(
666 dm, ODM_CMNINFO_ALNA,
667 (TYPE_ALNA1 & (mask_path_a | mask_path_b)));
668 } else if (dm->rfe_type == 7) {
669 odm_cmn_info_init(
670 dm, ODM_CMNINFO_GPA,
671 (TYPE_GPA2 & (mask_path_a | mask_path_b)));
672 odm_cmn_info_init(
673 dm, ODM_CMNINFO_APA,
674 (TYPE_APA2 & (mask_path_a | mask_path_b)));
675 odm_cmn_info_init(
676 dm, ODM_CMNINFO_GLNA,
677 (TYPE_GLNA2 & (mask_path_a | mask_path_b)));
678 odm_cmn_info_init(
679 dm, ODM_CMNINFO_ALNA,
680 (TYPE_ALNA2 & (mask_path_a | mask_path_b)));
681 } else {
682 odm_cmn_info_init(
683 dm, ODM_CMNINFO_GPA,
684 (TYPE_GPA0 & (mask_path_a | mask_path_b)));
685 odm_cmn_info_init(
686 dm, ODM_CMNINFO_APA,
687 (TYPE_APA0 & (mask_path_a | mask_path_b)));
688 odm_cmn_info_init(
689 dm, ODM_CMNINFO_GLNA,
690 (TYPE_GLNA0 & (mask_path_a | mask_path_b)));
691 odm_cmn_info_init(
692 dm, ODM_CMNINFO_ALNA,
693 (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
694 }
695
696 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
697
698 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true);
699 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
700 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true);
701 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
702 } else if (dm->rfe_type == 2) {
703 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
704 (ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA_5G));
705 odm_cmn_info_init(dm, ODM_CMNINFO_APA,
706 (TYPE_APA0 & (mask_path_a | mask_path_b)));
707 odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
708 (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
709
710 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
711
712 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
713 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
714 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
715 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
716 } else if (dm->rfe_type == 9) {
717 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
718 (ODM_BOARD_EXT_LNA_5G));
719 odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
720 (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
721
722 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
723
724 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
725 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
726 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
727 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
728 } else if ((dm->rfe_type == 3) || (dm->rfe_type == 5)) {
729 /* RFE type 3: 8822BS\8822BU TFBGA iFEM */
730 /* RFE type 5: 8822BE TFBGA iFEM */
731 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
732
733 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
734
735 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
736 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
737 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
738 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
739 } else if (dm->rfe_type == 4) {
740 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
741 (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G |
742 ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G));
743 odm_cmn_info_init(dm, ODM_CMNINFO_GPA,
744 (TYPE_GPA0 & (mask_path_a | mask_path_b)));
745 odm_cmn_info_init(dm, ODM_CMNINFO_APA,
746 (TYPE_APA0 & (mask_path_a | mask_path_b)));
747 odm_cmn_info_init(dm, ODM_CMNINFO_GLNA,
748 (TYPE_GLNA0 & (mask_path_a | mask_path_b)));
749 odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
750 (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
751
752 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
753
754 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true);
755 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
756 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true);
757 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
758 } else if (dm->rfe_type == 8) {
759 /* RFE type 8: TFBGA iFEM AP */
760 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
761
762 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
763
764 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
765 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
766 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
767 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
768 } else {
769 /* RFE Type 0 & 9 & 10: QFN iFEM */
770 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
771
772 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
773
774 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
775 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
776 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
777 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
778 }
779
780 dm->is_init_hw_info_by_rfe = true;
781
782 ODM_RT_TRACE(
783 dm, ODM_PHY_CONFIG,
784 "%s(): RFE type (%d), Board type (0x%x), Package type (%d)\n",
785 __func__, dm->rfe_type, dm->board_type, dm->package_type);
786 ODM_RT_TRACE(
787 dm, ODM_PHY_CONFIG,
788 "%s(): 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n",
789 __func__, dm->ext_pa_5g, dm->ext_lna_5g, dm->ext_pa,
790 dm->ext_lna);
791 ODM_RT_TRACE(
792 dm, ODM_PHY_CONFIG,
793 "%s(): 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n",
794 __func__, dm->type_apa, dm->type_alna, dm->type_gpa,
795 dm->type_glna);
796}
797
798s32 phydm_get_condition_number_8822B(struct phy_dm_struct *dm)
799{
800 s32 ret_val;
801
802 odm_set_bb_reg(dm, 0x1988, BIT(22), 0x1);
803 ret_val =
804 (s32)odm_get_bb_reg(dm, 0xf84, (BIT(17) | BIT(16) | MASKLWORD));
805
806 if (bw_8822b == 0) {
807 ret_val = ret_val << (8 - 4);
808 ret_val = ret_val / 234;
809 } else if (bw_8822b == 1) {
810 ret_val = ret_val << (7 - 4);
811 ret_val = ret_val / 108;
812 } else if (bw_8822b == 2) {
813 ret_val = ret_val << (6 - 4);
814 ret_val = ret_val / 52;
815 }
816
817 return ret_val;
818}
819
820/* ======================================================================== */
821
822/* ======================================================================== */
823/* These following functions can be used by driver*/
824
825u32 config_phydm_read_rf_reg_8822b(struct phy_dm_struct *dm,
826 enum odm_rf_radio_path rf_path, u32 reg_addr,
827 u32 bit_mask)
828{
829 u32 readback_value, direct_addr;
830 u32 offset_read_rf[2] = {0x2800, 0x2c00};
831 u32 power_RF[2] = {0x1c, 0xec};
832
833 /* Error handling.*/
834 if (rf_path > ODM_RF_PATH_B) {
835 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
836 "%s(): unsupported path (%d)\n", __func__,
837 rf_path);
838 return INVALID_RF_DATA;
839 }
840
841 /* Error handling. Check if RF power is enable or not */
842 /* 0xffffffff means RF power is disable */
843 if (odm_get_mac_reg(dm, power_RF[rf_path], MASKBYTE3) != 0x7) {
844 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
845 "%s(): Read fail, RF is disabled\n", __func__);
846 return INVALID_RF_DATA;
847 }
848
849 /* Calculate offset */
850 reg_addr &= 0xff;
851 direct_addr = offset_read_rf[rf_path] + (reg_addr << 2);
852
853 /* RF register only has 20bits */
854 bit_mask &= RFREGOFFSETMASK;
855
856 /* Read RF register directly */
857 readback_value = odm_get_bb_reg(dm, direct_addr, bit_mask);
858 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
859 "%s(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", __func__,
860 rf_path, reg_addr, readback_value, bit_mask);
861 return readback_value;
862}
863
864bool config_phydm_write_rf_reg_8822b(struct phy_dm_struct *dm,
865 enum odm_rf_radio_path rf_path,
866 u32 reg_addr, u32 bit_mask, u32 data)
867{
868 u32 data_and_addr = 0, data_original = 0;
869 u32 offset_write_rf[2] = {0xc90, 0xe90};
870 u32 power_RF[2] = {0x1c, 0xec};
871
872 /* Error handling.*/
873 if (rf_path > ODM_RF_PATH_B) {
874 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
875 "%s(): unsupported path (%d)\n", __func__,
876 rf_path);
877 return false;
878 }
879
880 /* Read RF register content first */
881 reg_addr &= 0xff;
882 bit_mask = bit_mask & RFREGOFFSETMASK;
883
884 if (bit_mask != RFREGOFFSETMASK) {
885 data_original = config_phydm_read_rf_reg_8822b(
886 dm, rf_path, reg_addr, RFREGOFFSETMASK);
887
888 /* Error handling. RF is disabled */
889 if (!config_phydm_read_rf_check_8822b(data_original)) {
890 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
891 "%s(): Write fail, RF is disable\n",
892 __func__);
893 return false;
894 }
895
896 /* check bit mask */
897 data = phydm_check_bit_mask(bit_mask, data_original, data);
898 } else if (odm_get_mac_reg(dm, power_RF[rf_path], MASKBYTE3) != 0x7) {
899 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
900 "%s(): Write fail, RF is disabled\n", __func__);
901 return false;
902 }
903
904 /* Put write addr in [27:20] and write data in [19:00] */
905 data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
906
907 /* Write operation */
908 odm_set_bb_reg(dm, offset_write_rf[rf_path], MASKDWORD, data_and_addr);
909 ODM_RT_TRACE(
910 dm, ODM_PHY_CONFIG,
911 "%s(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n",
912 __func__, rf_path, reg_addr, data, data_original, bit_mask);
913 return true;
914}
915
916bool config_phydm_write_txagc_8822b(struct phy_dm_struct *dm, u32 power_index,
917 enum odm_rf_radio_path path, u8 hw_rate)
918{
919 u32 offset_txagc[2] = {0x1d00, 0x1d80};
920 u8 rate_idx = (hw_rate & 0xfc);
921
922 /* Input need to be HW rate index, not driver rate index!!!! */
923
924 if (dm->is_disable_phy_api) {
925 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
926 "%s(): disable PHY API for debug!!\n", __func__);
927 return true;
928 }
929
930 /* Error handling */
931 if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
932 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
933 "%s(): unsupported path (%d)\n", __func__, path);
934 return false;
935 }
936
937 /* driver need to construct a 4-byte power index */
938 odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD,
939 power_index);
940
941 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
942 "%s(): path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
943 path, hw_rate, (offset_txagc[path] + hw_rate),
944 power_index);
945 return true;
946}
947
948u8 config_phydm_read_txagc_8822b(struct phy_dm_struct *dm,
949 enum odm_rf_radio_path path, u8 hw_rate)
950{
951 u8 read_back_data;
952
953 /* Input need to be HW rate index, not driver rate index!!!! */
954
955 /* Error handling */
956 if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
957 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
958 "%s(): unsupported path (%d)\n", __func__, path);
959 return INVALID_TXAGC_DATA;
960 }
961
962 /* Disable TX AGC report */
963 odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0); /* need to check */
964
965 /* Set data rate index (bit0~6) and path index (bit7) */
966 odm_set_bb_reg(dm, 0x1998, MASKBYTE0, (hw_rate | (path << 7)));
967
968 /* Enable TXAGC report */
969 odm_set_bb_reg(dm, 0x1998, BIT(16), 0x1);
970
971 /* Read TX AGC report */
972 read_back_data = (u8)odm_get_bb_reg(dm, 0xd30, 0x7f0000);
973
974 /* Driver have to disable TXAGC report after reading TXAGC
975 * (ref. user guide v11)
976 */
977 odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0);
978
979 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
980 "%s(): path-%d rate index 0x%x = 0x%x\n", __func__, path,
981 hw_rate, read_back_data);
982 return read_back_data;
983}
984
985bool config_phydm_switch_band_8822b(struct phy_dm_struct *dm, u8 central_ch)
986{
987 u32 rf_reg18;
988 bool rf_reg_status = true;
989
990 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()======================>\n",
991 __func__);
992
993 if (dm->is_disable_phy_api) {
994 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
995 "%s(): disable PHY API for debug!!\n", __func__);
996 return true;
997 }
998
999 rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
1000 RFREGOFFSETMASK);
1001 rf_reg_status =
1002 rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
1003
1004 if (central_ch <= 14) {
1005 /* 2.4G */
1006
1007 /* Enable CCK block */
1008 odm_set_bb_reg(dm, 0x808, BIT(28), 0x1);
1009
1010 /* Disable MAC CCK check */
1011 odm_set_bb_reg(dm, 0x454, BIT(7), 0x0);
1012
1013 /* Disable BB CCK check */
1014 odm_set_bb_reg(dm, 0xa80, BIT(18), 0x0);
1015
1016 /*CCA Mask*/
1017 odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/
1018
1019 /* RF band */
1020 rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
1021
1022 /* RxHP dynamic control */
1023 if ((dm->rfe_type == 2) || (dm->rfe_type == 3) ||
1024 (dm->rfe_type == 5)) {
1025 odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492);
1026 odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x29095612);
1027 }
1028
1029 } else if (central_ch > 35) {
1030 /* 5G */
1031
1032 /* Enable BB CCK check */
1033 odm_set_bb_reg(dm, 0xa80, BIT(18), 0x1);
1034
1035 /* Enable CCK check */
1036 odm_set_bb_reg(dm, 0x454, BIT(7), 0x1);
1037
1038 /* Disable CCK block */
1039 odm_set_bb_reg(dm, 0x808, BIT(28), 0x0);
1040
1041 /*CCA Mask*/
1042 odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/
1043
1044 /* RF band */
1045 rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
1046 rf_reg18 = (rf_reg18 | BIT(8) | BIT(16));
1047
1048 /* RxHP dynamic control */
1049 if ((dm->rfe_type == 2) || (dm->rfe_type == 3) ||
1050 (dm->rfe_type == 5)) {
1051 odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08100000);
1052 odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x21095612);
1053 }
1054
1055 } else {
1056 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1057 "%s(): Fail to switch band (ch: %d)\n", __func__,
1058 central_ch);
1059 return false;
1060 }
1061
1062 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1063 dm, ODM_RF_PATH_A, 0x18,
1064 RFREGOFFSETMASK, rf_reg18);
1065
1066 if (dm->rf_type > ODM_1T1R)
1067 rf_reg_status =
1068 rf_reg_status & config_phydm_write_rf_reg_8822b(
1069 dm, ODM_RF_PATH_B, 0x18,
1070 RFREGOFFSETMASK, rf_reg18);
1071
1072 if (!phydm_rfe_8822b(dm, central_ch))
1073 return false;
1074
1075 if (!rf_reg_status) {
1076 ODM_RT_TRACE(
1077 dm, ODM_PHY_CONFIG,
1078 "%s(): Fail to switch band (ch: %d), because writing RF register is fail\n",
1079 __func__, central_ch);
1080 return false;
1081 }
1082
1083 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1084 "%s(): Success to switch band (ch: %d)\n", __func__,
1085 central_ch);
1086 return true;
1087}
1088
1089bool config_phydm_switch_channel_8822b(struct phy_dm_struct *dm, u8 central_ch)
1090{
1091 struct dig_thres *dig_tab = &dm->dm_dig_table;
1092 u32 rf_reg18 = 0, rf_reg_b8 = 0, rf_reg_be = 0xff;
1093 bool rf_reg_status = true;
1094 u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff,
1095 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
1096 u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff,
1097 0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff,
1098 0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7};
1099 u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff,
1100 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
1101
1102 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()====================>\n",
1103 __func__);
1104
1105 if (dm->is_disable_phy_api) {
1106 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1107 "%s(): disable PHY API for debug!!\n", __func__);
1108 return true;
1109 }
1110
1111 central_ch_8822b = central_ch;
1112 rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
1113 RFREGOFFSETMASK);
1114 rf_reg_status =
1115 rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
1116 rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0)));
1117
1118 if (dm->cut_version == ODM_CUT_A) {
1119 rf_reg_b8 = config_phydm_read_rf_reg_8822b(
1120 dm, ODM_RF_PATH_A, 0xb8, RFREGOFFSETMASK);
1121 rf_reg_status = rf_reg_status &
1122 config_phydm_read_rf_check_8822b(rf_reg_b8);
1123 }
1124
1125 /* Switch band and channel */
1126 if (central_ch <= 14) {
1127 /* 2.4G */
1128
1129 /* 1. RF band and channel*/
1130 rf_reg18 = (rf_reg18 | central_ch);
1131
1132 /* 2. AGC table selection */
1133 odm_set_bb_reg(dm, 0x958, 0x1f, 0x0);
1134 dig_tab->agc_table_idx = 0x0;
1135
1136 /* 3. Set central frequency for clock offset tracking */
1137 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x96a);
1138
1139 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
1140 if (dm->cut_version == ODM_CUT_A)
1141 rf_reg_b8 = rf_reg_b8 | BIT(19);
1142
1143 /* CCK TX filter parameters */
1144 if (central_ch == 14) {
1145 odm_set_bb_reg(dm, 0xa20, MASKHWORD, 0x8488);
1146 odm_set_bb_reg(dm, 0xa24, MASKDWORD, 0x00006577);
1147 odm_set_bb_reg(dm, 0xa28, MASKLWORD, 0x0000);
1148 } else {
1149 odm_set_bb_reg(dm, 0xa20, MASKHWORD,
1150 (rega20_8822b >> 16));
1151 odm_set_bb_reg(dm, 0xa24, MASKDWORD, rega24_8822b);
1152 odm_set_bb_reg(dm, 0xa28, MASKLWORD,
1153 (rega28_8822b & MASKLWORD));
1154 }
1155
1156 } else if (central_ch > 35) {
1157 /* 5G */
1158
1159 /* 1. RF band and channel*/
1160 rf_reg18 = (rf_reg18 | central_ch);
1161
1162 /* 2. AGC table selection */
1163 if ((central_ch >= 36) && (central_ch <= 64)) {
1164 odm_set_bb_reg(dm, 0x958, 0x1f, 0x1);
1165 dig_tab->agc_table_idx = 0x1;
1166 } else if ((central_ch >= 100) && (central_ch <= 144)) {
1167 odm_set_bb_reg(dm, 0x958, 0x1f, 0x2);
1168 dig_tab->agc_table_idx = 0x2;
1169 } else if (central_ch >= 149) {
1170 odm_set_bb_reg(dm, 0x958, 0x1f, 0x3);
1171 dig_tab->agc_table_idx = 0x3;
1172 } else {
1173 ODM_RT_TRACE(
1174 dm, ODM_PHY_CONFIG,
1175 "%s(): Fail to switch channel (AGC) (ch: %d)\n",
1176 __func__, central_ch);
1177 return false;
1178 }
1179
1180 /* 3. Set central frequency for clock offset tracking */
1181 if ((central_ch >= 36) && (central_ch <= 48)) {
1182 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x494);
1183 } else if ((central_ch >= 52) && (central_ch <= 64)) {
1184 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x453);
1185 } else if ((central_ch >= 100) && (central_ch <= 116)) {
1186 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x452);
1187 } else if ((central_ch >= 118) && (central_ch <= 177)) {
1188 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x412);
1189 } else {
1190 ODM_RT_TRACE(
1191 dm, ODM_PHY_CONFIG,
1192 "%s(): Fail to switch channel (fc_area) (ch: %d)\n",
1193 __func__, central_ch);
1194 return false;
1195 }
1196
1197 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
1198 if (dm->cut_version == ODM_CUT_A) {
1199 if ((central_ch >= 57) && (central_ch <= 75))
1200 rf_reg_b8 = rf_reg_b8 & (~BIT(19));
1201 else
1202 rf_reg_b8 = rf_reg_b8 | BIT(19);
1203 }
1204 } else {
1205 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1206 "%s(): Fail to switch channel (ch: %d)\n",
1207 __func__, central_ch);
1208 return false;
1209 }
1210
1211 /* Modify IGI for MP driver to aviod PCIE interference */
1212 if (dm->mp_mode && ((dm->rfe_type == 3) || (dm->rfe_type == 5))) {
1213 if (central_ch == 14)
1214 odm_write_dig(dm, 0x26);
1215 else
1216 odm_write_dig(dm, 0x20);
1217 }
1218
1219 /* Modify the setting of register 0xBE to reduce phase noise */
1220 if (central_ch <= 14)
1221 rf_reg_be = 0x0;
1222 else if ((central_ch >= 36) && (central_ch <= 64))
1223 rf_reg_be = low_band[(central_ch - 36) >> 1];
1224 else if ((central_ch >= 100) && (central_ch <= 144))
1225 rf_reg_be = middle_band[(central_ch - 100) >> 1];
1226 else if ((central_ch >= 149) && (central_ch <= 177))
1227 rf_reg_be = high_band[(central_ch - 149) >> 1];
1228 else
1229 rf_reg_be = 0xff;
1230
1231 if (rf_reg_be != 0xff) {
1232 rf_reg_status =
1233 rf_reg_status & config_phydm_write_rf_reg_8822b(
1234 dm, ODM_RF_PATH_A, 0xbe,
1235 (BIT(17) | BIT(16) | BIT(15)),
1236 rf_reg_be);
1237 } else {
1238 ODM_RT_TRACE(
1239 dm, ODM_PHY_CONFIG,
1240 "%s(): Fail to switch channel (ch: %d, Phase noise)\n",
1241 __func__, central_ch);
1242 return false;
1243 }
1244
1245 /* Fix channel 144 issue, ask by RFSI Alvin*/
1246 /* 00 when freq < 5400; 01 when 5400<=freq<=5720; 10 when freq > 5720;
1247 * 2G don't care
1248 */
1249 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
1250 if (central_ch == 144) {
1251 rf_reg_status = rf_reg_status &
1252 config_phydm_write_rf_reg_8822b(
1253 dm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x1);
1254 rf_reg18 = (rf_reg18 | BIT(17));
1255 } else {
1256 rf_reg_status = rf_reg_status &
1257 config_phydm_write_rf_reg_8822b(
1258 dm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x0);
1259
1260 if (central_ch > 144)
1261 rf_reg18 = (rf_reg18 | BIT(18));
1262 else if (central_ch >= 80)
1263 rf_reg18 = (rf_reg18 | BIT(17));
1264 }
1265
1266 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1267 dm, ODM_RF_PATH_A, 0x18,
1268 RFREGOFFSETMASK, rf_reg18);
1269
1270 if (dm->cut_version == ODM_CUT_A)
1271 rf_reg_status =
1272 rf_reg_status & config_phydm_write_rf_reg_8822b(
1273 dm, ODM_RF_PATH_A, 0xb8,
1274 RFREGOFFSETMASK, rf_reg_b8);
1275
1276 if (dm->rf_type > ODM_1T1R) {
1277 rf_reg_status =
1278 rf_reg_status & config_phydm_write_rf_reg_8822b(
1279 dm, ODM_RF_PATH_B, 0x18,
1280 RFREGOFFSETMASK, rf_reg18);
1281
1282 if (dm->cut_version == ODM_CUT_A)
1283 rf_reg_status = rf_reg_status &
1284 config_phydm_write_rf_reg_8822b(
1285 dm, ODM_RF_PATH_B, 0xb8,
1286 RFREGOFFSETMASK, rf_reg_b8);
1287 }
1288
1289 if (!rf_reg_status) {
1290 ODM_RT_TRACE(
1291 dm, ODM_PHY_CONFIG,
1292 "%s(): Fail to switch channel (ch: %d), because writing RF register is fail\n",
1293 __func__, central_ch);
1294 return false;
1295 }
1296
1297 phydm_ccapar_by_rfe_8822b(dm);
1298 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1299 "%s(): Success to switch channel (ch: %d)\n", __func__,
1300 central_ch);
1301 return true;
1302}
1303
1304bool config_phydm_switch_bandwidth_8822b(struct phy_dm_struct *dm,
1305 u8 primary_ch_idx,
1306 enum odm_bw bandwidth)
1307{
1308 u32 rf_reg18;
1309 bool rf_reg_status = true;
1310 u8 IGI = 0;
1311
1312 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()===================>\n",
1313 __func__);
1314
1315 if (dm->is_disable_phy_api) {
1316 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1317 "%s(): disable PHY API for debug!!\n", __func__);
1318 return true;
1319 }
1320
1321 /* Error handling */
1322 if ((bandwidth >= ODM_BW_MAX) ||
1323 ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) ||
1324 ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) {
1325 ODM_RT_TRACE(
1326 dm, ODM_PHY_CONFIG,
1327 "%s(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
1328 __func__, bandwidth, primary_ch_idx);
1329 return false;
1330 }
1331
1332 bw_8822b = bandwidth;
1333 rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
1334 RFREGOFFSETMASK);
1335 rf_reg_status =
1336 rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
1337
1338 /* Switch bandwidth */
1339 switch (bandwidth) {
1340 case ODM_BW20M: {
1341 /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0,
1342 * rf mode([1:0]) = 20M
1343 */
1344 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, ODM_BW20M);
1345
1346 /* ADC clock = 160M clock for BW20 */
1347 odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x0);
1348 odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x1);
1349
1350 /* DAC clock = 160M clock for BW20 */
1351 odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x0);
1352 odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x1);
1353
1354 /* ADC buffer clock */
1355 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
1356
1357 /* RF bandwidth */
1358 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1359
1360 break;
1361 }
1362 case ODM_BW40M: {
1363 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel,
1364 * rf mode([1:0]) = 40M
1365 */
1366 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0,
1367 (((primary_ch_idx & 0xf) << 2) | ODM_BW40M));
1368
1369 /* CCK primary channel */
1370 if (primary_ch_idx == 1)
1371 odm_set_bb_reg(dm, 0xa00, BIT(4), primary_ch_idx);
1372 else
1373 odm_set_bb_reg(dm, 0xa00, BIT(4), 0);
1374
1375 /* ADC clock = 160M clock for BW40 */
1376 odm_set_bb_reg(dm, 0x8ac, (BIT(11) | BIT(10)), 0x0);
1377 odm_set_bb_reg(dm, 0x8ac, BIT(17), 0x1);
1378
1379 /* DAC clock = 160M clock for BW20 */
1380 odm_set_bb_reg(dm, 0x8ac, (BIT(23) | BIT(22)), 0x0);
1381 odm_set_bb_reg(dm, 0x8ac, BIT(29), 0x1);
1382
1383 /* ADC buffer clock */
1384 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
1385
1386 /* RF bandwidth */
1387 rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
1388 rf_reg18 = (rf_reg18 | BIT(11));
1389
1390 break;
1391 }
1392 case ODM_BW80M: {
1393 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel,
1394 * rf mode([1:0]) = 80M
1395 */
1396 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0,
1397 (((primary_ch_idx & 0xf) << 2) | ODM_BW80M));
1398
1399 /* ADC clock = 160M clock for BW80 */
1400 odm_set_bb_reg(dm, 0x8ac, (BIT(13) | BIT(12)), 0x0);
1401 odm_set_bb_reg(dm, 0x8ac, BIT(18), 0x1);
1402
1403 /* DAC clock = 160M clock for BW20 */
1404 odm_set_bb_reg(dm, 0x8ac, (BIT(25) | BIT(24)), 0x0);
1405 odm_set_bb_reg(dm, 0x8ac, BIT(30), 0x1);
1406
1407 /* ADC buffer clock */
1408 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
1409
1410 /* RF bandwidth */
1411 rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
1412 rf_reg18 = (rf_reg18 | BIT(10));
1413
1414 break;
1415 }
1416 case ODM_BW5M: {
1417 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0,
1418 * rf mode([1:0]) = 20M
1419 */
1420 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(6) | ODM_BW20M));
1421
1422 /* ADC clock = 40M clock */
1423 odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x2);
1424 odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);
1425
1426 /* DAC clock = 160M clock for BW20 */
1427 odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x2);
1428 odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);
1429
1430 /* ADC buffer clock */
1431 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0);
1432 odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1);
1433
1434 /* RF bandwidth */
1435 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1436
1437 break;
1438 }
1439 case ODM_BW10M: {
1440 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0,
1441 * rf mode([1:0]) = 20M
1442 */
1443 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(7) | ODM_BW20M));
1444
1445 /* ADC clock = 80M clock */
1446 odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x3);
1447 odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);
1448
1449 /* DAC clock = 160M clock for BW20 */
1450 odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x3);
1451 odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);
1452
1453 /* ADC buffer clock */
1454 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0);
1455 odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1);
1456
1457 /* RF bandwidth */
1458 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1459
1460 break;
1461 }
1462 default:
1463 ODM_RT_TRACE(
1464 dm, ODM_PHY_CONFIG,
1465 "%s(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
1466 __func__, bandwidth, primary_ch_idx);
1467 }
1468
1469 /* Write RF register */
1470 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1471 dm, ODM_RF_PATH_A, 0x18,
1472 RFREGOFFSETMASK, rf_reg18);
1473
1474 if (dm->rf_type > ODM_1T1R)
1475 rf_reg_status =
1476 rf_reg_status & config_phydm_write_rf_reg_8822b(
1477 dm, ODM_RF_PATH_B, 0x18,
1478 RFREGOFFSETMASK, rf_reg18);
1479
1480 if (!rf_reg_status) {
1481 ODM_RT_TRACE(
1482 dm, ODM_PHY_CONFIG,
1483 "%s(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n",
1484 __func__, bandwidth, primary_ch_idx);
1485 return false;
1486 }
1487
1488 /* Modify RX DFIR parameters */
1489 phydm_rxdfirpar_by_bw_8822b(dm, bandwidth);
1490
1491 /* Modify CCA parameters */
1492 phydm_ccapar_by_bw_8822b(dm, bandwidth);
1493 phydm_ccapar_by_rfe_8822b(dm);
1494
1495 /* Toggle RX path to avoid RX dead zone issue */
1496 odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x0);
1497 odm_set_bb_reg(dm, 0x808, MASKBYTE0,
1498 (dm->rx_ant_status | (dm->rx_ant_status << 4)));
1499
1500 /* Toggle IGI to let RF enter RX mode */
1501 IGI = (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
1502 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), IGI - 2);
1503 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), IGI - 2);
1504 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), IGI);
1505 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), IGI);
1506
1507 ODM_RT_TRACE(
1508 dm, ODM_PHY_CONFIG,
1509 "%s(): Success to switch bandwidth (bw: %d, primary ch: %d)\n",
1510 __func__, bandwidth, primary_ch_idx);
1511 return true;
1512}
1513
1514bool config_phydm_switch_channel_bw_8822b(struct phy_dm_struct *dm,
1515 u8 central_ch, u8 primary_ch_idx,
1516 enum odm_bw bandwidth)
1517{
1518 /* Switch band */
1519 if (!config_phydm_switch_band_8822b(dm, central_ch))
1520 return false;
1521
1522 /* Switch channel */
1523 if (!config_phydm_switch_channel_8822b(dm, central_ch))
1524 return false;
1525
1526 /* Switch bandwidth */
1527 if (!config_phydm_switch_bandwidth_8822b(dm, primary_ch_idx, bandwidth))
1528 return false;
1529
1530 return true;
1531}
1532
1533bool config_phydm_trx_mode_8822b(struct phy_dm_struct *dm,
1534 enum odm_rf_path tx_path,
1535 enum odm_rf_path rx_path, bool is_tx2_path)
1536{
1537 bool rf_reg_status = true;
1538 u8 IGI;
1539 u32 rf_reg33 = 0;
1540 u16 counter = 0;
1541
1542 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()=====================>\n",
1543 __func__);
1544
1545 if (dm->is_disable_phy_api) {
1546 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1547 "%s(): disable PHY API for debug!!\n", __func__);
1548 return true;
1549 }
1550
1551 if ((tx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) {
1552 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1553 "%s(): Wrong TX setting (TX: 0x%x)\n", __func__,
1554 tx_path);
1555 return false;
1556 }
1557
1558 if ((rx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) {
1559 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1560 "%s(): Wrong RX setting (RX: 0x%x)\n", __func__,
1561 rx_path);
1562 return false;
1563 }
1564
1565 /* RF mode of path-A and path-B */
1566 /* Cannot shut down path-A, beacause synthesizer will be shut down when
1567 * path-A is in shut down mode
1568 */
1569 if ((tx_path | rx_path) & ODM_RF_A)
1570 odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x3231);
1571 else
1572 odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x1111);
1573
1574 if ((tx_path | rx_path) & ODM_RF_B)
1575 odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x3231);
1576 else
1577 odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x1111);
1578
1579 /* Set TX antenna by Nsts */
1580 odm_set_bb_reg(dm, 0x93c, (BIT(19) | BIT(18)), 0x3);
1581 odm_set_bb_reg(dm, 0x80c, (BIT(29) | BIT(28)), 0x1);
1582
1583 /* Control CCK TX path by 0xa07[7] */
1584 odm_set_bb_reg(dm, 0x80c, BIT(30), 0x1);
1585
1586 /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/
1587 if (tx_path & ODM_RF_A) {
1588 odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x001);
1589 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8);
1590 } else if (tx_path & ODM_RF_B) {
1591 odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x002);
1592 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4);
1593 }
1594
1595 /* TX logic map and TX path en for Nsts = 2*/
1596 if ((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))
1597 odm_set_bb_reg(dm, 0x940, 0xfff0, 0x01);
1598 else
1599 odm_set_bb_reg(dm, 0x940, 0xfff0, 0x43);
1600
1601 /* TX path enable */
1602 odm_set_bb_reg(dm, 0x80c, MASKBYTE0, ((tx_path << 4) | tx_path));
1603
1604 /* Tx2path for 1ss */
1605 if (!((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))) {
1606 if (is_tx2_path || dm->mp_mode) {
1607 /* 2Tx for OFDM */
1608 odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x043);
1609
1610 /* 2Tx for CCK */
1611 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc);
1612 }
1613 }
1614
1615 /* Always disable MRC for CCK CCA */
1616 odm_set_bb_reg(dm, 0xa2c, BIT(22), 0x0);
1617
1618 /* Always disable MRC for CCK barker */
1619 odm_set_bb_reg(dm, 0xa2c, BIT(18), 0x0);
1620
1621 /* CCK RX 1st and 2nd path setting*/
1622 if (rx_path & ODM_RF_A)
1623 odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0);
1624 else if (rx_path & ODM_RF_B)
1625 odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x5);
1626
1627 /* RX path enable */
1628 odm_set_bb_reg(dm, 0x808, MASKBYTE0, ((rx_path << 4) | rx_path));
1629
1630 if ((rx_path == ODM_RF_A) || (rx_path == ODM_RF_B)) {
1631 /* 1R */
1632
1633 /* Disable MRC for CCA */
1634 /* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x0); */
1635
1636 /* Disable MRC for barker */
1637 /* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x0); */
1638
1639 /* Disable CCK antenna diversity */
1640 /* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */
1641
1642 /* Disable Antenna weighting */
1643 odm_set_bb_reg(dm, 0x1904, BIT(16), 0x0);
1644 odm_set_bb_reg(dm, 0x800, BIT(28), 0x0);
1645 odm_set_bb_reg(dm, 0x850, BIT(23), 0x0);
1646 } else {
1647 /* 2R */
1648
1649 /* Enable MRC for CCA */
1650 /* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x1); */
1651
1652 /* Enable MRC for barker */
1653 /* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x1); */
1654
1655 /* Disable CCK antenna diversity */
1656 /* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */
1657
1658 /* Enable Antenna weighting */
1659 odm_set_bb_reg(dm, 0x1904, BIT(16), 0x1);
1660 odm_set_bb_reg(dm, 0x800, BIT(28), 0x1);
1661 odm_set_bb_reg(dm, 0x850, BIT(23), 0x1);
1662 }
1663
1664 /* Update TXRX antenna status for PHYDM */
1665 dm->tx_ant_status = (tx_path & 0x3);
1666 dm->rx_ant_status = (rx_path & 0x3);
1667
1668 /* MP driver need to support path-B TX\RX */
1669
1670 while (1) {
1671 counter++;
1672 rf_reg_status =
1673 rf_reg_status & config_phydm_write_rf_reg_8822b(
1674 dm, ODM_RF_PATH_A, 0xef,
1675 RFREGOFFSETMASK, 0x80000);
1676 rf_reg_status =
1677 rf_reg_status & config_phydm_write_rf_reg_8822b(
1678 dm, ODM_RF_PATH_A, 0x33,
1679 RFREGOFFSETMASK, 0x00001);
1680
1681 ODM_delay_us(2);
1682 rf_reg33 = config_phydm_read_rf_reg_8822b(
1683 dm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK);
1684
1685 if ((rf_reg33 == 0x00001) &&
1686 (config_phydm_read_rf_check_8822b(rf_reg33)))
1687 break;
1688 else if (counter == 100) {
1689 ODM_RT_TRACE(
1690 dm, ODM_PHY_CONFIG,
1691 "%s(): Fail to set TRx mode setting, because writing RF mode table is fail\n",
1692 __func__);
1693 return false;
1694 }
1695 }
1696
1697 if ((dm->mp_mode) || *dm->antenna_test || (dm->normal_rx_path)) {
1698 /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e
1699 * 0xef 0x00000 suggested by Lucas
1700 */
1701 rf_reg_status =
1702 rf_reg_status & config_phydm_write_rf_reg_8822b(
1703 dm, ODM_RF_PATH_A, 0xef,
1704 RFREGOFFSETMASK, 0x80000);
1705 rf_reg_status =
1706 rf_reg_status & config_phydm_write_rf_reg_8822b(
1707 dm, ODM_RF_PATH_A, 0x33,
1708 RFREGOFFSETMASK, 0x00001);
1709 rf_reg_status =
1710 rf_reg_status & config_phydm_write_rf_reg_8822b(
1711 dm, ODM_RF_PATH_A, 0x3e,
1712 RFREGOFFSETMASK, 0x00034);
1713 rf_reg_status =
1714 rf_reg_status & config_phydm_write_rf_reg_8822b(
1715 dm, ODM_RF_PATH_A, 0x3f,
1716 RFREGOFFSETMASK, 0x4080e);
1717 rf_reg_status =
1718 rf_reg_status & config_phydm_write_rf_reg_8822b(
1719 dm, ODM_RF_PATH_A, 0xef,
1720 RFREGOFFSETMASK, 0x00000);
1721 ODM_RT_TRACE(
1722 dm, ODM_PHY_CONFIG,
1723 "%s(): MP mode or Antenna test mode!! support path-B TX and RX\n",
1724 __func__);
1725 } else {
1726 /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080c
1727 * 0xef 0x00000
1728 */
1729 rf_reg_status =
1730 rf_reg_status & config_phydm_write_rf_reg_8822b(
1731 dm, ODM_RF_PATH_A, 0xef,
1732 RFREGOFFSETMASK, 0x80000);
1733 rf_reg_status =
1734 rf_reg_status & config_phydm_write_rf_reg_8822b(
1735 dm, ODM_RF_PATH_A, 0x33,
1736 RFREGOFFSETMASK, 0x00001);
1737 rf_reg_status =
1738 rf_reg_status & config_phydm_write_rf_reg_8822b(
1739 dm, ODM_RF_PATH_A, 0x3e,
1740 RFREGOFFSETMASK, 0x00034);
1741 rf_reg_status =
1742 rf_reg_status & config_phydm_write_rf_reg_8822b(
1743 dm, ODM_RF_PATH_A, 0x3f,
1744 RFREGOFFSETMASK, 0x4080c);
1745 rf_reg_status =
1746 rf_reg_status & config_phydm_write_rf_reg_8822b(
1747 dm, ODM_RF_PATH_A, 0xef,
1748 RFREGOFFSETMASK, 0x00000);
1749 ODM_RT_TRACE(
1750 dm, ODM_PHY_CONFIG,
1751 "%s(): Normal mode!! Do not support path-B TX and RX\n",
1752 __func__);
1753 }
1754
1755 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1756 dm, ODM_RF_PATH_A, 0xef,
1757 RFREGOFFSETMASK, 0x00000);
1758
1759 if (!rf_reg_status) {
1760 ODM_RT_TRACE(
1761 dm, ODM_PHY_CONFIG,
1762 "%s(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n",
1763 __func__, tx_path, rx_path);
1764 return false;
1765 }
1766
1767 /* Toggle IGI to let RF enter RX mode,
1768 * because BB doesn't send 3-wire command when RX path is enable
1769 */
1770 IGI = (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
1771 odm_write_dig(dm, IGI - 2);
1772 odm_write_dig(dm, IGI);
1773
1774 /* Modify CCA parameters */
1775 phydm_ccapar_by_rxpath_8822b(dm);
1776 phydm_ccapar_by_rfe_8822b(dm);
1777 phydm_rfe_8822b(dm, central_ch_8822b);
1778
1779 ODM_RT_TRACE(
1780 dm, ODM_PHY_CONFIG,
1781 "%s(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n",
1782 __func__, tx_path, rx_path);
1783 return true;
1784}
1785
1786bool config_phydm_parameter_init(struct phy_dm_struct *dm,
1787 enum odm_parameter_init type)
1788{
1789 if (type == ODM_PRE_SETTING) {
1790 odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x0);
1791 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1792 "%s(): Pre setting: disable OFDM and CCK block\n",
1793 __func__);
1794 } else if (type == ODM_POST_SETTING) {
1795 odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x3);
1796 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1797 "%s(): Post setting: enable OFDM and CCK block\n",
1798 __func__);
1799 reg82c_8822b = odm_get_bb_reg(dm, 0x82c, MASKDWORD);
1800 reg838_8822b = odm_get_bb_reg(dm, 0x838, MASKDWORD);
1801 reg830_8822b = odm_get_bb_reg(dm, 0x830, MASKDWORD);
1802 reg83c_8822b = odm_get_bb_reg(dm, 0x83c, MASKDWORD);
1803 rega20_8822b = odm_get_bb_reg(dm, 0xa20, MASKDWORD);
1804 rega24_8822b = odm_get_bb_reg(dm, 0xa24, MASKDWORD);
1805 rega28_8822b = odm_get_bb_reg(dm, 0xa28, MASKDWORD);
1806 } else {
1807 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s(): Wrong type!!\n",
1808 __func__);
1809 return false;
1810 }
1811
1812 return true;
1813}
1814
1815/* ======================================================================== */
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_hal_api8822b.h b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_hal_api8822b.h
new file mode 100644
index 000000000000..279ef06298e2
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_hal_api8822b.h
@@ -0,0 +1,84 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __INC_PHYDM_API_H_8822B__
26#define __INC_PHYDM_API_H_8822B__
27
28/*2016.08.01 (HW user guide version: R27, SW user guide version: R05,
29 * Modification: R31)
30 */
31#define PHY_CONFIG_VERSION_8822B "27.5.31"
32
33#define INVALID_RF_DATA 0xffffffff
34#define INVALID_TXAGC_DATA 0xff
35
36#define config_phydm_read_rf_check_8822b(data) (data != INVALID_RF_DATA)
37#define config_phydm_read_txagc_check_8822b(data) (data != INVALID_TXAGC_DATA)
38
39u32 config_phydm_read_rf_reg_8822b(struct phy_dm_struct *dm,
40 enum odm_rf_radio_path rf_path, u32 reg_addr,
41 u32 bit_mask);
42
43bool config_phydm_write_rf_reg_8822b(struct phy_dm_struct *dm,
44 enum odm_rf_radio_path rf_path,
45 u32 reg_addr, u32 bit_mask, u32 data);
46
47bool config_phydm_write_txagc_8822b(struct phy_dm_struct *dm, u32 power_index,
48 enum odm_rf_radio_path path, u8 hw_rate);
49
50u8 config_phydm_read_txagc_8822b(struct phy_dm_struct *dm,
51 enum odm_rf_radio_path path, u8 hw_rate);
52
53bool config_phydm_switch_band_8822b(struct phy_dm_struct *dm, u8 central_ch);
54
55bool config_phydm_switch_channel_8822b(struct phy_dm_struct *dm, u8 central_ch);
56
57bool config_phydm_switch_bandwidth_8822b(struct phy_dm_struct *dm,
58 u8 primary_ch_idx,
59 enum odm_bw bandwidth);
60
61bool config_phydm_switch_channel_bw_8822b(struct phy_dm_struct *dm,
62 u8 central_ch, u8 primary_ch_idx,
63 enum odm_bw bandwidth);
64
65bool config_phydm_trx_mode_8822b(struct phy_dm_struct *dm,
66 enum odm_rf_path tx_path,
67 enum odm_rf_path rx_path, bool is_tx2_path);
68
69bool config_phydm_parameter_init(struct phy_dm_struct *dm,
70 enum odm_parameter_init type);
71
72/* ======================================================================== */
73/* These following functions can be used for PHY DM only*/
74
75bool phydm_write_txagc_1byte_8822b(struct phy_dm_struct *dm, u32 power_index,
76 enum odm_rf_radio_path path, u8 hw_rate);
77
78void phydm_init_hw_info_by_rfe_type_8822b(struct phy_dm_struct *dm);
79
80s32 phydm_get_condition_number_8822B(struct phy_dm_struct *dm);
81
82/* ======================================================================== */
83
84#endif /* __INC_PHYDM_API_H_8822B__ */
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_iqk_8822b.c b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_iqk_8822b.c
new file mode 100644
index 000000000000..d320311213cc
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_iqk_8822b.c
@@ -0,0 +1,1410 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../mp_precomp.h"
27#include "../phydm_precomp.h"
28
29/*---------------------------Define Local Constant---------------------------*/
30
31static bool _iqk_rx_iqk_by_path_8822b(void *, u8);
32
33static inline void phydm_set_iqk_info(struct phy_dm_struct *dm,
34 struct dm_iqk_info *iqk_info, u8 status)
35{
36 bool KFAIL = true;
37
38 while (1) {
39 KFAIL = _iqk_rx_iqk_by_path_8822b(dm, ODM_RF_PATH_A);
40 if (status == 0)
41 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
42 "[IQK]S0RXK KFail = 0x%x\n", KFAIL);
43 else if (status == 1)
44 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
45 "[IQK]S1RXK KFail = 0x%x\n", KFAIL);
46 if (iqk_info->rxiqk_step == 5) {
47 dm->rf_calibrate_info.iqk_step++;
48 iqk_info->rxiqk_step = 1;
49 if (KFAIL && status == 0)
50 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
51 "[IQK]S0RXK fail code: %d!!!\n",
52 iqk_info->rxiqk_fail_code
53 [0][ODM_RF_PATH_A]);
54 else if (KFAIL && status == 1)
55 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
56 "[IQK]S1RXK fail code: %d!!!\n",
57 iqk_info->rxiqk_fail_code
58 [0][ODM_RF_PATH_A]);
59 break;
60 }
61 }
62
63 iqk_info->kcount++;
64}
65
66static inline void phydm_init_iqk_information(struct dm_iqk_info *iqk_info)
67{
68 u8 i, j, k, m;
69
70 for (i = 0; i < 2; i++) {
71 iqk_info->iqk_channel[i] = 0x0;
72
73 for (j = 0; j < SS_8822B; j++) {
74 iqk_info->lok_idac[i][j] = 0x0;
75 iqk_info->rxiqk_agc[i][j] = 0x0;
76 iqk_info->bypass_iqk[i][j] = 0x0;
77
78 for (k = 0; k < 2; k++) {
79 iqk_info->iqk_fail_report[i][j][k] = true;
80 for (m = 0; m < 8; m++) {
81 iqk_info->iqk_cfir_real[i][j][k][m] =
82 0x0;
83 iqk_info->iqk_cfir_imag[i][j][k][m] =
84 0x0;
85 }
86 }
87
88 for (k = 0; k < 3; k++)
89 iqk_info->retry_count[i][j][k] = 0x0;
90 }
91 }
92}
93
94static inline void phydm_backup_iqk_information(struct dm_iqk_info *iqk_info)
95{
96 u8 i, j, k;
97
98 iqk_info->iqk_channel[1] = iqk_info->iqk_channel[0];
99 for (i = 0; i < 2; i++) {
100 iqk_info->lok_idac[1][i] = iqk_info->lok_idac[0][i];
101 iqk_info->rxiqk_agc[1][i] = iqk_info->rxiqk_agc[0][i];
102 iqk_info->bypass_iqk[1][i] = iqk_info->bypass_iqk[0][i];
103 iqk_info->rxiqk_fail_code[1][i] =
104 iqk_info->rxiqk_fail_code[0][i];
105 for (j = 0; j < 2; j++) {
106 iqk_info->iqk_fail_report[1][i][j] =
107 iqk_info->iqk_fail_report[0][i][j];
108 for (k = 0; k < 8; k++) {
109 iqk_info->iqk_cfir_real[1][i][j][k] =
110 iqk_info->iqk_cfir_real[0][i][j][k];
111 iqk_info->iqk_cfir_imag[1][i][j][k] =
112 iqk_info->iqk_cfir_imag[0][i][j][k];
113 }
114 }
115 }
116
117 for (i = 0; i < 4; i++) {
118 iqk_info->rxiqk_fail_code[0][i] = 0x0;
119 iqk_info->rxiqk_agc[0][i] = 0x0;
120 for (j = 0; j < 2; j++) {
121 iqk_info->iqk_fail_report[0][i][j] = true;
122 iqk_info->gs_retry_count[0][i][j] = 0x0;
123 }
124 for (j = 0; j < 3; j++)
125 iqk_info->retry_count[0][i][j] = 0x0;
126 }
127}
128
129static inline void phydm_set_iqk_cfir(struct phy_dm_struct *dm,
130 struct dm_iqk_info *iqk_info, u8 path)
131{
132 u8 idx, i;
133 u32 tmp;
134
135 for (idx = 0; idx < 2; idx++) {
136 odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1);
137
138 if (idx == 0)
139 odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3);
140 else
141 odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1);
142
143 odm_set_bb_reg(dm, 0x1bd4,
144 BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16),
145 0x10);
146
147 for (i = 0; i < 8; i++) {
148 odm_set_bb_reg(dm, 0x1bd8, MASKDWORD,
149 0xe0000001 + (i * 4));
150 tmp = odm_get_bb_reg(dm, 0x1bfc, MASKDWORD);
151 iqk_info->iqk_cfir_real[0][path][idx][i] =
152 (tmp & 0x0fff0000) >> 16;
153 iqk_info->iqk_cfir_imag[0][path][idx][i] = tmp & 0xfff;
154 }
155 }
156}
157
158static inline void phydm_get_read_counter(struct phy_dm_struct *dm)
159{
160 u32 counter = 0x0;
161
162 while (1) {
163 if (((odm_read_4byte(dm, 0x1bf0) >> 24) == 0x7f) ||
164 (counter > 300))
165 break;
166
167 counter++;
168 ODM_delay_ms(1);
169 }
170
171 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]counter = %d\n", counter);
172}
173
174/*---------------------------Define Local Constant---------------------------*/
175
176void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
177 u8 threshold)
178{
179 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
180
181 odm_reset_iqk_result(dm);
182
183 dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
184
185 phy_iq_calibrate_8822b(dm, true);
186}
187
188static void _iqk_fill_iqk_report_8822b(void *dm_void, u8 channel)
189{
190 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
191 struct dm_iqk_info *iqk_info = &dm->IQK_info;
192 u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0;
193 u8 i;
194
195 for (i = 0; i < SS_8822B; i++) {
196 tmp1 = tmp1 +
197 ((iqk_info->iqk_fail_report[channel][i][TX_IQK] & 0x1)
198 << i);
199 tmp2 = tmp2 +
200 ((iqk_info->iqk_fail_report[channel][i][RX_IQK] & 0x1)
201 << (i + 4));
202 tmp3 = tmp3 + ((iqk_info->rxiqk_fail_code[channel][i] & 0x3)
203 << (i * 2 + 8));
204 }
205 odm_write_4byte(dm, 0x1b00, 0xf8000008);
206 odm_set_bb_reg(dm, 0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3);
207
208 for (i = 0; i < 2; i++)
209 odm_write_4byte(
210 dm, 0x1be8 + (i * 4),
211 (iqk_info->rxiqk_agc[channel][(i * 2) + 1] << 16) |
212 iqk_info->rxiqk_agc[channel][i * 2]);
213}
214
215static void _iqk_backup_mac_bb_8822b(struct phy_dm_struct *dm, u32 *MAC_backup,
216 u32 *BB_backup, u32 *backup_mac_reg,
217 u32 *backup_bb_reg)
218{
219 u32 i;
220
221 for (i = 0; i < MAC_REG_NUM_8822B; i++)
222 MAC_backup[i] = odm_read_4byte(dm, backup_mac_reg[i]);
223
224 for (i = 0; i < BB_REG_NUM_8822B; i++)
225 BB_backup[i] = odm_read_4byte(dm, backup_bb_reg[i]);
226}
227
228static void _iqk_backup_rf_8822b(struct phy_dm_struct *dm, u32 RF_backup[][2],
229 u32 *backup_rf_reg)
230{
231 u32 i;
232
233 for (i = 0; i < RF_REG_NUM_8822B; i++) {
234 RF_backup[i][ODM_RF_PATH_A] = odm_get_rf_reg(
235 dm, ODM_RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK);
236 RF_backup[i][ODM_RF_PATH_B] = odm_get_rf_reg(
237 dm, ODM_RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK);
238 }
239}
240
241static void _iqk_agc_bnd_int_8822b(struct phy_dm_struct *dm)
242{
243 /*initialize RX AGC bnd, it must do after bbreset*/
244 odm_write_4byte(dm, 0x1b00, 0xf8000008);
245 odm_write_4byte(dm, 0x1b00, 0xf80a7008);
246 odm_write_4byte(dm, 0x1b00, 0xf8015008);
247 odm_write_4byte(dm, 0x1b00, 0xf8000008);
248}
249
250static void _iqk_bb_reset_8822b(struct phy_dm_struct *dm)
251{
252 bool cca_ing = false;
253 u32 count = 0;
254
255 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);
256 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);
257
258 while (1) {
259 odm_write_4byte(dm, 0x8fc, 0x0);
260 odm_set_bb_reg(dm, 0x198c, 0x7, 0x7);
261 cca_ing = (bool)odm_get_bb_reg(dm, 0xfa0, BIT(3));
262
263 if (count > 30)
264 cca_ing = false;
265
266 if (cca_ing) {
267 ODM_delay_ms(1);
268 count++;
269 } else {
270 odm_write_1byte(dm, 0x808, 0x0); /*RX ant off*/
271 odm_set_bb_reg(dm, 0xa04,
272 BIT(27) | BIT(26) | BIT(25) | BIT(24),
273 0x0); /*CCK RX path off*/
274
275 /*BBreset*/
276 odm_set_bb_reg(dm, 0x0, BIT(16), 0x0);
277 odm_set_bb_reg(dm, 0x0, BIT(16), 0x1);
278
279 if (odm_get_bb_reg(dm, 0x660, BIT(16)))
280 odm_write_4byte(dm, 0x6b4, 0x89000006);
281 break;
282 }
283 }
284}
285
286static void _iqk_afe_setting_8822b(struct phy_dm_struct *dm, bool do_iqk)
287{
288 if (do_iqk) {
289 odm_write_4byte(dm, 0xc60, 0x50000000);
290 odm_write_4byte(dm, 0xc60, 0x70070040);
291 odm_write_4byte(dm, 0xe60, 0x50000000);
292 odm_write_4byte(dm, 0xe60, 0x70070040);
293
294 odm_write_4byte(dm, 0xc58, 0xd8000402);
295 odm_write_4byte(dm, 0xc5c, 0xd1000120);
296 odm_write_4byte(dm, 0xc6c, 0x00000a15);
297 odm_write_4byte(dm, 0xe58, 0xd8000402);
298 odm_write_4byte(dm, 0xe5c, 0xd1000120);
299 odm_write_4byte(dm, 0xe6c, 0x00000a15);
300 _iqk_bb_reset_8822b(dm);
301 } else {
302 odm_write_4byte(dm, 0xc60, 0x50000000);
303 odm_write_4byte(dm, 0xc60, 0x70038040);
304 odm_write_4byte(dm, 0xe60, 0x50000000);
305 odm_write_4byte(dm, 0xe60, 0x70038040);
306
307 odm_write_4byte(dm, 0xc58, 0xd8020402);
308 odm_write_4byte(dm, 0xc5c, 0xde000120);
309 odm_write_4byte(dm, 0xc6c, 0x0000122a);
310 odm_write_4byte(dm, 0xe58, 0xd8020402);
311 odm_write_4byte(dm, 0xe5c, 0xde000120);
312 odm_write_4byte(dm, 0xe6c, 0x0000122a);
313 }
314}
315
316static void _iqk_restore_mac_bb_8822b(struct phy_dm_struct *dm, u32 *MAC_backup,
317 u32 *BB_backup, u32 *backup_mac_reg,
318 u32 *backup_bb_reg)
319{
320 u32 i;
321
322 for (i = 0; i < MAC_REG_NUM_8822B; i++)
323 odm_write_4byte(dm, backup_mac_reg[i], MAC_backup[i]);
324 for (i = 0; i < BB_REG_NUM_8822B; i++)
325 odm_write_4byte(dm, backup_bb_reg[i], BB_backup[i]);
326}
327
328static void _iqk_restore_rf_8822b(struct phy_dm_struct *dm, u32 *backup_rf_reg,
329 u32 RF_backup[][2])
330{
331 u32 i;
332
333 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x0);
334 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, RFREGOFFSETMASK, 0x0);
335 /*0xdf[4]=0*/
336 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK,
337 RF_backup[0][ODM_RF_PATH_A] & (~BIT(4)));
338 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xdf, RFREGOFFSETMASK,
339 RF_backup[0][ODM_RF_PATH_B] & (~BIT(4)));
340
341 for (i = 1; i < RF_REG_NUM_8822B; i++) {
342 odm_set_rf_reg(dm, ODM_RF_PATH_A, backup_rf_reg[i],
343 RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_A]);
344 odm_set_rf_reg(dm, ODM_RF_PATH_B, backup_rf_reg[i],
345 RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_B]);
346 }
347}
348
349static void _iqk_backup_iqk_8822b(struct phy_dm_struct *dm, u8 step)
350{
351 struct dm_iqk_info *iqk_info = &dm->IQK_info;
352 u8 path;
353 u16 iqk_apply[2] = {0xc94, 0xe94};
354
355 if (step == 0x0) {
356 phydm_backup_iqk_information(iqk_info);
357 } else {
358 iqk_info->iqk_channel[0] = iqk_info->rf_reg18;
359 for (path = 0; path < 2; path++) {
360 iqk_info->lok_idac[0][path] =
361 odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
362 0x58, RFREGOFFSETMASK);
363 iqk_info->bypass_iqk[0][path] =
364 odm_get_bb_reg(dm, iqk_apply[path], MASKDWORD);
365
366 phydm_set_iqk_cfir(dm, iqk_info, path);
367 odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);
368 odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0);
369 }
370 }
371}
372
373static void _iqk_reload_iqk_setting_8822b(
374 struct phy_dm_struct *dm, u8 channel,
375 u8 reload_idx /*1: reload TX, 2: reload LO, TX, RX*/
376 )
377{
378 struct dm_iqk_info *iqk_info = &dm->IQK_info;
379 u8 i, path, idx;
380 u16 iqk_apply[2] = {0xc94, 0xe94};
381
382 for (path = 0; path < 2; path++) {
383 if (reload_idx == 2) {
384 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xdf,
385 BIT(4), 0x1);
386 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x58,
387 RFREGOFFSETMASK,
388 iqk_info->lok_idac[channel][path]);
389 }
390
391 for (idx = 0; idx < reload_idx; idx++) {
392 odm_set_bb_reg(dm, 0x1b00, MASKDWORD,
393 0xf8000008 | path << 1);
394 odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x7);
395 odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000);
396 odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000);
397 odm_set_bb_reg(dm, 0x1bcc, MASKDWORD, 0x00000000);
398
399 if (idx == 0)
400 odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12),
401 0x3);
402 else
403 odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12),
404 0x1);
405
406 odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) |
407 BIT(17) | BIT(16),
408 0x10);
409
410 for (i = 0; i < 8; i++) {
411 odm_write_4byte(
412 dm, 0x1bd8,
413 ((0xc0000000 >> idx) + 0x3) + (i * 4) +
414 (iqk_info->iqk_cfir_real
415 [channel][path][idx][i]
416 << 9));
417 odm_write_4byte(
418 dm, 0x1bd8,
419 ((0xc0000000 >> idx) + 0x1) + (i * 4) +
420 (iqk_info->iqk_cfir_imag
421 [channel][path][idx][i]
422 << 9));
423 }
424 }
425 odm_set_bb_reg(dm, iqk_apply[path], MASKDWORD,
426 iqk_info->bypass_iqk[channel][path]);
427
428 odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);
429 odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0);
430 }
431}
432
433static bool _iqk_reload_iqk_8822b(struct phy_dm_struct *dm, bool reset)
434{
435 struct dm_iqk_info *iqk_info = &dm->IQK_info;
436 u8 i;
437 bool reload = false;
438
439 if (reset) {
440 for (i = 0; i < 2; i++)
441 iqk_info->iqk_channel[i] = 0x0;
442 } else {
443 iqk_info->rf_reg18 = odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18,
444 RFREGOFFSETMASK);
445
446 for (i = 0; i < 2; i++) {
447 if (iqk_info->rf_reg18 == iqk_info->iqk_channel[i]) {
448 _iqk_reload_iqk_setting_8822b(dm, i, 2);
449 _iqk_fill_iqk_report_8822b(dm, i);
450 ODM_RT_TRACE(
451 dm, ODM_COMP_CALIBRATION,
452 "[IQK]reload IQK result before!!!!\n");
453 reload = true;
454 }
455 }
456 }
457 return reload;
458}
459
460static void _iqk_rfe_setting_8822b(struct phy_dm_struct *dm, bool ext_pa_on)
461{
462 if (ext_pa_on) {
463 /*RFE setting*/
464 odm_write_4byte(dm, 0xcb0, 0x77777777);
465 odm_write_4byte(dm, 0xcb4, 0x00007777);
466 odm_write_4byte(dm, 0xcbc, 0x0000083B);
467 odm_write_4byte(dm, 0xeb0, 0x77777777);
468 odm_write_4byte(dm, 0xeb4, 0x00007777);
469 odm_write_4byte(dm, 0xebc, 0x0000083B);
470 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
471 "[IQK]external PA on!!!!\n");
472 } else {
473 /*RFE setting*/
474 odm_write_4byte(dm, 0xcb0, 0x77777777);
475 odm_write_4byte(dm, 0xcb4, 0x00007777);
476 odm_write_4byte(dm, 0xcbc, 0x00000100);
477 odm_write_4byte(dm, 0xeb0, 0x77777777);
478 odm_write_4byte(dm, 0xeb4, 0x00007777);
479 odm_write_4byte(dm, 0xebc, 0x00000100);
480 }
481}
482
483static void _iqk_rf_setting_8822b(struct phy_dm_struct *dm)
484{
485 u8 path;
486 u32 tmp;
487
488 odm_write_4byte(dm, 0x1b00, 0xf8000008);
489 odm_write_4byte(dm, 0x1bb8, 0x00000000);
490
491 for (path = 0; path < 2; path++) {
492 /*0xdf:B11 = 1,B4 = 0, B1 = 1*/
493 tmp = odm_get_rf_reg(dm, (enum odm_rf_radio_path)path, 0xdf,
494 RFREGOFFSETMASK);
495 tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11);
496 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xdf,
497 RFREGOFFSETMASK, tmp);
498
499 /*release 0x56 TXBB*/
500 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x65,
501 RFREGOFFSETMASK, 0x09000);
502
503 if (*dm->band_type == ODM_BAND_5G) {
504 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef,
505 BIT(19), 0x1);
506 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x33,
507 RFREGOFFSETMASK, 0x00026);
508 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x3e,
509 RFREGOFFSETMASK, 0x00037);
510 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x3f,
511 RFREGOFFSETMASK, 0xdefce);
512 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef,
513 BIT(19), 0x0);
514 } else {
515 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef,
516 BIT(19), 0x1);
517 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x33,
518 RFREGOFFSETMASK, 0x00026);
519 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x3e,
520 RFREGOFFSETMASK, 0x00037);
521 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x3f,
522 RFREGOFFSETMASK, 0x5efce);
523 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef,
524 BIT(19), 0x0);
525 }
526 }
527}
528
529static void _iqk_configure_macbb_8822b(struct phy_dm_struct *dm)
530{
531 /*MACBB register setting*/
532 odm_write_1byte(dm, 0x522, 0x7f);
533 odm_set_bb_reg(dm, 0x550, BIT(11) | BIT(3), 0x0);
534 odm_set_bb_reg(dm, 0x90c, BIT(15),
535 0x1); /*0x90c[15]=1: dac_buf reset selection*/
536 odm_set_bb_reg(dm, 0x9a4, BIT(31),
537 0x0); /*0x9a4[31]=0: Select da clock*/
538 /*0xc94[0]=1, 0xe94[0]=1: let tx through iqk*/
539 odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1);
540 odm_set_bb_reg(dm, 0xe94, BIT(0), 0x1);
541 /* 3-wire off*/
542 odm_write_4byte(dm, 0xc00, 0x00000004);
543 odm_write_4byte(dm, 0xe00, 0x00000004);
544}
545
546static void _iqk_lok_setting_8822b(struct phy_dm_struct *dm, u8 path)
547{
548 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
549 odm_write_4byte(dm, 0x1bcc, 0x9);
550 odm_write_1byte(dm, 0x1b23, 0x00);
551
552 switch (*dm->band_type) {
553 case ODM_BAND_2_4G:
554 odm_write_1byte(dm, 0x1b2b, 0x00);
555 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
556 RFREGOFFSETMASK, 0x50df2);
557 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
558 RFREGOFFSETMASK, 0xadc00);
559 /* WE_LUT_TX_LOK*/
560 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef, BIT(4),
561 0x1);
562 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x33,
563 BIT(1) | BIT(0), 0x0);
564 break;
565 case ODM_BAND_5G:
566 odm_write_1byte(dm, 0x1b2b, 0x80);
567 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
568 RFREGOFFSETMASK, 0x5086c);
569 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
570 RFREGOFFSETMASK, 0xa9c00);
571 /* WE_LUT_TX_LOK*/
572 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef, BIT(4),
573 0x1);
574 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x33,
575 BIT(1) | BIT(0), 0x1);
576 break;
577 }
578}
579
580static void _iqk_txk_setting_8822b(struct phy_dm_struct *dm, u8 path)
581{
582 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
583 odm_write_4byte(dm, 0x1bcc, 0x9);
584 odm_write_4byte(dm, 0x1b20, 0x01440008);
585
586 if (path == 0x0)
587 odm_write_4byte(dm, 0x1b00, 0xf800000a);
588 else
589 odm_write_4byte(dm, 0x1b00, 0xf8000008);
590 odm_write_4byte(dm, 0x1bcc, 0x3f);
591
592 switch (*dm->band_type) {
593 case ODM_BAND_2_4G:
594 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
595 RFREGOFFSETMASK, 0x50df2);
596 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
597 RFREGOFFSETMASK, 0xadc00);
598 odm_write_1byte(dm, 0x1b2b, 0x00);
599 break;
600 case ODM_BAND_5G:
601 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
602 RFREGOFFSETMASK, 0x500ef);
603 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
604 RFREGOFFSETMASK, 0xa9c00);
605 odm_write_1byte(dm, 0x1b2b, 0x80);
606 break;
607 }
608}
609
610static void _iqk_rxk1_setting_8822b(struct phy_dm_struct *dm, u8 path)
611{
612 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
613
614 switch (*dm->band_type) {
615 case ODM_BAND_2_4G:
616 odm_write_1byte(dm, 0x1bcc, 0x9);
617 odm_write_1byte(dm, 0x1b2b, 0x00);
618 odm_write_4byte(dm, 0x1b20, 0x01450008);
619 odm_write_4byte(dm, 0x1b24, 0x01460c88);
620 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
621 RFREGOFFSETMASK, 0x510e0);
622 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
623 RFREGOFFSETMASK, 0xacc00);
624 break;
625 case ODM_BAND_5G:
626 odm_write_1byte(dm, 0x1bcc, 0x09);
627 odm_write_1byte(dm, 0x1b2b, 0x80);
628 odm_write_4byte(dm, 0x1b20, 0x00850008);
629 odm_write_4byte(dm, 0x1b24, 0x00460048);
630 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
631 RFREGOFFSETMASK, 0x510e0);
632 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
633 RFREGOFFSETMASK, 0xadc00);
634 break;
635 }
636}
637
638static void _iqk_rxk2_setting_8822b(struct phy_dm_struct *dm, u8 path,
639 bool is_gs)
640{
641 struct dm_iqk_info *iqk_info = &dm->IQK_info;
642
643 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
644
645 switch (*dm->band_type) {
646 case ODM_BAND_2_4G:
647 if (is_gs)
648 iqk_info->tmp1bcc = 0x12;
649 odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
650 odm_write_1byte(dm, 0x1b2b, 0x00);
651 odm_write_4byte(dm, 0x1b20, 0x01450008);
652 odm_write_4byte(dm, 0x1b24, 0x01460848);
653 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
654 RFREGOFFSETMASK, 0x510e0);
655 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
656 RFREGOFFSETMASK, 0xa9c00);
657 break;
658 case ODM_BAND_5G:
659 if (is_gs) {
660 if (path == ODM_RF_PATH_A)
661 iqk_info->tmp1bcc = 0x12;
662 else
663 iqk_info->tmp1bcc = 0x09;
664 }
665 odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
666 odm_write_1byte(dm, 0x1b2b, 0x80);
667 odm_write_4byte(dm, 0x1b20, 0x00850008);
668 odm_write_4byte(dm, 0x1b24, 0x00460848);
669 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
670 RFREGOFFSETMASK, 0x51060);
671 odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
672 RFREGOFFSETMASK, 0xa9c00);
673 break;
674 }
675}
676
677static bool _iqk_check_cal_8822b(struct phy_dm_struct *dm, u32 IQK_CMD)
678{
679 bool notready = true, fail = true;
680 u32 delay_count = 0x0;
681
682 while (notready) {
683 if (odm_read_4byte(dm, 0x1b00) == (IQK_CMD & 0xffffff0f)) {
684 fail = (bool)odm_get_bb_reg(dm, 0x1b08, BIT(26));
685 notready = false;
686 } else {
687 ODM_delay_ms(1);
688 delay_count++;
689 }
690
691 if (delay_count >= 50) {
692 fail = true;
693 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
694 "[IQK]IQK timeout!!!\n");
695 break;
696 }
697 }
698 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]delay count = 0x%x!!!\n",
699 delay_count);
700 return fail;
701}
702
703static bool _iqk_rx_iqk_gain_search_fail_8822b(struct phy_dm_struct *dm,
704 u8 path, u8 step)
705{
706 struct dm_iqk_info *iqk_info = &dm->IQK_info;
707 bool fail = true;
708 u32 IQK_CMD = 0x0, rf_reg0, tmp, bb_idx;
709 u8 IQMUX[4] = {0x9, 0x12, 0x1b, 0x24};
710 u8 idx;
711
712 for (idx = 0; idx < 4; idx++)
713 if (iqk_info->tmp1bcc == IQMUX[idx])
714 break;
715
716 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
717 odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc);
718
719 if (step == RXIQK1)
720 ODM_RT_TRACE(
721 dm, ODM_COMP_CALIBRATION,
722 "[IQK]============ S%d RXIQK GainSearch ============\n",
723 path);
724
725 if (step == RXIQK1)
726 IQK_CMD = 0xf8000208 | (1 << (path + 4));
727 else
728 IQK_CMD = 0xf8000308 | (1 << (path + 4));
729
730 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]S%d GS%d_Trigger = 0x%x\n",
731 path, step, IQK_CMD);
732
733 odm_write_4byte(dm, 0x1b00, IQK_CMD);
734 odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
735 ODM_delay_ms(GS_delay_8822B);
736 fail = _iqk_check_cal_8822b(dm, IQK_CMD);
737
738 if (step == RXIQK2) {
739 rf_reg0 = odm_get_rf_reg(dm, (enum odm_rf_radio_path)path, 0x0,
740 RFREGOFFSETMASK);
741 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
742 ODM_RT_TRACE(
743 dm, ODM_COMP_CALIBRATION,
744 "[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n",
745 path, rf_reg0, iqk_info->tmp1bcc, idx,
746 odm_read_4byte(dm, 0x1b3c));
747 tmp = (rf_reg0 & 0x1fe0) >> 5;
748 iqk_info->lna_idx = tmp >> 5;
749 bb_idx = tmp & 0x1f;
750 if (bb_idx == 0x1) {
751 if (iqk_info->lna_idx != 0x0)
752 iqk_info->lna_idx--;
753 else if (idx != 3)
754 idx++;
755 else
756 iqk_info->isbnd = true;
757 fail = true;
758 } else if (bb_idx == 0xa) {
759 if (idx != 0)
760 idx--;
761 else if (iqk_info->lna_idx != 0x7)
762 iqk_info->lna_idx++;
763 else
764 iqk_info->isbnd = true;
765 fail = true;
766 } else {
767 fail = false;
768 }
769
770 if (iqk_info->isbnd)
771 fail = false;
772
773 iqk_info->tmp1bcc = IQMUX[idx];
774
775 if (fail) {
776 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
777 odm_write_4byte(
778 dm, 0x1b24,
779 (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) |
780 (iqk_info->lna_idx << 10));
781 }
782 }
783
784 return fail;
785}
786
787static bool _lok_one_shot_8822b(void *dm_void, u8 path)
788{
789 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
790 struct dm_iqk_info *iqk_info = &dm->IQK_info;
791 u8 delay_count = 0;
792 bool LOK_notready = false;
793 u32 LOK_temp = 0;
794 u32 IQK_CMD = 0x0;
795
796 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
797 "[IQK]==========S%d LOK ==========\n", path);
798
799 IQK_CMD = 0xf8000008 | (1 << (4 + path));
800
801 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]LOK_Trigger = 0x%x\n",
802 IQK_CMD);
803
804 odm_write_4byte(dm, 0x1b00, IQK_CMD);
805 odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
806 /*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/
807 /*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/
808 ODM_delay_ms(LOK_delay_8822B);
809
810 delay_count = 0;
811 LOK_notready = true;
812
813 while (LOK_notready) {
814 if (odm_read_4byte(dm, 0x1b00) == (IQK_CMD & 0xffffff0f))
815 LOK_notready = false;
816 else
817 LOK_notready = true;
818
819 if (LOK_notready) {
820 ODM_delay_ms(1);
821 delay_count++;
822 }
823
824 if (delay_count >= 50) {
825 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
826 "[IQK]S%d LOK timeout!!!\n", path);
827 break;
828 }
829 }
830
831 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
832 "[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count);
833 if (ODM_COMP_CALIBRATION) {
834 if (!LOK_notready) {
835 LOK_temp =
836 odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
837 0x58, RFREGOFFSETMASK);
838 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
839 "[IQK]0x58 = 0x%x\n", LOK_temp);
840 } else {
841 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
842 "[IQK]==>S%d LOK Fail!!!\n", path);
843 }
844 }
845 iqk_info->lok_fail[path] = LOK_notready;
846 return LOK_notready;
847}
848
849static bool _iqk_one_shot_8822b(void *dm_void, u8 path, u8 idx)
850{
851 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
852 struct dm_iqk_info *iqk_info = &dm->IQK_info;
853 u8 delay_count = 0;
854 bool notready = true, fail = true;
855 u32 IQK_CMD = 0x0;
856 u16 iqk_apply[2] = {0xc94, 0xe94};
857
858 if (idx == TXIQK)
859 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
860 "[IQK]============ S%d WBTXIQK ============\n",
861 path);
862 else if (idx == RXIQK1)
863 ODM_RT_TRACE(
864 dm, ODM_COMP_CALIBRATION,
865 "[IQK]============ S%d WBRXIQK STEP1============\n",
866 path);
867 else
868 ODM_RT_TRACE(
869 dm, ODM_COMP_CALIBRATION,
870 "[IQK]============ S%d WBRXIQK STEP2============\n",
871 path);
872
873 if (idx == TXIQK) {
874 IQK_CMD = 0xf8000008 | ((*dm->band_width + 4) << 8) |
875 (1 << (path + 4));
876 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
877 "[IQK]TXK_Trigger = 0x%x\n", IQK_CMD);
878 /*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/
879 /*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/
880 /*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/
881 } else if (idx == RXIQK1) {
882 if (*dm->band_width == 2)
883 IQK_CMD = 0xf8000808 | (1 << (path + 4));
884 else
885 IQK_CMD = 0xf8000708 | (1 << (path + 4));
886 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
887 "[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD);
888 /*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/
889 /*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/
890 /*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/
891 } else if (idx == RXIQK2) {
892 IQK_CMD = 0xf8000008 | ((*dm->band_width + 9) << 8) |
893 (1 << (path + 4));
894 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
895 "[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD);
896 /*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/
897 /*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/
898 /*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/
899 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
900 odm_write_4byte(dm, 0x1b24,
901 (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) |
902 ((iqk_info->lna_idx & 0x7) << 10));
903 }
904 odm_write_4byte(dm, 0x1b00, IQK_CMD);
905 odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
906 ODM_delay_ms(WBIQK_delay_8822B);
907
908 while (notready) {
909 if (odm_read_4byte(dm, 0x1b00) == (IQK_CMD & 0xffffff0f))
910 notready = false;
911 else
912 notready = true;
913
914 if (notready) {
915 ODM_delay_ms(1);
916 delay_count++;
917 } else {
918 fail = (bool)odm_get_bb_reg(dm, 0x1b08, BIT(26));
919 break;
920 }
921
922 if (delay_count >= 50) {
923 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
924 "[IQK]S%d IQK timeout!!!\n", path);
925 break;
926 }
927 }
928
929 if (dm->debug_components & ODM_COMP_CALIBRATION) {
930 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
931 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
932 "[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n",
933 path, odm_read_4byte(dm, 0x1b00),
934 odm_read_4byte(dm, 0x1b08));
935 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
936 "[IQK]S%d ==> delay_count = 0x%x\n", path,
937 delay_count);
938 if (idx != TXIQK)
939 ODM_RT_TRACE(
940 dm, ODM_COMP_CALIBRATION,
941 "[IQK]S%d ==> RF0x0 = 0x%x, RF0x56 = 0x%x\n",
942 path,
943 odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
944 0x0, RFREGOFFSETMASK),
945 odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
946 0x56, RFREGOFFSETMASK));
947 }
948
949 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
950
951 if (idx == TXIQK)
952 if (fail)
953 odm_set_bb_reg(dm, iqk_apply[path], BIT(0), 0x0);
954
955 if (idx == RXIQK2) {
956 iqk_info->rxiqk_agc[0][path] =
957 (u16)(((odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
958 0x0, RFREGOFFSETMASK) >>
959 5) &
960 0xff) |
961 (iqk_info->tmp1bcc << 8));
962
963 odm_write_4byte(dm, 0x1b38, 0x20000000);
964
965 if (!fail)
966 odm_set_bb_reg(dm, iqk_apply[path], (BIT(11) | BIT(10)),
967 0x1);
968 else
969 odm_set_bb_reg(dm, iqk_apply[path], (BIT(11) | BIT(10)),
970 0x0);
971 }
972
973 if (idx == TXIQK)
974 iqk_info->iqk_fail_report[0][path][TXIQK] = fail;
975 else
976 iqk_info->iqk_fail_report[0][path][RXIQK] = fail;
977
978 return fail;
979}
980
981static bool _iqk_rx_iqk_by_path_8822b(void *dm_void, u8 path)
982{
983 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
984 struct dm_iqk_info *iqk_info = &dm->IQK_info;
985 bool KFAIL = true, gonext;
986
987 switch (iqk_info->rxiqk_step) {
988 case 1: /*gain search_RXK1*/
989 _iqk_rxk1_setting_8822b(dm, path);
990 gonext = false;
991 while (1) {
992 KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(dm, path,
993 RXIQK1);
994 if (KFAIL &&
995 (iqk_info->gs_retry_count[0][path][GSRXK1] < 2))
996 iqk_info->gs_retry_count[0][path][GSRXK1]++;
997 else if (KFAIL) {
998 iqk_info->rxiqk_fail_code[0][path] = 0;
999 iqk_info->rxiqk_step = 5;
1000 gonext = true;
1001 } else {
1002 iqk_info->rxiqk_step++;
1003 gonext = true;
1004 }
1005 if (gonext)
1006 break;
1007 }
1008 break;
1009 case 2: /*gain search_RXK2*/
1010 _iqk_rxk2_setting_8822b(dm, path, true);
1011 iqk_info->isbnd = false;
1012 while (1) {
1013 KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(dm, path,
1014 RXIQK2);
1015 if (KFAIL &&
1016 (iqk_info->gs_retry_count[0][path][GSRXK2] <
1017 rxiqk_gs_limit)) {
1018 iqk_info->gs_retry_count[0][path][GSRXK2]++;
1019 } else {
1020 iqk_info->rxiqk_step++;
1021 break;
1022 }
1023 }
1024 break;
1025 case 3: /*RXK1*/
1026 _iqk_rxk1_setting_8822b(dm, path);
1027 gonext = false;
1028 while (1) {
1029 KFAIL = _iqk_one_shot_8822b(dm, path, RXIQK1);
1030 if (KFAIL &&
1031 (iqk_info->retry_count[0][path][RXIQK1] < 2))
1032 iqk_info->retry_count[0][path][RXIQK1]++;
1033 else if (KFAIL) {
1034 iqk_info->rxiqk_fail_code[0][path] = 1;
1035 iqk_info->rxiqk_step = 5;
1036 gonext = true;
1037 } else {
1038 iqk_info->rxiqk_step++;
1039 gonext = true;
1040 }
1041 if (gonext)
1042 break;
1043 }
1044 break;
1045 case 4: /*RXK2*/
1046 _iqk_rxk2_setting_8822b(dm, path, false);
1047 gonext = false;
1048 while (1) {
1049 KFAIL = _iqk_one_shot_8822b(dm, path, RXIQK2);
1050 if (KFAIL &&
1051 (iqk_info->retry_count[0][path][RXIQK2] < 2))
1052 iqk_info->retry_count[0][path][RXIQK2]++;
1053 else if (KFAIL) {
1054 iqk_info->rxiqk_fail_code[0][path] = 2;
1055 iqk_info->rxiqk_step = 5;
1056 gonext = true;
1057 } else {
1058 iqk_info->rxiqk_step++;
1059 gonext = true;
1060 }
1061 if (gonext)
1062 break;
1063 }
1064 break;
1065 }
1066 return KFAIL;
1067}
1068
1069static void _iqk_iqk_by_path_8822b(void *dm_void, bool segment_iqk)
1070{
1071 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1072 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1073 bool KFAIL = true;
1074 u8 i, kcount_limit;
1075
1076 if (*dm->band_width == 2)
1077 kcount_limit = kcount_limit_80m;
1078 else
1079 kcount_limit = kcount_limit_others;
1080
1081 while (1) {
1082 switch (dm->rf_calibrate_info.iqk_step) {
1083 case 1: /*S0 LOK*/
1084 _iqk_lok_setting_8822b(dm, ODM_RF_PATH_A);
1085 _lok_one_shot_8822b(dm, ODM_RF_PATH_A);
1086 dm->rf_calibrate_info.iqk_step++;
1087 break;
1088 case 2: /*S1 LOK*/
1089 _iqk_lok_setting_8822b(dm, ODM_RF_PATH_B);
1090 _lok_one_shot_8822b(dm, ODM_RF_PATH_B);
1091 dm->rf_calibrate_info.iqk_step++;
1092 break;
1093 case 3: /*S0 TXIQK*/
1094 _iqk_txk_setting_8822b(dm, ODM_RF_PATH_A);
1095 KFAIL = _iqk_one_shot_8822b(dm, ODM_RF_PATH_A, TXIQK);
1096 iqk_info->kcount++;
1097 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1098 "[IQK]S0TXK KFail = 0x%x\n", KFAIL);
1099
1100 if (KFAIL &&
1101 (iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK] <
1102 3))
1103 iqk_info->retry_count[0][ODM_RF_PATH_A]
1104 [TXIQK]++;
1105 else
1106 dm->rf_calibrate_info.iqk_step++;
1107 break;
1108 case 4: /*S1 TXIQK*/
1109 _iqk_txk_setting_8822b(dm, ODM_RF_PATH_B);
1110 KFAIL = _iqk_one_shot_8822b(dm, ODM_RF_PATH_B, TXIQK);
1111 iqk_info->kcount++;
1112 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1113 "[IQK]S1TXK KFail = 0x%x\n", KFAIL);
1114 if (KFAIL &&
1115 iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK] < 3)
1116 iqk_info->retry_count[0][ODM_RF_PATH_B]
1117 [TXIQK]++;
1118 else
1119 dm->rf_calibrate_info.iqk_step++;
1120 break;
1121 case 5: /*S0 RXIQK*/
1122 phydm_set_iqk_info(dm, iqk_info, 0);
1123 break;
1124 case 6: /*S1 RXIQK*/
1125 phydm_set_iqk_info(dm, iqk_info, 1);
1126 break;
1127 }
1128
1129 if (dm->rf_calibrate_info.iqk_step == 7) {
1130 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1131 "[IQK]==========LOK summary ==========\n");
1132 ODM_RT_TRACE(
1133 dm, ODM_COMP_CALIBRATION,
1134 "[IQK]PathA_LOK_notready = %d, PathB_LOK1_notready = %d\n",
1135 iqk_info->lok_fail[ODM_RF_PATH_A],
1136 iqk_info->lok_fail[ODM_RF_PATH_B]);
1137 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1138 "[IQK]==========IQK summary ==========\n");
1139 ODM_RT_TRACE(
1140 dm, ODM_COMP_CALIBRATION,
1141 "[IQK]PathA_TXIQK_fail = %d, PathB_TXIQK_fail = %d\n",
1142 iqk_info->iqk_fail_report[0][ODM_RF_PATH_A]
1143 [TXIQK],
1144 iqk_info->iqk_fail_report[0][ODM_RF_PATH_B]
1145 [TXIQK]);
1146 ODM_RT_TRACE(
1147 dm, ODM_COMP_CALIBRATION,
1148 "[IQK]PathA_RXIQK_fail = %d, PathB_RXIQK_fail = %d\n",
1149 iqk_info->iqk_fail_report[0][ODM_RF_PATH_A]
1150 [RXIQK],
1151 iqk_info->iqk_fail_report[0][ODM_RF_PATH_B]
1152 [RXIQK]);
1153 ODM_RT_TRACE(
1154 dm, ODM_COMP_CALIBRATION,
1155 "[IQK]PathA_TXIQK_retry = %d, PathB_TXIQK_retry = %d\n",
1156 iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK],
1157 iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK]);
1158 ODM_RT_TRACE(
1159 dm, ODM_COMP_CALIBRATION,
1160 "[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d, PathB_RXK1_retry = %d, PathB_RXK2_retry = %d\n",
1161 iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK1],
1162 iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK2],
1163 iqk_info->retry_count[0][ODM_RF_PATH_B][RXIQK1],
1164 iqk_info->retry_count[0][ODM_RF_PATH_B]
1165 [RXIQK2]);
1166 ODM_RT_TRACE(
1167 dm, ODM_COMP_CALIBRATION,
1168 "[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d, PathB_GS1_retry = %d, PathB_GS2_retry = %d\n",
1169 iqk_info->gs_retry_count[0][ODM_RF_PATH_A]
1170 [GSRXK1],
1171 iqk_info->gs_retry_count[0][ODM_RF_PATH_A]
1172 [GSRXK2],
1173 iqk_info->gs_retry_count[0][ODM_RF_PATH_B]
1174 [GSRXK1],
1175 iqk_info->gs_retry_count[0][ODM_RF_PATH_B]
1176 [GSRXK2]);
1177 for (i = 0; i < 2; i++) {
1178 odm_write_4byte(dm, 0x1b00,
1179 0xf8000008 | i << 1);
1180 odm_write_4byte(dm, 0x1b2c, 0x7);
1181 odm_write_4byte(dm, 0x1bcc, 0x0);
1182 }
1183 break;
1184 }
1185
1186 if (segment_iqk && (iqk_info->kcount == kcount_limit))
1187 break;
1188 }
1189}
1190
1191static void _iqk_start_iqk_8822b(struct phy_dm_struct *dm, bool segment_iqk)
1192{
1193 u32 tmp;
1194
1195 /*GNT_WL = 1*/
1196 tmp = odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK);
1197 tmp = tmp | BIT(5) | BIT(0);
1198 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK, tmp);
1199
1200 tmp = odm_get_rf_reg(dm, ODM_RF_PATH_B, 0x1, RFREGOFFSETMASK);
1201 tmp = tmp | BIT(5) | BIT(0);
1202 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x1, RFREGOFFSETMASK, tmp);
1203
1204 _iqk_iqk_by_path_8822b(dm, segment_iqk);
1205}
1206
1207static void _iq_calibrate_8822b_init(void *dm_void)
1208{
1209 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1210 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1211 u8 i, j;
1212
1213 if (iqk_info->iqk_times == 0) {
1214 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1215 "[IQK]=====>PHY_IQCalibrate_8822B_Init\n");
1216
1217 for (i = 0; i < SS_8822B; i++) {
1218 for (j = 0; j < 2; j++) {
1219 iqk_info->lok_fail[i] = true;
1220 iqk_info->iqk_fail[j][i] = true;
1221 iqk_info->iqc_matrix[j][i] = 0x20000000;
1222 }
1223 }
1224
1225 phydm_init_iqk_information(iqk_info);
1226 }
1227}
1228
1229static void _phy_iq_calibrate_8822b(struct phy_dm_struct *dm, bool reset)
1230{
1231 u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B],
1232 RF_backup[RF_REG_NUM_8822B][SS_8822B];
1233 u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550};
1234 u32 backup_bb_reg[BB_REG_NUM_8822B] = {
1235 0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00,
1236 0xeb0, 0xeb4, 0xebc, 0x1990, 0x9a4, 0xa04};
1237 u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1};
1238 bool segment_iqk = false, is_mp = false;
1239
1240 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1241
1242 if (dm->mp_mode)
1243 is_mp = true;
1244 else if (dm->is_linked)
1245 segment_iqk = true;
1246
1247 if (!is_mp)
1248 if (_iqk_reload_iqk_8822b(dm, reset))
1249 return;
1250
1251 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1252 "[IQK]==========IQK strat!!!!!==========\n");
1253
1254 ODM_RT_TRACE(
1255 dm, ODM_COMP_CALIBRATION,
1256 "[IQK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n",
1257 (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width,
1258 dm->ext_pa, dm->ext_pa_5g);
1259 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1260 "[IQK]Interface = %d, cut_version = %x\n",
1261 dm->support_interface, dm->cut_version);
1262
1263 iqk_info->iqk_times++;
1264
1265 iqk_info->kcount = 0;
1266 dm->rf_calibrate_info.iqk_total_progressing_time = 0;
1267 dm->rf_calibrate_info.iqk_step = 1;
1268 iqk_info->rxiqk_step = 1;
1269
1270 _iqk_backup_iqk_8822b(dm, 0);
1271 _iqk_backup_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg,
1272 backup_bb_reg);
1273 _iqk_backup_rf_8822b(dm, RF_backup, backup_rf_reg);
1274
1275 while (1) {
1276 if (!is_mp)
1277 dm->rf_calibrate_info.iqk_start_time =
1278 odm_get_current_time(dm);
1279
1280 _iqk_configure_macbb_8822b(dm);
1281 _iqk_afe_setting_8822b(dm, true);
1282 _iqk_rfe_setting_8822b(dm, false);
1283 _iqk_agc_bnd_int_8822b(dm);
1284 _iqk_rf_setting_8822b(dm);
1285
1286 _iqk_start_iqk_8822b(dm, segment_iqk);
1287
1288 _iqk_afe_setting_8822b(dm, false);
1289 _iqk_restore_mac_bb_8822b(dm, MAC_backup, BB_backup,
1290 backup_mac_reg, backup_bb_reg);
1291 _iqk_restore_rf_8822b(dm, backup_rf_reg, RF_backup);
1292
1293 if (!is_mp) {
1294 dm->rf_calibrate_info.iqk_progressing_time =
1295 odm_get_progressing_time(
1296 dm,
1297 dm->rf_calibrate_info.iqk_start_time);
1298 dm->rf_calibrate_info.iqk_total_progressing_time +=
1299 odm_get_progressing_time(
1300 dm,
1301 dm->rf_calibrate_info.iqk_start_time);
1302 ODM_RT_TRACE(
1303 dm, ODM_COMP_CALIBRATION,
1304 "[IQK]IQK progressing_time = %lld ms\n",
1305 dm->rf_calibrate_info.iqk_progressing_time);
1306 }
1307
1308 if (dm->rf_calibrate_info.iqk_step == 7)
1309 break;
1310
1311 iqk_info->kcount = 0;
1312 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]delay 50ms!!!\n");
1313 ODM_delay_ms(50);
1314 };
1315
1316 _iqk_backup_iqk_8822b(dm, 1);
1317 _iqk_fill_iqk_report_8822b(dm, 0);
1318
1319 if (!is_mp)
1320 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1321 "[IQK]Total IQK progressing_time = %lld ms\n",
1322 dm->rf_calibrate_info.iqk_total_progressing_time);
1323
1324 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1325 "[IQK]==========IQK end!!!!!==========\n");
1326}
1327
1328static void _phy_iq_calibrate_by_fw_8822b(void *dm_void, u8 clear) {}
1329
1330/*IQK version:v3.3, NCTL v0.6*/
1331/*1.The new gainsearch method for RXIQK*/
1332/*2.The new format of IQK report register: 0x1be8/0x1bec*/
1333/*3. add the option of segment IQK*/
1334void phy_iq_calibrate_8822b(void *dm_void, bool clear)
1335{
1336 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1337
1338 dm->iqk_fw_offload = 0;
1339
1340 /*FW IQK*/
1341 if (dm->iqk_fw_offload) {
1342 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
1343 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1344 dm->rf_calibrate_info.is_iqk_in_progress = true;
1345 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1346
1347 dm->rf_calibrate_info.iqk_start_time =
1348 odm_get_current_time(dm);
1349
1350 odm_write_4byte(dm, 0x1b00, 0xf8000008);
1351 odm_set_bb_reg(dm, 0x1bf0, 0xff000000, 0xff);
1352 ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
1353 "[IQK]0x1bf0 = 0x%x\n",
1354 odm_read_4byte(dm, 0x1bf0));
1355
1356 _phy_iq_calibrate_by_fw_8822b(dm, clear);
1357 phydm_get_read_counter(dm);
1358
1359 dm->rf_calibrate_info.iqk_progressing_time =
1360 odm_get_progressing_time(
1361 dm,
1362 dm->rf_calibrate_info.iqk_start_time);
1363
1364 ODM_RT_TRACE(
1365 dm, ODM_COMP_CALIBRATION,
1366 "[IQK]IQK progressing_time = %lld ms\n",
1367 dm->rf_calibrate_info.iqk_progressing_time);
1368
1369 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1370 dm->rf_calibrate_info.is_iqk_in_progress = false;
1371 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1372 } else {
1373 ODM_RT_TRACE(
1374 dm, ODM_COMP_CALIBRATION,
1375 "== Return the IQK CMD, because the IQK in Progress ==\n");
1376 }
1377
1378 } else {
1379 _iq_calibrate_8822b_init(dm_void);
1380
1381 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
1382 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1383 dm->rf_calibrate_info.is_iqk_in_progress = true;
1384 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1385 if (dm->mp_mode)
1386 dm->rf_calibrate_info.iqk_start_time =
1387 odm_get_current_time(dm);
1388
1389 _phy_iq_calibrate_8822b(dm, clear);
1390 if (dm->mp_mode) {
1391 dm->rf_calibrate_info.iqk_progressing_time =
1392 odm_get_progressing_time(
1393 dm, dm->rf_calibrate_info
1394 .iqk_start_time);
1395 ODM_RT_TRACE(
1396 dm, ODM_COMP_CALIBRATION,
1397 "[IQK]IQK progressing_time = %lld ms\n",
1398 dm->rf_calibrate_info
1399 .iqk_progressing_time);
1400 }
1401 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1402 dm->rf_calibrate_info.is_iqk_in_progress = false;
1403 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1404 } else {
1405 ODM_RT_TRACE(
1406 dm, ODM_COMP_CALIBRATION,
1407 "[IQK]== Return the IQK CMD, because the IQK in Progress ==\n");
1408 }
1409 }
1410}
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_iqk_8822b.h b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_iqk_8822b.h
new file mode 100644
index 000000000000..ea19deb512d5
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_iqk_8822b.h
@@ -0,0 +1,48 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __PHYDM_IQK_8822B_H__
26#define __PHYDM_IQK_8822B_H__
27
28/*--------------------------Define Parameters-------------------------------*/
29#define MAC_REG_NUM_8822B 2
30#define BB_REG_NUM_8822B 13
31#define RF_REG_NUM_8822B 5
32
33#define LOK_delay_8822B 2
34#define GS_delay_8822B 2
35#define WBIQK_delay_8822B 2
36
37#define TXIQK 0
38#define RXIQK 1
39#define SS_8822B 2
40
41/*------------------------End Define Parameters-------------------------------*/
42
43void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
44 u8 threshold);
45
46void phy_iq_calibrate_8822b(void *dm_void, bool clear);
47
48#endif /* #ifndef __PHYDM_IQK_8822B_H__*/
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_regconfig8822b.c b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_regconfig8822b.c
new file mode 100644
index 000000000000..644fca822c61
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_regconfig8822b.c
@@ -0,0 +1,168 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../mp_precomp.h"
27#include "../phydm_precomp.h"
28
29void odm_config_rf_reg_8822b(struct phy_dm_struct *dm, u32 addr, u32 data,
30 enum odm_rf_radio_path RF_PATH, u32 reg_addr)
31{
32 if (addr == 0xffe) {
33 ODM_sleep_ms(50);
34 } else if (addr == 0xfe) {
35 ODM_delay_us(100);
36 } else {
37 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
38
39 /* Add 1us delay between BB/RF register setting. */
40 ODM_delay_us(1);
41 }
42}
43
44void odm_config_rf_radio_a_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
45{
46 u32 content = 0x1000; /* RF_Content: radioa_txt */
47 u32 maskfor_phy_set = (u32)(content & 0xE000);
48
49 odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_A,
50 addr | maskfor_phy_set);
51
52 ODM_RT_TRACE(
53 dm, ODM_COMP_INIT,
54 "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
55 addr, data);
56}
57
58void odm_config_rf_radio_b_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
59{
60 u32 content = 0x1001; /* RF_Content: radiob_txt */
61 u32 maskfor_phy_set = (u32)(content & 0xE000);
62
63 odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_B,
64 addr | maskfor_phy_set);
65
66 ODM_RT_TRACE(
67 dm, ODM_COMP_INIT,
68 "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
69 addr, data);
70}
71
72void odm_config_mac_8822b(struct phy_dm_struct *dm, u32 addr, u8 data)
73{
74 odm_write_1byte(dm, addr, data);
75 ODM_RT_TRACE(
76 dm, ODM_COMP_INIT,
77 "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
78 addr, data);
79}
80
81void odm_update_agc_big_jump_lmt_8822b(struct phy_dm_struct *dm, u32 addr,
82 u32 data)
83{
84 struct dig_thres *dig_tab = &dm->dm_dig_table;
85 u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);
86 u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);
87 u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);
88 static bool is_limit;
89
90 if (addr != 0x81c)
91 return;
92
93 if (bb_gain_idx > 0x3c) {
94 if ((rf_gain_idx == dig_tab->rf_gain_idx) && !is_limit) {
95 is_limit = true;
96 dig_tab->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;
97 ODM_RT_TRACE(
98 dm, ODM_COMP_DIG,
99 "===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n",
100 agc_table_idx,
101 dig_tab->big_jump_lmt[agc_table_idx]);
102 }
103 } else {
104 is_limit = false;
105 }
106
107 dig_tab->rf_gain_idx = rf_gain_idx;
108}
109
110void odm_config_bb_agc_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
111 u32 data)
112{
113 odm_update_agc_big_jump_lmt_8822b(dm, addr, data);
114
115 odm_set_bb_reg(dm, addr, bitmask, data);
116
117 /* Add 1us delay between BB/RF register setting. */
118 ODM_delay_us(1);
119
120 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [AGC_TAB] %08X %08X\n",
121 __func__, addr, data);
122}
123
124void odm_config_bb_phy_reg_pg_8822b(struct phy_dm_struct *dm, u32 band,
125 u32 rf_path, u32 tx_num, u32 addr,
126 u32 bitmask, u32 data)
127{
128 if (addr == 0xfe || addr == 0xffe) {
129 ODM_sleep_ms(50);
130 } else {
131 phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num,
132 addr, bitmask, data);
133 }
134 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X %08X\n",
135 __func__, addr, bitmask, data);
136}
137
138void odm_config_bb_phy_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
139 u32 data)
140{
141 if (addr == 0xfe)
142 ODM_sleep_ms(50);
143 else if (addr == 0xfd)
144 ODM_delay_ms(5);
145 else if (addr == 0xfc)
146 ODM_delay_ms(1);
147 else if (addr == 0xfb)
148 ODM_delay_us(50);
149 else if (addr == 0xfa)
150 ODM_delay_us(5);
151 else if (addr == 0xf9)
152 ODM_delay_us(1);
153 else
154 odm_set_bb_reg(dm, addr, bitmask, data);
155
156 /* Add 1us delay between BB/RF register setting. */
157 ODM_delay_us(1);
158 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X\n",
159 __func__, addr, data);
160}
161
162void odm_config_bb_txpwr_lmt_8822b(struct phy_dm_struct *dm, u8 *regulation,
163 u8 *band, u8 *bandwidth, u8 *rate_section,
164 u8 *rf_path, u8 *channel, u8 *power_limit)
165{
166 phy_set_tx_power_limit(dm, regulation, band, bandwidth, rate_section,
167 rf_path, channel, power_limit);
168}
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_regconfig8822b.h b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_regconfig8822b.h
new file mode 100644
index 000000000000..4817cf6b1ed9
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_regconfig8822b.h
@@ -0,0 +1,54 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __INC_ODM_REGCONFIG_H_8822B
26#define __INC_ODM_REGCONFIG_H_8822B
27
28void odm_config_rf_reg_8822b(struct phy_dm_struct *dm, u32 addr, u32 data,
29 enum odm_rf_radio_path RF_PATH, u32 reg_addr);
30
31void odm_config_rf_radio_a_8822b(struct phy_dm_struct *dm, u32 addr, u32 data);
32
33void odm_config_rf_radio_b_8822b(struct phy_dm_struct *dm, u32 addr, u32 data);
34
35void odm_config_mac_8822b(struct phy_dm_struct *dm, u32 addr, u8 data);
36
37void odm_update_agc_big_jump_lmt_8822b(struct phy_dm_struct *dm, u32 addr,
38 u32 data);
39
40void odm_config_bb_agc_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
41 u32 data);
42
43void odm_config_bb_phy_reg_pg_8822b(struct phy_dm_struct *dm, u32 band,
44 u32 rf_path, u32 tx_num, u32 addr,
45 u32 bitmask, u32 data);
46
47void odm_config_bb_phy_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
48 u32 data);
49
50void odm_config_bb_txpwr_lmt_8822b(struct phy_dm_struct *dm, u8 *regulation,
51 u8 *band, u8 *bandwidth, u8 *rate_section,
52 u8 *rf_path, u8 *channel, u8 *power_limit);
53
54#endif /* RTL8822B_SUPPORT == 1*/
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_rtl8822b.c b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_rtl8822b.c
new file mode 100644
index 000000000000..59adabda09de
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_rtl8822b.c
@@ -0,0 +1,225 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../mp_precomp.h"
27#include "../phydm_precomp.h"
28
29static void phydm_dynamic_switch_htstf_mumimo_8822b(struct phy_dm_struct *dm)
30{
31 /*if rssi > 40dBm, enable HT-STF gain controller,
32 *otherwise, if rssi < 40dBm, disable the controller
33 */
34 /*add by Chun-Hung Ho 20160711 */
35 if (dm->rssi_min >= 40)
36 odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x1);
37 else if (dm->rssi_min < 35)
38 odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0);
39
40 ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s, rssi_min = %d\n", __func__,
41 dm->rssi_min);
42}
43
44static void _set_tx_a_cali_value(struct phy_dm_struct *dm, u8 rf_path,
45 u8 offset, u8 tx_a_bias_offset)
46{
47 u32 modi_tx_a_value = 0;
48 u8 tmp1_byte = 0;
49 bool is_minus = false;
50 u8 comp_value = 0;
51
52 switch (offset) {
53 case 0x0:
54 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10124);
55 break;
56 case 0x1:
57 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10524);
58 break;
59 case 0x2:
60 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10924);
61 break;
62 case 0x3:
63 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10D24);
64 break;
65 case 0x4:
66 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30164);
67 break;
68 case 0x5:
69 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30564);
70 break;
71 case 0x6:
72 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30964);
73 break;
74 case 0x7:
75 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30D64);
76 break;
77 case 0x8:
78 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50195);
79 break;
80 case 0x9:
81 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50595);
82 break;
83 case 0xa:
84 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50995);
85 break;
86 case 0xb:
87 odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50D95);
88 break;
89 default:
90 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
91 "Invalid TxA band offset...\n");
92 return;
93 }
94
95 /* Get TxA value */
96 modi_tx_a_value = odm_get_rf_reg(dm, rf_path, 0x61, 0xFFFFF);
97 tmp1_byte = (u8)modi_tx_a_value & (BIT(3) | BIT(2) | BIT(1) | BIT(0));
98
99 /* check how much need to calibration */
100 switch (tx_a_bias_offset) {
101 case 0xF6:
102 is_minus = true;
103 comp_value = 3;
104 break;
105
106 case 0xF4:
107 is_minus = true;
108 comp_value = 2;
109 break;
110
111 case 0xF2:
112 is_minus = true;
113 comp_value = 1;
114 break;
115
116 case 0xF3:
117 is_minus = false;
118 comp_value = 1;
119 break;
120
121 case 0xF5:
122 is_minus = false;
123 comp_value = 2;
124 break;
125
126 case 0xF7:
127 is_minus = false;
128 comp_value = 3;
129 break;
130
131 case 0xF9:
132 is_minus = false;
133 comp_value = 4;
134 break;
135
136 /* do nothing case */
137 case 0xF0:
138 default:
139 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
140 "No need to do TxA bias current calibration\n");
141 return;
142 }
143
144 /* calc correct value to calibrate */
145 if (is_minus) {
146 if (tmp1_byte >= comp_value) {
147 tmp1_byte -= comp_value;
148 /*modi_tx_a_value += tmp1_byte;*/
149 } else {
150 tmp1_byte = 0;
151 }
152 } else {
153 tmp1_byte += comp_value;
154 if (tmp1_byte >= 7)
155 tmp1_byte = 7;
156 }
157
158 /* Write back to RF reg */
159 odm_set_rf_reg(dm, rf_path, 0x30, 0xFFFF,
160 (offset << 12 | (modi_tx_a_value & 0xFF0) | tmp1_byte));
161}
162
163static void _txa_bias_cali_4_each_path(struct phy_dm_struct *dm, u8 rf_path,
164 u8 efuse_value)
165{
166 /* switch on set TxA bias */
167 odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x200);
168
169 /* Set 12 sets of TxA value */
170 _set_tx_a_cali_value(dm, rf_path, 0x0, efuse_value);
171 _set_tx_a_cali_value(dm, rf_path, 0x1, efuse_value);
172 _set_tx_a_cali_value(dm, rf_path, 0x2, efuse_value);
173 _set_tx_a_cali_value(dm, rf_path, 0x3, efuse_value);
174 _set_tx_a_cali_value(dm, rf_path, 0x4, efuse_value);
175 _set_tx_a_cali_value(dm, rf_path, 0x5, efuse_value);
176 _set_tx_a_cali_value(dm, rf_path, 0x6, efuse_value);
177 _set_tx_a_cali_value(dm, rf_path, 0x7, efuse_value);
178 _set_tx_a_cali_value(dm, rf_path, 0x8, efuse_value);
179 _set_tx_a_cali_value(dm, rf_path, 0x9, efuse_value);
180 _set_tx_a_cali_value(dm, rf_path, 0xa, efuse_value);
181 _set_tx_a_cali_value(dm, rf_path, 0xb, efuse_value);
182
183 /* switch off set TxA bias */
184 odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x0);
185}
186
187/*
188 * for 8822B PCIE D-cut patch only
189 * Normal driver and MP driver need this patch
190 */
191
192void phydm_txcurrentcalibration(struct phy_dm_struct *dm)
193{
194 u8 efuse0x3D8, efuse0x3D7;
195 u32 orig_rf0x18_path_a = 0, orig_rf0x18_path_b = 0;
196
197 /* save original 0x18 value */
198 orig_rf0x18_path_a = odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xFFFFF);
199 orig_rf0x18_path_b = odm_get_rf_reg(dm, ODM_RF_PATH_B, 0x18, 0xFFFFF);
200
201 /* define efuse content */
202 efuse0x3D8 = dm->efuse0x3d8;
203 efuse0x3D7 = dm->efuse0x3d7;
204
205 /* check efuse content to judge whether need to calibration or not */
206 if (efuse0x3D7 == 0xFF) {
207 ODM_RT_TRACE(
208 dm, ODM_COMP_COMMON,
209 "efuse content 0x3D7 == 0xFF, No need to do TxA cali\n");
210 return;
211 }
212
213 /* write RF register for calibration */
214 _txa_bias_cali_4_each_path(dm, ODM_RF_PATH_A, efuse0x3D7);
215 _txa_bias_cali_4_each_path(dm, ODM_RF_PATH_B, efuse0x3D8);
216
217 /* restore original 0x18 value */
218 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xFFFFF, orig_rf0x18_path_a);
219 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x18, 0xFFFFF, orig_rf0x18_path_b);
220}
221
222void phydm_hwsetting_8822b(struct phy_dm_struct *dm)
223{
224 phydm_dynamic_switch_htstf_mumimo_8822b(dm);
225}
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_rtl8822b.h b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_rtl8822b.h
new file mode 100644
index 000000000000..af91a6f958ed
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/phydm_rtl8822b.h
@@ -0,0 +1,30 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __ODM_RTL8822B_H__
26#define __ODM_RTL8822B_H__
27
28void phydm_hwsetting_8822b(struct phy_dm_struct *dm);
29
30#endif /* #define __ODM_RTL8822B_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/rtl8822b/version_rtl8822b.h b/drivers/staging/rtlwifi/phydm/rtl8822b/version_rtl8822b.h
new file mode 100644
index 000000000000..ad0d32fce0a9
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl8822b/version_rtl8822b.h
@@ -0,0 +1,34 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25/*RTL8822B PHY Parameters*/
26/*
27 * [Caution]
28 * Since 01/Aug/2015, the commit rules will be simplified.
29 * You do not need to fill up the version.h anymore,
30 * only the maintenance supervisor fills it before formal release.
31 */
32#define RELEASE_DATE_8822B 20161103
33#define COMMIT_BY_8822B "BB_JOE"
34#define RELEASE_VERSION_8822B 67
diff --git a/drivers/staging/rtlwifi/phydm/rtl_phydm.c b/drivers/staging/rtlwifi/phydm/rtl_phydm.c
new file mode 100644
index 000000000000..85e490d3601f
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl_phydm.c
@@ -0,0 +1,874 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#include "mp_precomp.h"
26#include "phydm_precomp.h"
27#include <linux/module.h>
28
29static int _rtl_phydm_init_com_info(struct rtl_priv *rtlpriv,
30 enum odm_ic_type ic_type,
31 struct rtl_phydm_params *params)
32{
33 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
34 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
35 struct rtl_phy *rtlphy = &rtlpriv->phy;
36 struct rtl_mac *mac = rtl_mac(rtlpriv);
37 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
38 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
39 u8 odm_board_type = ODM_BOARD_DEFAULT;
40 u32 support_ability;
41 int i;
42
43 dm->adapter = (void *)rtlpriv;
44
45 odm_cmn_info_init(dm, ODM_CMNINFO_PLATFORM, ODM_CE);
46
47 odm_cmn_info_init(dm, ODM_CMNINFO_IC_TYPE, ic_type);
48
49 odm_cmn_info_init(dm, ODM_CMNINFO_INTERFACE, ODM_ITRF_PCIE);
50
51 odm_cmn_info_init(dm, ODM_CMNINFO_MP_TEST_CHIP, params->mp_chip);
52
53 odm_cmn_info_init(dm, ODM_CMNINFO_PATCH_ID, rtlhal->oem_id);
54
55 odm_cmn_info_init(dm, ODM_CMNINFO_BWIFI_TEST, 1);
56
57 if (rtlphy->rf_type == RF_1T1R)
58 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_1T1R);
59 else if (rtlphy->rf_type == RF_1T2R)
60 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_1T2R);
61 else if (rtlphy->rf_type == RF_2T2R)
62 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_2T2R);
63 else if (rtlphy->rf_type == RF_2T2R_GREEN)
64 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_2T2R_GREEN);
65 else if (rtlphy->rf_type == RF_2T3R)
66 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_2T3R);
67 else if (rtlphy->rf_type == RF_2T4R)
68 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_2T4R);
69 else if (rtlphy->rf_type == RF_3T3R)
70 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_3T3R);
71 else if (rtlphy->rf_type == RF_3T4R)
72 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_3T4R);
73 else if (rtlphy->rf_type == RF_4T4R)
74 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_4T4R);
75 else
76 odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_XTXR);
77
78 /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
79 if (rtlhal->external_lna_2g != 0) {
80 odm_board_type |= ODM_BOARD_EXT_LNA;
81 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, 1);
82 }
83 if (rtlhal->external_lna_5g != 0) {
84 odm_board_type |= ODM_BOARD_EXT_LNA_5G;
85 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, 1);
86 }
87 if (rtlhal->external_pa_2g != 0) {
88 odm_board_type |= ODM_BOARD_EXT_PA;
89 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, 1);
90 }
91 if (rtlhal->external_pa_5g != 0) {
92 odm_board_type |= ODM_BOARD_EXT_PA_5G;
93 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, 1);
94 }
95 if (rtlpriv->cfg->ops->get_btc_status())
96 odm_board_type |= ODM_BOARD_BT;
97
98 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
99 /* 1 ============== End of BoardType ============== */
100
101 odm_cmn_info_init(dm, ODM_CMNINFO_GPA, rtlhal->type_gpa);
102 odm_cmn_info_init(dm, ODM_CMNINFO_APA, rtlhal->type_apa);
103 odm_cmn_info_init(dm, ODM_CMNINFO_GLNA, rtlhal->type_glna);
104 odm_cmn_info_init(dm, ODM_CMNINFO_ALNA, rtlhal->type_alna);
105
106 odm_cmn_info_init(dm, ODM_CMNINFO_RFE_TYPE, rtlhal->rfe_type);
107
108 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_TRSW, 0);
109
110 /*Add by YuChen for kfree init*/
111 odm_cmn_info_init(dm, ODM_CMNINFO_REGRFKFREEENABLE, 2);
112 odm_cmn_info_init(dm, ODM_CMNINFO_RFKFREEENABLE, 0);
113
114 /*Antenna diversity relative parameters*/
115 odm_cmn_info_hook(dm, ODM_CMNINFO_ANT_DIV,
116 &rtlefuse->antenna_div_cfg);
117 odm_cmn_info_init(dm, ODM_CMNINFO_RF_ANTENNA_TYPE,
118 rtlefuse->antenna_div_type);
119 odm_cmn_info_init(dm, ODM_CMNINFO_BE_FIX_TX_ANT, 0);
120 odm_cmn_info_init(dm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 0);
121
122 /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
123 odm_cmn_info_init(dm, ODM_CMNINFO_EFUSE0X3D7, params->efuse0x3d7);
124 odm_cmn_info_init(dm, ODM_CMNINFO_EFUSE0X3D8, params->efuse0x3d8);
125
126 /*Add by YuChen for adaptivity init*/
127 odm_cmn_info_hook(dm, ODM_CMNINFO_ADAPTIVITY,
128 &rtlpriv->phydm.adaptivity_en);
129 phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE,
130 false);
131 phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_DCBACKOFF, 0);
132 phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
133 false);
134 phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_TH_L2H_INI, 0);
135 phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, 0);
136
137 odm_cmn_info_init(dm, ODM_CMNINFO_IQKFWOFFLOAD, 0);
138
139 /* Pointer reference */
140 odm_cmn_info_hook(dm, ODM_CMNINFO_TX_UNI,
141 &rtlpriv->stats.txbytesunicast);
142 odm_cmn_info_hook(dm, ODM_CMNINFO_RX_UNI,
143 &rtlpriv->stats.rxbytesunicast);
144 odm_cmn_info_hook(dm, ODM_CMNINFO_BAND, &rtlhal->current_bandtype);
145 odm_cmn_info_hook(dm, ODM_CMNINFO_FORCED_RATE,
146 &rtlpriv->phydm.forced_data_rate);
147 odm_cmn_info_hook(dm, ODM_CMNINFO_FORCED_IGI_LB,
148 &rtlpriv->phydm.forced_igi_lb);
149
150 odm_cmn_info_hook(dm, ODM_CMNINFO_SEC_CHNL_OFFSET,
151 &mac->cur_40_prime_sc);
152 odm_cmn_info_hook(dm, ODM_CMNINFO_BW, &rtlphy->current_chan_bw);
153 odm_cmn_info_hook(dm, ODM_CMNINFO_CHNL, &rtlphy->current_channel);
154
155 odm_cmn_info_hook(dm, ODM_CMNINFO_SCAN, &mac->act_scanning);
156 odm_cmn_info_hook(dm, ODM_CMNINFO_POWER_SAVING,
157 &ppsc->dot11_psmode); /* may add new boolean flag */
158 /*Add by Yuchen for phydm beamforming*/
159 odm_cmn_info_hook(dm, ODM_CMNINFO_TX_TP,
160 &rtlpriv->stats.txbytesunicast_inperiod_tp);
161 odm_cmn_info_hook(dm, ODM_CMNINFO_RX_TP,
162 &rtlpriv->stats.rxbytesunicast_inperiod_tp);
163 odm_cmn_info_hook(dm, ODM_CMNINFO_ANT_TEST,
164 &rtlpriv->phydm.antenna_test);
165 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
166 odm_cmn_info_ptr_array_hook(dm, ODM_CMNINFO_STA_STATUS, i,
167 NULL);
168
169 phydm_init_debug_setting(dm);
170
171 odm_cmn_info_init(dm, ODM_CMNINFO_FAB_VER, params->fab_ver);
172 odm_cmn_info_init(dm, ODM_CMNINFO_CUT_VER, params->cut_ver);
173
174 /* after ifup, ability is updated again */
175 support_ability = ODM_RF_CALIBRATION | ODM_RF_TX_PWR_TRACK;
176 odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY, support_ability);
177
178 return 0;
179}
180
181static int rtl_phydm_init_priv(struct rtl_priv *rtlpriv,
182 struct rtl_phydm_params *params)
183{
184 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
185 enum odm_ic_type ic;
186
187 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
188 ic = ODM_RTL8822B;
189 else
190 return 0;
191
192 rtlpriv->phydm.internal =
193 kzalloc(sizeof(struct phy_dm_struct), GFP_KERNEL);
194
195 _rtl_phydm_init_com_info(rtlpriv, ic, params);
196
197 odm_init_all_timers(dm);
198
199 return 1;
200}
201
202static int rtl_phydm_deinit_priv(struct rtl_priv *rtlpriv)
203{
204 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
205
206 odm_cancel_all_timers(dm);
207
208 kfree(rtlpriv->phydm.internal);
209 rtlpriv->phydm.internal = NULL;
210
211 return 0;
212}
213
214static bool rtl_phydm_load_txpower_by_rate(struct rtl_priv *rtlpriv)
215{
216 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
217 enum hal_status status;
218
219 status = odm_config_bb_with_header_file(dm, CONFIG_BB_PHY_REG_PG);
220 if (status != HAL_STATUS_SUCCESS)
221 return false;
222
223 return true;
224}
225
226static bool rtl_phydm_load_txpower_limit(struct rtl_priv *rtlpriv)
227{
228 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
229 enum hal_status status;
230
231 if (IS_HARDWARE_TYPE_8822B(rtlpriv)) {
232 odm_read_and_config_mp_8822b_txpwr_lmt(dm);
233 } else {
234 status = odm_config_rf_with_header_file(dm, CONFIG_RF_TXPWR_LMT,
235 0);
236 if (status != HAL_STATUS_SUCCESS)
237 return false;
238 }
239
240 return true;
241}
242
243static int rtl_phydm_init_dm(struct rtl_priv *rtlpriv)
244{
245 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
246 u32 support_ability = 0;
247
248 /* clang-format off */
249 support_ability = 0
250 | ODM_BB_DIG
251 | ODM_BB_RA_MASK
252 | ODM_BB_DYNAMIC_TXPWR
253 | ODM_BB_FA_CNT
254 | ODM_BB_RSSI_MONITOR
255 | ODM_BB_CCK_PD
256 /* | ODM_BB_PWR_SAVE*/
257 | ODM_BB_CFO_TRACKING
258 | ODM_MAC_EDCA_TURBO
259 | ODM_RF_TX_PWR_TRACK
260 | ODM_RF_CALIBRATION
261 | ODM_BB_NHM_CNT
262 /* | ODM_BB_PWR_TRAIN*/
263 ;
264 /* clang-format on */
265
266 odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY, support_ability);
267
268 odm_dm_init(dm);
269
270 return 0;
271}
272
273static int rtl_phydm_deinit_dm(struct rtl_priv *rtlpriv)
274{
275 return 0;
276}
277
278static int rtl_phydm_reset_dm(struct rtl_priv *rtlpriv)
279{
280 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
281
282 odm_dm_reset(dm);
283
284 return 0;
285}
286
287static bool rtl_phydm_parameter_init(struct rtl_priv *rtlpriv, bool post)
288{
289 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
290
291 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
292 return config_phydm_parameter_init(dm, post ? ODM_POST_SETTING :
293 ODM_PRE_SETTING);
294
295 return false;
296}
297
298static bool rtl_phydm_phy_bb_config(struct rtl_priv *rtlpriv)
299{
300 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
301 enum hal_status status;
302
303 status = odm_config_bb_with_header_file(dm, CONFIG_BB_PHY_REG);
304 if (status != HAL_STATUS_SUCCESS)
305 return false;
306
307 status = odm_config_bb_with_header_file(dm, CONFIG_BB_AGC_TAB);
308 if (status != HAL_STATUS_SUCCESS)
309 return false;
310
311 return true;
312}
313
314static bool rtl_phydm_phy_rf_config(struct rtl_priv *rtlpriv)
315{
316 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
317 struct rtl_phy *rtlphy = &rtlpriv->phy;
318 enum hal_status status;
319 enum odm_rf_radio_path rfpath;
320
321 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
322 status = odm_config_rf_with_header_file(dm, CONFIG_RF_RADIO,
323 rfpath);
324 if (status != HAL_STATUS_SUCCESS)
325 return false;
326 }
327
328 status = odm_config_rf_with_tx_pwr_track_header_file(dm);
329 if (status != HAL_STATUS_SUCCESS)
330 return false;
331
332 return true;
333}
334
335static bool rtl_phydm_phy_mac_config(struct rtl_priv *rtlpriv)
336{
337 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
338 enum hal_status status;
339
340 status = odm_config_mac_with_header_file(dm);
341 if (status != HAL_STATUS_SUCCESS)
342 return false;
343
344 return true;
345}
346
347static bool rtl_phydm_trx_mode(struct rtl_priv *rtlpriv,
348 enum radio_mask tx_path, enum radio_mask rx_path,
349 bool is_tx2_path)
350{
351 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
352
353 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
354 return config_phydm_trx_mode_8822b(dm,
355 (enum odm_rf_path)tx_path,
356 (enum odm_rf_path)rx_path,
357 is_tx2_path);
358
359 return false;
360}
361
362static bool rtl_phydm_watchdog(struct rtl_priv *rtlpriv)
363{
364 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
365 struct rtl_mac *mac = rtl_mac(rtlpriv);
366 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
367 bool fw_current_inpsmode = false;
368 bool fw_ps_awake = true;
369 u8 is_linked = false;
370 u8 bsta_state = false;
371 u8 is_bt_enabled = false;
372
373 /* check whether do watchdog */
374 rtlpriv->cfg->ops->get_hw_reg(rtlpriv->hw, HW_VAR_FW_PSMODE_STATUS,
375 (u8 *)(&fw_current_inpsmode));
376 rtlpriv->cfg->ops->get_hw_reg(rtlpriv->hw, HW_VAR_FWLPS_RF_ON,
377 (u8 *)(&fw_ps_awake));
378 if (ppsc->p2p_ps_info.p2p_ps_mode)
379 fw_ps_awake = false;
380
381 if ((ppsc->rfpwr_state == ERFON) &&
382 ((!fw_current_inpsmode) && fw_ps_awake) &&
383 (!ppsc->rfchange_inprogress))
384 ;
385 else
386 return false;
387
388 /* update common info before doing watchdog */
389 if (mac->link_state >= MAC80211_LINKED) {
390 is_linked = true;
391 if (mac->vif && mac->vif->type == NL80211_IFTYPE_STATION)
392 bsta_state = true;
393 }
394
395 if (rtlpriv->cfg->ops->get_btc_status())
396 is_bt_enabled = !rtlpriv->btcoexist.btc_ops->btc_is_bt_disabled(
397 rtlpriv);
398
399 odm_cmn_info_update(dm, ODM_CMNINFO_LINK, is_linked);
400 odm_cmn_info_update(dm, ODM_CMNINFO_STATION_STATE, bsta_state);
401 odm_cmn_info_update(dm, ODM_CMNINFO_BT_ENABLED, is_bt_enabled);
402
403 /* do watchdog */
404 odm_dm_watchdog(dm);
405
406 return true;
407}
408
409static bool rtl_phydm_switch_band(struct rtl_priv *rtlpriv, u8 central_ch)
410{
411 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
412
413 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
414 return config_phydm_switch_band_8822b(dm, central_ch);
415
416 return false;
417}
418
419static bool rtl_phydm_switch_channel(struct rtl_priv *rtlpriv, u8 central_ch)
420{
421 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
422
423 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
424 return config_phydm_switch_channel_8822b(dm, central_ch);
425
426 return false;
427}
428
429static bool rtl_phydm_switch_bandwidth(struct rtl_priv *rtlpriv,
430 u8 primary_ch_idx,
431 enum ht_channel_width bandwidth)
432{
433 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
434 enum odm_bw odm_bw = (enum odm_bw)bandwidth;
435
436 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
437 return config_phydm_switch_bandwidth_8822b(dm, primary_ch_idx,
438 odm_bw);
439
440 return false;
441}
442
443static bool rtl_phydm_iq_calibrate(struct rtl_priv *rtlpriv)
444{
445 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
446
447 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
448 phy_iq_calibrate_8822b(dm, false);
449 else
450 return false;
451
452 return true;
453}
454
455static bool rtl_phydm_clear_txpowertracking_state(struct rtl_priv *rtlpriv)
456{
457 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
458
459 odm_clear_txpowertracking_state(dm);
460
461 return true;
462}
463
464static bool rtl_phydm_pause_dig(struct rtl_priv *rtlpriv, bool pause)
465{
466 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
467
468 if (pause)
469 odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x1e);
470 else /* resume */
471 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, 0xff);
472
473 return true;
474}
475
476static u32 rtl_phydm_read_rf_reg(struct rtl_priv *rtlpriv,
477 enum radio_path rfpath, u32 addr, u32 mask)
478{
479 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
480 enum odm_rf_radio_path odm_rfpath = (enum odm_rf_radio_path)rfpath;
481
482 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
483 return config_phydm_read_rf_reg_8822b(dm, odm_rfpath, addr,
484 mask);
485
486 return -1;
487}
488
489static bool rtl_phydm_write_rf_reg(struct rtl_priv *rtlpriv,
490 enum radio_path rfpath, u32 addr, u32 mask,
491 u32 data)
492{
493 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
494 enum odm_rf_radio_path odm_rfpath = (enum odm_rf_radio_path)rfpath;
495
496 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
497 return config_phydm_write_rf_reg_8822b(dm, odm_rfpath, addr,
498 mask, data);
499
500 return false;
501}
502
503static u8 rtl_phydm_read_txagc(struct rtl_priv *rtlpriv, enum radio_path rfpath,
504 u8 hw_rate)
505{
506 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
507 enum odm_rf_radio_path odm_rfpath = (enum odm_rf_radio_path)rfpath;
508
509 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
510 return config_phydm_read_txagc_8822b(dm, odm_rfpath, hw_rate);
511
512 return -1;
513}
514
515static bool rtl_phydm_write_txagc(struct rtl_priv *rtlpriv, u32 power_index,
516 enum radio_path rfpath, u8 hw_rate)
517{
518 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
519 enum odm_rf_radio_path odm_rfpath = (enum odm_rf_radio_path)rfpath;
520
521 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
522 return config_phydm_write_txagc_8822b(dm, power_index,
523 odm_rfpath, hw_rate);
524
525 return false;
526}
527
528static bool rtl_phydm_c2h_content_parsing(struct rtl_priv *rtlpriv, u8 cmd_id,
529 u8 cmd_len, u8 *content)
530{
531 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
532
533 if (phydm_c2H_content_parsing(dm, cmd_id, cmd_len, content))
534 return true;
535
536 return false;
537}
538
539static bool rtl_phydm_query_phy_status(struct rtl_priv *rtlpriv, u8 *phystrpt,
540 struct ieee80211_hdr *hdr,
541 struct rtl_stats *pstatus)
542{
543 /* NOTE: phystrpt may be NULL, and need to fill default value */
544
545 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
546 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
547 struct rtl_mac *mac = rtl_mac(rtlpriv);
548 struct dm_per_pkt_info pktinfo; /* input of pydm */
549 struct dm_phy_status_info phy_info; /* output of phydm */
550 __le16 fc = hdr->frame_control;
551
552 /* fill driver pstatus */
553 ether_addr_copy(pstatus->psaddr, ieee80211_get_SA(hdr));
554
555 /* fill pktinfo */
556 memset(&pktinfo, 0, sizeof(pktinfo));
557
558 pktinfo.data_rate = pstatus->rate;
559
560 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION) {
561 pktinfo.station_id = 0;
562 } else {
563 /* TODO: use rtl_find_sta() to find ID */
564 pktinfo.station_id = 0xFF;
565 }
566
567 pktinfo.is_packet_match_bssid =
568 (!ieee80211_is_ctl(fc) &&
569 (ether_addr_equal(mac->bssid,
570 ieee80211_has_tods(fc) ?
571 hdr->addr1 :
572 ieee80211_has_fromds(fc) ?
573 hdr->addr2 :
574 hdr->addr3)) &&
575 (!pstatus->hwerror) && (!pstatus->crc) && (!pstatus->icv));
576 pktinfo.is_packet_to_self =
577 pktinfo.is_packet_match_bssid &&
578 (ether_addr_equal(hdr->addr1, rtlefuse->dev_addr));
579 pktinfo.is_to_self = (!pstatus->icv) && (!pstatus->crc) &&
580 (ether_addr_equal(hdr->addr1, rtlefuse->dev_addr));
581 pktinfo.is_packet_beacon = (ieee80211_is_beacon(fc) ? true : false);
582
583 /* query phy status */
584 if (phystrpt)
585 odm_phy_status_query(dm, &phy_info, phystrpt, &pktinfo);
586 else
587 memset(&phy_info, 0, sizeof(phy_info));
588
589 /* copy phy_info from phydm to driver */
590 pstatus->rx_pwdb_all = phy_info.rx_pwdb_all;
591 pstatus->bt_rx_rssi_percentage = phy_info.bt_rx_rssi_percentage;
592 pstatus->recvsignalpower = phy_info.recv_signal_power;
593 pstatus->signalquality = phy_info.signal_quality;
594 pstatus->rx_mimo_signalquality[0] = phy_info.rx_mimo_signal_quality[0];
595 pstatus->rx_mimo_signalquality[1] = phy_info.rx_mimo_signal_quality[1];
596 pstatus->rx_packet_bw =
597 phy_info.band_width; /* HT_CHANNEL_WIDTH_20 <- ODM_BW20M */
598
599 /* fill driver pstatus */
600 pstatus->packet_matchbssid = pktinfo.is_packet_match_bssid;
601 pstatus->packet_toself = pktinfo.is_packet_to_self;
602 pstatus->packet_beacon = pktinfo.is_packet_beacon;
603
604 return true;
605}
606
607static u8 rtl_phydm_rate_id_mapping(struct rtl_priv *rtlpriv,
608 enum wireless_mode wireless_mode,
609 enum rf_type rf_type,
610 enum ht_channel_width bw)
611{
612 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
613
614 return phydm_rate_id_mapping(dm, wireless_mode, rf_type, bw);
615}
616
617static bool rtl_phydm_get_ra_bitmap(struct rtl_priv *rtlpriv,
618 enum wireless_mode wireless_mode,
619 enum rf_type rf_type,
620 enum ht_channel_width bw,
621 u8 tx_rate_level, /* 0~6 */
622 u32 *tx_bitmap_msb,
623 u32 *tx_bitmap_lsb)
624{
625 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
626 const u8 mimo_ps_enable = 0;
627 const u8 disable_cck_rate = 0;
628
629 phydm_update_hal_ra_mask(dm, wireless_mode, rf_type, bw, mimo_ps_enable,
630 disable_cck_rate, tx_bitmap_msb, tx_bitmap_lsb,
631 tx_rate_level);
632
633 return true;
634}
635
636static u8 _rtl_phydm_get_macid(struct rtl_priv *rtlpriv,
637 struct ieee80211_sta *sta)
638{
639 struct rtl_mac *mac = rtl_mac(rtlpriv);
640
641 if (mac->opmode == NL80211_IFTYPE_STATION ||
642 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
643 return 0;
644 } else if (mac->opmode == NL80211_IFTYPE_AP ||
645 mac->opmode == NL80211_IFTYPE_ADHOC)
646 return sta->aid + 1;
647
648 return 0;
649}
650
651static bool rtl_phydm_add_sta(struct rtl_priv *rtlpriv,
652 struct ieee80211_sta *sta)
653{
654 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
655 struct rtl_sta_info *sta_entry = (struct rtl_sta_info *)sta->drv_priv;
656 u8 mac_id = _rtl_phydm_get_macid(rtlpriv, sta);
657
658 odm_cmn_info_ptr_array_hook(dm, ODM_CMNINFO_STA_STATUS, mac_id,
659 sta_entry);
660
661 return true;
662}
663
664static bool rtl_phydm_del_sta(struct rtl_priv *rtlpriv,
665 struct ieee80211_sta *sta)
666{
667 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
668 u8 mac_id = _rtl_phydm_get_macid(rtlpriv, sta);
669
670 odm_cmn_info_ptr_array_hook(dm, ODM_CMNINFO_STA_STATUS, mac_id, NULL);
671
672 return true;
673}
674
675static u32 rtl_phydm_get_version(struct rtl_priv *rtlpriv)
676{
677 u32 ver = 0;
678
679 if (IS_HARDWARE_TYPE_8822B(rtlpriv))
680 ver = RELEASE_VERSION_8822B;
681
682 return ver;
683}
684
685static bool rtl_phydm_modify_ra_pcr_threshold(struct rtl_priv *rtlpriv,
686 u8 ra_offset_direction,
687 u8 ra_threshold_offset)
688{
689 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
690
691 phydm_modify_RA_PCR_threshold(dm, ra_offset_direction,
692 ra_threshold_offset);
693
694 return true;
695}
696
697static u32 rtl_phydm_query_counter(struct rtl_priv *rtlpriv,
698 const char *info_type)
699{
700 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
701 static const struct query_entry {
702 const char *query_name;
703 enum phydm_info_query query_id;
704 } query_table[] = {
705#define QUERY_ENTRY(name) {#name, name}
706 QUERY_ENTRY(PHYDM_INFO_FA_OFDM),
707 QUERY_ENTRY(PHYDM_INFO_FA_CCK),
708 QUERY_ENTRY(PHYDM_INFO_CCA_OFDM),
709 QUERY_ENTRY(PHYDM_INFO_CCA_CCK),
710 QUERY_ENTRY(PHYDM_INFO_CRC32_OK_CCK),
711 QUERY_ENTRY(PHYDM_INFO_CRC32_OK_LEGACY),
712 QUERY_ENTRY(PHYDM_INFO_CRC32_OK_HT),
713 QUERY_ENTRY(PHYDM_INFO_CRC32_OK_VHT),
714 QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_CCK),
715 QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_LEGACY),
716 QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_HT),
717 QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_VHT),
718 };
719#define QUERY_TABLE_SIZE ARRAY_SIZE(query_table)
720
721 int i;
722 const struct query_entry *entry;
723
724 if (!strcmp(info_type, "IQK_TOTAL"))
725 return dm->n_iqk_cnt;
726
727 if (!strcmp(info_type, "IQK_OK"))
728 return dm->n_iqk_ok_cnt;
729
730 if (!strcmp(info_type, "IQK_FAIL"))
731 return dm->n_iqk_fail_cnt;
732
733 for (i = 0; i < QUERY_TABLE_SIZE; i++) {
734 entry = &query_table[i];
735
736 if (!strcmp(info_type, entry->query_name))
737 return phydm_cmn_info_query(dm, entry->query_id);
738 }
739
740 pr_err("Unrecognized info_type:%s!!!!:\n", info_type);
741
742 return 0xDEADDEAD;
743}
744
745static bool rtl_phydm_debug_cmd(struct rtl_priv *rtlpriv, char *in, u32 in_len,
746 char *out, u32 out_len)
747{
748 struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
749
750 phydm_cmd(dm, in, in_len, 1, out, out_len);
751
752 return true;
753}
754
755static struct rtl_phydm_ops rtl_phydm_operation = {
756 /* init/deinit priv */
757 .phydm_init_priv = rtl_phydm_init_priv,
758 .phydm_deinit_priv = rtl_phydm_deinit_priv,
759 .phydm_load_txpower_by_rate = rtl_phydm_load_txpower_by_rate,
760 .phydm_load_txpower_limit = rtl_phydm_load_txpower_limit,
761
762 /* init hw */
763 .phydm_init_dm = rtl_phydm_init_dm,
764 .phydm_deinit_dm = rtl_phydm_deinit_dm,
765 .phydm_reset_dm = rtl_phydm_reset_dm,
766 .phydm_parameter_init = rtl_phydm_parameter_init,
767 .phydm_phy_bb_config = rtl_phydm_phy_bb_config,
768 .phydm_phy_rf_config = rtl_phydm_phy_rf_config,
769 .phydm_phy_mac_config = rtl_phydm_phy_mac_config,
770 .phydm_trx_mode = rtl_phydm_trx_mode,
771
772 /* watchdog */
773 .phydm_watchdog = rtl_phydm_watchdog,
774
775 /* channel */
776 .phydm_switch_band = rtl_phydm_switch_band,
777 .phydm_switch_channel = rtl_phydm_switch_channel,
778 .phydm_switch_bandwidth = rtl_phydm_switch_bandwidth,
779 .phydm_iq_calibrate = rtl_phydm_iq_calibrate,
780 .phydm_clear_txpowertracking_state =
781 rtl_phydm_clear_txpowertracking_state,
782 .phydm_pause_dig = rtl_phydm_pause_dig,
783
784 /* read/write reg */
785 .phydm_read_rf_reg = rtl_phydm_read_rf_reg,
786 .phydm_write_rf_reg = rtl_phydm_write_rf_reg,
787 .phydm_read_txagc = rtl_phydm_read_txagc,
788 .phydm_write_txagc = rtl_phydm_write_txagc,
789
790 /* RX */
791 .phydm_c2h_content_parsing = rtl_phydm_c2h_content_parsing,
792 .phydm_query_phy_status = rtl_phydm_query_phy_status,
793
794 /* TX */
795 .phydm_rate_id_mapping = rtl_phydm_rate_id_mapping,
796 .phydm_get_ra_bitmap = rtl_phydm_get_ra_bitmap,
797
798 /* STA */
799 .phydm_add_sta = rtl_phydm_add_sta,
800 .phydm_del_sta = rtl_phydm_del_sta,
801
802 /* BTC */
803 .phydm_get_version = rtl_phydm_get_version,
804 .phydm_modify_ra_pcr_threshold = rtl_phydm_modify_ra_pcr_threshold,
805 .phydm_query_counter = rtl_phydm_query_counter,
806
807 /* debug */
808 .phydm_debug_cmd = rtl_phydm_debug_cmd,
809};
810
811struct rtl_phydm_ops *rtl_phydm_get_ops_pointer(void)
812{
813 return &rtl_phydm_operation;
814}
815EXPORT_SYMBOL(rtl_phydm_get_ops_pointer);
816
817/* ********************************************************
818 * Define phydm callout function in below
819 * ********************************************************
820 */
821
822u8 phy_get_tx_power_index(void *adapter, u8 rf_path, u8 rate,
823 enum ht_channel_width bandwidth, u8 channel)
824{
825 /* rate: DESC_RATE1M */
826 struct rtl_priv *rtlpriv = (struct rtl_priv *)adapter;
827
828 return rtlpriv->cfg->ops->get_txpower_index(rtlpriv->hw, rf_path, rate,
829 bandwidth, channel);
830}
831
832void phy_set_tx_power_index_by_rs(void *adapter, u8 ch, u8 path, u8 rs)
833{
834 struct rtl_priv *rtlpriv = (struct rtl_priv *)adapter;
835
836 return rtlpriv->cfg->ops->set_tx_power_index_by_rs(rtlpriv->hw, ch,
837 path, rs);
838}
839
840void phy_store_tx_power_by_rate(void *adapter, u32 band, u32 rfpath, u32 txnum,
841 u32 regaddr, u32 bitmask, u32 data)
842{
843 struct rtl_priv *rtlpriv = (struct rtl_priv *)adapter;
844
845 rtlpriv->cfg->ops->store_tx_power_by_rate(
846 rtlpriv->hw, band, rfpath, txnum, regaddr, bitmask, data);
847}
848
849void phy_set_tx_power_limit(void *dm, u8 *regulation, u8 *band, u8 *bandwidth,
850 u8 *rate_section, u8 *rf_path, u8 *channel,
851 u8 *power_limit)
852{
853 struct rtl_priv *rtlpriv =
854 (struct rtl_priv *)((struct phy_dm_struct *)dm)->adapter;
855
856 rtlpriv->cfg->ops->phy_set_txpower_limit(rtlpriv->hw, regulation, band,
857 bandwidth, rate_section,
858 rf_path, channel, power_limit);
859}
860
861void rtl_hal_update_ra_mask(void *adapter, struct rtl_sta_info *psta,
862 u8 rssi_level)
863{
864 struct rtl_priv *rtlpriv = (struct rtl_priv *)adapter;
865 struct ieee80211_sta *sta =
866 container_of((void *)psta, struct ieee80211_sta, drv_priv);
867
868 rtlpriv->cfg->ops->update_rate_tbl(rtlpriv->hw, sta, rssi_level, false);
869}
870
871MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
872MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
873MODULE_LICENSE("GPL");
874MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
diff --git a/drivers/staging/rtlwifi/phydm/rtl_phydm.h b/drivers/staging/rtlwifi/phydm/rtl_phydm.h
new file mode 100644
index 000000000000..483d2418699b
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/rtl_phydm.h
@@ -0,0 +1,45 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __RTL_PHYDM_H__
26#define __RTL_PHYDM_H__
27
28struct rtl_phydm_ops *rtl_phydm_get_ops_pointer(void);
29
30#define rtlpriv_to_phydm(priv) \
31 ((struct phy_dm_struct *)((priv)->phydm.internal))
32
33u8 phy_get_tx_power_index(void *adapter, u8 rf_path, u8 rate,
34 enum ht_channel_width bandwidth, u8 channel);
35void phy_set_tx_power_index_by_rs(void *adapter, u8 ch, u8 path, u8 rs);
36void phy_store_tx_power_by_rate(void *adapter, u32 band, u32 rfpath, u32 txnum,
37 u32 regaddr, u32 bitmask, u32 data);
38void phy_set_tx_power_limit(void *dm, u8 *regulation, u8 *band, u8 *bandwidth,
39 u8 *rate_section, u8 *rf_path, u8 *channel,
40 u8 *power_limit);
41
42void rtl_hal_update_ra_mask(void *adapter, struct rtl_sta_info *psta,
43 u8 rssi_level);
44
45#endif
diff --git a/drivers/staging/rtlwifi/phydm/txbf/halcomtxbf.h b/drivers/staging/rtlwifi/phydm/txbf/halcomtxbf.h
new file mode 100644
index 000000000000..6cacca12d792
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/txbf/halcomtxbf.h
@@ -0,0 +1,67 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __HAL_COM_TXBF_H__
26#define __HAL_COM_TXBF_H__
27
28enum txbf_set_type {
29 TXBF_SET_SOUNDING_ENTER,
30 TXBF_SET_SOUNDING_LEAVE,
31 TXBF_SET_SOUNDING_RATE,
32 TXBF_SET_SOUNDING_STATUS,
33 TXBF_SET_SOUNDING_FW_NDPA,
34 TXBF_SET_SOUNDING_CLK,
35 TXBF_SET_TX_PATH_RESET,
36 TXBF_SET_GET_TX_RATE
37};
38
39enum txbf_get_type {
40 TXBF_GET_EXPLICIT_BEAMFORMEE,
41 TXBF_GET_EXPLICIT_BEAMFORMER,
42 TXBF_GET_MU_MIMO_STA,
43 TXBF_GET_MU_MIMO_AP
44};
45
46/* 2 HAL TXBF related */
47struct _HAL_TXBF_INFO {
48 u8 txbf_idx;
49 u8 ndpa_idx;
50 u8 BW;
51 u8 rate;
52
53 struct timer_list txbf_fw_ndpa_timer;
54};
55
56#define hal_com_txbf_beamform_init(dm_void) NULL
57#define hal_com_txbf_config_gtab(dm_void) NULL
58#define hal_com_txbf_enter_work_item_callback(_adapter) NULL
59#define hal_com_txbf_leave_work_item_callback(_adapter) NULL
60#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL
61#define hal_com_txbf_clk_work_item_callback(_adapter) NULL
62#define hal_com_txbf_rate_work_item_callback(_adapter) NULL
63#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL
64#define hal_com_txbf_status_work_item_callback(_adapter) NULL
65#define hal_com_txbf_get(_adapter, _get_type, _pout_buf)
66
67#endif /* #ifndef __HAL_COM_TXBF_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/txbf/haltxbf8822b.h b/drivers/staging/rtlwifi/phydm/txbf/haltxbf8822b.h
new file mode 100644
index 000000000000..5c92c4326f7e
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/txbf/haltxbf8822b.h
@@ -0,0 +1,39 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __HAL_TXBF_8822B_H__
26#define __HAL_TXBF_8822B_H__
27
28#define hal_txbf_8822b_enter(dm_void, idx)
29#define hal_txbf_8822b_leave(dm_void, idx)
30#define hal_txbf_8822b_status(dm_void, idx)
31#define hal_txbf_8822b_fw_txbf(dm_void, idx)
32#define hal_txbf_8822b_config_gtab(dm_void)
33
34void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
35
36void phydm_8822b_sutxbfer_workaroud(void *dm_void, bool enable_su_bfer, u8 nc,
37 u8 nr, u8 ng, u8 CB, u8 BW, bool is_vht);
38
39#endif
diff --git a/drivers/staging/rtlwifi/phydm/txbf/haltxbfinterface.h b/drivers/staging/rtlwifi/phydm/txbf/haltxbfinterface.h
new file mode 100644
index 000000000000..82aeac1ff3e0
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/txbf/haltxbfinterface.h
@@ -0,0 +1,38 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __HAL_TXBF_INTERFACE_H__
26#define __HAL_TXBF_INTERFACE_H__
27
28#define beamforming_get_ndpa_frame(dm, _pdu_os)
29#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE
30#define send_fw_ht_ndpa_packet(dm_void, RA, BW)
31#define send_sw_ht_ndpa_packet(dm_void, RA, BW)
32#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW)
33#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW)
34#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx)
35#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)
36#define send_sw_vht_mu_ndpa_packet(dm_void, BW)
37
38#endif
diff --git a/drivers/staging/rtlwifi/phydm/txbf/haltxbfjaguar.h b/drivers/staging/rtlwifi/phydm/txbf/haltxbfjaguar.h
new file mode 100644
index 000000000000..c5ddd9cb9cd5
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/txbf/haltxbfjaguar.h
@@ -0,0 +1,36 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __HAL_TXBF_JAGUAR_H__
26#define __HAL_TXBF_JAGUAR_H__
27
28#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
29#define hal_txbf_jaguar_enter(dm_void, idx)
30#define hal_txbf_jaguar_leave(dm_void, idx)
31#define hal_txbf_jaguar_status(dm_void, idx)
32#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
33#define hal_txbf_jaguar_patch(dm_void, operation)
34#define hal_txbf_jaguar_clk_8812a(dm_void)
35
36#endif /* #ifndef __HAL_TXBF_JAGUAR_H__ */
diff --git a/drivers/staging/rtlwifi/phydm/txbf/phydm_hal_txbf_api.h b/drivers/staging/rtlwifi/phydm/txbf/phydm_hal_txbf_api.h
new file mode 100644
index 000000000000..41358fce2875
--- /dev/null
+++ b/drivers/staging/rtlwifi/phydm/txbf/phydm_hal_txbf_api.h
@@ -0,0 +1,41 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25#ifndef __PHYDM_HAL_TXBF_API_H__
26#define __PHYDM_HAL_TXBF_API_H__
27
28#define tx_bf_nr(a, b) ((a > b) ? (b) : (a))
29
30u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 comp_steering_num_of_bfer);
31
32u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 comp_steering_num_of_bfer);
33
34u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *troughput,
35 u8 total_bfee_num, u8 *tx_rate);
36
37u8 phydm_get_ndpa_rate(void *dm_void);
38
39u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput);
40
41#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 10:46:17 -0400