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authorDave Airlie <airlied@redhat.com>2018-01-11 20:46:19 -0500
committerDave Airlie <airlied@redhat.com>2018-01-11 20:46:19 -0500
commit9be712ef4612268c28b9f1e2d850d3ceab06ef66 (patch)
treeaf5831ce1017c604da8f96dc6a321df4ff6a7adb
parent323b20c4af6e315e665b0ea85035fea7d738e0cc (diff)
parent8f62142e490d761ceb92b55a7c05bb79294d6c6c (diff)
Merge tag 'drm/tegra/for-4.16-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v4.16-rc1 The bulk of these changes are preparation work and addition of support for Tegra186. Currently only HDMI output (the primary output on Jetson TX2) is supported, but the hardware is also capable of doing DSI and DisplayPort. Tegra DRM now also uses the atomic commit helpers instead of the open- coded variant that was only doing half its job. As a bit of a byproduct of the Tegra186 support the driver also gained HDMI 2.0 as well as zpos property support. Along the way there are also a few patches to clean up a few things and fix minor issues. * tag 'drm/tegra/for-4.16-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux: (51 commits) drm/tegra: dc: Properly cleanup overlay planes drm/tegra: dc: Fix possible_crtcs mask for planes drm/tegra: dc: Restore YUV overlay support drm/tegra: dc: Implement legacy blending drm/tegra: Correct timeout in tegra_syncpt_wait drm/tegra: gem: Correct iommu_map_sg() error checking drm/tegra: dc: Link DC1 to DC0 on Tegra20 drm/tegra: Fix non-debugfs builds drm/tegra: dpaux: Keep reset defaults for hybrid pad parameters drm/tegra: Mark Tegra186 display hub PM functions __maybe_unused drm/tegra: Use IOMMU groups gpu: host1x: Use IOMMU groups drm/tegra: Implement zpos property drm/tegra: dc: Remove redundant spinlock drm/tegra: dc: Use direct offset to plane registers drm/tegra: dc: Support more formats drm/tegra: fb: Force alpha formats drm/tegra: dpaux: Add Tegra186 support drm/tegra: dpaux: Implement runtime PM drm/tegra: sor: Support HDMI 2.0 modes ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt14
-rw-r--r--drivers/gpu/drm/tegra/Makefile2
-rw-r--r--drivers/gpu/drm/tegra/dc.c1914
-rw-r--r--drivers/gpu/drm/tegra/dc.h289
-rw-r--r--drivers/gpu/drm/tegra/dpaux.c120
-rw-r--r--drivers/gpu/drm/tegra/drm.c164
-rw-r--r--drivers/gpu/drm/tegra/drm.h26
-rw-r--r--drivers/gpu/drm/tegra/dsi.c228
-rw-r--r--drivers/gpu/drm/tegra/fb.c36
-rw-r--r--drivers/gpu/drm/tegra/gem.c15
-rw-r--r--drivers/gpu/drm/tegra/hdmi.c504
-rw-r--r--drivers/gpu/drm/tegra/hub.c806
-rw-r--r--drivers/gpu/drm/tegra/hub.h81
-rw-r--r--drivers/gpu/drm/tegra/output.c24
-rw-r--r--drivers/gpu/drm/tegra/plane.c383
-rw-r--r--drivers/gpu/drm/tegra/plane.h70
-rw-r--r--drivers/gpu/drm/tegra/sor.c1119
-rw-r--r--drivers/gpu/drm/tegra/sor.h16
-rw-r--r--drivers/gpu/drm/tegra/vic.c20
-rw-r--r--drivers/gpu/host1x/bus.c11
-rw-r--r--drivers/gpu/host1x/dev.c36
-rw-r--r--drivers/gpu/host1x/dev.h1
-rw-r--r--include/uapi/drm/drm_fourcc.h38
23 files changed, 4085 insertions, 1832 deletions
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
index 844e0103fb0d..593be44a53c9 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -206,21 +206,33 @@ of the following host1x client modules:
206 - "nvidia,tegra132-sor": for Tegra132 206 - "nvidia,tegra132-sor": for Tegra132
207 - "nvidia,tegra210-sor": for Tegra210 207 - "nvidia,tegra210-sor": for Tegra210
208 - "nvidia,tegra210-sor1": for Tegra210 208 - "nvidia,tegra210-sor1": for Tegra210
209 - "nvidia,tegra186-sor": for Tegra186
210 - "nvidia,tegra186-sor1": for Tegra186
209 - reg: Physical base address and length of the controller's registers. 211 - reg: Physical base address and length of the controller's registers.
210 - interrupts: The interrupt outputs from the controller. 212 - interrupts: The interrupt outputs from the controller.
211 - clocks: Must contain an entry for each entry in clock-names. 213 - clocks: Must contain an entry for each entry in clock-names.
212 See ../clocks/clock-bindings.txt for details. 214 See ../clocks/clock-bindings.txt for details.
213 - clock-names: Must include the following entries: 215 - clock-names: Must include the following entries:
214 - sor: clock input for the SOR hardware 216 - sor: clock input for the SOR hardware
215 - source: source clock for the SOR clock 217 - out: SOR output clock
216 - parent: input for the pixel clock 218 - parent: input for the pixel clock
217 - dp: reference clock for the SOR clock 219 - dp: reference clock for the SOR clock
218 - safe: safe reference for the SOR clock during power up 220 - safe: safe reference for the SOR clock during power up
221
222 For Tegra186 and later:
223 - pad: SOR pad output clock (on Tegra186 and later)
224
225 Obsolete:
226 - source: source clock for the SOR clock (obsolete, use "out" instead)
227
219 - resets: Must contain an entry for each entry in reset-names. 228 - resets: Must contain an entry for each entry in reset-names.
220 See ../reset/reset.txt for details. 229 See ../reset/reset.txt for details.
221 - reset-names: Must include the following entries: 230 - reset-names: Must include the following entries:
222 - sor 231 - sor
223 232
233 Required properties on Tegra186 and later:
234 - nvidia,interface: index of the SOR interface
235
224 Optional properties: 236 Optional properties:
225 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 237 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
226 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 238 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
index 46d65d39214d..2e0d6213f6bc 100644
--- a/drivers/gpu/drm/tegra/Makefile
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -5,6 +5,8 @@ tegra-drm-y := \
5 drm.o \ 5 drm.o \
6 gem.o \ 6 gem.o \
7 fb.o \ 7 fb.o \
8 hub.o \
9 plane.o \
8 dc.o \ 10 dc.o \
9 output.o \ 11 output.o \
10 rgb.o \ 12 rgb.o \
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index fc70351b9017..b8403ed48285 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -19,82 +19,79 @@
19#include "dc.h" 19#include "dc.h"
20#include "drm.h" 20#include "drm.h"
21#include "gem.h" 21#include "gem.h"
22#include "hub.h"
23#include "plane.h"
22 24
23#include <drm/drm_atomic.h> 25#include <drm/drm_atomic.h>
24#include <drm/drm_atomic_helper.h> 26#include <drm/drm_atomic_helper.h>
25#include <drm/drm_plane_helper.h> 27#include <drm/drm_plane_helper.h>
26 28
27struct tegra_plane { 29static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
28 struct drm_plane base;
29 unsigned int index;
30};
31
32static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
33{ 30{
34 return container_of(plane, struct tegra_plane, base); 31 stats->frames = 0;
32 stats->vblank = 0;
33 stats->underflow = 0;
34 stats->overflow = 0;
35} 35}
36 36
37struct tegra_dc_state { 37/* Reads the active copy of a register. */
38 struct drm_crtc_state base; 38static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
39{
40 u32 value;
39 41
40 struct clk *clk; 42 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
41 unsigned long pclk; 43 value = tegra_dc_readl(dc, offset);
42 unsigned int div; 44 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
43 45
44 u32 planes; 46 return value;
45}; 47}
46 48
47static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) 49static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
50 unsigned int offset)
48{ 51{
49 if (state) 52 if (offset >= 0x500 && offset <= 0x638) {
50 return container_of(state, struct tegra_dc_state, base); 53 offset = 0x000 + (offset - 0x500);
51 54 return plane->offset + offset;
52 return NULL; 55 }
53}
54 56
55struct tegra_plane_state { 57 if (offset >= 0x700 && offset <= 0x719) {
56 struct drm_plane_state base; 58 offset = 0x180 + (offset - 0x700);
59 return plane->offset + offset;
60 }
57 61
58 struct tegra_bo_tiling tiling; 62 if (offset >= 0x800 && offset <= 0x839) {
59 u32 format; 63 offset = 0x1c0 + (offset - 0x800);
60 u32 swap; 64 return plane->offset + offset;
61}; 65 }
62 66
63static inline struct tegra_plane_state * 67 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
64to_tegra_plane_state(struct drm_plane_state *state)
65{
66 if (state)
67 return container_of(state, struct tegra_plane_state, base);
68 68
69 return NULL; 69 return plane->offset + offset;
70} 70}
71 71
72static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) 72static inline u32 tegra_plane_readl(struct tegra_plane *plane,
73 unsigned int offset)
73{ 74{
74 stats->frames = 0; 75 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
75 stats->vblank = 0;
76 stats->underflow = 0;
77 stats->overflow = 0;
78} 76}
79 77
80/* 78static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
81 * Reads the active copy of a register. This takes the dc->lock spinlock to 79 unsigned int offset)
82 * prevent races with the VBLANK processing which also needs access to the
83 * active copy of some registers.
84 */
85static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
86{ 80{
87 unsigned long flags; 81 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
88 u32 value; 82}
89 83
90 spin_lock_irqsave(&dc->lock, flags); 84bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
85{
86 struct device_node *np = dc->dev->of_node;
87 struct of_phandle_iterator it;
88 int err;
91 89
92 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 90 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
93 value = tegra_dc_readl(dc, offset); 91 if (it.node == dev->of_node)
94 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); 92 return true;
95 93
96 spin_unlock_irqrestore(&dc->lock, flags); 94 return false;
97 return value;
98} 95}
99 96
100/* 97/*
@@ -115,81 +112,6 @@ void tegra_dc_commit(struct tegra_dc *dc)
115 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 112 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
116} 113}
117 114
118static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
119{
120 /* assume no swapping of fetched data */
121 if (swap)
122 *swap = BYTE_SWAP_NOSWAP;
123
124 switch (fourcc) {
125 case DRM_FORMAT_XBGR8888:
126 *format = WIN_COLOR_DEPTH_R8G8B8A8;
127 break;
128
129 case DRM_FORMAT_XRGB8888:
130 *format = WIN_COLOR_DEPTH_B8G8R8A8;
131 break;
132
133 case DRM_FORMAT_RGB565:
134 *format = WIN_COLOR_DEPTH_B5G6R5;
135 break;
136
137 case DRM_FORMAT_UYVY:
138 *format = WIN_COLOR_DEPTH_YCbCr422;
139 break;
140
141 case DRM_FORMAT_YUYV:
142 if (swap)
143 *swap = BYTE_SWAP_SWAP2;
144
145 *format = WIN_COLOR_DEPTH_YCbCr422;
146 break;
147
148 case DRM_FORMAT_YUV420:
149 *format = WIN_COLOR_DEPTH_YCbCr420P;
150 break;
151
152 case DRM_FORMAT_YUV422:
153 *format = WIN_COLOR_DEPTH_YCbCr422P;
154 break;
155
156 default:
157 return -EINVAL;
158 }
159
160 return 0;
161}
162
163static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
164{
165 switch (format) {
166 case WIN_COLOR_DEPTH_YCbCr422:
167 case WIN_COLOR_DEPTH_YUV422:
168 if (planar)
169 *planar = false;
170
171 return true;
172
173 case WIN_COLOR_DEPTH_YCbCr420P:
174 case WIN_COLOR_DEPTH_YUV420P:
175 case WIN_COLOR_DEPTH_YCbCr422P:
176 case WIN_COLOR_DEPTH_YUV422P:
177 case WIN_COLOR_DEPTH_YCbCr422R:
178 case WIN_COLOR_DEPTH_YUV422R:
179 case WIN_COLOR_DEPTH_YCbCr422RA:
180 case WIN_COLOR_DEPTH_YUV422RA:
181 if (planar)
182 *planar = true;
183
184 return true;
185 }
186
187 if (planar)
188 *planar = false;
189
190 return false;
191}
192
193static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, 115static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
194 unsigned int bpp) 116 unsigned int bpp)
195{ 117{
@@ -230,36 +152,104 @@ static inline u32 compute_initial_dda(unsigned int in)
230 return dfixed_frac(inf); 152 return dfixed_frac(inf);
231} 153}
232 154
233static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, 155static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
156{
157 u32 background[3] = {
158 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
159 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
160 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
161 };
162 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
163 BLEND_COLOR_KEY_NONE;
164 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
165 struct tegra_plane_state *state;
166 unsigned int i;
167
168 state = to_tegra_plane_state(plane->base.state);
169
170 /* alpha contribution is 1 minus sum of overlapping windows */
171 for (i = 0; i < 3; i++) {
172 if (state->dependent[i])
173 background[i] |= BLEND_CONTROL_DEPENDENT;
174 }
175
176 /* enable alpha blending if pixel format has an alpha component */
177 if (!state->opaque)
178 foreground |= BLEND_CONTROL_ALPHA;
179
180 /*
181 * Disable blending and assume Window A is the bottom-most window,
182 * Window C is the top-most window and Window B is in the middle.
183 */
184 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
185 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
186
187 switch (plane->index) {
188 case 0:
189 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
190 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
191 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
192 break;
193
194 case 1:
195 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
196 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
197 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
198 break;
199
200 case 2:
201 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
202 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
203 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
204 break;
205 }
206}
207
208static void tegra_plane_setup_blending(struct tegra_plane *plane,
209 const struct tegra_dc_window *window)
210{
211 u32 value;
212
213 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
214 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
215 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
216 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
217
218 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
219 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
220 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
221 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
222
223 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
224 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
225}
226
227static void tegra_dc_setup_window(struct tegra_plane *plane,
234 const struct tegra_dc_window *window) 228 const struct tegra_dc_window *window)
235{ 229{
236 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 230 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
237 unsigned long value, flags; 231 struct tegra_dc *dc = plane->dc;
238 bool yuv, planar; 232 bool yuv, planar;
233 u32 value;
239 234
240 /* 235 /*
241 * For YUV planar modes, the number of bytes per pixel takes into 236 * For YUV planar modes, the number of bytes per pixel takes into
242 * account only the luma component and therefore is 1. 237 * account only the luma component and therefore is 1.
243 */ 238 */
244 yuv = tegra_dc_format_is_yuv(window->format, &planar); 239 yuv = tegra_plane_format_is_yuv(window->format, &planar);
245 if (!yuv) 240 if (!yuv)
246 bpp = window->bits_per_pixel / 8; 241 bpp = window->bits_per_pixel / 8;
247 else 242 else
248 bpp = planar ? 1 : 2; 243 bpp = planar ? 1 : 2;
249 244
250 spin_lock_irqsave(&dc->lock, flags); 245 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
251 246 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
252 value = WINDOW_A_SELECT << index;
253 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
254
255 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
256 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
257 247
258 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); 248 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
259 tegra_dc_writel(dc, value, DC_WIN_POSITION); 249 tegra_plane_writel(plane, value, DC_WIN_POSITION);
260 250
261 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); 251 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
262 tegra_dc_writel(dc, value, DC_WIN_SIZE); 252 tegra_plane_writel(plane, value, DC_WIN_SIZE);
263 253
264 h_offset = window->src.x * bpp; 254 h_offset = window->src.x * bpp;
265 v_offset = window->src.y; 255 v_offset = window->src.y;
@@ -267,7 +257,7 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
267 v_size = window->src.h; 257 v_size = window->src.h;
268 258
269 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); 259 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
270 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); 260 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
271 261
272 /* 262 /*
273 * For DDA computations the number of bytes per pixel for YUV planar 263 * For DDA computations the number of bytes per pixel for YUV planar
@@ -280,33 +270,33 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
280 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); 270 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
281 271
282 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 272 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
283 tegra_dc_writel(dc, value, DC_WIN_DDA_INC); 273 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
284 274
285 h_dda = compute_initial_dda(window->src.x); 275 h_dda = compute_initial_dda(window->src.x);
286 v_dda = compute_initial_dda(window->src.y); 276 v_dda = compute_initial_dda(window->src.y);
287 277
288 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); 278 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
289 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); 279 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
290 280
291 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); 281 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
292 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); 282 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
293 283
294 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); 284 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
295 285
296 if (yuv && planar) { 286 if (yuv && planar) {
297 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); 287 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
298 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); 288 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
299 value = window->stride[1] << 16 | window->stride[0]; 289 value = window->stride[1] << 16 | window->stride[0];
300 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); 290 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
301 } else { 291 } else {
302 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); 292 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
303 } 293 }
304 294
305 if (window->bottom_up) 295 if (window->bottom_up)
306 v_offset += window->src.h - 1; 296 v_offset += window->src.h - 1;
307 297
308 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); 298 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
309 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); 299 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
310 300
311 if (dc->soc->supports_block_linear) { 301 if (dc->soc->supports_block_linear) {
312 unsigned long height = window->tiling.value; 302 unsigned long height = window->tiling.value;
@@ -326,7 +316,7 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
326 break; 316 break;
327 } 317 }
328 318
329 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); 319 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
330 } else { 320 } else {
331 switch (window->tiling.mode) { 321 switch (window->tiling.mode) {
332 case TEGRA_BO_TILING_MODE_PITCH: 322 case TEGRA_BO_TILING_MODE_PITCH:
@@ -347,21 +337,21 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
347 break; 337 break;
348 } 338 }
349 339
350 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); 340 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
351 } 341 }
352 342
353 value = WIN_ENABLE; 343 value = WIN_ENABLE;
354 344
355 if (yuv) { 345 if (yuv) {
356 /* setup default colorspace conversion coefficients */ 346 /* setup default colorspace conversion coefficients */
357 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); 347 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
358 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); 348 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
359 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); 349 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
360 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); 350 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
361 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); 351 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
362 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); 352 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
363 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); 353 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
364 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); 354 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
365 355
366 value |= CSC_ENABLE; 356 value |= CSC_ENABLE;
367 } else if (window->bits_per_pixel < 24) { 357 } else if (window->bits_per_pixel < 24) {
@@ -371,137 +361,74 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
371 if (window->bottom_up) 361 if (window->bottom_up)
372 value |= V_DIRECTION; 362 value |= V_DIRECTION;
373 363
374 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); 364 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
375
376 /*
377 * Disable blending and assume Window A is the bottom-most window,
378 * Window C is the top-most window and Window B is in the middle.
379 */
380 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
381 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
382
383 switch (index) {
384 case 0:
385 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
386 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
387 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
388 break;
389
390 case 1:
391 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
394 break;
395
396 case 2:
397 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
399 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
400 break;
401 }
402
403 spin_unlock_irqrestore(&dc->lock, flags);
404}
405 365
406static void tegra_plane_destroy(struct drm_plane *plane) 366 if (dc->soc->supports_blending)
407{ 367 tegra_plane_setup_blending(plane, window);
408 struct tegra_plane *p = to_tegra_plane(plane); 368 else
409 369 tegra_plane_setup_blending_legacy(plane);
410 drm_plane_cleanup(plane);
411 kfree(p);
412} 370}
413 371
414static const u32 tegra_primary_plane_formats[] = { 372static const u32 tegra20_primary_formats[] = {
373 DRM_FORMAT_ARGB4444,
374 DRM_FORMAT_ARGB1555,
375 DRM_FORMAT_RGB565,
376 DRM_FORMAT_RGBA5551,
377 DRM_FORMAT_ABGR8888,
378 DRM_FORMAT_ARGB8888,
379 /* non-native formats */
380 DRM_FORMAT_XRGB1555,
381 DRM_FORMAT_RGBX5551,
415 DRM_FORMAT_XBGR8888, 382 DRM_FORMAT_XBGR8888,
416 DRM_FORMAT_XRGB8888, 383 DRM_FORMAT_XRGB8888,
417 DRM_FORMAT_RGB565,
418}; 384};
419 385
420static void tegra_primary_plane_destroy(struct drm_plane *plane) 386static const u32 tegra114_primary_formats[] = {
421{ 387 DRM_FORMAT_ARGB4444,
422 tegra_plane_destroy(plane); 388 DRM_FORMAT_ARGB1555,
423} 389 DRM_FORMAT_RGB565,
424 390 DRM_FORMAT_RGBA5551,
425static void tegra_plane_reset(struct drm_plane *plane) 391 DRM_FORMAT_ABGR8888,
426{ 392 DRM_FORMAT_ARGB8888,
427 struct tegra_plane_state *state; 393 /* new on Tegra114 */
428 394 DRM_FORMAT_ABGR4444,
429 if (plane->state) 395 DRM_FORMAT_ABGR1555,
430 __drm_atomic_helper_plane_destroy_state(plane->state); 396 DRM_FORMAT_BGRA5551,
431 397 DRM_FORMAT_XRGB1555,
432 kfree(plane->state); 398 DRM_FORMAT_RGBX5551,
433 plane->state = NULL; 399 DRM_FORMAT_XBGR1555,
434 400 DRM_FORMAT_BGRX5551,
435 state = kzalloc(sizeof(*state), GFP_KERNEL); 401 DRM_FORMAT_BGR565,
436 if (state) { 402 DRM_FORMAT_BGRA8888,
437 plane->state = &state->base; 403 DRM_FORMAT_RGBA8888,
438 plane->state->plane = plane; 404 DRM_FORMAT_XRGB8888,
439 } 405 DRM_FORMAT_XBGR8888,
440}
441
442static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
443{
444 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
445 struct tegra_plane_state *copy;
446
447 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
448 if (!copy)
449 return NULL;
450
451 __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
452 copy->tiling = state->tiling;
453 copy->format = state->format;
454 copy->swap = state->swap;
455
456 return &copy->base;
457}
458
459static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
460 struct drm_plane_state *state)
461{
462 __drm_atomic_helper_plane_destroy_state(state);
463 kfree(state);
464}
465
466static const struct drm_plane_funcs tegra_primary_plane_funcs = {
467 .update_plane = drm_atomic_helper_update_plane,
468 .disable_plane = drm_atomic_helper_disable_plane,
469 .destroy = tegra_primary_plane_destroy,
470 .reset = tegra_plane_reset,
471 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
472 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
473}; 406};
474 407
475static int tegra_plane_state_add(struct tegra_plane *plane, 408static const u32 tegra124_primary_formats[] = {
476 struct drm_plane_state *state) 409 DRM_FORMAT_ARGB4444,
477{ 410 DRM_FORMAT_ARGB1555,
478 struct drm_crtc_state *crtc_state; 411 DRM_FORMAT_RGB565,
479 struct tegra_dc_state *tegra; 412 DRM_FORMAT_RGBA5551,
480 struct drm_rect clip; 413 DRM_FORMAT_ABGR8888,
481 int err; 414 DRM_FORMAT_ARGB8888,
482 415 /* new on Tegra114 */
483 /* Propagate errors from allocation or locking failures. */ 416 DRM_FORMAT_ABGR4444,
484 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 417 DRM_FORMAT_ABGR1555,
485 if (IS_ERR(crtc_state)) 418 DRM_FORMAT_BGRA5551,
486 return PTR_ERR(crtc_state); 419 DRM_FORMAT_XRGB1555,
487 420 DRM_FORMAT_RGBX5551,
488 clip.x1 = 0; 421 DRM_FORMAT_XBGR1555,
489 clip.y1 = 0; 422 DRM_FORMAT_BGRX5551,
490 clip.x2 = crtc_state->mode.hdisplay; 423 DRM_FORMAT_BGR565,
491 clip.y2 = crtc_state->mode.vdisplay; 424 DRM_FORMAT_BGRA8888,
492 425 DRM_FORMAT_RGBA8888,
493 /* Check plane state for visibility and calculate clipping bounds */ 426 DRM_FORMAT_XRGB8888,
494 err = drm_atomic_helper_check_plane_state(state, crtc_state, &clip, 427 DRM_FORMAT_XBGR8888,
495 0, INT_MAX, true, true); 428 /* new on Tegra124 */
496 if (err < 0) 429 DRM_FORMAT_RGBX8888,
497 return err; 430 DRM_FORMAT_BGRX8888,
498 431};
499 tegra = to_dc_state(crtc_state);
500
501 tegra->planes |= WIN_A_ACT_REQ << plane->index;
502
503 return 0;
504}
505 432
506static int tegra_plane_atomic_check(struct drm_plane *plane, 433static int tegra_plane_atomic_check(struct drm_plane *plane,
507 struct drm_plane_state *state) 434 struct drm_plane_state *state)
@@ -510,17 +437,40 @@ static int tegra_plane_atomic_check(struct drm_plane *plane,
510 struct tegra_bo_tiling *tiling = &plane_state->tiling; 437 struct tegra_bo_tiling *tiling = &plane_state->tiling;
511 struct tegra_plane *tegra = to_tegra_plane(plane); 438 struct tegra_plane *tegra = to_tegra_plane(plane);
512 struct tegra_dc *dc = to_tegra_dc(state->crtc); 439 struct tegra_dc *dc = to_tegra_dc(state->crtc);
440 unsigned int format;
513 int err; 441 int err;
514 442
515 /* no need for further checks if the plane is being disabled */ 443 /* no need for further checks if the plane is being disabled */
516 if (!state->crtc) 444 if (!state->crtc)
517 return 0; 445 return 0;
518 446
519 err = tegra_dc_format(state->fb->format->format, &plane_state->format, 447 err = tegra_plane_format(state->fb->format->format, &format,
520 &plane_state->swap); 448 &plane_state->swap);
521 if (err < 0) 449 if (err < 0)
522 return err; 450 return err;
523 451
452 /*
453 * Tegra20 and Tegra30 are special cases here because they support
454 * only variants of specific formats with an alpha component, but not
455 * the corresponding opaque formats. However, the opaque formats can
456 * be emulated by disabling alpha blending for the plane.
457 */
458 if (!dc->soc->supports_blending) {
459 if (!tegra_plane_format_has_alpha(format)) {
460 err = tegra_plane_format_get_alpha(format, &format);
461 if (err < 0)
462 return err;
463
464 plane_state->opaque = true;
465 } else {
466 plane_state->opaque = false;
467 }
468
469 tegra_plane_check_dependent(tegra, plane_state);
470 }
471
472 plane_state->format = format;
473
524 err = tegra_fb_get_tiling(state->fb, tiling); 474 err = tegra_fb_get_tiling(state->fb, tiling);
525 if (err < 0) 475 if (err < 0)
526 return err; 476 return err;
@@ -553,32 +503,22 @@ static int tegra_plane_atomic_check(struct drm_plane *plane,
553static void tegra_plane_atomic_disable(struct drm_plane *plane, 503static void tegra_plane_atomic_disable(struct drm_plane *plane,
554 struct drm_plane_state *old_state) 504 struct drm_plane_state *old_state)
555{ 505{
556 struct tegra_dc *dc = to_tegra_dc(old_state->crtc);
557 struct tegra_plane *p = to_tegra_plane(plane); 506 struct tegra_plane *p = to_tegra_plane(plane);
558 unsigned long flags;
559 u32 value; 507 u32 value;
560 508
561 /* rien ne va plus */ 509 /* rien ne va plus */
562 if (!old_state || !old_state->crtc) 510 if (!old_state || !old_state->crtc)
563 return; 511 return;
564 512
565 spin_lock_irqsave(&dc->lock, flags); 513 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
566
567 value = WINDOW_A_SELECT << p->index;
568 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
569
570 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
571 value &= ~WIN_ENABLE; 514 value &= ~WIN_ENABLE;
572 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); 515 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
573
574 spin_unlock_irqrestore(&dc->lock, flags);
575} 516}
576 517
577static void tegra_plane_atomic_update(struct drm_plane *plane, 518static void tegra_plane_atomic_update(struct drm_plane *plane,
578 struct drm_plane_state *old_state) 519 struct drm_plane_state *old_state)
579{ 520{
580 struct tegra_plane_state *state = to_tegra_plane_state(plane->state); 521 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
581 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
582 struct drm_framebuffer *fb = plane->state->fb; 522 struct drm_framebuffer *fb = plane->state->fb;
583 struct tegra_plane *p = to_tegra_plane(plane); 523 struct tegra_plane *p = to_tegra_plane(plane);
584 struct tegra_dc_window window; 524 struct tegra_dc_window window;
@@ -604,6 +544,7 @@ static void tegra_plane_atomic_update(struct drm_plane *plane,
604 window.bottom_up = tegra_fb_is_bottom_up(fb); 544 window.bottom_up = tegra_fb_is_bottom_up(fb);
605 545
606 /* copy from state */ 546 /* copy from state */
547 window.zpos = plane->state->normalized_zpos;
607 window.tiling = state->tiling; 548 window.tiling = state->tiling;
608 window.format = state->format; 549 window.format = state->format;
609 window.swap = state->swap; 550 window.swap = state->swap;
@@ -622,7 +563,7 @@ static void tegra_plane_atomic_update(struct drm_plane *plane,
622 window.stride[i] = fb->pitches[i]; 563 window.stride[i] = fb->pitches[i];
623 } 564 }
624 565
625 tegra_dc_setup_window(dc, p->index, &window); 566 tegra_dc_setup_window(p, &window);
626} 567}
627 568
628static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = { 569static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
@@ -631,8 +572,7 @@ static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
631 .atomic_update = tegra_plane_atomic_update, 572 .atomic_update = tegra_plane_atomic_update,
632}; 573};
633 574
634static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, 575static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
635 struct tegra_dc *dc)
636{ 576{
637 /* 577 /*
638 * Ideally this would use drm_crtc_mask(), but that would require the 578 * Ideally this would use drm_crtc_mask(), but that would require the
@@ -646,7 +586,14 @@ static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
646 * of CRTCs that have been registered, and should therefore always be 586 * of CRTCs that have been registered, and should therefore always be
647 * the same as drm_crtc_index() after registration. 587 * the same as drm_crtc_index() after registration.
648 */ 588 */
649 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc; 589 return 1 << drm->mode_config.num_crtc;
590}
591
592static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
593 struct tegra_dc *dc)
594{
595 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
596 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
650 struct tegra_plane *plane; 597 struct tegra_plane *plane;
651 unsigned int num_formats; 598 unsigned int num_formats;
652 const u32 *formats; 599 const u32 *formats;
@@ -656,13 +603,17 @@ static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
656 if (!plane) 603 if (!plane)
657 return ERR_PTR(-ENOMEM); 604 return ERR_PTR(-ENOMEM);
658 605
659 num_formats = ARRAY_SIZE(tegra_primary_plane_formats); 606 /* Always use window A as primary window */
660 formats = tegra_primary_plane_formats; 607 plane->offset = 0xa00;
608 plane->index = 0;
609 plane->dc = dc;
610
611 num_formats = dc->soc->num_primary_formats;
612 formats = dc->soc->primary_formats;
661 613
662 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 614 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
663 &tegra_primary_plane_funcs, formats, 615 &tegra_plane_funcs, formats,
664 num_formats, NULL, 616 num_formats, NULL, type, NULL);
665 DRM_PLANE_TYPE_PRIMARY, NULL);
666 if (err < 0) { 617 if (err < 0) {
667 kfree(plane); 618 kfree(plane);
668 return ERR_PTR(err); 619 return ERR_PTR(err);
@@ -670,6 +621,9 @@ static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
670 621
671 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 622 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
672 623
624 if (dc->soc->supports_blending)
625 drm_plane_create_zpos_property(&plane->base, 0, 0, 255);
626
673 return &plane->base; 627 return &plane->base;
674} 628}
675 629
@@ -786,15 +740,6 @@ static void tegra_cursor_atomic_disable(struct drm_plane *plane,
786 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 740 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
787} 741}
788 742
789static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
790 .update_plane = drm_atomic_helper_update_plane,
791 .disable_plane = drm_atomic_helper_disable_plane,
792 .destroy = tegra_plane_destroy,
793 .reset = tegra_plane_reset,
794 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
795 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
796};
797
798static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { 743static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
799 .atomic_check = tegra_cursor_atomic_check, 744 .atomic_check = tegra_cursor_atomic_check,
800 .atomic_update = tegra_cursor_atomic_update, 745 .atomic_update = tegra_cursor_atomic_update,
@@ -804,6 +749,7 @@ static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
804static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, 749static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
805 struct tegra_dc *dc) 750 struct tegra_dc *dc)
806{ 751{
752 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
807 struct tegra_plane *plane; 753 struct tegra_plane *plane;
808 unsigned int num_formats; 754 unsigned int num_formats;
809 const u32 *formats; 755 const u32 *formats;
@@ -821,12 +767,13 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
821 * need to special-casing the cursor plane. 767 * need to special-casing the cursor plane.
822 */ 768 */
823 plane->index = 6; 769 plane->index = 6;
770 plane->dc = dc;
824 771
825 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); 772 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
826 formats = tegra_cursor_plane_formats; 773 formats = tegra_cursor_plane_formats;
827 774
828 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, 775 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
829 &tegra_cursor_plane_funcs, formats, 776 &tegra_plane_funcs, formats,
830 num_formats, NULL, 777 num_formats, NULL,
831 DRM_PLANE_TYPE_CURSOR, NULL); 778 DRM_PLANE_TYPE_CURSOR, NULL);
832 if (err < 0) { 779 if (err < 0) {
@@ -839,24 +786,76 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
839 return &plane->base; 786 return &plane->base;
840} 787}
841 788
842static void tegra_overlay_plane_destroy(struct drm_plane *plane) 789static const u32 tegra20_overlay_formats[] = {
843{ 790 DRM_FORMAT_ARGB4444,
844 tegra_plane_destroy(plane); 791 DRM_FORMAT_ARGB1555,
845} 792 DRM_FORMAT_RGB565,
846 793 DRM_FORMAT_RGBA5551,
847static const struct drm_plane_funcs tegra_overlay_plane_funcs = { 794 DRM_FORMAT_ABGR8888,
848 .update_plane = drm_atomic_helper_update_plane, 795 DRM_FORMAT_ARGB8888,
849 .disable_plane = drm_atomic_helper_disable_plane, 796 /* non-native formats */
850 .destroy = tegra_overlay_plane_destroy, 797 DRM_FORMAT_XRGB1555,
851 .reset = tegra_plane_reset, 798 DRM_FORMAT_RGBX5551,
852 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, 799 DRM_FORMAT_XBGR8888,
853 .atomic_destroy_state = tegra_plane_atomic_destroy_state, 800 DRM_FORMAT_XRGB8888,
801 /* planar formats */
802 DRM_FORMAT_UYVY,
803 DRM_FORMAT_YUYV,
804 DRM_FORMAT_YUV420,
805 DRM_FORMAT_YUV422,
854}; 806};
855 807
856static const uint32_t tegra_overlay_plane_formats[] = { 808static const u32 tegra114_overlay_formats[] = {
857 DRM_FORMAT_XBGR8888, 809 DRM_FORMAT_ARGB4444,
810 DRM_FORMAT_ARGB1555,
811 DRM_FORMAT_RGB565,
812 DRM_FORMAT_RGBA5551,
813 DRM_FORMAT_ABGR8888,
814 DRM_FORMAT_ARGB8888,
815 /* new on Tegra114 */
816 DRM_FORMAT_ABGR4444,
817 DRM_FORMAT_ABGR1555,
818 DRM_FORMAT_BGRA5551,
819 DRM_FORMAT_XRGB1555,
820 DRM_FORMAT_RGBX5551,
821 DRM_FORMAT_XBGR1555,
822 DRM_FORMAT_BGRX5551,
823 DRM_FORMAT_BGR565,
824 DRM_FORMAT_BGRA8888,
825 DRM_FORMAT_RGBA8888,
858 DRM_FORMAT_XRGB8888, 826 DRM_FORMAT_XRGB8888,
827 DRM_FORMAT_XBGR8888,
828 /* planar formats */
829 DRM_FORMAT_UYVY,
830 DRM_FORMAT_YUYV,
831 DRM_FORMAT_YUV420,
832 DRM_FORMAT_YUV422,
833};
834
835static const u32 tegra124_overlay_formats[] = {
836 DRM_FORMAT_ARGB4444,
837 DRM_FORMAT_ARGB1555,
859 DRM_FORMAT_RGB565, 838 DRM_FORMAT_RGB565,
839 DRM_FORMAT_RGBA5551,
840 DRM_FORMAT_ABGR8888,
841 DRM_FORMAT_ARGB8888,
842 /* new on Tegra114 */
843 DRM_FORMAT_ABGR4444,
844 DRM_FORMAT_ABGR1555,
845 DRM_FORMAT_BGRA5551,
846 DRM_FORMAT_XRGB1555,
847 DRM_FORMAT_RGBX5551,
848 DRM_FORMAT_XBGR1555,
849 DRM_FORMAT_BGRX5551,
850 DRM_FORMAT_BGR565,
851 DRM_FORMAT_BGRA8888,
852 DRM_FORMAT_RGBA8888,
853 DRM_FORMAT_XRGB8888,
854 DRM_FORMAT_XBGR8888,
855 /* new on Tegra124 */
856 DRM_FORMAT_RGBX8888,
857 DRM_FORMAT_BGRX8888,
858 /* planar formats */
860 DRM_FORMAT_UYVY, 859 DRM_FORMAT_UYVY,
861 DRM_FORMAT_YUYV, 860 DRM_FORMAT_YUYV,
862 DRM_FORMAT_YUV420, 861 DRM_FORMAT_YUV420,
@@ -867,6 +866,7 @@ static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
867 struct tegra_dc *dc, 866 struct tegra_dc *dc,
868 unsigned int index) 867 unsigned int index)
869{ 868{
869 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
870 struct tegra_plane *plane; 870 struct tegra_plane *plane;
871 unsigned int num_formats; 871 unsigned int num_formats;
872 const u32 *formats; 872 const u32 *formats;
@@ -876,13 +876,15 @@ static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
876 if (!plane) 876 if (!plane)
877 return ERR_PTR(-ENOMEM); 877 return ERR_PTR(-ENOMEM);
878 878
879 plane->offset = 0xa00 + 0x200 * index;
879 plane->index = index; 880 plane->index = index;
881 plane->dc = dc;
880 882
881 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats); 883 num_formats = dc->soc->num_overlay_formats;
882 formats = tegra_overlay_plane_formats; 884 formats = dc->soc->overlay_formats;
883 885
884 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, 886 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
885 &tegra_overlay_plane_funcs, formats, 887 &tegra_plane_funcs, formats,
886 num_formats, NULL, 888 num_formats, NULL,
887 DRM_PLANE_TYPE_OVERLAY, NULL); 889 DRM_PLANE_TYPE_OVERLAY, NULL);
888 if (err < 0) { 890 if (err < 0) {
@@ -892,97 +894,71 @@ static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
892 894
893 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 895 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
894 896
897 if (dc->soc->supports_blending)
898 drm_plane_create_zpos_property(&plane->base, 0, 0, 255);
899
895 return &plane->base; 900 return &plane->base;
896} 901}
897 902
898static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) 903static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
904 struct tegra_dc *dc)
899{ 905{
900 struct drm_plane *plane; 906 struct drm_plane *plane, *primary = NULL;
901 unsigned int i; 907 unsigned int i, j;
902 908
903 for (i = 0; i < 2; i++) { 909 for (i = 0; i < dc->soc->num_wgrps; i++) {
904 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); 910 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
905 if (IS_ERR(plane)) 911
906 return PTR_ERR(plane); 912 if (wgrp->dc == dc->pipe) {
913 for (j = 0; j < wgrp->num_windows; j++) {
914 unsigned int index = wgrp->windows[j];
915
916 plane = tegra_shared_plane_create(drm, dc,
917 wgrp->index,
918 index);
919 if (IS_ERR(plane))
920 return plane;
921
922 /*
923 * Choose the first shared plane owned by this
924 * head as the primary plane.
925 */
926 if (!primary) {
927 plane->type = DRM_PLANE_TYPE_PRIMARY;
928 primary = plane;
929 }
930 }
931 }
907 } 932 }
908 933
909 return 0; 934 return primary;
910}
911
912static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
913{
914 struct tegra_dc *dc = to_tegra_dc(crtc);
915
916 if (dc->syncpt)
917 return host1x_syncpt_read(dc->syncpt);
918
919 /* fallback to software emulated VBLANK counter */
920 return drm_crtc_vblank_count(&dc->base);
921} 935}
922 936
923static int tegra_dc_enable_vblank(struct drm_crtc *crtc) 937static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
938 struct tegra_dc *dc)
924{ 939{
925 struct tegra_dc *dc = to_tegra_dc(crtc); 940 struct drm_plane *planes[2], *primary;
926 unsigned long value, flags; 941 unsigned int i;
927 942 int err;
928 spin_lock_irqsave(&dc->lock, flags);
929
930 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
931 value |= VBLANK_INT;
932 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
933
934 spin_unlock_irqrestore(&dc->lock, flags);
935
936 return 0;
937}
938
939static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
940{
941 struct tegra_dc *dc = to_tegra_dc(crtc);
942 unsigned long value, flags;
943
944 spin_lock_irqsave(&dc->lock, flags);
945
946 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
947 value &= ~VBLANK_INT;
948 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
949
950 spin_unlock_irqrestore(&dc->lock, flags);
951}
952
953static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
954{
955 struct drm_device *drm = dc->base.dev;
956 struct drm_crtc *crtc = &dc->base;
957 unsigned long flags, base;
958 struct tegra_bo *bo;
959
960 spin_lock_irqsave(&drm->event_lock, flags);
961
962 if (!dc->event) {
963 spin_unlock_irqrestore(&drm->event_lock, flags);
964 return;
965 }
966
967 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
968 943
969 spin_lock(&dc->lock); 944 primary = tegra_primary_plane_create(drm, dc);
945 if (IS_ERR(primary))
946 return primary;
970 947
971 /* check if new start address has been latched */ 948 for (i = 0; i < 2; i++) {
972 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); 949 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
973 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 950 if (IS_ERR(planes[i])) {
974 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); 951 err = PTR_ERR(planes[i]);
975 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
976 952
977 spin_unlock(&dc->lock); 953 while (i--)
954 tegra_plane_funcs.destroy(planes[i]);
978 955
979 if (base == bo->paddr + crtc->primary->fb->offsets[0]) { 956 tegra_plane_funcs.destroy(primary);
980 drm_crtc_send_vblank_event(crtc, dc->event); 957 return ERR_PTR(err);
981 drm_crtc_vblank_put(crtc); 958 }
982 dc->event = NULL;
983 } 959 }
984 960
985 spin_unlock_irqrestore(&drm->event_lock, flags); 961 return primary;
986} 962}
987 963
988static void tegra_dc_destroy(struct drm_crtc *crtc) 964static void tegra_dc_destroy(struct drm_crtc *crtc)
@@ -1035,6 +1011,379 @@ static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1035 kfree(state); 1011 kfree(state);
1036} 1012}
1037 1013
1014#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1015
1016static const struct debugfs_reg32 tegra_dc_regs[] = {
1017 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1018 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1019 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1020 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1021 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1022 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1023 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1024 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1025 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1026 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1027 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1028 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1029 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1030 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1031 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1032 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1033 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1034 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1035 DEBUGFS_REG32(DC_CMD_INT_MASK),
1036 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1037 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1038 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1039 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1040 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1041 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1042 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1043 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1044 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1045 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1046 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1047 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1048 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1049 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1050 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1051 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1052 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1053 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1054 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1055 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1056 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1057 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1058 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1059 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1060 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1061 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1062 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1063 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1064 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1065 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1066 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1067 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1068 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1069 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1070 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1071 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1072 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1073 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1074 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1075 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1076 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1077 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1078 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1079 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1080 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1081 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1082 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1083 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1084 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1085 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1086 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1087 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1088 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1089 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1090 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1091 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1092 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1093 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1094 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1095 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1096 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1097 DEBUGFS_REG32(DC_DISP_ACTIVE),
1098 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1099 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1100 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1101 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1102 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1103 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1104 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1105 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1106 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1107 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1108 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1109 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1110 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1111 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1112 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1113 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1114 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1115 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1116 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1117 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1118 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1119 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1120 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1121 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1122 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1123 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1124 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1125 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1126 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1127 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1128 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1129 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1130 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1131 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1132 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1133 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1134 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1135 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1136 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1137 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1138 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1139 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1140 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1141 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1142 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1143 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1144 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1145 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1146 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1147 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1148 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1149 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1150 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1151 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1152 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1153 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1154 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1155 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1156 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1157 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1158 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1159 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1160 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1161 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1162 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1163 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1164 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1165 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1166 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1167 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1168 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1169 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1170 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1171 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1172 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1173 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1174 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1175 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1176 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1177 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1178 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1179 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1180 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1181 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1182 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1183 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1184 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1185 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1186 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1187 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1188 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1189 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1190 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1191 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1192 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1193 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1194 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1195 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1196 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1197 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1198 DEBUGFS_REG32(DC_WIN_POSITION),
1199 DEBUGFS_REG32(DC_WIN_SIZE),
1200 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1201 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1202 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1203 DEBUGFS_REG32(DC_WIN_DDA_INC),
1204 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1205 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1206 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1207 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1208 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1209 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1210 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1211 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1212 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1213 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1214 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1215 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1216 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1217 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1218 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1219 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1220 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1221 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1222 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1223 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1224 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1225 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1226 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1227 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1228 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1229};
1230
1231static int tegra_dc_show_regs(struct seq_file *s, void *data)
1232{
1233 struct drm_info_node *node = s->private;
1234 struct tegra_dc *dc = node->info_ent->data;
1235 unsigned int i;
1236 int err = 0;
1237
1238 drm_modeset_lock(&dc->base.mutex, NULL);
1239
1240 if (!dc->base.state->active) {
1241 err = -EBUSY;
1242 goto unlock;
1243 }
1244
1245 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1246 unsigned int offset = tegra_dc_regs[i].offset;
1247
1248 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1249 offset, tegra_dc_readl(dc, offset));
1250 }
1251
1252unlock:
1253 drm_modeset_unlock(&dc->base.mutex);
1254 return err;
1255}
1256
1257static int tegra_dc_show_crc(struct seq_file *s, void *data)
1258{
1259 struct drm_info_node *node = s->private;
1260 struct tegra_dc *dc = node->info_ent->data;
1261 int err = 0;
1262 u32 value;
1263
1264 drm_modeset_lock(&dc->base.mutex, NULL);
1265
1266 if (!dc->base.state->active) {
1267 err = -EBUSY;
1268 goto unlock;
1269 }
1270
1271 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1272 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1273 tegra_dc_commit(dc);
1274
1275 drm_crtc_wait_one_vblank(&dc->base);
1276 drm_crtc_wait_one_vblank(&dc->base);
1277
1278 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1279 seq_printf(s, "%08x\n", value);
1280
1281 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1282
1283unlock:
1284 drm_modeset_unlock(&dc->base.mutex);
1285 return err;
1286}
1287
1288static int tegra_dc_show_stats(struct seq_file *s, void *data)
1289{
1290 struct drm_info_node *node = s->private;
1291 struct tegra_dc *dc = node->info_ent->data;
1292
1293 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1294 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1295 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1296 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1297
1298 return 0;
1299}
1300
1301static struct drm_info_list debugfs_files[] = {
1302 { "regs", tegra_dc_show_regs, 0, NULL },
1303 { "crc", tegra_dc_show_crc, 0, NULL },
1304 { "stats", tegra_dc_show_stats, 0, NULL },
1305};
1306
1307static int tegra_dc_late_register(struct drm_crtc *crtc)
1308{
1309 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1310 struct drm_minor *minor = crtc->dev->primary;
1311 struct dentry *root;
1312 struct tegra_dc *dc = to_tegra_dc(crtc);
1313 int err;
1314
1315#ifdef CONFIG_DEBUG_FS
1316 root = crtc->debugfs_entry;
1317#else
1318 root = NULL;
1319#endif
1320
1321 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1322 GFP_KERNEL);
1323 if (!dc->debugfs_files)
1324 return -ENOMEM;
1325
1326 for (i = 0; i < count; i++)
1327 dc->debugfs_files[i].data = dc;
1328
1329 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1330 if (err < 0)
1331 goto free;
1332
1333 return 0;
1334
1335free:
1336 kfree(dc->debugfs_files);
1337 dc->debugfs_files = NULL;
1338
1339 return err;
1340}
1341
1342static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1343{
1344 unsigned int count = ARRAY_SIZE(debugfs_files);
1345 struct drm_minor *minor = crtc->dev->primary;
1346 struct tegra_dc *dc = to_tegra_dc(crtc);
1347
1348 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1349 kfree(dc->debugfs_files);
1350 dc->debugfs_files = NULL;
1351}
1352
1353static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1354{
1355 struct tegra_dc *dc = to_tegra_dc(crtc);
1356
1357 /* XXX vblank syncpoints don't work with nvdisplay yet */
1358 if (dc->syncpt && !dc->soc->has_nvdisplay)
1359 return host1x_syncpt_read(dc->syncpt);
1360
1361 /* fallback to software emulated VBLANK counter */
1362 return drm_crtc_vblank_count(&dc->base);
1363}
1364
1365static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1366{
1367 struct tegra_dc *dc = to_tegra_dc(crtc);
1368 u32 value;
1369
1370 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1371 value |= VBLANK_INT;
1372 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1373
1374 return 0;
1375}
1376
1377static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1378{
1379 struct tegra_dc *dc = to_tegra_dc(crtc);
1380 u32 value;
1381
1382 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1383 value &= ~VBLANK_INT;
1384 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1385}
1386
1038static const struct drm_crtc_funcs tegra_crtc_funcs = { 1387static const struct drm_crtc_funcs tegra_crtc_funcs = {
1039 .page_flip = drm_atomic_helper_page_flip, 1388 .page_flip = drm_atomic_helper_page_flip,
1040 .set_config = drm_atomic_helper_set_config, 1389 .set_config = drm_atomic_helper_set_config,
@@ -1042,6 +1391,8 @@ static const struct drm_crtc_funcs tegra_crtc_funcs = {
1042 .reset = tegra_crtc_reset, 1391 .reset = tegra_crtc_reset,
1043 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, 1392 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1044 .atomic_destroy_state = tegra_crtc_atomic_destroy_state, 1393 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1394 .late_register = tegra_dc_late_register,
1395 .early_unregister = tegra_dc_early_unregister,
1045 .get_vblank_counter = tegra_dc_get_vblank_counter, 1396 .get_vblank_counter = tegra_dc_get_vblank_counter,
1046 .enable_vblank = tegra_dc_enable_vblank, 1397 .enable_vblank = tegra_dc_enable_vblank,
1047 .disable_vblank = tegra_dc_disable_vblank, 1398 .disable_vblank = tegra_dc_disable_vblank,
@@ -1054,10 +1405,12 @@ static int tegra_dc_set_timings(struct tegra_dc *dc,
1054 unsigned int v_ref_to_sync = 1; 1405 unsigned int v_ref_to_sync = 1;
1055 unsigned long value; 1406 unsigned long value;
1056 1407
1057 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 1408 if (!dc->soc->has_nvdisplay) {
1409 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1058 1410
1059 value = (v_ref_to_sync << 16) | h_ref_to_sync; 1411 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1060 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 1412 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1413 }
1061 1414
1062 value = ((mode->vsync_end - mode->vsync_start) << 16) | 1415 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1063 ((mode->hsync_end - mode->hsync_start) << 0); 1416 ((mode->hsync_end - mode->hsync_start) << 0);
@@ -1136,8 +1489,10 @@ static void tegra_dc_commit_state(struct tegra_dc *dc,
1136 state->div); 1489 state->div);
1137 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); 1490 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1138 1491
1139 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; 1492 if (!dc->soc->has_nvdisplay) {
1140 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 1493 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1494 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1495 }
1141 1496
1142 err = clk_set_rate(dc->clk, state->pclk); 1497 err = clk_set_rate(dc->clk, state->pclk);
1143 if (err < 0) 1498 if (err < 0)
@@ -1223,6 +1578,15 @@ static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1223 tegra_dc_stats_reset(&dc->stats); 1578 tegra_dc_stats_reset(&dc->stats);
1224 drm_crtc_vblank_off(crtc); 1579 drm_crtc_vblank_off(crtc);
1225 1580
1581 spin_lock_irq(&crtc->dev->event_lock);
1582
1583 if (crtc->state->event) {
1584 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1585 crtc->state->event = NULL;
1586 }
1587
1588 spin_unlock_irq(&crtc->dev->event_lock);
1589
1226 pm_runtime_put_sync(dc->dev); 1590 pm_runtime_put_sync(dc->dev);
1227} 1591}
1228 1592
@@ -1238,41 +1602,70 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1238 1602
1239 /* initialize display controller */ 1603 /* initialize display controller */
1240 if (dc->syncpt) { 1604 if (dc->syncpt) {
1241 u32 syncpt = host1x_syncpt_id(dc->syncpt); 1605 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1606
1607 if (dc->soc->has_nvdisplay)
1608 enable = 1 << 31;
1609 else
1610 enable = 1 << 8;
1242 1611
1243 value = SYNCPT_CNTRL_NO_STALL; 1612 value = SYNCPT_CNTRL_NO_STALL;
1244 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 1613 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1245 1614
1246 value = SYNCPT_VSYNC_ENABLE | syncpt; 1615 value = enable | syncpt;
1247 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); 1616 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1248 } 1617 }
1249 1618
1250 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1619 if (dc->soc->has_nvdisplay) {
1251 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1620 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1252 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1621 DSC_OBUF_UF_INT;
1253 1622 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1254 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1255 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1256 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1257 1623
1258 /* initialize timer */ 1624 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1259 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 1625 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1260 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 1626 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1261 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 1627 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1628 VBLANK_INT | FRAME_END_INT;
1629 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1262 1630
1263 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 1631 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1264 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 1632 FRAME_END_INT;
1265 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 1633 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1266 1634
1267 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1635 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1268 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1636 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1269 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1270 1637
1271 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1638 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1272 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1639 } else {
1273 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1640 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1641 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1642 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1643
1644 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1645 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1646 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1647
1648 /* initialize timer */
1649 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1650 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1651 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1652
1653 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1654 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1655 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1656
1657 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1658 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1659 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1660
1661 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1662 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1663 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1664 }
1274 1665
1275 if (dc->soc->supports_border_color) 1666 if (dc->soc->supports_background_color)
1667 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1668 else
1276 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 1669 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1277 1670
1278 /* apply PLL and pixel clock changes */ 1671 /* apply PLL and pixel clock changes */
@@ -1293,10 +1686,18 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1293 value |= DISP_CTRL_MODE_C_DISPLAY; 1686 value |= DISP_CTRL_MODE_C_DISPLAY;
1294 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1687 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1295 1688
1296 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1689 if (!dc->soc->has_nvdisplay) {
1297 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1690 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1298 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 1691 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1299 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1692 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1693 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1694 }
1695
1696 /* enable underflow reporting and display red for missing pixels */
1697 if (dc->soc->has_nvdisplay) {
1698 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1699 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1700 }
1300 1701
1301 tegra_dc_commit(dc); 1702 tegra_dc_commit(dc);
1302 1703
@@ -1306,20 +1707,43 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1306static int tegra_crtc_atomic_check(struct drm_crtc *crtc, 1707static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1307 struct drm_crtc_state *state) 1708 struct drm_crtc_state *state)
1308{ 1709{
1710 struct tegra_atomic_state *s = to_tegra_atomic_state(state->state);
1711 struct tegra_dc_state *tegra = to_dc_state(state);
1712
1713 /*
1714 * The display hub display clock needs to be fed by the display clock
1715 * with the highest frequency to ensure proper functioning of all the
1716 * displays.
1717 *
1718 * Note that this isn't used before Tegra186, but it doesn't hurt and
1719 * conditionalizing it would make the code less clean.
1720 */
1721 if (state->active) {
1722 if (!s->clk_disp || tegra->pclk > s->rate) {
1723 s->dc = to_tegra_dc(crtc);
1724 s->clk_disp = s->dc->clk;
1725 s->rate = tegra->pclk;
1726 }
1727 }
1728
1309 return 0; 1729 return 0;
1310} 1730}
1311 1731
1312static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, 1732static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1313 struct drm_crtc_state *old_crtc_state) 1733 struct drm_crtc_state *old_crtc_state)
1314{ 1734{
1315 struct tegra_dc *dc = to_tegra_dc(crtc); 1735 unsigned long flags;
1316 1736
1317 if (crtc->state->event) { 1737 if (crtc->state->event) {
1318 crtc->state->event->pipe = drm_crtc_index(crtc); 1738 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1319 1739
1320 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1740 if (drm_crtc_vblank_get(crtc) != 0)
1741 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1742 else
1743 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1744
1745 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1321 1746
1322 dc->event = crtc->state->event;
1323 crtc->state->event = NULL; 1747 crtc->state->event = NULL;
1324 } 1748 }
1325} 1749}
@@ -1329,9 +1753,15 @@ static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1329{ 1753{
1330 struct tegra_dc_state *state = to_dc_state(crtc->state); 1754 struct tegra_dc_state *state = to_dc_state(crtc->state);
1331 struct tegra_dc *dc = to_tegra_dc(crtc); 1755 struct tegra_dc *dc = to_tegra_dc(crtc);
1756 u32 value;
1332 1757
1333 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); 1758 value = state->planes << 8 | GENERAL_UPDATE;
1334 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); 1759 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1760 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1761
1762 value = state->planes | GENERAL_ACT_REQ;
1763 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1764 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1335} 1765}
1336 1766
1337static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 1767static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
@@ -1362,7 +1792,6 @@ static irqreturn_t tegra_dc_irq(int irq, void *data)
1362 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 1792 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1363 */ 1793 */
1364 drm_crtc_handle_vblank(&dc->base); 1794 drm_crtc_handle_vblank(&dc->base);
1365 tegra_dc_finish_page_flip(dc);
1366 dc->stats.vblank++; 1795 dc->stats.vblank++;
1367 } 1796 }
1368 1797
@@ -1380,357 +1809,18 @@ static irqreturn_t tegra_dc_irq(int irq, void *data)
1380 dc->stats.overflow++; 1809 dc->stats.overflow++;
1381 } 1810 }
1382 1811
1383 return IRQ_HANDLED; 1812 if (status & HEAD_UF_INT) {
1384} 1813 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1385 1814 dc->stats.underflow++;
1386static int tegra_dc_show_regs(struct seq_file *s, void *data)
1387{
1388 struct drm_info_node *node = s->private;
1389 struct tegra_dc *dc = node->info_ent->data;
1390 int err = 0;
1391
1392 drm_modeset_lock(&dc->base.mutex, NULL);
1393
1394 if (!dc->base.state->active) {
1395 err = -EBUSY;
1396 goto unlock;
1397 }
1398
1399#define DUMP_REG(name) \
1400 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1401 tegra_dc_readl(dc, name))
1402
1403 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1404 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1405 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1406 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1407 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1408 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1409 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1410 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1411 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1412 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1413 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1414 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1415 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1416 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1417 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1418 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1419 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1420 DUMP_REG(DC_CMD_INT_STATUS);
1421 DUMP_REG(DC_CMD_INT_MASK);
1422 DUMP_REG(DC_CMD_INT_ENABLE);
1423 DUMP_REG(DC_CMD_INT_TYPE);
1424 DUMP_REG(DC_CMD_INT_POLARITY);
1425 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1426 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1427 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1428 DUMP_REG(DC_CMD_STATE_ACCESS);
1429 DUMP_REG(DC_CMD_STATE_CONTROL);
1430 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1431 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1432 DUMP_REG(DC_COM_CRC_CONTROL);
1433 DUMP_REG(DC_COM_CRC_CHECKSUM);
1434 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1435 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1436 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1437 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1438 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1439 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1440 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1441 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1442 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1443 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1444 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1445 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1446 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1447 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1448 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1449 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1450 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1451 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1452 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1453 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1454 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1455 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1456 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1457 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1458 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1459 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1460 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1461 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1462 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1463 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1464 DUMP_REG(DC_COM_SPI_CONTROL);
1465 DUMP_REG(DC_COM_SPI_START_BYTE);
1466 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1467 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1468 DUMP_REG(DC_COM_HSPI_CS_DC);
1469 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1470 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1471 DUMP_REG(DC_COM_GPIO_CTRL);
1472 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1473 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1474 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1475 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1476 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1477 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1478 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1479 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1480 DUMP_REG(DC_DISP_REF_TO_SYNC);
1481 DUMP_REG(DC_DISP_SYNC_WIDTH);
1482 DUMP_REG(DC_DISP_BACK_PORCH);
1483 DUMP_REG(DC_DISP_ACTIVE);
1484 DUMP_REG(DC_DISP_FRONT_PORCH);
1485 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1486 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1487 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1488 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1489 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1490 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1491 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1492 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1493 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1494 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1495 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1496 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1497 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1498 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1499 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1500 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1501 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1502 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1503 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1504 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1505 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1506 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1507 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1508 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1509 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1510 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1511 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1512 DUMP_REG(DC_DISP_M0_CONTROL);
1513 DUMP_REG(DC_DISP_M1_CONTROL);
1514 DUMP_REG(DC_DISP_DI_CONTROL);
1515 DUMP_REG(DC_DISP_PP_CONTROL);
1516 DUMP_REG(DC_DISP_PP_SELECT_A);
1517 DUMP_REG(DC_DISP_PP_SELECT_B);
1518 DUMP_REG(DC_DISP_PP_SELECT_C);
1519 DUMP_REG(DC_DISP_PP_SELECT_D);
1520 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1521 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1522 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1523 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1524 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1525 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1526 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1527 DUMP_REG(DC_DISP_BORDER_COLOR);
1528 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1529 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1530 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1531 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1532 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1533 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1534 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1535 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1536 DUMP_REG(DC_DISP_CURSOR_POSITION);
1537 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1538 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1539 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1540 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1541 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1542 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1543 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1544 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1545 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1546 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1547 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1548 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1549 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1550 DUMP_REG(DC_DISP_SD_CONTROL);
1551 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1552 DUMP_REG(DC_DISP_SD_LUT(0));
1553 DUMP_REG(DC_DISP_SD_LUT(1));
1554 DUMP_REG(DC_DISP_SD_LUT(2));
1555 DUMP_REG(DC_DISP_SD_LUT(3));
1556 DUMP_REG(DC_DISP_SD_LUT(4));
1557 DUMP_REG(DC_DISP_SD_LUT(5));
1558 DUMP_REG(DC_DISP_SD_LUT(6));
1559 DUMP_REG(DC_DISP_SD_LUT(7));
1560 DUMP_REG(DC_DISP_SD_LUT(8));
1561 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1562 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1563 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1564 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1565 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1566 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1567 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1568 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1569 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1570 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1571 DUMP_REG(DC_DISP_SD_BL_TF(0));
1572 DUMP_REG(DC_DISP_SD_BL_TF(1));
1573 DUMP_REG(DC_DISP_SD_BL_TF(2));
1574 DUMP_REG(DC_DISP_SD_BL_TF(3));
1575 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1576 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1577 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1578 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1579 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1580 DUMP_REG(DC_WIN_WIN_OPTIONS);
1581 DUMP_REG(DC_WIN_BYTE_SWAP);
1582 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1583 DUMP_REG(DC_WIN_COLOR_DEPTH);
1584 DUMP_REG(DC_WIN_POSITION);
1585 DUMP_REG(DC_WIN_SIZE);
1586 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1587 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1588 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1589 DUMP_REG(DC_WIN_DDA_INC);
1590 DUMP_REG(DC_WIN_LINE_STRIDE);
1591 DUMP_REG(DC_WIN_BUF_STRIDE);
1592 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1593 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1594 DUMP_REG(DC_WIN_DV_CONTROL);
1595 DUMP_REG(DC_WIN_BLEND_NOKEY);
1596 DUMP_REG(DC_WIN_BLEND_1WIN);
1597 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1598 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1599 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1600 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1601 DUMP_REG(DC_WINBUF_START_ADDR);
1602 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1603 DUMP_REG(DC_WINBUF_START_ADDR_U);
1604 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1605 DUMP_REG(DC_WINBUF_START_ADDR_V);
1606 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1607 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1608 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1609 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1610 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1611 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1612 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1613 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1614 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1615
1616#undef DUMP_REG
1617
1618unlock:
1619 drm_modeset_unlock(&dc->base.mutex);
1620 return err;
1621}
1622
1623static int tegra_dc_show_crc(struct seq_file *s, void *data)
1624{
1625 struct drm_info_node *node = s->private;
1626 struct tegra_dc *dc = node->info_ent->data;
1627 int err = 0;
1628 u32 value;
1629
1630 drm_modeset_lock(&dc->base.mutex, NULL);
1631
1632 if (!dc->base.state->active) {
1633 err = -EBUSY;
1634 goto unlock;
1635 }
1636
1637 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1638 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1639 tegra_dc_commit(dc);
1640
1641 drm_crtc_wait_one_vblank(&dc->base);
1642 drm_crtc_wait_one_vblank(&dc->base);
1643
1644 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1645 seq_printf(s, "%08x\n", value);
1646
1647 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1648
1649unlock:
1650 drm_modeset_unlock(&dc->base.mutex);
1651 return err;
1652}
1653
1654static int tegra_dc_show_stats(struct seq_file *s, void *data)
1655{
1656 struct drm_info_node *node = s->private;
1657 struct tegra_dc *dc = node->info_ent->data;
1658
1659 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1660 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1661 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1662 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1663
1664 return 0;
1665}
1666
1667static struct drm_info_list debugfs_files[] = {
1668 { "regs", tegra_dc_show_regs, 0, NULL },
1669 { "crc", tegra_dc_show_crc, 0, NULL },
1670 { "stats", tegra_dc_show_stats, 0, NULL },
1671};
1672
1673static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1674{
1675 unsigned int i;
1676 char *name;
1677 int err;
1678
1679 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1680 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1681 kfree(name);
1682
1683 if (!dc->debugfs)
1684 return -ENOMEM;
1685
1686 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1687 GFP_KERNEL);
1688 if (!dc->debugfs_files) {
1689 err = -ENOMEM;
1690 goto remove;
1691 } 1815 }
1692 1816
1693 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 1817 return IRQ_HANDLED;
1694 dc->debugfs_files[i].data = dc;
1695
1696 err = drm_debugfs_create_files(dc->debugfs_files,
1697 ARRAY_SIZE(debugfs_files),
1698 dc->debugfs, minor);
1699 if (err < 0)
1700 goto free;
1701
1702 dc->minor = minor;
1703
1704 return 0;
1705
1706free:
1707 kfree(dc->debugfs_files);
1708 dc->debugfs_files = NULL;
1709remove:
1710 debugfs_remove(dc->debugfs);
1711 dc->debugfs = NULL;
1712
1713 return err;
1714}
1715
1716static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1717{
1718 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1719 dc->minor);
1720 dc->minor = NULL;
1721
1722 kfree(dc->debugfs_files);
1723 dc->debugfs_files = NULL;
1724
1725 debugfs_remove(dc->debugfs);
1726 dc->debugfs = NULL;
1727
1728 return 0;
1729} 1818}
1730 1819
1731static int tegra_dc_init(struct host1x_client *client) 1820static int tegra_dc_init(struct host1x_client *client)
1732{ 1821{
1733 struct drm_device *drm = dev_get_drvdata(client->parent); 1822 struct drm_device *drm = dev_get_drvdata(client->parent);
1823 struct iommu_group *group = iommu_group_get(client->dev);
1734 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; 1824 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1735 struct tegra_dc *dc = host1x_client_to_dc(client); 1825 struct tegra_dc *dc = host1x_client_to_dc(client);
1736 struct tegra_drm *tegra = drm->dev_private; 1826 struct tegra_drm *tegra = drm->dev_private;
@@ -1742,18 +1832,27 @@ static int tegra_dc_init(struct host1x_client *client)
1742 if (!dc->syncpt) 1832 if (!dc->syncpt)
1743 dev_warn(dc->dev, "failed to allocate syncpoint\n"); 1833 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1744 1834
1745 if (tegra->domain) { 1835 if (group && tegra->domain) {
1746 err = iommu_attach_device(tegra->domain, dc->dev); 1836 if (group != tegra->group) {
1747 if (err < 0) { 1837 err = iommu_attach_group(tegra->domain, group);
1748 dev_err(dc->dev, "failed to attach to domain: %d\n", 1838 if (err < 0) {
1749 err); 1839 dev_err(dc->dev,
1750 return err; 1840 "failed to attach to domain: %d\n",
1841 err);
1842 return err;
1843 }
1844
1845 tegra->group = group;
1751 } 1846 }
1752 1847
1753 dc->domain = tegra->domain; 1848 dc->domain = tegra->domain;
1754 } 1849 }
1755 1850
1756 primary = tegra_dc_primary_plane_create(drm, dc); 1851 if (dc->soc->wgrps)
1852 primary = tegra_dc_add_shared_planes(drm, dc);
1853 else
1854 primary = tegra_dc_add_planes(drm, dc);
1855
1757 if (IS_ERR(primary)) { 1856 if (IS_ERR(primary)) {
1758 err = PTR_ERR(primary); 1857 err = PTR_ERR(primary);
1759 goto cleanup; 1858 goto cleanup;
@@ -1787,16 +1886,6 @@ static int tegra_dc_init(struct host1x_client *client)
1787 goto cleanup; 1886 goto cleanup;
1788 } 1887 }
1789 1888
1790 err = tegra_dc_add_planes(drm, dc);
1791 if (err < 0)
1792 goto cleanup;
1793
1794 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1795 err = tegra_dc_debugfs_init(dc, drm->primary);
1796 if (err < 0)
1797 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1798 }
1799
1800 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, 1889 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1801 dev_name(dc->dev), dc); 1890 dev_name(dc->dev), dc);
1802 if (err < 0) { 1891 if (err < 0) {
@@ -1808,14 +1897,14 @@ static int tegra_dc_init(struct host1x_client *client)
1808 return 0; 1897 return 0;
1809 1898
1810cleanup: 1899cleanup:
1811 if (cursor) 1900 if (!IS_ERR_OR_NULL(cursor))
1812 drm_plane_cleanup(cursor); 1901 drm_plane_cleanup(cursor);
1813 1902
1814 if (primary) 1903 if (!IS_ERR(primary))
1815 drm_plane_cleanup(primary); 1904 drm_plane_cleanup(primary);
1816 1905
1817 if (tegra->domain) { 1906 if (group && tegra->domain) {
1818 iommu_detach_device(tegra->domain, dc->dev); 1907 iommu_detach_group(tegra->domain, group);
1819 dc->domain = NULL; 1908 dc->domain = NULL;
1820 } 1909 }
1821 1910
@@ -1824,25 +1913,20 @@ cleanup:
1824 1913
1825static int tegra_dc_exit(struct host1x_client *client) 1914static int tegra_dc_exit(struct host1x_client *client)
1826{ 1915{
1916 struct iommu_group *group = iommu_group_get(client->dev);
1827 struct tegra_dc *dc = host1x_client_to_dc(client); 1917 struct tegra_dc *dc = host1x_client_to_dc(client);
1828 int err; 1918 int err;
1829 1919
1830 devm_free_irq(dc->dev, dc->irq, dc); 1920 devm_free_irq(dc->dev, dc->irq, dc);
1831 1921
1832 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1833 err = tegra_dc_debugfs_exit(dc);
1834 if (err < 0)
1835 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1836 }
1837
1838 err = tegra_dc_rgb_exit(dc); 1922 err = tegra_dc_rgb_exit(dc);
1839 if (err) { 1923 if (err) {
1840 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 1924 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1841 return err; 1925 return err;
1842 } 1926 }
1843 1927
1844 if (dc->domain) { 1928 if (group && dc->domain) {
1845 iommu_detach_device(dc->domain, dc->dev); 1929 iommu_detach_group(dc->domain, group);
1846 dc->domain = NULL; 1930 dc->domain = NULL;
1847 } 1931 }
1848 1932
@@ -1857,57 +1941,138 @@ static const struct host1x_client_ops dc_client_ops = {
1857}; 1941};
1858 1942
1859static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 1943static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1860 .supports_border_color = true, 1944 .supports_background_color = false,
1861 .supports_interlacing = false, 1945 .supports_interlacing = false,
1862 .supports_cursor = false, 1946 .supports_cursor = false,
1863 .supports_block_linear = false, 1947 .supports_block_linear = false,
1948 .supports_blending = false,
1864 .pitch_align = 8, 1949 .pitch_align = 8,
1865 .has_powergate = false, 1950 .has_powergate = false,
1866 .broken_reset = true, 1951 .coupled_pm = true,
1952 .has_nvdisplay = false,
1953 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1954 .primary_formats = tegra20_primary_formats,
1955 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1956 .overlay_formats = tegra20_overlay_formats,
1867}; 1957};
1868 1958
1869static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 1959static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1870 .supports_border_color = true, 1960 .supports_background_color = false,
1871 .supports_interlacing = false, 1961 .supports_interlacing = false,
1872 .supports_cursor = false, 1962 .supports_cursor = false,
1873 .supports_block_linear = false, 1963 .supports_block_linear = false,
1964 .supports_blending = false,
1874 .pitch_align = 8, 1965 .pitch_align = 8,
1875 .has_powergate = false, 1966 .has_powergate = false,
1876 .broken_reset = false, 1967 .coupled_pm = false,
1968 .has_nvdisplay = false,
1969 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1970 .primary_formats = tegra20_primary_formats,
1971 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1972 .overlay_formats = tegra20_overlay_formats,
1877}; 1973};
1878 1974
1879static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 1975static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1880 .supports_border_color = true, 1976 .supports_background_color = false,
1881 .supports_interlacing = false, 1977 .supports_interlacing = false,
1882 .supports_cursor = false, 1978 .supports_cursor = false,
1883 .supports_block_linear = false, 1979 .supports_block_linear = false,
1980 .supports_blending = false,
1884 .pitch_align = 64, 1981 .pitch_align = 64,
1885 .has_powergate = true, 1982 .has_powergate = true,
1886 .broken_reset = false, 1983 .coupled_pm = false,
1984 .has_nvdisplay = false,
1985 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
1986 .primary_formats = tegra114_primary_formats,
1987 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
1988 .overlay_formats = tegra114_overlay_formats,
1887}; 1989};
1888 1990
1889static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 1991static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1890 .supports_border_color = false, 1992 .supports_background_color = true,
1891 .supports_interlacing = true, 1993 .supports_interlacing = true,
1892 .supports_cursor = true, 1994 .supports_cursor = true,
1893 .supports_block_linear = true, 1995 .supports_block_linear = true,
1996 .supports_blending = true,
1894 .pitch_align = 64, 1997 .pitch_align = 64,
1895 .has_powergate = true, 1998 .has_powergate = true,
1896 .broken_reset = false, 1999 .coupled_pm = false,
2000 .has_nvdisplay = false,
2001 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2002 .primary_formats = tegra114_primary_formats,
2003 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2004 .overlay_formats = tegra114_overlay_formats,
1897}; 2005};
1898 2006
1899static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 2007static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1900 .supports_border_color = false, 2008 .supports_background_color = true,
1901 .supports_interlacing = true, 2009 .supports_interlacing = true,
1902 .supports_cursor = true, 2010 .supports_cursor = true,
1903 .supports_block_linear = true, 2011 .supports_block_linear = true,
2012 .supports_blending = true,
1904 .pitch_align = 64, 2013 .pitch_align = 64,
1905 .has_powergate = true, 2014 .has_powergate = true,
1906 .broken_reset = false, 2015 .coupled_pm = false,
2016 .has_nvdisplay = false,
2017 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2018 .primary_formats = tegra114_primary_formats,
2019 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2020 .overlay_formats = tegra114_overlay_formats,
2021};
2022
2023static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2024 {
2025 .index = 0,
2026 .dc = 0,
2027 .windows = (const unsigned int[]) { 0 },
2028 .num_windows = 1,
2029 }, {
2030 .index = 1,
2031 .dc = 1,
2032 .windows = (const unsigned int[]) { 1 },
2033 .num_windows = 1,
2034 }, {
2035 .index = 2,
2036 .dc = 1,
2037 .windows = (const unsigned int[]) { 2 },
2038 .num_windows = 1,
2039 }, {
2040 .index = 3,
2041 .dc = 2,
2042 .windows = (const unsigned int[]) { 3 },
2043 .num_windows = 1,
2044 }, {
2045 .index = 4,
2046 .dc = 2,
2047 .windows = (const unsigned int[]) { 4 },
2048 .num_windows = 1,
2049 }, {
2050 .index = 5,
2051 .dc = 2,
2052 .windows = (const unsigned int[]) { 5 },
2053 .num_windows = 1,
2054 },
2055};
2056
2057static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2058 .supports_background_color = true,
2059 .supports_interlacing = true,
2060 .supports_cursor = true,
2061 .supports_block_linear = true,
2062 .supports_blending = true,
2063 .pitch_align = 64,
2064 .has_powergate = false,
2065 .coupled_pm = false,
2066 .has_nvdisplay = true,
2067 .wgrps = tegra186_dc_wgrps,
2068 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
1907}; 2069};
1908 2070
1909static const struct of_device_id tegra_dc_of_match[] = { 2071static const struct of_device_id tegra_dc_of_match[] = {
1910 { 2072 {
2073 .compatible = "nvidia,tegra186-dc",
2074 .data = &tegra186_dc_soc_info,
2075 }, {
1911 .compatible = "nvidia,tegra210-dc", 2076 .compatible = "nvidia,tegra210-dc",
1912 .data = &tegra210_dc_soc_info, 2077 .data = &tegra210_dc_soc_info,
1913 }, { 2078 }, {
@@ -1965,6 +2130,43 @@ static int tegra_dc_parse_dt(struct tegra_dc *dc)
1965 return 0; 2130 return 0;
1966} 2131}
1967 2132
2133static int tegra_dc_match_by_pipe(struct device *dev, void *data)
2134{
2135 struct tegra_dc *dc = dev_get_drvdata(dev);
2136 unsigned int pipe = (unsigned long)data;
2137
2138 return dc->pipe == pipe;
2139}
2140
2141static int tegra_dc_couple(struct tegra_dc *dc)
2142{
2143 /*
2144 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2145 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2146 * POWER_CONTROL registers during CRTC enabling.
2147 */
2148 if (dc->soc->coupled_pm && dc->pipe == 1) {
2149 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE;
2150 struct device_link *link;
2151 struct device *partner;
2152
2153 partner = driver_find_device(dc->dev->driver, NULL, 0,
2154 tegra_dc_match_by_pipe);
2155 if (!partner)
2156 return -EPROBE_DEFER;
2157
2158 link = device_link_add(dc->dev, partner, flags);
2159 if (!link) {
2160 dev_err(dc->dev, "failed to link controllers\n");
2161 return -EINVAL;
2162 }
2163
2164 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2165 }
2166
2167 return 0;
2168}
2169
1968static int tegra_dc_probe(struct platform_device *pdev) 2170static int tegra_dc_probe(struct platform_device *pdev)
1969{ 2171{
1970 struct resource *regs; 2172 struct resource *regs;
@@ -1977,7 +2179,6 @@ static int tegra_dc_probe(struct platform_device *pdev)
1977 2179
1978 dc->soc = of_device_get_match_data(&pdev->dev); 2180 dc->soc = of_device_get_match_data(&pdev->dev);
1979 2181
1980 spin_lock_init(&dc->lock);
1981 INIT_LIST_HEAD(&dc->list); 2182 INIT_LIST_HEAD(&dc->list);
1982 dc->dev = &pdev->dev; 2183 dc->dev = &pdev->dev;
1983 2184
@@ -1985,6 +2186,10 @@ static int tegra_dc_probe(struct platform_device *pdev)
1985 if (err < 0) 2186 if (err < 0)
1986 return err; 2187 return err;
1987 2188
2189 err = tegra_dc_couple(dc);
2190 if (err < 0)
2191 return err;
2192
1988 dc->clk = devm_clk_get(&pdev->dev, NULL); 2193 dc->clk = devm_clk_get(&pdev->dev, NULL);
1989 if (IS_ERR(dc->clk)) { 2194 if (IS_ERR(dc->clk)) {
1990 dev_err(&pdev->dev, "failed to get clock\n"); 2195 dev_err(&pdev->dev, "failed to get clock\n");
@@ -1998,21 +2203,19 @@ static int tegra_dc_probe(struct platform_device *pdev)
1998 } 2203 }
1999 2204
2000 /* assert reset and disable clock */ 2205 /* assert reset and disable clock */
2001 if (!dc->soc->broken_reset) { 2206 err = clk_prepare_enable(dc->clk);
2002 err = clk_prepare_enable(dc->clk); 2207 if (err < 0)
2003 if (err < 0) 2208 return err;
2004 return err;
2005 2209
2006 usleep_range(2000, 4000); 2210 usleep_range(2000, 4000);
2007 2211
2008 err = reset_control_assert(dc->rst); 2212 err = reset_control_assert(dc->rst);
2009 if (err < 0) 2213 if (err < 0)
2010 return err; 2214 return err;
2011 2215
2012 usleep_range(2000, 4000); 2216 usleep_range(2000, 4000);
2013 2217
2014 clk_disable_unprepare(dc->clk); 2218 clk_disable_unprepare(dc->clk);
2015 }
2016 2219
2017 if (dc->soc->has_powergate) { 2220 if (dc->soc->has_powergate) {
2018 if (dc->pipe == 0) 2221 if (dc->pipe == 0)
@@ -2086,12 +2289,10 @@ static int tegra_dc_suspend(struct device *dev)
2086 struct tegra_dc *dc = dev_get_drvdata(dev); 2289 struct tegra_dc *dc = dev_get_drvdata(dev);
2087 int err; 2290 int err;
2088 2291
2089 if (!dc->soc->broken_reset) { 2292 err = reset_control_assert(dc->rst);
2090 err = reset_control_assert(dc->rst); 2293 if (err < 0) {
2091 if (err < 0) { 2294 dev_err(dev, "failed to assert reset: %d\n", err);
2092 dev_err(dev, "failed to assert reset: %d\n", err); 2295 return err;
2093 return err;
2094 }
2095 } 2296 }
2096 2297
2097 if (dc->soc->has_powergate) 2298 if (dc->soc->has_powergate)
@@ -2121,13 +2322,10 @@ static int tegra_dc_resume(struct device *dev)
2121 return err; 2322 return err;
2122 } 2323 }
2123 2324
2124 if (!dc->soc->broken_reset) { 2325 err = reset_control_deassert(dc->rst);
2125 err = reset_control_deassert(dc->rst); 2326 if (err < 0) {
2126 if (err < 0) { 2327 dev_err(dev, "failed to deassert reset: %d\n", err);
2127 dev_err(dev, 2328 return err;
2128 "failed to deassert reset: %d\n", err);
2129 return err;
2130 }
2131 } 2329 }
2132 } 2330 }
2133 2331
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h
index cb100b6e3282..096a81ad6d8d 100644
--- a/drivers/gpu/drm/tegra/dc.h
+++ b/drivers/gpu/drm/tegra/dc.h
@@ -18,6 +18,24 @@
18 18
19struct tegra_output; 19struct tegra_output;
20 20
21struct tegra_dc_state {
22 struct drm_crtc_state base;
23
24 struct clk *clk;
25 unsigned long pclk;
26 unsigned int div;
27
28 u32 planes;
29};
30
31static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
32{
33 if (state)
34 return container_of(state, struct tegra_dc_state, base);
35
36 return NULL;
37}
38
21struct tegra_dc_stats { 39struct tegra_dc_stats {
22 unsigned long frames; 40 unsigned long frames;
23 unsigned long vblank; 41 unsigned long vblank;
@@ -25,21 +43,35 @@ struct tegra_dc_stats {
25 unsigned long overflow; 43 unsigned long overflow;
26}; 44};
27 45
46struct tegra_windowgroup_soc {
47 unsigned int index;
48 unsigned int dc;
49 const unsigned int *windows;
50 unsigned int num_windows;
51};
52
28struct tegra_dc_soc_info { 53struct tegra_dc_soc_info {
29 bool supports_border_color; 54 bool supports_background_color;
30 bool supports_interlacing; 55 bool supports_interlacing;
31 bool supports_cursor; 56 bool supports_cursor;
32 bool supports_block_linear; 57 bool supports_block_linear;
58 bool supports_blending;
33 unsigned int pitch_align; 59 unsigned int pitch_align;
34 bool has_powergate; 60 bool has_powergate;
35 bool broken_reset; 61 bool coupled_pm;
62 bool has_nvdisplay;
63 const struct tegra_windowgroup_soc *wgrps;
64 unsigned int num_wgrps;
65 const u32 *primary_formats;
66 unsigned int num_primary_formats;
67 const u32 *overlay_formats;
68 unsigned int num_overlay_formats;
36}; 69};
37 70
38struct tegra_dc { 71struct tegra_dc {
39 struct host1x_client client; 72 struct host1x_client client;
40 struct host1x_syncpt *syncpt; 73 struct host1x_syncpt *syncpt;
41 struct device *dev; 74 struct device *dev;
42 spinlock_t lock;
43 75
44 struct drm_crtc base; 76 struct drm_crtc base;
45 unsigned int powergate; 77 unsigned int powergate;
@@ -56,11 +88,6 @@ struct tegra_dc {
56 struct list_head list; 88 struct list_head list;
57 89
58 struct drm_info_list *debugfs_files; 90 struct drm_info_list *debugfs_files;
59 struct drm_minor *minor;
60 struct dentry *debugfs;
61
62 /* page-flip handling */
63 struct drm_pending_vblank_event *event;
64 91
65 const struct tegra_dc_soc_info *soc; 92 const struct tegra_dc_soc_info *soc;
66 93
@@ -110,6 +137,7 @@ struct tegra_dc_window {
110 unsigned int bits_per_pixel; 137 unsigned int bits_per_pixel;
111 unsigned int stride[2]; 138 unsigned int stride[2];
112 unsigned long base[3]; 139 unsigned long base[3];
140 unsigned int zpos;
113 bool bottom_up; 141 bool bottom_up;
114 142
115 struct tegra_bo_tiling tiling; 143 struct tegra_bo_tiling tiling;
@@ -118,6 +146,7 @@ struct tegra_dc_window {
118}; 146};
119 147
120/* from dc.c */ 148/* from dc.c */
149bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev);
121void tegra_dc_commit(struct tegra_dc *dc); 150void tegra_dc_commit(struct tegra_dc *dc);
122int tegra_dc_state_setup_clock(struct tegra_dc *dc, 151int tegra_dc_state_setup_clock(struct tegra_dc *dc,
123 struct drm_crtc_state *crtc_state, 152 struct drm_crtc_state *crtc_state,
@@ -167,15 +196,26 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
167#define DC_CMD_INT_ENABLE 0x039 196#define DC_CMD_INT_ENABLE 0x039
168#define DC_CMD_INT_TYPE 0x03a 197#define DC_CMD_INT_TYPE 0x03a
169#define DC_CMD_INT_POLARITY 0x03b 198#define DC_CMD_INT_POLARITY 0x03b
170#define CTXSW_INT (1 << 0) 199#define CTXSW_INT (1 << 0)
171#define FRAME_END_INT (1 << 1) 200#define FRAME_END_INT (1 << 1)
172#define VBLANK_INT (1 << 2) 201#define VBLANK_INT (1 << 2)
173#define WIN_A_UF_INT (1 << 8) 202#define V_PULSE3_INT (1 << 4)
174#define WIN_B_UF_INT (1 << 9) 203#define V_PULSE2_INT (1 << 5)
175#define WIN_C_UF_INT (1 << 10) 204#define REGION_CRC_INT (1 << 6)
176#define WIN_A_OF_INT (1 << 14) 205#define REG_TMOUT_INT (1 << 7)
177#define WIN_B_OF_INT (1 << 15) 206#define WIN_A_UF_INT (1 << 8)
178#define WIN_C_OF_INT (1 << 16) 207#define WIN_B_UF_INT (1 << 9)
208#define WIN_C_UF_INT (1 << 10)
209#define MSF_INT (1 << 12)
210#define WIN_A_OF_INT (1 << 14)
211#define WIN_B_OF_INT (1 << 15)
212#define WIN_C_OF_INT (1 << 16)
213#define HEAD_UF_INT (1 << 23)
214#define SD3_BUCKET_WALK_DONE_INT (1 << 24)
215#define DSC_OBUF_UF_INT (1 << 26)
216#define DSC_RBUF_UF_INT (1 << 27)
217#define DSC_BBUF_UF_INT (1 << 28)
218#define DSC_TO_UF_INT (1 << 29)
179 219
180#define DC_CMD_SIGNAL_RAISE1 0x03c 220#define DC_CMD_SIGNAL_RAISE1 0x03c
181#define DC_CMD_SIGNAL_RAISE2 0x03d 221#define DC_CMD_SIGNAL_RAISE2 0x03d
@@ -196,6 +236,8 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
196#define WIN_B_UPDATE (1 << 10) 236#define WIN_B_UPDATE (1 << 10)
197#define WIN_C_UPDATE (1 << 11) 237#define WIN_C_UPDATE (1 << 11)
198#define CURSOR_UPDATE (1 << 15) 238#define CURSOR_UPDATE (1 << 15)
239#define COMMON_ACTREQ (1 << 16)
240#define COMMON_UPDATE (1 << 17)
199#define NC_HOST_TRIG (1 << 24) 241#define NC_HOST_TRIG (1 << 24)
200 242
201#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 243#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
@@ -238,6 +280,10 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
238#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 280#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
239#define DC_COM_CRC_CHECKSUM_LATCHED 0x329 281#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
240 282
283#define DC_COM_RG_UNDERFLOW 0x365
284#define UNDERFLOW_MODE_RED (1 << 8)
285#define UNDERFLOW_REPORT_ENABLE (1 << 0)
286
241#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 287#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
242#define H_PULSE0_ENABLE (1 << 8) 288#define H_PULSE0_ENABLE (1 << 8)
243#define H_PULSE1_ENABLE (1 << 10) 289#define H_PULSE1_ENABLE (1 << 10)
@@ -249,10 +295,10 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
249#define HDMI_ENABLE (1 << 30) 295#define HDMI_ENABLE (1 << 30)
250#define DSI_ENABLE (1 << 29) 296#define DSI_ENABLE (1 << 29)
251#define SOR1_TIMING_CYA (1 << 27) 297#define SOR1_TIMING_CYA (1 << 27)
252#define SOR1_ENABLE (1 << 26)
253#define SOR_ENABLE (1 << 25)
254#define CURSOR_ENABLE (1 << 16) 298#define CURSOR_ENABLE (1 << 16)
255 299
300#define SOR_ENABLE(x) (1 << (25 + (x)))
301
256#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 302#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
257#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) 303#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
258#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) 304#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
@@ -360,29 +406,33 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
360#define DISP_ORDER_BLUE_RED (1 << 9) 406#define DISP_ORDER_BLUE_RED (1 << 9)
361 407
362#define DC_DISP_DISP_COLOR_CONTROL 0x430 408#define DC_DISP_DISP_COLOR_CONTROL 0x430
363#define BASE_COLOR_SIZE666 (0 << 0) 409#define BASE_COLOR_SIZE666 ( 0 << 0)
364#define BASE_COLOR_SIZE111 (1 << 0) 410#define BASE_COLOR_SIZE111 ( 1 << 0)
365#define BASE_COLOR_SIZE222 (2 << 0) 411#define BASE_COLOR_SIZE222 ( 2 << 0)
366#define BASE_COLOR_SIZE333 (3 << 0) 412#define BASE_COLOR_SIZE333 ( 3 << 0)
367#define BASE_COLOR_SIZE444 (4 << 0) 413#define BASE_COLOR_SIZE444 ( 4 << 0)
368#define BASE_COLOR_SIZE555 (5 << 0) 414#define BASE_COLOR_SIZE555 ( 5 << 0)
369#define BASE_COLOR_SIZE565 (6 << 0) 415#define BASE_COLOR_SIZE565 ( 6 << 0)
370#define BASE_COLOR_SIZE332 (7 << 0) 416#define BASE_COLOR_SIZE332 ( 7 << 0)
371#define BASE_COLOR_SIZE888 (8 << 0) 417#define BASE_COLOR_SIZE888 ( 8 << 0)
418#define BASE_COLOR_SIZE101010 (10 << 0)
419#define BASE_COLOR_SIZE121212 (12 << 0)
372#define DITHER_CONTROL_MASK (3 << 8) 420#define DITHER_CONTROL_MASK (3 << 8)
373#define DITHER_CONTROL_DISABLE (0 << 8) 421#define DITHER_CONTROL_DISABLE (0 << 8)
374#define DITHER_CONTROL_ORDERED (2 << 8) 422#define DITHER_CONTROL_ORDERED (2 << 8)
375#define DITHER_CONTROL_ERRDIFF (3 << 8) 423#define DITHER_CONTROL_ERRDIFF (3 << 8)
376#define BASE_COLOR_SIZE_MASK (0xf << 0) 424#define BASE_COLOR_SIZE_MASK (0xf << 0)
377#define BASE_COLOR_SIZE_666 (0 << 0) 425#define BASE_COLOR_SIZE_666 ( 0 << 0)
378#define BASE_COLOR_SIZE_111 (1 << 0) 426#define BASE_COLOR_SIZE_111 ( 1 << 0)
379#define BASE_COLOR_SIZE_222 (2 << 0) 427#define BASE_COLOR_SIZE_222 ( 2 << 0)
380#define BASE_COLOR_SIZE_333 (3 << 0) 428#define BASE_COLOR_SIZE_333 ( 3 << 0)
381#define BASE_COLOR_SIZE_444 (4 << 0) 429#define BASE_COLOR_SIZE_444 ( 4 << 0)
382#define BASE_COLOR_SIZE_555 (5 << 0) 430#define BASE_COLOR_SIZE_555 ( 5 << 0)
383#define BASE_COLOR_SIZE_565 (6 << 0) 431#define BASE_COLOR_SIZE_565 ( 6 << 0)
384#define BASE_COLOR_SIZE_332 (7 << 0) 432#define BASE_COLOR_SIZE_332 ( 7 << 0)
385#define BASE_COLOR_SIZE_888 (8 << 0) 433#define BASE_COLOR_SIZE_888 ( 8 << 0)
434#define BASE_COLOR_SIZE_101010 ( 10 << 0)
435#define BASE_COLOR_SIZE_121212 ( 12 << 0)
386 436
387#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 437#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
388#define SC1_H_QUALIFIER_NONE (1 << 16) 438#define SC1_H_QUALIFIER_NONE (1 << 16)
@@ -449,6 +499,12 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
449#define DC_DISP_SD_HW_K_VALUES 0x4dd 499#define DC_DISP_SD_HW_K_VALUES 0x4dd
450#define DC_DISP_SD_MAN_K_VALUES 0x4de 500#define DC_DISP_SD_MAN_K_VALUES 0x4de
451 501
502#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4
503#define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
504#define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16)
505#define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
506#define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0)
507
452#define DC_DISP_INTERLACE_CONTROL 0x4e5 508#define DC_DISP_INTERLACE_CONTROL 0x4e5
453#define INTERLACE_STATUS (1 << 2) 509#define INTERLACE_STATUS (1 << 2)
454#define INTERLACE_START (1 << 1) 510#define INTERLACE_START (1 << 1)
@@ -467,6 +523,35 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
467#define CURSOR_SRC_BLEND_MASK (3 << 8) 523#define CURSOR_SRC_BLEND_MASK (3 << 8)
468#define CURSOR_ALPHA 0xff 524#define CURSOR_ALPHA 0xff
469 525
526#define DC_WIN_CORE_ACT_CONTROL 0x50e
527#define VCOUNTER (0 << 0)
528#define HCOUNTER (1 << 0)
529
530#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543
531#define LATENCY_CTL_MODE_ENABLE (1 << 2)
532
533#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544
534#define WATERMARK_MASK 0x1fffffff
535
536#define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560
537#define PIPE_METER_INT(x) (((x) & 0xff) << 8)
538#define PIPE_METER_FRAC(x) (((x) & 0xff) << 0)
539
540#define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561
541#define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0)
542
543#define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562
544#define SLOTS(x) (((x) & 0xff) << 0)
545
546#define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563
547#define MODE_TWO_LINES (0 << 14)
548#define MODE_FOUR_LINES (1 << 14)
549
550#define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568
551#define THREAD_NUM_MASK (0x1f << 1)
552#define THREAD_NUM(x) (((x) & 0x1f) << 1)
553#define THREAD_GROUP_ENABLE (1 << 0)
554
470#define DC_WIN_CSC_YOF 0x611 555#define DC_WIN_CSC_YOF 0x611
471#define DC_WIN_CSC_KYRGB 0x612 556#define DC_WIN_CSC_KYRGB 0x612
472#define DC_WIN_CSC_KUR 0x613 557#define DC_WIN_CSC_KUR 0x613
@@ -502,9 +587,9 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
502#define WIN_COLOR_DEPTH_P4 2 587#define WIN_COLOR_DEPTH_P4 2
503#define WIN_COLOR_DEPTH_P8 3 588#define WIN_COLOR_DEPTH_P8 3
504#define WIN_COLOR_DEPTH_B4G4R4A4 4 589#define WIN_COLOR_DEPTH_B4G4R4A4 4
505#define WIN_COLOR_DEPTH_B5G5R5A 5 590#define WIN_COLOR_DEPTH_B5G5R5A1 5
506#define WIN_COLOR_DEPTH_B5G6R5 6 591#define WIN_COLOR_DEPTH_B5G6R5 6
507#define WIN_COLOR_DEPTH_AB5G5R5 7 592#define WIN_COLOR_DEPTH_A1B5G5R5 7
508#define WIN_COLOR_DEPTH_B8G8R8A8 12 593#define WIN_COLOR_DEPTH_B8G8R8A8 12
509#define WIN_COLOR_DEPTH_R8G8B8A8 13 594#define WIN_COLOR_DEPTH_R8G8B8A8 13
510#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14 595#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
@@ -519,18 +604,32 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
519#define WIN_COLOR_DEPTH_YUV422R 23 604#define WIN_COLOR_DEPTH_YUV422R 23
520#define WIN_COLOR_DEPTH_YCbCr422RA 24 605#define WIN_COLOR_DEPTH_YCbCr422RA 24
521#define WIN_COLOR_DEPTH_YUV422RA 25 606#define WIN_COLOR_DEPTH_YUV422RA 25
607#define WIN_COLOR_DEPTH_R4G4B4A4 27
608#define WIN_COLOR_DEPTH_R5G5B5A 28
609#define WIN_COLOR_DEPTH_AR5G5B5 29
610#define WIN_COLOR_DEPTH_B5G5R5X1 30
611#define WIN_COLOR_DEPTH_X1B5G5R5 31
612#define WIN_COLOR_DEPTH_R5G5B5X1 32
613#define WIN_COLOR_DEPTH_X1R5G5B5 33
614#define WIN_COLOR_DEPTH_R5G6B5 34
615#define WIN_COLOR_DEPTH_A8R8G8B8 35
616#define WIN_COLOR_DEPTH_A8B8G8R8 36
617#define WIN_COLOR_DEPTH_B8G8R8X8 37
618#define WIN_COLOR_DEPTH_R8G8B8X8 38
619#define WIN_COLOR_DEPTH_X8B8G8R8 65
620#define WIN_COLOR_DEPTH_X8R8G8B8 66
522 621
523#define DC_WIN_POSITION 0x704 622#define DC_WIN_POSITION 0x704
524#define H_POSITION(x) (((x) & 0x1fff) << 0) 623#define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
525#define V_POSITION(x) (((x) & 0x1fff) << 16) 624#define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
526 625
527#define DC_WIN_SIZE 0x705 626#define DC_WIN_SIZE 0x705
528#define H_SIZE(x) (((x) & 0x1fff) << 0) 627#define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
529#define V_SIZE(x) (((x) & 0x1fff) << 16) 628#define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
530 629
531#define DC_WIN_PRESCALED_SIZE 0x706 630#define DC_WIN_PRESCALED_SIZE 0x706
532#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) 631#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
533#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) 632#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
534 633
535#define DC_WIN_H_INITIAL_DDA 0x707 634#define DC_WIN_H_INITIAL_DDA 0x707
536#define DC_WIN_V_INITIAL_DDA 0x708 635#define DC_WIN_V_INITIAL_DDA 0x708
@@ -546,11 +645,24 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
546#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0) 645#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
547#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16) 646#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
548#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16) 647#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
648
549#define DC_WIN_DV_CONTROL 0x70e 649#define DC_WIN_DV_CONTROL 0x70e
550 650
551#define DC_WIN_BLEND_NOKEY 0x70f 651#define DC_WIN_BLEND_NOKEY 0x70f
652#define BLEND_WEIGHT1(x) (((x) & 0xff) << 16)
653#define BLEND_WEIGHT0(x) (((x) & 0xff) << 8)
654
552#define DC_WIN_BLEND_1WIN 0x710 655#define DC_WIN_BLEND_1WIN 0x710
656#define BLEND_CONTROL_FIX (0 << 2)
657#define BLEND_CONTROL_ALPHA (1 << 2)
658#define BLEND_COLOR_KEY_NONE (0 << 0)
659#define BLEND_COLOR_KEY_0 (1 << 0)
660#define BLEND_COLOR_KEY_1 (2 << 0)
661#define BLEND_COLOR_KEY_BOTH (3 << 0)
662
553#define DC_WIN_BLEND_2WIN_X 0x711 663#define DC_WIN_BLEND_2WIN_X 0x711
664#define BLEND_CONTROL_DEPENDENT (2 << 2)
665
554#define DC_WIN_BLEND_2WIN_Y 0x712 666#define DC_WIN_BLEND_2WIN_Y 0x712
555#define DC_WIN_BLEND_3WIN_XY 0x713 667#define DC_WIN_BLEND_3WIN_XY 0x713
556 668
@@ -575,8 +687,97 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
575#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) 687#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
576#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) 688#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
577 689
690#define DC_WINBUF_START_ADDR_HI 0x80d
691
692#define DC_WINBUF_CDE_CONTROL 0x82f
693#define ENABLE_SURFACE (1 << 0)
694
578#define DC_WINBUF_AD_UFLOW_STATUS 0xbca 695#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
579#define DC_WINBUF_BD_UFLOW_STATUS 0xdca 696#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
580#define DC_WINBUF_CD_UFLOW_STATUS 0xfca 697#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
581 698
699/* Tegra186 and later */
700#define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x))
701#define PROTOCOL_MASK (0xf << 8)
702#define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
703
704#define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
705#define OWNER_MASK (0xf << 0)
706#define OWNER(x) (((x) & 0xf) << 0)
707
708#define DC_WIN_CROPPED_SIZE 0x706
709
710#define DC_WIN_PLANAR_STORAGE 0x709
711#define PITCH(x) (((x) >> 6) & 0x1fff)
712
713#define DC_WIN_SET_PARAMS 0x70d
714#define CLAMP_BEFORE_BLEND (1 << 15)
715#define DEGAMMA_NONE (0 << 13)
716#define DEGAMMA_SRGB (1 << 13)
717#define DEGAMMA_YUV8_10 (2 << 13)
718#define DEGAMMA_YUV12 (3 << 13)
719#define INPUT_RANGE_BYPASS (0 << 10)
720#define INPUT_RANGE_LIMITED (1 << 10)
721#define INPUT_RANGE_FULL (2 << 10)
722#define COLOR_SPACE_RGB (0 << 8)
723#define COLOR_SPACE_YUV_601 (1 << 8)
724#define COLOR_SPACE_YUV_709 (2 << 8)
725#define COLOR_SPACE_YUV_2020 (3 << 8)
726
727#define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e
728#define HORIZONTAL_TAPS_2 (1 << 3)
729#define HORIZONTAL_TAPS_5 (4 << 3)
730#define VERTICAL_TAPS_2 (1 << 0)
731#define VERTICAL_TAPS_5 (4 << 0)
732
733#define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711
734#define INPUT_SCALER_USE422 (1 << 2)
735#define INPUT_SCALER_VBYPASS (1 << 1)
736#define INPUT_SCALER_HBYPASS (1 << 0)
737
738#define DC_WIN_BLEND_LAYER_CONTROL 0x716
739#define COLOR_KEY_NONE (0 << 25)
740#define COLOR_KEY_SRC (1 << 25)
741#define COLOR_KEY_DST (2 << 25)
742#define BLEND_BYPASS (1 << 24)
743#define K2(x) (((x) & 0xff) << 16)
744#define K1(x) (((x) & 0xff) << 8)
745#define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0)
746
747#define DC_WIN_BLEND_MATCH_SELECT 0x717
748#define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12)
749#define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12)
750#define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12)
751#define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12)
752#define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8)
753#define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8)
754#define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8)
755#define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8)
756#define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4)
757#define BLEND_FACTOR_DST_COLOR_ONE (1 << 4)
758#define BLEND_FACTOR_DST_COLOR_K1 (2 << 4)
759#define BLEND_FACTOR_DST_COLOR_K2 (3 << 4)
760#define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4)
761#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4)
762#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4)
763#define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4)
764#define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0)
765#define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0)
766#define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0)
767#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0)
768#define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0)
769#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0)
770
771#define DC_WIN_BLEND_NOMATCH_SELECT 0x718
772
773#define DC_WIN_PRECOMP_WGRP_PARAMS 0x724
774#define SWAP_UV (1 << 0)
775
776#define DC_WIN_WINDOW_SET_CONTROL 0x730
777#define CONTROL_CSC_ENABLE (1 << 5)
778
779#define DC_WINBUF_CROPPED_POINT 0x806
780#define OFFSET_Y(x) (((x) & 0xffff) << 16)
781#define OFFSET_X(x) (((x) & 0xffff) << 0)
782
582#endif /* TEGRA_DC_H */ 783#endif /* TEGRA_DC_H */
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index e4da041ba89b..d84e81ff36ad 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -15,6 +15,7 @@
15#include <linux/pinctrl/pinconf-generic.h> 15#include <linux/pinctrl/pinconf-generic.h>
16#include <linux/pinctrl/pinctrl.h> 16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h> 17#include <linux/pinctrl/pinmux.h>
18#include <linux/pm_runtime.h>
18#include <linux/platform_device.h> 19#include <linux/platform_device.h>
19#include <linux/reset.h> 20#include <linux/reset.h>
20#include <linux/regulator/consumer.h> 21#include <linux/regulator/consumer.h>
@@ -321,6 +322,9 @@ static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
321 case DPAUX_PADCTL_FUNC_I2C: 322 case DPAUX_PADCTL_FUNC_I2C:
322 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV | 323 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
323 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV | 324 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
325 DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
326 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
327 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
324 DPAUX_HYBRID_PADCTL_MODE_I2C; 328 DPAUX_HYBRID_PADCTL_MODE_I2C;
325 break; 329 break;
326 330
@@ -467,52 +471,37 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
467 return PTR_ERR(dpaux->clk); 471 return PTR_ERR(dpaux->clk);
468 } 472 }
469 473
470 err = clk_prepare_enable(dpaux->clk);
471 if (err < 0) {
472 dev_err(&pdev->dev, "failed to enable module clock: %d\n",
473 err);
474 return err;
475 }
476
477 if (dpaux->rst)
478 reset_control_deassert(dpaux->rst);
479
480 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); 474 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
481 if (IS_ERR(dpaux->clk_parent)) { 475 if (IS_ERR(dpaux->clk_parent)) {
482 dev_err(&pdev->dev, "failed to get parent clock: %ld\n", 476 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
483 PTR_ERR(dpaux->clk_parent)); 477 PTR_ERR(dpaux->clk_parent));
484 err = PTR_ERR(dpaux->clk_parent); 478 return PTR_ERR(dpaux->clk_parent);
485 goto assert_reset;
486 }
487
488 err = clk_prepare_enable(dpaux->clk_parent);
489 if (err < 0) {
490 dev_err(&pdev->dev, "failed to enable parent clock: %d\n",
491 err);
492 goto assert_reset;
493 } 479 }
494 480
495 err = clk_set_rate(dpaux->clk_parent, 270000000); 481 err = clk_set_rate(dpaux->clk_parent, 270000000);
496 if (err < 0) { 482 if (err < 0) {
497 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n", 483 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
498 err); 484 err);
499 goto disable_parent_clk; 485 return err;
500 } 486 }
501 487
502 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd"); 488 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
503 if (IS_ERR(dpaux->vdd)) { 489 if (IS_ERR(dpaux->vdd)) {
504 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n", 490 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
505 PTR_ERR(dpaux->vdd)); 491 PTR_ERR(dpaux->vdd));
506 err = PTR_ERR(dpaux->vdd); 492 return PTR_ERR(dpaux->vdd);
507 goto disable_parent_clk;
508 } 493 }
509 494
495 platform_set_drvdata(pdev, dpaux);
496 pm_runtime_enable(&pdev->dev);
497 pm_runtime_get_sync(&pdev->dev);
498
510 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, 499 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
511 dev_name(dpaux->dev), dpaux); 500 dev_name(dpaux->dev), dpaux);
512 if (err < 0) { 501 if (err < 0) {
513 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", 502 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
514 dpaux->irq, err); 503 dpaux->irq, err);
515 goto disable_parent_clk; 504 return err;
516 } 505 }
517 506
518 disable_irq(dpaux->irq); 507 disable_irq(dpaux->irq);
@@ -522,7 +511,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
522 511
523 err = drm_dp_aux_register(&dpaux->aux); 512 err = drm_dp_aux_register(&dpaux->aux);
524 if (err < 0) 513 if (err < 0)
525 goto disable_parent_clk; 514 return err;
526 515
527 /* 516 /*
528 * Assume that by default the DPAUX/I2C pads will be used for HDMI, 517 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
@@ -560,47 +549,97 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
560 list_add_tail(&dpaux->list, &dpaux_list); 549 list_add_tail(&dpaux->list, &dpaux_list);
561 mutex_unlock(&dpaux_lock); 550 mutex_unlock(&dpaux_lock);
562 551
563 platform_set_drvdata(pdev, dpaux);
564
565 return 0; 552 return 0;
566
567disable_parent_clk:
568 clk_disable_unprepare(dpaux->clk_parent);
569assert_reset:
570 if (dpaux->rst)
571 reset_control_assert(dpaux->rst);
572
573 clk_disable_unprepare(dpaux->clk);
574
575 return err;
576} 553}
577 554
578static int tegra_dpaux_remove(struct platform_device *pdev) 555static int tegra_dpaux_remove(struct platform_device *pdev)
579{ 556{
580 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev); 557 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
581 558
559 cancel_work_sync(&dpaux->work);
560
582 /* make sure pads are powered down when not in use */ 561 /* make sure pads are powered down when not in use */
583 tegra_dpaux_pad_power_down(dpaux); 562 tegra_dpaux_pad_power_down(dpaux);
584 563
564 pm_runtime_put(&pdev->dev);
565 pm_runtime_disable(&pdev->dev);
566
585 drm_dp_aux_unregister(&dpaux->aux); 567 drm_dp_aux_unregister(&dpaux->aux);
586 568
587 mutex_lock(&dpaux_lock); 569 mutex_lock(&dpaux_lock);
588 list_del(&dpaux->list); 570 list_del(&dpaux->list);
589 mutex_unlock(&dpaux_lock); 571 mutex_unlock(&dpaux_lock);
590 572
591 cancel_work_sync(&dpaux->work); 573 return 0;
574}
592 575
593 clk_disable_unprepare(dpaux->clk_parent); 576#ifdef CONFIG_PM
577static int tegra_dpaux_suspend(struct device *dev)
578{
579 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
580 int err = 0;
581
582 if (dpaux->rst) {
583 err = reset_control_assert(dpaux->rst);
584 if (err < 0) {
585 dev_err(dev, "failed to assert reset: %d\n", err);
586 return err;
587 }
588 }
594 589
595 if (dpaux->rst) 590 usleep_range(1000, 2000);
596 reset_control_assert(dpaux->rst);
597 591
592 clk_disable_unprepare(dpaux->clk_parent);
598 clk_disable_unprepare(dpaux->clk); 593 clk_disable_unprepare(dpaux->clk);
599 594
595 return err;
596}
597
598static int tegra_dpaux_resume(struct device *dev)
599{
600 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
601 int err;
602
603 err = clk_prepare_enable(dpaux->clk);
604 if (err < 0) {
605 dev_err(dev, "failed to enable clock: %d\n", err);
606 return err;
607 }
608
609 err = clk_prepare_enable(dpaux->clk_parent);
610 if (err < 0) {
611 dev_err(dev, "failed to enable parent clock: %d\n", err);
612 goto disable_clk;
613 }
614
615 usleep_range(1000, 2000);
616
617 if (dpaux->rst) {
618 err = reset_control_deassert(dpaux->rst);
619 if (err < 0) {
620 dev_err(dev, "failed to deassert reset: %d\n", err);
621 goto disable_parent;
622 }
623
624 usleep_range(1000, 2000);
625 }
626
600 return 0; 627 return 0;
628
629disable_parent:
630 clk_disable_unprepare(dpaux->clk_parent);
631disable_clk:
632 clk_disable_unprepare(dpaux->clk);
633 return err;
601} 634}
635#endif
636
637static const struct dev_pm_ops tegra_dpaux_pm_ops = {
638 SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
639};
602 640
603static const struct of_device_id tegra_dpaux_of_match[] = { 641static const struct of_device_id tegra_dpaux_of_match[] = {
642 { .compatible = "nvidia,tegra186-dpaux", },
604 { .compatible = "nvidia,tegra210-dpaux", }, 643 { .compatible = "nvidia,tegra210-dpaux", },
605 { .compatible = "nvidia,tegra124-dpaux", }, 644 { .compatible = "nvidia,tegra124-dpaux", },
606 { }, 645 { },
@@ -611,6 +650,7 @@ struct platform_driver tegra_dpaux_driver = {
611 .driver = { 650 .driver = {
612 .name = "tegra-dpaux", 651 .name = "tegra-dpaux",
613 .of_match_table = tegra_dpaux_of_match, 652 .of_match_table = tegra_dpaux_of_match,
653 .pm = &tegra_dpaux_pm_ops,
614 }, 654 },
615 .probe = tegra_dpaux_probe, 655 .probe = tegra_dpaux_probe,
616 .remove = tegra_dpaux_remove, 656 .remove = tegra_dpaux_remove,
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index f157bc675269..d50bddb2e447 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -33,97 +33,91 @@ struct tegra_drm_file {
33 struct mutex lock; 33 struct mutex lock;
34}; 34};
35 35
36static void tegra_atomic_schedule(struct tegra_drm *tegra, 36static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state) 37 struct drm_atomic_state *state)
38{ 38{
39 tegra->commit.state = state; 39 int err;
40 schedule_work(&tegra->commit.work);
41}
42 40
43static void tegra_atomic_complete(struct tegra_drm *tegra, 41 err = drm_atomic_helper_check_modeset(drm, state);
44 struct drm_atomic_state *state) 42 if (err < 0)
45{ 43 return err;
46 struct drm_device *drm = tegra->drm;
47 44
48 /* 45 err = drm_atomic_normalize_zpos(drm, state);
49 * Everything below can be run asynchronously without the need to grab 46 if (err < 0)
50 * any modeset locks at all under one condition: It must be guaranteed 47 return err;
51 * that the asynchronous work has either been cancelled (if the driver
52 * supports it, which at least requires that the framebuffers get
53 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
54 * before the new state gets committed on the software side with
55 * drm_atomic_helper_swap_state().
56 *
57 * This scheme allows new atomic state updates to be prepared and
58 * checked in parallel to the asynchronous completion of the previous
59 * update. Which is important since compositors need to figure out the
60 * composition of the next frame right after having submitted the
61 * current layout.
62 */
63 48
64 drm_atomic_helper_commit_modeset_disables(drm, state); 49 err = drm_atomic_helper_check_planes(drm, state);
65 drm_atomic_helper_commit_modeset_enables(drm, state); 50 if (err < 0)
66 drm_atomic_helper_commit_planes(drm, state, 51 return err;
67 DRM_PLANE_COMMIT_ACTIVE_ONLY);
68 52
69 drm_atomic_helper_wait_for_vblanks(drm, state); 53 if (state->legacy_cursor_update)
54 state->async_update = !drm_atomic_helper_async_check(drm, state);
70 55
71 drm_atomic_helper_cleanup_planes(drm, state); 56 return 0;
72 drm_atomic_state_put(state);
73} 57}
74 58
75static void tegra_atomic_work(struct work_struct *work) 59static struct drm_atomic_state *
60tegra_atomic_state_alloc(struct drm_device *drm)
76{ 61{
77 struct tegra_drm *tegra = container_of(work, struct tegra_drm, 62 struct tegra_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
78 commit.work); 63
64 if (!state || drm_atomic_state_init(drm, &state->base) < 0) {
65 kfree(state);
66 return NULL;
67 }
79 68
80 tegra_atomic_complete(tegra, tegra->commit.state); 69 return &state->base;
81} 70}
82 71
83static int tegra_atomic_commit(struct drm_device *drm, 72static void tegra_atomic_state_clear(struct drm_atomic_state *state)
84 struct drm_atomic_state *state, bool nonblock)
85{ 73{
86 struct tegra_drm *tegra = drm->dev_private; 74 struct tegra_atomic_state *tegra = to_tegra_atomic_state(state);
87 int err;
88
89 err = drm_atomic_helper_prepare_planes(drm, state);
90 if (err)
91 return err;
92
93 /* serialize outstanding nonblocking commits */
94 mutex_lock(&tegra->commit.lock);
95 flush_work(&tegra->commit.work);
96
97 /*
98 * This is the point of no return - everything below never fails except
99 * when the hw goes bonghits. Which means we can commit the new state on
100 * the software side now.
101 */
102
103 err = drm_atomic_helper_swap_state(state, true);
104 if (err) {
105 mutex_unlock(&tegra->commit.lock);
106 drm_atomic_helper_cleanup_planes(drm, state);
107 return err;
108 }
109 75
110 drm_atomic_state_get(state); 76 drm_atomic_state_default_clear(state);
111 if (nonblock) 77 tegra->clk_disp = NULL;
112 tegra_atomic_schedule(tegra, state); 78 tegra->dc = NULL;
113 else 79 tegra->rate = 0;
114 tegra_atomic_complete(tegra, state); 80}
115 81
116 mutex_unlock(&tegra->commit.lock); 82static void tegra_atomic_state_free(struct drm_atomic_state *state)
117 return 0; 83{
84 drm_atomic_state_default_release(state);
85 kfree(state);
118} 86}
119 87
120static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { 88static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
121 .fb_create = tegra_fb_create, 89 .fb_create = tegra_fb_create,
122#ifdef CONFIG_DRM_FBDEV_EMULATION 90#ifdef CONFIG_DRM_FBDEV_EMULATION
123 .output_poll_changed = drm_fb_helper_output_poll_changed, 91 .output_poll_changed = drm_fb_helper_output_poll_changed,
124#endif 92#endif
125 .atomic_check = drm_atomic_helper_check, 93 .atomic_check = tegra_atomic_check,
126 .atomic_commit = tegra_atomic_commit, 94 .atomic_commit = drm_atomic_helper_commit,
95 .atomic_state_alloc = tegra_atomic_state_alloc,
96 .atomic_state_clear = tegra_atomic_state_clear,
97 .atomic_state_free = tegra_atomic_state_free,
98};
99
100static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
101{
102 struct drm_device *drm = old_state->dev;
103 struct tegra_drm *tegra = drm->dev_private;
104
105 if (tegra->hub) {
106 drm_atomic_helper_commit_modeset_disables(drm, old_state);
107 tegra_display_hub_atomic_commit(drm, old_state);
108 drm_atomic_helper_commit_planes(drm, old_state, 0);
109 drm_atomic_helper_commit_modeset_enables(drm, old_state);
110 drm_atomic_helper_commit_hw_done(old_state);
111 drm_atomic_helper_wait_for_vblanks(drm, old_state);
112 drm_atomic_helper_cleanup_planes(drm, old_state);
113 } else {
114 drm_atomic_helper_commit_tail_rpm(old_state);
115 }
116}
117
118static const struct drm_mode_config_helper_funcs
119tegra_drm_mode_config_helpers = {
120 .atomic_commit_tail = tegra_atomic_commit_tail,
127}; 121};
128 122
129static int tegra_drm_load(struct drm_device *drm, unsigned long flags) 123static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
@@ -172,9 +166,6 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
172 mutex_init(&tegra->clients_lock); 166 mutex_init(&tegra->clients_lock);
173 INIT_LIST_HEAD(&tegra->clients); 167 INIT_LIST_HEAD(&tegra->clients);
174 168
175 mutex_init(&tegra->commit.lock);
176 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
177
178 drm->dev_private = tegra; 169 drm->dev_private = tegra;
179 tegra->drm = drm; 170 tegra->drm = drm;
180 171
@@ -188,7 +179,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
188 179
189 drm->mode_config.allow_fb_modifiers = true; 180 drm->mode_config.allow_fb_modifiers = true;
190 181
191 drm->mode_config.funcs = &tegra_drm_mode_funcs; 182 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
183 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
192 184
193 err = tegra_drm_fb_prepare(drm); 185 err = tegra_drm_fb_prepare(drm);
194 if (err < 0) 186 if (err < 0)
@@ -200,6 +192,12 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
200 if (err < 0) 192 if (err < 0)
201 goto fbdev; 193 goto fbdev;
202 194
195 if (tegra->hub) {
196 err = tegra_display_hub_prepare(tegra->hub);
197 if (err < 0)
198 goto device;
199 }
200
203 /* 201 /*
204 * We don't use the drm_irq_install() helpers provided by the DRM 202 * We don't use the drm_irq_install() helpers provided by the DRM
205 * core, so we need to set this manually in order to allow the 203 * core, so we need to set this manually in order to allow the
@@ -212,16 +210,19 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
212 210
213 err = drm_vblank_init(drm, drm->mode_config.num_crtc); 211 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
214 if (err < 0) 212 if (err < 0)
215 goto device; 213 goto hub;
216 214
217 drm_mode_config_reset(drm); 215 drm_mode_config_reset(drm);
218 216
219 err = tegra_drm_fb_init(drm); 217 err = tegra_drm_fb_init(drm);
220 if (err < 0) 218 if (err < 0)
221 goto device; 219 goto hub;
222 220
223 return 0; 221 return 0;
224 222
223hub:
224 if (tegra->hub)
225 tegra_display_hub_cleanup(tegra->hub);
225device: 226device:
226 host1x_device_exit(device); 227 host1x_device_exit(device);
227fbdev: 228fbdev:
@@ -651,7 +652,8 @@ static int tegra_syncpt_wait(struct drm_device *drm, void *data,
651 if (!sp) 652 if (!sp)
652 return -EINVAL; 653 return -EINVAL;
653 654
654 return host1x_syncpt_wait(sp, args->thresh, args->timeout, 655 return host1x_syncpt_wait(sp, args->thresh,
656 msecs_to_jiffies(args->timeout),
655 &args->value); 657 &args->value);
656} 658}
657 659
@@ -1139,8 +1141,7 @@ int tegra_drm_unregister_client(struct tegra_drm *tegra,
1139 return 0; 1141 return 0;
1140} 1142}
1141 1143
1142void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, 1144void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
1143 dma_addr_t *dma)
1144{ 1145{
1145 struct iova *alloc; 1146 struct iova *alloc;
1146 void *virt; 1147 void *virt;
@@ -1308,6 +1309,10 @@ static const struct of_device_id host1x_drm_subdevs[] = {
1308 { .compatible = "nvidia,tegra210-sor", }, 1309 { .compatible = "nvidia,tegra210-sor", },
1309 { .compatible = "nvidia,tegra210-sor1", }, 1310 { .compatible = "nvidia,tegra210-sor1", },
1310 { .compatible = "nvidia,tegra210-vic", }, 1311 { .compatible = "nvidia,tegra210-vic", },
1312 { .compatible = "nvidia,tegra186-display", },
1313 { .compatible = "nvidia,tegra186-dc", },
1314 { .compatible = "nvidia,tegra186-sor", },
1315 { .compatible = "nvidia,tegra186-sor1", },
1311 { .compatible = "nvidia,tegra186-vic", }, 1316 { .compatible = "nvidia,tegra186-vic", },
1312 { /* sentinel */ } 1317 { /* sentinel */ }
1313}; 1318};
@@ -1323,6 +1328,7 @@ static struct host1x_driver host1x_drm_driver = {
1323}; 1328};
1324 1329
1325static struct platform_driver * const drivers[] = { 1330static struct platform_driver * const drivers[] = {
1331 &tegra_display_hub_driver,
1326 &tegra_dc_driver, 1332 &tegra_dc_driver,
1327 &tegra_hdmi_driver, 1333 &tegra_hdmi_driver,
1328 &tegra_dsi_driver, 1334 &tegra_dsi_driver,
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 0009f6ea21b6..73b661ce7086 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -16,6 +16,7 @@
16#include <linux/of_gpio.h> 16#include <linux/of_gpio.h>
17 17
18#include <drm/drmP.h> 18#include <drm/drmP.h>
19#include <drm/drm_atomic.h>
19#include <drm/drm_crtc_helper.h> 20#include <drm/drm_crtc_helper.h>
20#include <drm/drm_edid.h> 21#include <drm/drm_edid.h>
21#include <drm/drm_encoder.h> 22#include <drm/drm_encoder.h>
@@ -23,6 +24,7 @@
23#include <drm/drm_fixed.h> 24#include <drm/drm_fixed.h>
24 25
25#include "gem.h" 26#include "gem.h"
27#include "hub.h"
26#include "trace.h" 28#include "trace.h"
27 29
28struct reset_control; 30struct reset_control;
@@ -40,10 +42,25 @@ struct tegra_fbdev {
40}; 42};
41#endif 43#endif
42 44
45struct tegra_atomic_state {
46 struct drm_atomic_state base;
47
48 struct clk *clk_disp;
49 struct tegra_dc *dc;
50 unsigned long rate;
51};
52
53static inline struct tegra_atomic_state *
54to_tegra_atomic_state(struct drm_atomic_state *state)
55{
56 return container_of(state, struct tegra_atomic_state, base);
57}
58
43struct tegra_drm { 59struct tegra_drm {
44 struct drm_device *drm; 60 struct drm_device *drm;
45 61
46 struct iommu_domain *domain; 62 struct iommu_domain *domain;
63 struct iommu_group *group;
47 struct mutex mm_lock; 64 struct mutex mm_lock;
48 struct drm_mm mm; 65 struct drm_mm mm;
49 66
@@ -62,11 +79,7 @@ struct tegra_drm {
62 79
63 unsigned int pitch_align; 80 unsigned int pitch_align;
64 81
65 struct { 82 struct tegra_display_hub *hub;
66 struct drm_atomic_state *state;
67 struct work_struct work;
68 struct mutex lock;
69 } commit;
70 83
71 struct drm_atomic_state *state; 84 struct drm_atomic_state *state;
72}; 85};
@@ -152,6 +165,8 @@ int tegra_output_probe(struct tegra_output *output);
152void tegra_output_remove(struct tegra_output *output); 165void tegra_output_remove(struct tegra_output *output);
153int tegra_output_init(struct drm_device *drm, struct tegra_output *output); 166int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
154void tegra_output_exit(struct tegra_output *output); 167void tegra_output_exit(struct tegra_output *output);
168void tegra_output_find_possible_crtcs(struct tegra_output *output,
169 struct drm_device *drm);
155 170
156int tegra_output_connector_get_modes(struct drm_connector *connector); 171int tegra_output_connector_get_modes(struct drm_connector *connector);
157enum drm_connector_status 172enum drm_connector_status
@@ -189,6 +204,7 @@ void tegra_drm_fb_exit(struct drm_device *drm);
189void tegra_drm_fb_suspend(struct drm_device *drm); 204void tegra_drm_fb_suspend(struct drm_device *drm);
190void tegra_drm_fb_resume(struct drm_device *drm); 205void tegra_drm_fb_resume(struct drm_device *drm);
191 206
207extern struct platform_driver tegra_display_hub_driver;
192extern struct platform_driver tegra_dc_driver; 208extern struct platform_driver tegra_dc_driver;
193extern struct platform_driver tegra_hdmi_driver; 209extern struct platform_driver tegra_hdmi_driver;
194extern struct platform_driver tegra_dsi_driver; 210extern struct platform_driver tegra_dsi_driver;
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 046649ec9441..4d2ed966f9e3 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -65,8 +65,6 @@ struct tegra_dsi {
65 struct clk *clk; 65 struct clk *clk;
66 66
67 struct drm_info_list *debugfs_files; 67 struct drm_info_list *debugfs_files;
68 struct drm_minor *minor;
69 struct dentry *debugfs;
70 68
71 unsigned long flags; 69 unsigned long flags;
72 enum mipi_dsi_pixel_format format; 70 enum mipi_dsi_pixel_format format;
@@ -122,12 +120,89 @@ static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
122 writel(value, dsi->regs + (offset << 2)); 120 writel(value, dsi->regs + (offset << 2));
123} 121}
124 122
123#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
124
125static const struct debugfs_reg32 tegra_dsi_regs[] = {
126 DEBUGFS_REG32(DSI_INCR_SYNCPT),
127 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
128 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
129 DEBUGFS_REG32(DSI_CTXSW),
130 DEBUGFS_REG32(DSI_RD_DATA),
131 DEBUGFS_REG32(DSI_WR_DATA),
132 DEBUGFS_REG32(DSI_POWER_CONTROL),
133 DEBUGFS_REG32(DSI_INT_ENABLE),
134 DEBUGFS_REG32(DSI_INT_STATUS),
135 DEBUGFS_REG32(DSI_INT_MASK),
136 DEBUGFS_REG32(DSI_HOST_CONTROL),
137 DEBUGFS_REG32(DSI_CONTROL),
138 DEBUGFS_REG32(DSI_SOL_DELAY),
139 DEBUGFS_REG32(DSI_MAX_THRESHOLD),
140 DEBUGFS_REG32(DSI_TRIGGER),
141 DEBUGFS_REG32(DSI_TX_CRC),
142 DEBUGFS_REG32(DSI_STATUS),
143 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
144 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
151 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
152 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
153 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
154 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
155 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
156 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
157 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
158 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
159 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
160 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
161 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
162 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
163 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
164 DEBUGFS_REG32(DSI_DCS_CMDS),
165 DEBUGFS_REG32(DSI_PKT_LEN_0_1),
166 DEBUGFS_REG32(DSI_PKT_LEN_2_3),
167 DEBUGFS_REG32(DSI_PKT_LEN_4_5),
168 DEBUGFS_REG32(DSI_PKT_LEN_6_7),
169 DEBUGFS_REG32(DSI_PHY_TIMING_0),
170 DEBUGFS_REG32(DSI_PHY_TIMING_1),
171 DEBUGFS_REG32(DSI_PHY_TIMING_2),
172 DEBUGFS_REG32(DSI_BTA_TIMING),
173 DEBUGFS_REG32(DSI_TIMEOUT_0),
174 DEBUGFS_REG32(DSI_TIMEOUT_1),
175 DEBUGFS_REG32(DSI_TO_TALLY),
176 DEBUGFS_REG32(DSI_PAD_CONTROL_0),
177 DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
178 DEBUGFS_REG32(DSI_PAD_CD_STATUS),
179 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
180 DEBUGFS_REG32(DSI_PAD_CONTROL_1),
181 DEBUGFS_REG32(DSI_PAD_CONTROL_2),
182 DEBUGFS_REG32(DSI_PAD_CONTROL_3),
183 DEBUGFS_REG32(DSI_PAD_CONTROL_4),
184 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
185 DEBUGFS_REG32(DSI_GANGED_MODE_START),
186 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
187 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
188 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
189 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
196 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
197};
198
125static int tegra_dsi_show_regs(struct seq_file *s, void *data) 199static int tegra_dsi_show_regs(struct seq_file *s, void *data)
126{ 200{
127 struct drm_info_node *node = s->private; 201 struct drm_info_node *node = s->private;
128 struct tegra_dsi *dsi = node->info_ent->data; 202 struct tegra_dsi *dsi = node->info_ent->data;
129 struct drm_crtc *crtc = dsi->output.encoder.crtc; 203 struct drm_crtc *crtc = dsi->output.encoder.crtc;
130 struct drm_device *drm = node->minor->dev; 204 struct drm_device *drm = node->minor->dev;
205 unsigned int i;
131 int err = 0; 206 int err = 0;
132 207
133 drm_modeset_lock_all(drm); 208 drm_modeset_lock_all(drm);
@@ -137,93 +212,12 @@ static int tegra_dsi_show_regs(struct seq_file *s, void *data)
137 goto unlock; 212 goto unlock;
138 } 213 }
139 214
140#define DUMP_REG(name) \ 215 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
141 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \ 216 unsigned int offset = tegra_dsi_regs[i].offset;
142 tegra_dsi_readl(dsi, name)) 217
143 218 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
144 DUMP_REG(DSI_INCR_SYNCPT); 219 offset, tegra_dsi_readl(dsi, offset));
145 DUMP_REG(DSI_INCR_SYNCPT_CONTROL); 220 }
146 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
147 DUMP_REG(DSI_CTXSW);
148 DUMP_REG(DSI_RD_DATA);
149 DUMP_REG(DSI_WR_DATA);
150 DUMP_REG(DSI_POWER_CONTROL);
151 DUMP_REG(DSI_INT_ENABLE);
152 DUMP_REG(DSI_INT_STATUS);
153 DUMP_REG(DSI_INT_MASK);
154 DUMP_REG(DSI_HOST_CONTROL);
155 DUMP_REG(DSI_CONTROL);
156 DUMP_REG(DSI_SOL_DELAY);
157 DUMP_REG(DSI_MAX_THRESHOLD);
158 DUMP_REG(DSI_TRIGGER);
159 DUMP_REG(DSI_TX_CRC);
160 DUMP_REG(DSI_STATUS);
161
162 DUMP_REG(DSI_INIT_SEQ_CONTROL);
163 DUMP_REG(DSI_INIT_SEQ_DATA_0);
164 DUMP_REG(DSI_INIT_SEQ_DATA_1);
165 DUMP_REG(DSI_INIT_SEQ_DATA_2);
166 DUMP_REG(DSI_INIT_SEQ_DATA_3);
167 DUMP_REG(DSI_INIT_SEQ_DATA_4);
168 DUMP_REG(DSI_INIT_SEQ_DATA_5);
169 DUMP_REG(DSI_INIT_SEQ_DATA_6);
170 DUMP_REG(DSI_INIT_SEQ_DATA_7);
171
172 DUMP_REG(DSI_PKT_SEQ_0_LO);
173 DUMP_REG(DSI_PKT_SEQ_0_HI);
174 DUMP_REG(DSI_PKT_SEQ_1_LO);
175 DUMP_REG(DSI_PKT_SEQ_1_HI);
176 DUMP_REG(DSI_PKT_SEQ_2_LO);
177 DUMP_REG(DSI_PKT_SEQ_2_HI);
178 DUMP_REG(DSI_PKT_SEQ_3_LO);
179 DUMP_REG(DSI_PKT_SEQ_3_HI);
180 DUMP_REG(DSI_PKT_SEQ_4_LO);
181 DUMP_REG(DSI_PKT_SEQ_4_HI);
182 DUMP_REG(DSI_PKT_SEQ_5_LO);
183 DUMP_REG(DSI_PKT_SEQ_5_HI);
184
185 DUMP_REG(DSI_DCS_CMDS);
186
187 DUMP_REG(DSI_PKT_LEN_0_1);
188 DUMP_REG(DSI_PKT_LEN_2_3);
189 DUMP_REG(DSI_PKT_LEN_4_5);
190 DUMP_REG(DSI_PKT_LEN_6_7);
191
192 DUMP_REG(DSI_PHY_TIMING_0);
193 DUMP_REG(DSI_PHY_TIMING_1);
194 DUMP_REG(DSI_PHY_TIMING_2);
195 DUMP_REG(DSI_BTA_TIMING);
196
197 DUMP_REG(DSI_TIMEOUT_0);
198 DUMP_REG(DSI_TIMEOUT_1);
199 DUMP_REG(DSI_TO_TALLY);
200
201 DUMP_REG(DSI_PAD_CONTROL_0);
202 DUMP_REG(DSI_PAD_CONTROL_CD);
203 DUMP_REG(DSI_PAD_CD_STATUS);
204 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
205 DUMP_REG(DSI_PAD_CONTROL_1);
206 DUMP_REG(DSI_PAD_CONTROL_2);
207 DUMP_REG(DSI_PAD_CONTROL_3);
208 DUMP_REG(DSI_PAD_CONTROL_4);
209
210 DUMP_REG(DSI_GANGED_MODE_CONTROL);
211 DUMP_REG(DSI_GANGED_MODE_START);
212 DUMP_REG(DSI_GANGED_MODE_SIZE);
213
214 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
215 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
216
217 DUMP_REG(DSI_INIT_SEQ_DATA_8);
218 DUMP_REG(DSI_INIT_SEQ_DATA_9);
219 DUMP_REG(DSI_INIT_SEQ_DATA_10);
220 DUMP_REG(DSI_INIT_SEQ_DATA_11);
221 DUMP_REG(DSI_INIT_SEQ_DATA_12);
222 DUMP_REG(DSI_INIT_SEQ_DATA_13);
223 DUMP_REG(DSI_INIT_SEQ_DATA_14);
224 DUMP_REG(DSI_INIT_SEQ_DATA_15);
225
226#undef DUMP_REG
227 221
228unlock: 222unlock:
229 drm_modeset_unlock_all(drm); 223 drm_modeset_unlock_all(drm);
@@ -234,58 +228,46 @@ static struct drm_info_list debugfs_files[] = {
234 { "regs", tegra_dsi_show_regs, 0, NULL }, 228 { "regs", tegra_dsi_show_regs, 0, NULL },
235}; 229};
236 230
237static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi, 231static int tegra_dsi_late_register(struct drm_connector *connector)
238 struct drm_minor *minor)
239{ 232{
240 const char *name = dev_name(dsi->dev); 233 struct tegra_output *output = connector_to_output(connector);
241 unsigned int i; 234 unsigned int i, count = ARRAY_SIZE(debugfs_files);
235 struct drm_minor *minor = connector->dev->primary;
236 struct dentry *root = connector->debugfs_entry;
237 struct tegra_dsi *dsi = to_dsi(output);
242 int err; 238 int err;
243 239
244 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
245 if (!dsi->debugfs)
246 return -ENOMEM;
247
248 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 240 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
249 GFP_KERNEL); 241 GFP_KERNEL);
250 if (!dsi->debugfs_files) { 242 if (!dsi->debugfs_files)
251 err = -ENOMEM; 243 return -ENOMEM;
252 goto remove;
253 }
254 244
255 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 245 for (i = 0; i < count; i++)
256 dsi->debugfs_files[i].data = dsi; 246 dsi->debugfs_files[i].data = dsi;
257 247
258 err = drm_debugfs_create_files(dsi->debugfs_files, 248 err = drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
259 ARRAY_SIZE(debugfs_files),
260 dsi->debugfs, minor);
261 if (err < 0) 249 if (err < 0)
262 goto free; 250 goto free;
263 251
264 dsi->minor = minor;
265
266 return 0; 252 return 0;
267 253
268free: 254free:
269 kfree(dsi->debugfs_files); 255 kfree(dsi->debugfs_files);
270 dsi->debugfs_files = NULL; 256 dsi->debugfs_files = NULL;
271remove:
272 debugfs_remove(dsi->debugfs);
273 dsi->debugfs = NULL;
274 257
275 return err; 258 return err;
276} 259}
277 260
278static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi) 261static void tegra_dsi_early_unregister(struct drm_connector *connector)
279{ 262{
280 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files), 263 struct tegra_output *output = connector_to_output(connector);
281 dsi->minor); 264 unsigned int count = ARRAY_SIZE(debugfs_files);
282 dsi->minor = NULL; 265 struct tegra_dsi *dsi = to_dsi(output);
283 266
267 drm_debugfs_remove_files(dsi->debugfs_files, count,
268 connector->dev->primary);
284 kfree(dsi->debugfs_files); 269 kfree(dsi->debugfs_files);
285 dsi->debugfs_files = NULL; 270 dsi->debugfs_files = NULL;
286
287 debugfs_remove(dsi->debugfs);
288 dsi->debugfs = NULL;
289} 271}
290 272
291#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) 273#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
@@ -827,6 +809,8 @@ static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
827 .destroy = tegra_output_connector_destroy, 809 .destroy = tegra_output_connector_destroy,
828 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, 810 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
829 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 811 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
812 .late_register = tegra_dsi_late_register,
813 .early_unregister = tegra_dsi_early_unregister,
830}; 814};
831 815
832static enum drm_mode_status 816static enum drm_mode_status
@@ -1080,12 +1064,6 @@ static int tegra_dsi_init(struct host1x_client *client)
1080 dsi->output.encoder.possible_crtcs = 0x3; 1064 dsi->output.encoder.possible_crtcs = 0x3;
1081 } 1065 }
1082 1066
1083 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1084 err = tegra_dsi_debugfs_init(dsi, drm->primary);
1085 if (err < 0)
1086 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
1087 }
1088
1089 return 0; 1067 return 0;
1090} 1068}
1091 1069
@@ -1094,10 +1072,6 @@ static int tegra_dsi_exit(struct host1x_client *client)
1094 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1072 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1095 1073
1096 tegra_output_exit(&dsi->output); 1074 tegra_output_exit(&dsi->output);
1097
1098 if (IS_ENABLED(CONFIG_DEBUG_FS))
1099 tegra_dsi_debugfs_exit(dsi);
1100
1101 regulator_disable(dsi->vdd); 1075 regulator_disable(dsi->vdd);
1102 1076
1103 return 0; 1077 return 0;
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
index 8dfe3c6c217e..001cb77e2f59 100644
--- a/drivers/gpu/drm/tegra/fb.c
+++ b/drivers/gpu/drm/tegra/fb.c
@@ -54,17 +54,40 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
54 struct tegra_fb *fb = to_tegra_fb(framebuffer); 54 struct tegra_fb *fb = to_tegra_fb(framebuffer);
55 uint64_t modifier = fb->base.modifier; 55 uint64_t modifier = fb->base.modifier;
56 56
57 switch (fourcc_mod_tegra_mod(modifier)) { 57 switch (modifier) {
58 case NV_FORMAT_MOD_TEGRA_TILED: 58 case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
59 tiling->mode = TEGRA_BO_TILING_MODE_TILED; 59 tiling->mode = TEGRA_BO_TILING_MODE_TILED;
60 tiling->value = 0; 60 tiling->value = 0;
61 break; 61 break;
62 62
63 case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): 63 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
64 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; 64 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
65 tiling->value = fourcc_mod_tegra_param(modifier); 65 tiling->value = 0;
66 if (tiling->value > 5) 66 break;
67 return -EINVAL; 67
68 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
69 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
70 tiling->value = 1;
71 break;
72
73 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
74 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
75 tiling->value = 2;
76 break;
77
78 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
79 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
80 tiling->value = 3;
81 break;
82
83 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
84 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
85 tiling->value = 4;
86 break;
87
88 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
89 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
90 tiling->value = 5;
68 break; 91 break;
69 92
70 default: 93 default:
@@ -230,6 +253,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper,
230 cmd.height = sizes->surface_height; 253 cmd.height = sizes->surface_height;
231 cmd.pitches[0] = round_up(sizes->surface_width * bytes_per_pixel, 254 cmd.pitches[0] = round_up(sizes->surface_width * bytes_per_pixel,
232 tegra->pitch_align); 255 tegra->pitch_align);
256
233 cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, 257 cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
234 sizes->surface_depth); 258 sizes->surface_depth);
235 259
diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index ab1e53d434e8..49b9bf28f872 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -114,7 +114,7 @@ static const struct host1x_bo_ops tegra_bo_ops = {
114static int tegra_bo_iommu_map(struct tegra_drm *tegra, struct tegra_bo *bo) 114static int tegra_bo_iommu_map(struct tegra_drm *tegra, struct tegra_bo *bo)
115{ 115{
116 int prot = IOMMU_READ | IOMMU_WRITE; 116 int prot = IOMMU_READ | IOMMU_WRITE;
117 ssize_t err; 117 int err;
118 118
119 if (bo->mm) 119 if (bo->mm)
120 return -EBUSY; 120 return -EBUSY;
@@ -128,22 +128,21 @@ static int tegra_bo_iommu_map(struct tegra_drm *tegra, struct tegra_bo *bo)
128 err = drm_mm_insert_node_generic(&tegra->mm, 128 err = drm_mm_insert_node_generic(&tegra->mm,
129 bo->mm, bo->gem.size, PAGE_SIZE, 0, 0); 129 bo->mm, bo->gem.size, PAGE_SIZE, 0, 0);
130 if (err < 0) { 130 if (err < 0) {
131 dev_err(tegra->drm->dev, "out of I/O virtual memory: %zd\n", 131 dev_err(tegra->drm->dev, "out of I/O virtual memory: %d\n",
132 err); 132 err);
133 goto unlock; 133 goto unlock;
134 } 134 }
135 135
136 bo->paddr = bo->mm->start; 136 bo->paddr = bo->mm->start;
137 137
138 err = iommu_map_sg(tegra->domain, bo->paddr, bo->sgt->sgl, 138 bo->size = iommu_map_sg(tegra->domain, bo->paddr, bo->sgt->sgl,
139 bo->sgt->nents, prot); 139 bo->sgt->nents, prot);
140 if (err < 0) { 140 if (!bo->size) {
141 dev_err(tegra->drm->dev, "failed to map buffer: %zd\n", err); 141 dev_err(tegra->drm->dev, "failed to map buffer\n");
142 err = -ENOMEM;
142 goto remove; 143 goto remove;
143 } 144 }
144 145
145 bo->size = err;
146
147 mutex_unlock(&tegra->mm_lock); 146 mutex_unlock(&tegra->mm_lock);
148 147
149 return 0; 148 return 0;
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 6434b3d3d1ba..784739a9f497 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -79,8 +79,6 @@ struct tegra_hdmi {
79 bool dvi; 79 bool dvi;
80 80
81 struct drm_info_list *debugfs_files; 81 struct drm_info_list *debugfs_files;
82 struct drm_minor *minor;
83 struct dentry *debugfs;
84}; 82};
85 83
86static inline struct tegra_hdmi * 84static inline struct tegra_hdmi *
@@ -910,6 +908,249 @@ tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
910 return status; 908 return status;
911} 909}
912 910
911#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
912
913static const struct debugfs_reg32 tegra_hdmi_regs[] = {
914 DEBUGFS_REG32(HDMI_CTXSW),
915 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
916 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
917 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
918 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
919 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
920 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
921 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
922 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
923 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
924 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
925 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
926 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
927 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
928 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
929 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
930 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
931 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
932 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
933 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
934 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
935 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
936 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
937 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
938 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
939 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
940 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
941 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
942 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
943 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
944 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
945 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
946 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
947 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
948 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
949 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
950 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
951 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
952 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
953 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
954 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
955 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
956 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
957 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
958 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
959 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
960 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
961 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
962 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
963 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
964 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
965 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
966 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
967 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
968 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
969 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
970 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
971 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
972 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
973 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
974 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
975 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
976 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
977 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
978 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
979 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
980 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
981 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
982 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
983 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
984 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
985 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
986 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
987 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
988 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
989 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
990 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
991 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
992 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
993 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
994 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
995 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
996 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
997 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
998 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
999 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
1000 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
1001 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
1002 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
1003 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
1004 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
1005 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
1006 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
1007 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
1008 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
1009 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
1010 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
1011 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
1012 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
1013 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
1014 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
1015 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
1016 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
1017 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
1018 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
1019 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
1020 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
1021 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
1022 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
1023 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
1024 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
1025 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
1026 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
1027 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
1028 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
1029 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
1030 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
1031 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
1032 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
1033 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
1034 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
1035 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
1036 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
1037 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
1038 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
1039 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
1040 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
1041 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
1042 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
1043 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
1044 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
1045 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
1046 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
1047 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
1048 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
1049 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
1050 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
1051 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1052 DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1053 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1054 DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1055 DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1056 DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1057 DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1058 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1059 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1060 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1061 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1062 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1063 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1064 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1065 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1066 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1067 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1068 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1069 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1070 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1071 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1072 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1073 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1074 DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1075 DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1076 DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1077 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1078};
1079
1080static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1081{
1082 struct drm_info_node *node = s->private;
1083 struct tegra_hdmi *hdmi = node->info_ent->data;
1084 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1085 struct drm_device *drm = node->minor->dev;
1086 unsigned int i;
1087 int err = 0;
1088
1089 drm_modeset_lock_all(drm);
1090
1091 if (!crtc || !crtc->state->active) {
1092 err = -EBUSY;
1093 goto unlock;
1094 }
1095
1096 for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1097 unsigned int offset = tegra_hdmi_regs[i].offset;
1098
1099 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1100 offset, tegra_hdmi_readl(hdmi, offset));
1101 }
1102
1103unlock:
1104 drm_modeset_unlock_all(drm);
1105 return err;
1106}
1107
1108static struct drm_info_list debugfs_files[] = {
1109 { "regs", tegra_hdmi_show_regs, 0, NULL },
1110};
1111
1112static int tegra_hdmi_late_register(struct drm_connector *connector)
1113{
1114 struct tegra_output *output = connector_to_output(connector);
1115 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1116 struct drm_minor *minor = connector->dev->primary;
1117 struct dentry *root = connector->debugfs_entry;
1118 struct tegra_hdmi *hdmi = to_hdmi(output);
1119 int err;
1120
1121 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1122 GFP_KERNEL);
1123 if (!hdmi->debugfs_files)
1124 return -ENOMEM;
1125
1126 for (i = 0; i < count; i++)
1127 hdmi->debugfs_files[i].data = hdmi;
1128
1129 err = drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1130 if (err < 0)
1131 goto free;
1132
1133 return 0;
1134
1135free:
1136 kfree(hdmi->debugfs_files);
1137 hdmi->debugfs_files = NULL;
1138
1139 return err;
1140}
1141
1142static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1143{
1144 struct tegra_output *output = connector_to_output(connector);
1145 struct drm_minor *minor = connector->dev->primary;
1146 unsigned int count = ARRAY_SIZE(debugfs_files);
1147 struct tegra_hdmi *hdmi = to_hdmi(output);
1148
1149 drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
1150 kfree(hdmi->debugfs_files);
1151 hdmi->debugfs_files = NULL;
1152}
1153
913static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { 1154static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
914 .reset = drm_atomic_helper_connector_reset, 1155 .reset = drm_atomic_helper_connector_reset,
915 .detect = tegra_hdmi_connector_detect, 1156 .detect = tegra_hdmi_connector_detect,
@@ -917,6 +1158,8 @@ static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
917 .destroy = tegra_output_connector_destroy, 1158 .destroy = tegra_output_connector_destroy,
918 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1159 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
919 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1160 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1161 .late_register = tegra_hdmi_late_register,
1162 .early_unregister = tegra_hdmi_early_unregister,
920}; 1163};
921 1164
922static enum drm_mode_status 1165static enum drm_mode_status
@@ -1225,254 +1468,6 @@ static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1225 .atomic_check = tegra_hdmi_encoder_atomic_check, 1468 .atomic_check = tegra_hdmi_encoder_atomic_check,
1226}; 1469};
1227 1470
1228static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1229{
1230 struct drm_info_node *node = s->private;
1231 struct tegra_hdmi *hdmi = node->info_ent->data;
1232 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1233 struct drm_device *drm = node->minor->dev;
1234 int err = 0;
1235
1236 drm_modeset_lock_all(drm);
1237
1238 if (!crtc || !crtc->state->active) {
1239 err = -EBUSY;
1240 goto unlock;
1241 }
1242
1243#define DUMP_REG(name) \
1244 seq_printf(s, "%-56s %#05x %08x\n", #name, name, \
1245 tegra_hdmi_readl(hdmi, name))
1246
1247 DUMP_REG(HDMI_CTXSW);
1248 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
1249 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
1250 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
1251 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
1252 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
1253 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
1254 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
1255 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1256 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1257 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1258 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1259 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1260 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1261 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1262 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1263 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1264 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1265 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1266 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1267 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1268 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1269 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1270 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1271 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1272 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1273 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1274 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1275 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1276 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1277 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1278 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1279 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1280 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1281 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1282 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1283 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1284 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1285 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1286 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1287 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1288 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1289 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1290 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1291 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1292 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1293 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1294 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1295 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1296 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1297 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1298 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1299 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1300 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1301 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1302 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1303 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1304 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1305 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1306 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1307 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1308 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1309 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1310 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1311 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1312 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1313 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1314 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1315 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1316 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1317 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1318 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1319 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1320 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1321 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1322 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1323 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1324 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1325 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1326 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1327 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1328 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1329 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1330 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1331 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1332 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1333 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1334 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1335 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1336 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1337 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1338 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1339 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1340 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1341 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1342 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1343 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1344 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1345 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1346 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1347 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1348 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1349 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1350 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1351 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1352 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1353 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1354 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1355 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1356 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1357 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1358 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1359 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1360 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1361 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1362 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1363 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1364 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1365 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1366 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1367 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1368 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1369 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1370 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1371 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1372 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1373 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1374 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1375 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1376 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1377 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1378 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1379 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1380 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1381 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1382 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1383 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1384 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1385 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1386 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1387 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1388 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1389 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1390 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1391 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1392 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1393 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1394 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1395 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1396 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1397 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1398 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1399 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1400 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1401 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1402 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
1403 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1404 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1);
1405 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1406 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1407 DUMP_REG(HDMI_NV_PDISP_INT_STATUS);
1408 DUMP_REG(HDMI_NV_PDISP_INT_MASK);
1409 DUMP_REG(HDMI_NV_PDISP_INT_ENABLE);
1410 DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1411
1412#undef DUMP_REG
1413
1414unlock:
1415 drm_modeset_unlock_all(drm);
1416 return err;
1417}
1418
1419static struct drm_info_list debugfs_files[] = {
1420 { "regs", tegra_hdmi_show_regs, 0, NULL },
1421};
1422
1423static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1424 struct drm_minor *minor)
1425{
1426 unsigned int i;
1427 int err;
1428
1429 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1430 if (!hdmi->debugfs)
1431 return -ENOMEM;
1432
1433 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1434 GFP_KERNEL);
1435 if (!hdmi->debugfs_files) {
1436 err = -ENOMEM;
1437 goto remove;
1438 }
1439
1440 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1441 hdmi->debugfs_files[i].data = hdmi;
1442
1443 err = drm_debugfs_create_files(hdmi->debugfs_files,
1444 ARRAY_SIZE(debugfs_files),
1445 hdmi->debugfs, minor);
1446 if (err < 0)
1447 goto free;
1448
1449 hdmi->minor = minor;
1450
1451 return 0;
1452
1453free:
1454 kfree(hdmi->debugfs_files);
1455 hdmi->debugfs_files = NULL;
1456remove:
1457 debugfs_remove(hdmi->debugfs);
1458 hdmi->debugfs = NULL;
1459
1460 return err;
1461}
1462
1463static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1464{
1465 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1466 hdmi->minor);
1467 hdmi->minor = NULL;
1468
1469 kfree(hdmi->debugfs_files);
1470 hdmi->debugfs_files = NULL;
1471
1472 debugfs_remove(hdmi->debugfs);
1473 hdmi->debugfs = NULL;
1474}
1475
1476static int tegra_hdmi_init(struct host1x_client *client) 1471static int tegra_hdmi_init(struct host1x_client *client)
1477{ 1472{
1478 struct drm_device *drm = dev_get_drvdata(client->parent); 1473 struct drm_device *drm = dev_get_drvdata(client->parent);
@@ -1505,12 +1500,6 @@ static int tegra_hdmi_init(struct host1x_client *client)
1505 1500
1506 hdmi->output.encoder.possible_crtcs = 0x3; 1501 hdmi->output.encoder.possible_crtcs = 0x3;
1507 1502
1508 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1509 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1510 if (err < 0)
1511 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1512 }
1513
1514 err = regulator_enable(hdmi->hdmi); 1503 err = regulator_enable(hdmi->hdmi);
1515 if (err < 0) { 1504 if (err < 0) {
1516 dev_err(client->dev, "failed to enable HDMI regulator: %d\n", 1505 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
@@ -1543,9 +1532,6 @@ static int tegra_hdmi_exit(struct host1x_client *client)
1543 regulator_disable(hdmi->pll); 1532 regulator_disable(hdmi->pll);
1544 regulator_disable(hdmi->hdmi); 1533 regulator_disable(hdmi->hdmi);
1545 1534
1546 if (IS_ENABLED(CONFIG_DEBUG_FS))
1547 tegra_hdmi_debugfs_exit(hdmi);
1548
1549 return 0; 1535 return 0;
1550} 1536}
1551 1537
diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c
new file mode 100644
index 000000000000..e10a47d57313
--- /dev/null
+++ b/drivers/gpu/drm/tegra/hub.c
@@ -0,0 +1,806 @@
1/*
2 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
10#include <linux/host1x.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/of_graph.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18
19#include <drm/drmP.h>
20#include <drm/drm_atomic.h>
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_crtc_helper.h>
23
24#include "drm.h"
25#include "dc.h"
26#include "plane.h"
27
28static const u32 tegra_shared_plane_formats[] = {
29 DRM_FORMAT_ARGB1555,
30 DRM_FORMAT_RGB565,
31 DRM_FORMAT_RGBA5551,
32 DRM_FORMAT_ARGB8888,
33 DRM_FORMAT_ABGR8888,
34 /* new on Tegra114 */
35 DRM_FORMAT_ABGR4444,
36 DRM_FORMAT_ABGR1555,
37 DRM_FORMAT_BGRA5551,
38 DRM_FORMAT_XRGB1555,
39 DRM_FORMAT_RGBX5551,
40 DRM_FORMAT_XBGR1555,
41 DRM_FORMAT_BGRX5551,
42 DRM_FORMAT_BGR565,
43 DRM_FORMAT_XRGB8888,
44 DRM_FORMAT_XBGR8888,
45 /* planar formats */
46 DRM_FORMAT_UYVY,
47 DRM_FORMAT_YUYV,
48 DRM_FORMAT_YUV420,
49 DRM_FORMAT_YUV422,
50};
51
52static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
53 unsigned int offset)
54{
55 if (offset >= 0x500 && offset <= 0x581) {
56 offset = 0x000 + (offset - 0x500);
57 return plane->offset + offset;
58 }
59
60 if (offset >= 0x700 && offset <= 0x73c) {
61 offset = 0x180 + (offset - 0x700);
62 return plane->offset + offset;
63 }
64
65 if (offset >= 0x800 && offset <= 0x83e) {
66 offset = 0x1c0 + (offset - 0x800);
67 return plane->offset + offset;
68 }
69
70 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
71
72 return plane->offset + offset;
73}
74
75static inline u32 tegra_plane_readl(struct tegra_plane *plane,
76 unsigned int offset)
77{
78 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
79}
80
81static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
82 unsigned int offset)
83{
84 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
85}
86
87static int tegra_windowgroup_enable(struct tegra_windowgroup *wgrp)
88{
89 mutex_lock(&wgrp->lock);
90
91 if (wgrp->usecount == 0) {
92 pm_runtime_get_sync(wgrp->parent);
93 reset_control_deassert(wgrp->rst);
94 }
95
96 wgrp->usecount++;
97 mutex_unlock(&wgrp->lock);
98
99 return 0;
100}
101
102static void tegra_windowgroup_disable(struct tegra_windowgroup *wgrp)
103{
104 int err;
105
106 mutex_lock(&wgrp->lock);
107
108 if (wgrp->usecount == 1) {
109 err = reset_control_assert(wgrp->rst);
110 if (err < 0) {
111 pr_err("failed to assert reset for window group %u\n",
112 wgrp->index);
113 }
114
115 pm_runtime_put(wgrp->parent);
116 }
117
118 wgrp->usecount--;
119 mutex_unlock(&wgrp->lock);
120}
121
122int tegra_display_hub_prepare(struct tegra_display_hub *hub)
123{
124 unsigned int i;
125
126 /*
127 * XXX Enabling/disabling windowgroups needs to happen when the owner
128 * display controller is disabled. There's currently no good point at
129 * which this could be executed, so unconditionally enable all window
130 * groups for now.
131 */
132 for (i = 0; i < hub->soc->num_wgrps; i++) {
133 struct tegra_windowgroup *wgrp = &hub->wgrps[i];
134
135 tegra_windowgroup_enable(wgrp);
136 }
137
138 return 0;
139}
140
141void tegra_display_hub_cleanup(struct tegra_display_hub *hub)
142{
143 unsigned int i;
144
145 /*
146 * XXX Remove this once window groups can be more fine-grainedly
147 * enabled and disabled.
148 */
149 for (i = 0; i < hub->soc->num_wgrps; i++) {
150 struct tegra_windowgroup *wgrp = &hub->wgrps[i];
151
152 tegra_windowgroup_disable(wgrp);
153 }
154}
155
156static void tegra_shared_plane_update(struct tegra_plane *plane)
157{
158 struct tegra_dc *dc = plane->dc;
159 unsigned long timeout;
160 u32 mask, value;
161
162 mask = COMMON_UPDATE | WIN_A_UPDATE << plane->base.index;
163 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
164
165 timeout = jiffies + msecs_to_jiffies(1000);
166
167 while (time_before(jiffies, timeout)) {
168 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
169 if ((value & mask) == 0)
170 break;
171
172 usleep_range(100, 400);
173 }
174}
175
176static void tegra_shared_plane_activate(struct tegra_plane *plane)
177{
178 struct tegra_dc *dc = plane->dc;
179 unsigned long timeout;
180 u32 mask, value;
181
182 mask = COMMON_ACTREQ | WIN_A_ACT_REQ << plane->base.index;
183 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
184
185 timeout = jiffies + msecs_to_jiffies(1000);
186
187 while (time_before(jiffies, timeout)) {
188 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
189 if ((value & mask) == 0)
190 break;
191
192 usleep_range(100, 400);
193 }
194}
195
196static unsigned int
197tegra_shared_plane_get_owner(struct tegra_plane *plane, struct tegra_dc *dc)
198{
199 unsigned int offset =
200 tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
201
202 return tegra_dc_readl(dc, offset) & OWNER_MASK;
203}
204
205static bool tegra_dc_owns_shared_plane(struct tegra_dc *dc,
206 struct tegra_plane *plane)
207{
208 struct device *dev = dc->dev;
209
210 if (tegra_shared_plane_get_owner(plane, dc) == dc->pipe) {
211 if (plane->dc == dc)
212 return true;
213
214 dev_WARN(dev, "head %u owns window %u but is not attached\n",
215 dc->pipe, plane->index);
216 }
217
218 return false;
219}
220
221static int tegra_shared_plane_set_owner(struct tegra_plane *plane,
222 struct tegra_dc *new)
223{
224 unsigned int offset =
225 tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
226 struct tegra_dc *old = plane->dc, *dc = new ? new : old;
227 struct device *dev = new ? new->dev : old->dev;
228 unsigned int owner, index = plane->index;
229 u32 value;
230
231 value = tegra_dc_readl(dc, offset);
232 owner = value & OWNER_MASK;
233
234 if (new && (owner != OWNER_MASK && owner != new->pipe)) {
235 dev_WARN(dev, "window %u owned by head %u\n", index, owner);
236 return -EBUSY;
237 }
238
239 /*
240 * This seems to happen whenever the head has been disabled with one
241 * or more windows being active. This is harmless because we'll just
242 * reassign the window to the new head anyway.
243 */
244 if (old && owner == OWNER_MASK)
245 dev_dbg(dev, "window %u not owned by head %u but %u\n", index,
246 old->pipe, owner);
247
248 value &= ~OWNER_MASK;
249
250 if (new)
251 value |= OWNER(new->pipe);
252 else
253 value |= OWNER_MASK;
254
255 tegra_dc_writel(dc, value, offset);
256
257 plane->dc = new;
258
259 return 0;
260}
261
262static void tegra_dc_assign_shared_plane(struct tegra_dc *dc,
263 struct tegra_plane *plane)
264{
265 u32 value;
266 int err;
267
268 if (!tegra_dc_owns_shared_plane(dc, plane)) {
269 err = tegra_shared_plane_set_owner(plane, dc);
270 if (err < 0)
271 return;
272 }
273
274 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
275 value |= MODE_FOUR_LINES;
276 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
277
278 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
279 value = SLOTS(1);
280 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
281
282 /* disable watermark */
283 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
284 value &= ~LATENCY_CTL_MODE_ENABLE;
285 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
286
287 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
288 value |= WATERMARK_MASK;
289 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
290
291 /* pipe meter */
292 value = tegra_plane_readl(plane, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
293 value = PIPE_METER_INT(0) | PIPE_METER_FRAC(0);
294 tegra_plane_writel(plane, value, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
295
296 /* mempool entries */
297 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
298 value = MEMPOOL_ENTRIES(0x331);
299 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
300
301 value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_THREAD_GROUP);
302 value &= ~THREAD_NUM_MASK;
303 value |= THREAD_NUM(plane->base.index);
304 value |= THREAD_GROUP_ENABLE;
305 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_THREAD_GROUP);
306
307 tegra_shared_plane_update(plane);
308 tegra_shared_plane_activate(plane);
309}
310
311static void tegra_dc_remove_shared_plane(struct tegra_dc *dc,
312 struct tegra_plane *plane)
313{
314 tegra_shared_plane_set_owner(plane, NULL);
315}
316
317static int tegra_shared_plane_atomic_check(struct drm_plane *plane,
318 struct drm_plane_state *state)
319{
320 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
321 struct tegra_shared_plane *tegra = to_tegra_shared_plane(plane);
322 struct tegra_bo_tiling *tiling = &plane_state->tiling;
323 struct tegra_dc *dc = to_tegra_dc(state->crtc);
324 int err;
325
326 /* no need for further checks if the plane is being disabled */
327 if (!state->crtc || !state->fb)
328 return 0;
329
330 err = tegra_plane_format(state->fb->format->format,
331 &plane_state->format,
332 &plane_state->swap);
333 if (err < 0)
334 return err;
335
336 err = tegra_fb_get_tiling(state->fb, tiling);
337 if (err < 0)
338 return err;
339
340 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
341 !dc->soc->supports_block_linear) {
342 DRM_ERROR("hardware doesn't support block linear mode\n");
343 return -EINVAL;
344 }
345
346 /*
347 * Tegra doesn't support different strides for U and V planes so we
348 * error out if the user tries to display a framebuffer with such a
349 * configuration.
350 */
351 if (state->fb->format->num_planes > 2) {
352 if (state->fb->pitches[2] != state->fb->pitches[1]) {
353 DRM_ERROR("unsupported UV-plane configuration\n");
354 return -EINVAL;
355 }
356 }
357
358 /* XXX scaling is not yet supported, add a check here */
359
360 err = tegra_plane_state_add(&tegra->base, state);
361 if (err < 0)
362 return err;
363
364 return 0;
365}
366
367static void tegra_shared_plane_atomic_disable(struct drm_plane *plane,
368 struct drm_plane_state *old_state)
369{
370 struct tegra_dc *dc = to_tegra_dc(old_state->crtc);
371 struct tegra_plane *p = to_tegra_plane(plane);
372 u32 value;
373
374 /* rien ne va plus */
375 if (!old_state || !old_state->crtc)
376 return;
377
378 /*
379 * XXX Legacy helpers seem to sometimes call ->atomic_disable() even
380 * on planes that are already disabled. Make sure we fallback to the
381 * head for this particular state instead of crashing.
382 */
383 if (WARN_ON(p->dc == NULL))
384 p->dc = dc;
385
386 pm_runtime_get_sync(dc->dev);
387
388 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
389 value &= ~WIN_ENABLE;
390 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
391
392 tegra_dc_remove_shared_plane(dc, p);
393
394 pm_runtime_put(dc->dev);
395}
396
397static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
398 struct drm_plane_state *old_state)
399{
400 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
401 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
402 unsigned int zpos = plane->state->normalized_zpos;
403 struct drm_framebuffer *fb = plane->state->fb;
404 struct tegra_plane *p = to_tegra_plane(plane);
405 struct tegra_bo *bo;
406 dma_addr_t base;
407 u32 value;
408
409 /* rien ne va plus */
410 if (!plane->state->crtc || !plane->state->fb)
411 return;
412
413 if (!plane->state->visible) {
414 tegra_shared_plane_atomic_disable(plane, old_state);
415 return;
416 }
417
418 pm_runtime_get_sync(dc->dev);
419
420 tegra_dc_assign_shared_plane(dc, p);
421
422 tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL);
423
424 /* blending */
425 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
426 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
427 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
428 tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT);
429
430 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
431 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
432 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
433 tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT);
434
435 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos);
436 tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL);
437
438 /* bypass scaling */
439 value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5;
440 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER);
441
442 value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS;
443 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);
444
445 /* disable compression */
446 tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL);
447
448 bo = tegra_fb_get_plane(fb, 0);
449 base = bo->paddr;
450
451 tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH);
452 tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS);
453
454 value = V_POSITION(plane->state->crtc_y) |
455 H_POSITION(plane->state->crtc_x);
456 tegra_plane_writel(p, value, DC_WIN_POSITION);
457
458 value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
459 tegra_plane_writel(p, value, DC_WIN_SIZE);
460
461 value = WIN_ENABLE | COLOR_EXPAND;
462 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
463
464 value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
465 tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE);
466
467 tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI);
468 tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR);
469
470 value = PITCH(fb->pitches[0]);
471 tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
472
473 value = CLAMP_BEFORE_BLEND | DEGAMMA_SRGB | INPUT_RANGE_FULL;
474 tegra_plane_writel(p, value, DC_WIN_SET_PARAMS);
475
476 value = OFFSET_X(plane->state->src_y >> 16) |
477 OFFSET_Y(plane->state->src_x >> 16);
478 tegra_plane_writel(p, value, DC_WINBUF_CROPPED_POINT);
479
480 if (dc->soc->supports_block_linear) {
481 unsigned long height = state->tiling.value;
482
483 /* XXX */
484 switch (state->tiling.mode) {
485 case TEGRA_BO_TILING_MODE_PITCH:
486 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(0) |
487 DC_WINBUF_SURFACE_KIND_PITCH;
488 break;
489
490 /* XXX not supported on Tegra186 and later */
491 case TEGRA_BO_TILING_MODE_TILED:
492 value = DC_WINBUF_SURFACE_KIND_TILED;
493 break;
494
495 case TEGRA_BO_TILING_MODE_BLOCK:
496 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
497 DC_WINBUF_SURFACE_KIND_BLOCK;
498 break;
499 }
500
501 tegra_plane_writel(p, value, DC_WINBUF_SURFACE_KIND);
502 }
503
504 /* disable gamut CSC */
505 value = tegra_plane_readl(p, DC_WIN_WINDOW_SET_CONTROL);
506 value &= ~CONTROL_CSC_ENABLE;
507 tegra_plane_writel(p, value, DC_WIN_WINDOW_SET_CONTROL);
508
509 pm_runtime_put(dc->dev);
510}
511
512static const struct drm_plane_helper_funcs tegra_shared_plane_helper_funcs = {
513 .atomic_check = tegra_shared_plane_atomic_check,
514 .atomic_update = tegra_shared_plane_atomic_update,
515 .atomic_disable = tegra_shared_plane_atomic_disable,
516};
517
518struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
519 struct tegra_dc *dc,
520 unsigned int wgrp,
521 unsigned int index)
522{
523 enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
524 struct tegra_drm *tegra = drm->dev_private;
525 struct tegra_display_hub *hub = tegra->hub;
526 /* planes can be assigned to arbitrary CRTCs */
527 unsigned int possible_crtcs = 0x7;
528 struct tegra_shared_plane *plane;
529 unsigned int num_formats;
530 struct drm_plane *p;
531 const u32 *formats;
532 int err;
533
534 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
535 if (!plane)
536 return ERR_PTR(-ENOMEM);
537
538 plane->base.offset = 0x0a00 + 0x0300 * index;
539 plane->base.index = index;
540
541 plane->wgrp = &hub->wgrps[wgrp];
542 plane->wgrp->parent = dc->dev;
543
544 p = &plane->base.base;
545
546 num_formats = ARRAY_SIZE(tegra_shared_plane_formats);
547 formats = tegra_shared_plane_formats;
548
549 err = drm_universal_plane_init(drm, p, possible_crtcs,
550 &tegra_plane_funcs, formats,
551 num_formats, NULL, type, NULL);
552 if (err < 0) {
553 kfree(plane);
554 return ERR_PTR(err);
555 }
556
557 drm_plane_helper_add(p, &tegra_shared_plane_helper_funcs);
558 drm_plane_create_zpos_property(p, 0, 0, 255);
559
560 return p;
561}
562
563static void tegra_display_hub_update(struct tegra_dc *dc)
564{
565 u32 value;
566
567 pm_runtime_get_sync(dc->dev);
568
569 value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL);
570 value &= ~LATENCY_EVENT;
571 tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);
572
573 value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
574 value = CURS_SLOTS(1) | WGRP_SLOTS(1);
575 tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
576
577 tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
578 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
579 tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
580 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
581
582 pm_runtime_put(dc->dev);
583}
584
585void tegra_display_hub_atomic_commit(struct drm_device *drm,
586 struct drm_atomic_state *state)
587{
588 struct tegra_atomic_state *s = to_tegra_atomic_state(state);
589 struct tegra_drm *tegra = drm->dev_private;
590 struct tegra_display_hub *hub = tegra->hub;
591 struct device *dev = hub->client.dev;
592 int err;
593
594 if (s->clk_disp) {
595 err = clk_set_rate(s->clk_disp, s->rate);
596 if (err < 0)
597 dev_err(dev, "failed to set rate of %pC to %lu Hz\n",
598 s->clk_disp, s->rate);
599
600 err = clk_set_parent(hub->clk_disp, s->clk_disp);
601 if (err < 0)
602 dev_err(dev, "failed to set parent of %pC to %pC: %d\n",
603 hub->clk_disp, s->clk_disp, err);
604 }
605
606 if (s->dc)
607 tegra_display_hub_update(s->dc);
608}
609
610static int tegra_display_hub_init(struct host1x_client *client)
611{
612 struct tegra_display_hub *hub = to_tegra_display_hub(client);
613 struct drm_device *drm = dev_get_drvdata(client->parent);
614 struct tegra_drm *tegra = drm->dev_private;
615
616 tegra->hub = hub;
617
618 return 0;
619}
620
621static int tegra_display_hub_exit(struct host1x_client *client)
622{
623 struct drm_device *drm = dev_get_drvdata(client->parent);
624 struct tegra_drm *tegra = drm->dev_private;
625
626 tegra->hub = NULL;
627
628 return 0;
629}
630
631static const struct host1x_client_ops tegra_display_hub_ops = {
632 .init = tegra_display_hub_init,
633 .exit = tegra_display_hub_exit,
634};
635
636static int tegra_display_hub_probe(struct platform_device *pdev)
637{
638 struct tegra_display_hub *hub;
639 unsigned int i;
640 int err;
641
642 hub = devm_kzalloc(&pdev->dev, sizeof(*hub), GFP_KERNEL);
643 if (!hub)
644 return -ENOMEM;
645
646 hub->soc = of_device_get_match_data(&pdev->dev);
647
648 hub->clk_disp = devm_clk_get(&pdev->dev, "disp");
649 if (IS_ERR(hub->clk_disp)) {
650 err = PTR_ERR(hub->clk_disp);
651 return err;
652 }
653
654 hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc");
655 if (IS_ERR(hub->clk_dsc)) {
656 err = PTR_ERR(hub->clk_dsc);
657 return err;
658 }
659
660 hub->clk_hub = devm_clk_get(&pdev->dev, "hub");
661 if (IS_ERR(hub->clk_hub)) {
662 err = PTR_ERR(hub->clk_hub);
663 return err;
664 }
665
666 hub->rst = devm_reset_control_get(&pdev->dev, "misc");
667 if (IS_ERR(hub->rst)) {
668 err = PTR_ERR(hub->rst);
669 return err;
670 }
671
672 hub->wgrps = devm_kcalloc(&pdev->dev, hub->soc->num_wgrps,
673 sizeof(*hub->wgrps), GFP_KERNEL);
674 if (!hub->wgrps)
675 return -ENOMEM;
676
677 for (i = 0; i < hub->soc->num_wgrps; i++) {
678 struct tegra_windowgroup *wgrp = &hub->wgrps[i];
679 char id[8];
680
681 snprintf(id, sizeof(id), "wgrp%u", i);
682 mutex_init(&wgrp->lock);
683 wgrp->usecount = 0;
684 wgrp->index = i;
685
686 wgrp->rst = devm_reset_control_get(&pdev->dev, id);
687 if (IS_ERR(wgrp->rst))
688 return PTR_ERR(wgrp->rst);
689
690 err = reset_control_assert(wgrp->rst);
691 if (err < 0)
692 return err;
693 }
694
695 /* XXX: enable clock across reset? */
696 err = reset_control_assert(hub->rst);
697 if (err < 0)
698 return err;
699
700 platform_set_drvdata(pdev, hub);
701 pm_runtime_enable(&pdev->dev);
702
703 INIT_LIST_HEAD(&hub->client.list);
704 hub->client.ops = &tegra_display_hub_ops;
705 hub->client.dev = &pdev->dev;
706
707 err = host1x_client_register(&hub->client);
708 if (err < 0)
709 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
710 err);
711
712 return err;
713}
714
715static int tegra_display_hub_remove(struct platform_device *pdev)
716{
717 struct tegra_display_hub *hub = platform_get_drvdata(pdev);
718 int err;
719
720 err = host1x_client_unregister(&hub->client);
721 if (err < 0) {
722 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
723 err);
724 }
725
726 pm_runtime_disable(&pdev->dev);
727
728 return err;
729}
730
731static int __maybe_unused tegra_display_hub_suspend(struct device *dev)
732{
733 struct tegra_display_hub *hub = dev_get_drvdata(dev);
734 int err;
735
736 err = reset_control_assert(hub->rst);
737 if (err < 0)
738 return err;
739
740 clk_disable_unprepare(hub->clk_hub);
741 clk_disable_unprepare(hub->clk_dsc);
742 clk_disable_unprepare(hub->clk_disp);
743
744 return 0;
745}
746
747static int __maybe_unused tegra_display_hub_resume(struct device *dev)
748{
749 struct tegra_display_hub *hub = dev_get_drvdata(dev);
750 int err;
751
752 err = clk_prepare_enable(hub->clk_disp);
753 if (err < 0)
754 return err;
755
756 err = clk_prepare_enable(hub->clk_dsc);
757 if (err < 0)
758 goto disable_disp;
759
760 err = clk_prepare_enable(hub->clk_hub);
761 if (err < 0)
762 goto disable_dsc;
763
764 err = reset_control_deassert(hub->rst);
765 if (err < 0)
766 goto disable_hub;
767
768 return 0;
769
770disable_hub:
771 clk_disable_unprepare(hub->clk_hub);
772disable_dsc:
773 clk_disable_unprepare(hub->clk_dsc);
774disable_disp:
775 clk_disable_unprepare(hub->clk_disp);
776 return err;
777}
778
779static const struct dev_pm_ops tegra_display_hub_pm_ops = {
780 SET_RUNTIME_PM_OPS(tegra_display_hub_suspend,
781 tegra_display_hub_resume, NULL)
782};
783
784static const struct tegra_display_hub_soc tegra186_display_hub = {
785 .num_wgrps = 6,
786};
787
788static const struct of_device_id tegra_display_hub_of_match[] = {
789 {
790 .compatible = "nvidia,tegra186-display",
791 .data = &tegra186_display_hub
792 }, {
793 /* sentinel */
794 }
795};
796MODULE_DEVICE_TABLE(of, tegra_display_hub_of_match);
797
798struct platform_driver tegra_display_hub_driver = {
799 .driver = {
800 .name = "tegra-display-hub",
801 .of_match_table = tegra_display_hub_of_match,
802 .pm = &tegra_display_hub_pm_ops,
803 },
804 .probe = tegra_display_hub_probe,
805 .remove = tegra_display_hub_remove,
806};
diff --git a/drivers/gpu/drm/tegra/hub.h b/drivers/gpu/drm/tegra/hub.h
new file mode 100644
index 000000000000..890a47cd05c3
--- /dev/null
+++ b/drivers/gpu/drm/tegra/hub.h
@@ -0,0 +1,81 @@
1/*
2 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef TEGRA_HUB_H
10#define TEGRA_HUB_H 1
11
12#include <drm/drmP.h>
13#include <drm/drm_plane.h>
14
15#include "plane.h"
16
17struct tegra_dc;
18
19struct tegra_windowgroup {
20 unsigned int usecount;
21 struct mutex lock;
22
23 unsigned int index;
24 struct device *parent;
25 struct reset_control *rst;
26};
27
28struct tegra_shared_plane {
29 struct tegra_plane base;
30 struct tegra_windowgroup *wgrp;
31};
32
33static inline struct tegra_shared_plane *
34to_tegra_shared_plane(struct drm_plane *plane)
35{
36 return container_of(plane, struct tegra_shared_plane, base.base);
37}
38
39struct tegra_display_hub_soc {
40 unsigned int num_wgrps;
41};
42
43struct tegra_display_hub {
44 struct host1x_client client;
45 struct clk *clk_disp;
46 struct clk *clk_dsc;
47 struct clk *clk_hub;
48 struct reset_control *rst;
49
50 const struct tegra_display_hub_soc *soc;
51 struct tegra_windowgroup *wgrps;
52};
53
54static inline struct tegra_display_hub *
55to_tegra_display_hub(struct host1x_client *client)
56{
57 return container_of(client, struct tegra_display_hub, client);
58}
59
60struct tegra_dc;
61struct tegra_plane;
62
63int tegra_display_hub_prepare(struct tegra_display_hub *hub);
64void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
65
66struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
67 struct tegra_dc *dc,
68 unsigned int wgrp,
69 unsigned int index);
70
71void tegra_display_hub_atomic_commit(struct drm_device *drm,
72 struct drm_atomic_state *state);
73
74#define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
75#define LATENCY_EVENT (1 << 3)
76
77#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
78#define CURS_SLOTS(x) (((x) & 0xff) << 8)
79#define WGRP_SLOTS(x) (((x) & 0xff) << 0)
80
81#endif /* TEGRA_HUB_H */
diff --git a/drivers/gpu/drm/tegra/output.c b/drivers/gpu/drm/tegra/output.c
index 24f8a3b712b4..ffe34bd0bb9d 100644
--- a/drivers/gpu/drm/tegra/output.c
+++ b/drivers/gpu/drm/tegra/output.c
@@ -9,7 +9,9 @@
9 9
10#include <drm/drm_atomic_helper.h> 10#include <drm/drm_atomic_helper.h>
11#include <drm/drm_panel.h> 11#include <drm/drm_panel.h>
12
12#include "drm.h" 13#include "drm.h"
14#include "dc.h"
13 15
14#include <media/cec-notifier.h> 16#include <media/cec-notifier.h>
15 17
@@ -218,3 +220,25 @@ void tegra_output_exit(struct tegra_output *output)
218 if (output->panel) 220 if (output->panel)
219 drm_panel_detach(output->panel); 221 drm_panel_detach(output->panel);
220} 222}
223
224void tegra_output_find_possible_crtcs(struct tegra_output *output,
225 struct drm_device *drm)
226{
227 struct device *dev = output->dev;
228 struct drm_crtc *crtc;
229 unsigned int mask = 0;
230
231 drm_for_each_crtc(crtc, drm) {
232 struct tegra_dc *dc = to_tegra_dc(crtc);
233
234 if (tegra_dc_has_output(dc, dev))
235 mask |= drm_crtc_mask(crtc);
236 }
237
238 if (mask == 0) {
239 dev_warn(dev, "missing output definition for heads in DT\n");
240 mask = 0x3;
241 }
242
243 output->encoder.possible_crtcs = mask;
244}
diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c
new file mode 100644
index 000000000000..36a06a993698
--- /dev/null
+++ b/drivers/gpu/drm/tegra/plane.c
@@ -0,0 +1,383 @@
1/*
2 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <drm/drm_atomic.h>
10#include <drm/drm_atomic_helper.h>
11#include <drm/drm_plane_helper.h>
12
13#include "dc.h"
14#include "plane.h"
15
16static void tegra_plane_destroy(struct drm_plane *plane)
17{
18 struct tegra_plane *p = to_tegra_plane(plane);
19
20 drm_plane_cleanup(plane);
21 kfree(p);
22}
23
24static void tegra_plane_reset(struct drm_plane *plane)
25{
26 struct tegra_plane_state *state;
27
28 if (plane->state)
29 __drm_atomic_helper_plane_destroy_state(plane->state);
30
31 kfree(plane->state);
32 plane->state = NULL;
33
34 state = kzalloc(sizeof(*state), GFP_KERNEL);
35 if (state) {
36 plane->state = &state->base;
37 plane->state->plane = plane;
38 }
39}
40
41static struct drm_plane_state *
42tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
43{
44 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
45 struct tegra_plane_state *copy;
46 unsigned int i;
47
48 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
49 if (!copy)
50 return NULL;
51
52 __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
53 copy->tiling = state->tiling;
54 copy->format = state->format;
55 copy->swap = state->swap;
56 copy->opaque = state->opaque;
57
58 for (i = 0; i < 3; i++)
59 copy->dependent[i] = state->dependent[i];
60
61 return &copy->base;
62}
63
64static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
65 struct drm_plane_state *state)
66{
67 __drm_atomic_helper_plane_destroy_state(state);
68 kfree(state);
69}
70
71const struct drm_plane_funcs tegra_plane_funcs = {
72 .update_plane = drm_atomic_helper_update_plane,
73 .disable_plane = drm_atomic_helper_disable_plane,
74 .destroy = tegra_plane_destroy,
75 .reset = tegra_plane_reset,
76 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
77 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
78};
79
80int tegra_plane_state_add(struct tegra_plane *plane,
81 struct drm_plane_state *state)
82{
83 struct drm_crtc_state *crtc_state;
84 struct tegra_dc_state *tegra;
85 struct drm_rect clip;
86 int err;
87
88 /* Propagate errors from allocation or locking failures. */
89 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
90 if (IS_ERR(crtc_state))
91 return PTR_ERR(crtc_state);
92
93 clip.x1 = 0;
94 clip.y1 = 0;
95 clip.x2 = crtc_state->mode.hdisplay;
96 clip.y2 = crtc_state->mode.vdisplay;
97
98 /* Check plane state for visibility and calculate clipping bounds */
99 err = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
100 0, INT_MAX, true, true);
101 if (err < 0)
102 return err;
103
104 tegra = to_dc_state(crtc_state);
105
106 tegra->planes |= WIN_A_ACT_REQ << plane->index;
107
108 return 0;
109}
110
111int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
112{
113 /* assume no swapping of fetched data */
114 if (swap)
115 *swap = BYTE_SWAP_NOSWAP;
116
117 switch (fourcc) {
118 case DRM_FORMAT_ARGB4444:
119 *format = WIN_COLOR_DEPTH_B4G4R4A4;
120 break;
121
122 case DRM_FORMAT_ARGB1555:
123 *format = WIN_COLOR_DEPTH_B5G5R5A1;
124 break;
125
126 case DRM_FORMAT_RGB565:
127 *format = WIN_COLOR_DEPTH_B5G6R5;
128 break;
129
130 case DRM_FORMAT_RGBA5551:
131 *format = WIN_COLOR_DEPTH_A1B5G5R5;
132 break;
133
134 case DRM_FORMAT_ARGB8888:
135 *format = WIN_COLOR_DEPTH_B8G8R8A8;
136 break;
137
138 case DRM_FORMAT_ABGR8888:
139 *format = WIN_COLOR_DEPTH_R8G8B8A8;
140 break;
141
142 case DRM_FORMAT_ABGR4444:
143 *format = WIN_COLOR_DEPTH_R4G4B4A4;
144 break;
145
146 case DRM_FORMAT_ABGR1555:
147 *format = WIN_COLOR_DEPTH_R5G5B5A;
148 break;
149
150 case DRM_FORMAT_BGRA5551:
151 *format = WIN_COLOR_DEPTH_AR5G5B5;
152 break;
153
154 case DRM_FORMAT_XRGB1555:
155 *format = WIN_COLOR_DEPTH_B5G5R5X1;
156 break;
157
158 case DRM_FORMAT_RGBX5551:
159 *format = WIN_COLOR_DEPTH_X1B5G5R5;
160 break;
161
162 case DRM_FORMAT_XBGR1555:
163 *format = WIN_COLOR_DEPTH_R5G5B5X1;
164 break;
165
166 case DRM_FORMAT_BGRX5551:
167 *format = WIN_COLOR_DEPTH_X1R5G5B5;
168 break;
169
170 case DRM_FORMAT_BGR565:
171 *format = WIN_COLOR_DEPTH_R5G6B5;
172 break;
173
174 case DRM_FORMAT_BGRA8888:
175 *format = WIN_COLOR_DEPTH_A8R8G8B8;
176 break;
177
178 case DRM_FORMAT_RGBA8888:
179 *format = WIN_COLOR_DEPTH_A8B8G8R8;
180 break;
181
182 case DRM_FORMAT_XRGB8888:
183 *format = WIN_COLOR_DEPTH_B8G8R8X8;
184 break;
185
186 case DRM_FORMAT_XBGR8888:
187 *format = WIN_COLOR_DEPTH_R8G8B8X8;
188 break;
189
190 case DRM_FORMAT_UYVY:
191 *format = WIN_COLOR_DEPTH_YCbCr422;
192 break;
193
194 case DRM_FORMAT_YUYV:
195 if (!swap)
196 return -EINVAL;
197
198 *format = WIN_COLOR_DEPTH_YCbCr422;
199 *swap = BYTE_SWAP_SWAP2;
200 break;
201
202 case DRM_FORMAT_YUV420:
203 *format = WIN_COLOR_DEPTH_YCbCr420P;
204 break;
205
206 case DRM_FORMAT_YUV422:
207 *format = WIN_COLOR_DEPTH_YCbCr422P;
208 break;
209
210 default:
211 return -EINVAL;
212 }
213
214 return 0;
215}
216
217bool tegra_plane_format_is_yuv(unsigned int format, bool *planar)
218{
219 switch (format) {
220 case WIN_COLOR_DEPTH_YCbCr422:
221 case WIN_COLOR_DEPTH_YUV422:
222 if (planar)
223 *planar = false;
224
225 return true;
226
227 case WIN_COLOR_DEPTH_YCbCr420P:
228 case WIN_COLOR_DEPTH_YUV420P:
229 case WIN_COLOR_DEPTH_YCbCr422P:
230 case WIN_COLOR_DEPTH_YUV422P:
231 case WIN_COLOR_DEPTH_YCbCr422R:
232 case WIN_COLOR_DEPTH_YUV422R:
233 case WIN_COLOR_DEPTH_YCbCr422RA:
234 case WIN_COLOR_DEPTH_YUV422RA:
235 if (planar)
236 *planar = true;
237
238 return true;
239 }
240
241 if (planar)
242 *planar = false;
243
244 return false;
245}
246
247static bool __drm_format_has_alpha(u32 format)
248{
249 switch (format) {
250 case DRM_FORMAT_ARGB1555:
251 case DRM_FORMAT_RGBA5551:
252 case DRM_FORMAT_ABGR8888:
253 case DRM_FORMAT_ARGB8888:
254 return true;
255 }
256
257 return false;
258}
259
260/*
261 * This is applicable to Tegra20 and Tegra30 only where the opaque formats can
262 * be emulated using the alpha formats and alpha blending disabled.
263 */
264bool tegra_plane_format_has_alpha(unsigned int format)
265{
266 switch (format) {
267 case WIN_COLOR_DEPTH_B5G5R5A1:
268 case WIN_COLOR_DEPTH_A1B5G5R5:
269 case WIN_COLOR_DEPTH_R8G8B8A8:
270 case WIN_COLOR_DEPTH_B8G8R8A8:
271 return true;
272 }
273
274 return false;
275}
276
277int tegra_plane_format_get_alpha(unsigned int opaque, unsigned int *alpha)
278{
279 if (tegra_plane_format_is_yuv(opaque, NULL)) {
280 *alpha = opaque;
281 return 0;
282 }
283
284 switch (opaque) {
285 case WIN_COLOR_DEPTH_B5G5R5X1:
286 *alpha = WIN_COLOR_DEPTH_B5G5R5A1;
287 return 0;
288
289 case WIN_COLOR_DEPTH_X1B5G5R5:
290 *alpha = WIN_COLOR_DEPTH_A1B5G5R5;
291 return 0;
292
293 case WIN_COLOR_DEPTH_R8G8B8X8:
294 *alpha = WIN_COLOR_DEPTH_R8G8B8A8;
295 return 0;
296
297 case WIN_COLOR_DEPTH_B8G8R8X8:
298 *alpha = WIN_COLOR_DEPTH_B8G8R8A8;
299 return 0;
300 }
301
302 return -EINVAL;
303}
304
305unsigned int tegra_plane_get_overlap_index(struct tegra_plane *plane,
306 struct tegra_plane *other)
307{
308 unsigned int index = 0, i;
309
310 WARN_ON(plane == other);
311
312 for (i = 0; i < 3; i++) {
313 if (i == plane->index)
314 continue;
315
316 if (i == other->index)
317 break;
318
319 index++;
320 }
321
322 return index;
323}
324
325void tegra_plane_check_dependent(struct tegra_plane *tegra,
326 struct tegra_plane_state *state)
327{
328 struct drm_plane_state *old, *new;
329 struct drm_plane *plane;
330 unsigned int zpos[2];
331 unsigned int i;
332
333 for (i = 0; i < 3; i++)
334 state->dependent[i] = false;
335
336 for (i = 0; i < 2; i++)
337 zpos[i] = 0;
338
339 for_each_oldnew_plane_in_state(state->base.state, plane, old, new, i) {
340 struct tegra_plane *p = to_tegra_plane(plane);
341 unsigned index;
342
343 /* skip this plane and planes on different CRTCs */
344 if (p == tegra || new->crtc != state->base.crtc)
345 continue;
346
347 index = tegra_plane_get_overlap_index(tegra, p);
348
349 /*
350 * If any of the other planes is on top of this plane and uses
351 * a format with an alpha component, mark this plane as being
352 * dependent, meaning it's alpha value will be 1 minus the sum
353 * of alpha components of the overlapping planes.
354 */
355 if (p->index > tegra->index) {
356 if (__drm_format_has_alpha(new->fb->format->format))
357 state->dependent[index] = true;
358
359 /* keep track of the Z position */
360 zpos[index] = p->index;
361 }
362 }
363
364 /*
365 * The region where three windows overlap is the intersection of the
366 * two regions where two windows overlap. It contributes to the area
367 * if any of the windows on top of it have an alpha component.
368 */
369 for (i = 0; i < 2; i++)
370 state->dependent[2] = state->dependent[2] ||
371 state->dependent[i];
372
373 /*
374 * However, if any of the windows on top of this window is opaque, it
375 * will completely conceal this window within that area, so avoid the
376 * window from contributing to the area.
377 */
378 for (i = 0; i < 2; i++) {
379 if (zpos[i] > tegra->index)
380 state->dependent[2] = state->dependent[2] &&
381 state->dependent[i];
382 }
383}
diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h
new file mode 100644
index 000000000000..6938719e7e5d
--- /dev/null
+++ b/drivers/gpu/drm/tegra/plane.h
@@ -0,0 +1,70 @@
1/*
2 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef TEGRA_PLANE_H
10#define TEGRA_PLANE_H 1
11
12#include <drm/drm_plane.h>
13
14struct tegra_bo;
15struct tegra_dc;
16
17struct tegra_plane {
18 struct drm_plane base;
19 struct tegra_dc *dc;
20 unsigned int offset;
21 unsigned int index;
22};
23
24struct tegra_cursor {
25 struct tegra_plane base;
26
27 struct tegra_bo *bo;
28 unsigned int width;
29 unsigned int height;
30};
31
32static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
33{
34 return container_of(plane, struct tegra_plane, base);
35}
36
37struct tegra_plane_state {
38 struct drm_plane_state base;
39
40 struct tegra_bo_tiling tiling;
41 u32 format;
42 u32 swap;
43
44 /* used for legacy blending support only */
45 bool opaque;
46 bool dependent[3];
47};
48
49static inline struct tegra_plane_state *
50to_tegra_plane_state(struct drm_plane_state *state)
51{
52 if (state)
53 return container_of(state, struct tegra_plane_state, base);
54
55 return NULL;
56}
57
58extern const struct drm_plane_funcs tegra_plane_funcs;
59
60int tegra_plane_state_add(struct tegra_plane *plane,
61 struct drm_plane_state *state);
62
63int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
64bool tegra_plane_format_is_yuv(unsigned int format, bool *planar);
65bool tegra_plane_format_has_alpha(unsigned int format);
66int tegra_plane_format_get_alpha(unsigned int opaque, unsigned int *alpha);
67void tegra_plane_check_dependent(struct tegra_plane *tegra,
68 struct tegra_plane_state *state);
69
70#endif /* TEGRA_PLANE_H */
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index b0a1dedac802..4be9edf9c6fe 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -22,23 +22,37 @@
22#include <drm/drm_atomic_helper.h> 22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_dp_helper.h> 23#include <drm/drm_dp_helper.h>
24#include <drm/drm_panel.h> 24#include <drm/drm_panel.h>
25#include <drm/drm_scdc_helper.h>
25 26
26#include "dc.h" 27#include "dc.h"
27#include "drm.h" 28#include "drm.h"
28#include "sor.h" 29#include "sor.h"
29#include "trace.h" 30#include "trace.h"
30 31
32/*
33 * XXX Remove this after the commit adding it to soc/tegra/pmc.h has been
34 * merged. Having this around after the commit is merged should be safe since
35 * the preprocessor will effectively replace all occurrences and therefore no
36 * duplicate will be defined.
37 */
38#define TEGRA_IO_PAD_HDMI_DP0 26
39
31#define SOR_REKEY 0x38 40#define SOR_REKEY 0x38
32 41
33struct tegra_sor_hdmi_settings { 42struct tegra_sor_hdmi_settings {
34 unsigned long frequency; 43 unsigned long frequency;
35 44
36 u8 vcocap; 45 u8 vcocap;
46 u8 filter;
37 u8 ichpmp; 47 u8 ichpmp;
38 u8 loadadj; 48 u8 loadadj;
39 u8 termadj; 49 u8 tmds_termadj;
40 u8 tx_pu; 50 u8 tx_pu_value;
41 u8 bg_vref; 51 u8 bg_temp_coef;
52 u8 bg_vref_level;
53 u8 avdd10_level;
54 u8 avdd14_level;
55 u8 sparepll;
42 56
43 u8 drive_current[4]; 57 u8 drive_current[4];
44 u8 preemphasis[4]; 58 u8 preemphasis[4];
@@ -49,51 +63,76 @@ static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
49 { 63 {
50 .frequency = 54000000, 64 .frequency = 54000000,
51 .vcocap = 0x0, 65 .vcocap = 0x0,
66 .filter = 0x0,
52 .ichpmp = 0x1, 67 .ichpmp = 0x1,
53 .loadadj = 0x3, 68 .loadadj = 0x3,
54 .termadj = 0x9, 69 .tmds_termadj = 0x9,
55 .tx_pu = 0x10, 70 .tx_pu_value = 0x10,
56 .bg_vref = 0x8, 71 .bg_temp_coef = 0x3,
72 .bg_vref_level = 0x8,
73 .avdd10_level = 0x4,
74 .avdd14_level = 0x4,
75 .sparepll = 0x0,
57 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 76 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
58 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 77 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
59 }, { 78 }, {
60 .frequency = 75000000, 79 .frequency = 75000000,
61 .vcocap = 0x3, 80 .vcocap = 0x3,
81 .filter = 0x0,
62 .ichpmp = 0x1, 82 .ichpmp = 0x1,
63 .loadadj = 0x3, 83 .loadadj = 0x3,
64 .termadj = 0x9, 84 .tmds_termadj = 0x9,
65 .tx_pu = 0x40, 85 .tx_pu_value = 0x40,
66 .bg_vref = 0x8, 86 .bg_temp_coef = 0x3,
87 .bg_vref_level = 0x8,
88 .avdd10_level = 0x4,
89 .avdd14_level = 0x4,
90 .sparepll = 0x0,
67 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 91 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
68 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 92 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
69 }, { 93 }, {
70 .frequency = 150000000, 94 .frequency = 150000000,
71 .vcocap = 0x3, 95 .vcocap = 0x3,
96 .filter = 0x0,
72 .ichpmp = 0x1, 97 .ichpmp = 0x1,
73 .loadadj = 0x3, 98 .loadadj = 0x3,
74 .termadj = 0x9, 99 .tmds_termadj = 0x9,
75 .tx_pu = 0x66, 100 .tx_pu_value = 0x66,
76 .bg_vref = 0x8, 101 .bg_temp_coef = 0x3,
102 .bg_vref_level = 0x8,
103 .avdd10_level = 0x4,
104 .avdd14_level = 0x4,
105 .sparepll = 0x0,
77 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 106 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
78 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 107 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
79 }, { 108 }, {
80 .frequency = 300000000, 109 .frequency = 300000000,
81 .vcocap = 0x3, 110 .vcocap = 0x3,
111 .filter = 0x0,
82 .ichpmp = 0x1, 112 .ichpmp = 0x1,
83 .loadadj = 0x3, 113 .loadadj = 0x3,
84 .termadj = 0x9, 114 .tmds_termadj = 0x9,
85 .tx_pu = 0x66, 115 .tx_pu_value = 0x66,
86 .bg_vref = 0xa, 116 .bg_temp_coef = 0x3,
117 .bg_vref_level = 0xa,
118 .avdd10_level = 0x4,
119 .avdd14_level = 0x4,
120 .sparepll = 0x0,
87 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 121 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
88 .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 122 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
89 }, { 123 }, {
90 .frequency = 600000000, 124 .frequency = 600000000,
91 .vcocap = 0x3, 125 .vcocap = 0x3,
126 .filter = 0x0,
92 .ichpmp = 0x1, 127 .ichpmp = 0x1,
93 .loadadj = 0x3, 128 .loadadj = 0x3,
94 .termadj = 0x9, 129 .tmds_termadj = 0x9,
95 .tx_pu = 0x66, 130 .tx_pu_value = 0x66,
96 .bg_vref = 0x8, 131 .bg_temp_coef = 0x3,
132 .bg_vref_level = 0x8,
133 .avdd10_level = 0x4,
134 .avdd14_level = 0x4,
135 .sparepll = 0x0,
97 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 136 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
98 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 137 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
99 }, 138 },
@@ -103,53 +142,170 @@ static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
103 { 142 {
104 .frequency = 75000000, 143 .frequency = 75000000,
105 .vcocap = 0x3, 144 .vcocap = 0x3,
145 .filter = 0x0,
106 .ichpmp = 0x1, 146 .ichpmp = 0x1,
107 .loadadj = 0x3, 147 .loadadj = 0x3,
108 .termadj = 0x9, 148 .tmds_termadj = 0x9,
109 .tx_pu = 0x40, 149 .tx_pu_value = 0x40,
110 .bg_vref = 0x8, 150 .bg_temp_coef = 0x3,
151 .bg_vref_level = 0x8,
152 .avdd10_level = 0x4,
153 .avdd14_level = 0x4,
154 .sparepll = 0x0,
111 .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 155 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
112 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 156 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
113 }, { 157 }, {
114 .frequency = 150000000, 158 .frequency = 150000000,
115 .vcocap = 0x3, 159 .vcocap = 0x3,
160 .filter = 0x0,
116 .ichpmp = 0x1, 161 .ichpmp = 0x1,
117 .loadadj = 0x3, 162 .loadadj = 0x3,
118 .termadj = 0x9, 163 .tmds_termadj = 0x9,
119 .tx_pu = 0x66, 164 .tx_pu_value = 0x66,
120 .bg_vref = 0x8, 165 .bg_temp_coef = 0x3,
166 .bg_vref_level = 0x8,
167 .avdd10_level = 0x4,
168 .avdd14_level = 0x4,
169 .sparepll = 0x0,
121 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 170 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
122 .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 171 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
123 }, { 172 }, {
124 .frequency = 300000000, 173 .frequency = 300000000,
125 .vcocap = 0x3, 174 .vcocap = 0x3,
175 .filter = 0x0,
126 .ichpmp = 0x6, 176 .ichpmp = 0x6,
127 .loadadj = 0x3, 177 .loadadj = 0x3,
128 .termadj = 0x9, 178 .tmds_termadj = 0x9,
129 .tx_pu = 0x66, 179 .tx_pu_value = 0x66,
130 .bg_vref = 0xf, 180 .bg_temp_coef = 0x3,
181 .bg_vref_level = 0xf,
182 .avdd10_level = 0x4,
183 .avdd14_level = 0x4,
184 .sparepll = 0x0,
131 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 185 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
132 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 186 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
133 }, { 187 }, {
134 .frequency = 600000000, 188 .frequency = 600000000,
135 .vcocap = 0x3, 189 .vcocap = 0x3,
190 .filter = 0x0,
136 .ichpmp = 0xa, 191 .ichpmp = 0xa,
137 .loadadj = 0x3, 192 .loadadj = 0x3,
138 .termadj = 0xb, 193 .tmds_termadj = 0xb,
139 .tx_pu = 0x66, 194 .tx_pu_value = 0x66,
140 .bg_vref = 0xe, 195 .bg_temp_coef = 0x3,
196 .bg_vref_level = 0xe,
197 .avdd10_level = 0x4,
198 .avdd14_level = 0x4,
199 .sparepll = 0x0,
141 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 200 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
142 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 201 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
143 }, 202 },
144}; 203};
145#endif 204#endif
146 205
206static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
207 {
208 .frequency = 54000000,
209 .vcocap = 0,
210 .filter = 5,
211 .ichpmp = 5,
212 .loadadj = 3,
213 .tmds_termadj = 0xf,
214 .tx_pu_value = 0,
215 .bg_temp_coef = 3,
216 .bg_vref_level = 8,
217 .avdd10_level = 4,
218 .avdd14_level = 4,
219 .sparepll = 0x54,
220 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
221 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
222 }, {
223 .frequency = 75000000,
224 .vcocap = 1,
225 .filter = 5,
226 .ichpmp = 5,
227 .loadadj = 3,
228 .tmds_termadj = 0xf,
229 .tx_pu_value = 0,
230 .bg_temp_coef = 3,
231 .bg_vref_level = 8,
232 .avdd10_level = 4,
233 .avdd14_level = 4,
234 .sparepll = 0x44,
235 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
236 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
237 }, {
238 .frequency = 150000000,
239 .vcocap = 3,
240 .filter = 5,
241 .ichpmp = 5,
242 .loadadj = 3,
243 .tmds_termadj = 15,
244 .tx_pu_value = 0x66 /* 0 */,
245 .bg_temp_coef = 3,
246 .bg_vref_level = 8,
247 .avdd10_level = 4,
248 .avdd14_level = 4,
249 .sparepll = 0x00, /* 0x34 */
250 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
251 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
252 }, {
253 .frequency = 300000000,
254 .vcocap = 3,
255 .filter = 5,
256 .ichpmp = 5,
257 .loadadj = 3,
258 .tmds_termadj = 15,
259 .tx_pu_value = 64,
260 .bg_temp_coef = 3,
261 .bg_vref_level = 8,
262 .avdd10_level = 4,
263 .avdd14_level = 4,
264 .sparepll = 0x34,
265 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
266 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
267 }, {
268 .frequency = 600000000,
269 .vcocap = 3,
270 .filter = 5,
271 .ichpmp = 5,
272 .loadadj = 3,
273 .tmds_termadj = 12,
274 .tx_pu_value = 96,
275 .bg_temp_coef = 3,
276 .bg_vref_level = 8,
277 .avdd10_level = 4,
278 .avdd14_level = 4,
279 .sparepll = 0x34,
280 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
281 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
282 }
283};
284
285struct tegra_sor_regs {
286 unsigned int head_state0;
287 unsigned int head_state1;
288 unsigned int head_state2;
289 unsigned int head_state3;
290 unsigned int head_state4;
291 unsigned int head_state5;
292 unsigned int pll0;
293 unsigned int pll1;
294 unsigned int pll2;
295 unsigned int pll3;
296 unsigned int dp_padctl0;
297 unsigned int dp_padctl2;
298};
299
147struct tegra_sor_soc { 300struct tegra_sor_soc {
148 bool supports_edp; 301 bool supports_edp;
149 bool supports_lvds; 302 bool supports_lvds;
150 bool supports_hdmi; 303 bool supports_hdmi;
151 bool supports_dp; 304 bool supports_dp;
152 305
306 const struct tegra_sor_regs *regs;
307 bool has_nvdisplay;
308
153 const struct tegra_sor_hdmi_settings *settings; 309 const struct tegra_sor_hdmi_settings *settings;
154 unsigned int num_settings; 310 unsigned int num_settings;
155 311
@@ -171,6 +327,7 @@ struct tegra_sor {
171 327
172 const struct tegra_sor_soc *soc; 328 const struct tegra_sor_soc *soc;
173 void __iomem *regs; 329 void __iomem *regs;
330 unsigned int index;
174 331
175 struct reset_control *rst; 332 struct reset_control *rst;
176 struct clk *clk_parent; 333 struct clk *clk_parent;
@@ -183,10 +340,9 @@ struct tegra_sor {
183 struct drm_dp_aux *aux; 340 struct drm_dp_aux *aux;
184 341
185 struct drm_info_list *debugfs_files; 342 struct drm_info_list *debugfs_files;
186 struct drm_minor *minor;
187 struct dentry *debugfs;
188 343
189 const struct tegra_sor_ops *ops; 344 const struct tegra_sor_ops *ops;
345 enum tegra_io_pad pad;
190 346
191 /* for HDMI 2.0 */ 347 /* for HDMI 2.0 */
192 struct tegra_sor_hdmi_settings *settings; 348 struct tegra_sor_hdmi_settings *settings;
@@ -195,11 +351,16 @@ struct tegra_sor {
195 struct regulator *avdd_io_supply; 351 struct regulator *avdd_io_supply;
196 struct regulator *vdd_pll_supply; 352 struct regulator *vdd_pll_supply;
197 struct regulator *hdmi_supply; 353 struct regulator *hdmi_supply;
354
355 struct delayed_work scdc;
356 bool scdc_enabled;
198}; 357};
199 358
200struct tegra_sor_state { 359struct tegra_sor_state {
201 struct drm_connector_state base; 360 struct drm_connector_state base;
202 361
362 unsigned int link_speed;
363 unsigned long pclk;
203 unsigned int bpc; 364 unsigned int bpc;
204}; 365};
205 366
@@ -389,23 +550,23 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
389 /* disable LVDS mode */ 550 /* disable LVDS mode */
390 tegra_sor_writel(sor, 0, SOR_LVDS); 551 tegra_sor_writel(sor, 0, SOR_LVDS);
391 552
392 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 553 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
393 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 554 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
394 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 555 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
395 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ 556 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
396 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 557 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
397 558
398 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 559 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
399 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 560 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
400 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; 561 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
401 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 562 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
402 563
403 usleep_range(10, 100); 564 usleep_range(10, 100);
404 565
405 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 566 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
406 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 567 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
407 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 568 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
408 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 569 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
409 570
410 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); 571 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
411 if (err < 0) 572 if (err < 0)
@@ -465,47 +626,6 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
465 return 0; 626 return 0;
466} 627}
467 628
468static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
469{
470 u32 mask = 0x08, adj = 0, value;
471
472 /* enable pad calibration logic */
473 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
474 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
475 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
476
477 value = tegra_sor_readl(sor, SOR_PLL1);
478 value |= SOR_PLL1_TMDS_TERM;
479 tegra_sor_writel(sor, value, SOR_PLL1);
480
481 while (mask) {
482 adj |= mask;
483
484 value = tegra_sor_readl(sor, SOR_PLL1);
485 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
486 value |= SOR_PLL1_TMDS_TERMADJ(adj);
487 tegra_sor_writel(sor, value, SOR_PLL1);
488
489 usleep_range(100, 200);
490
491 value = tegra_sor_readl(sor, SOR_PLL1);
492 if (value & SOR_PLL1_TERM_COMPOUT)
493 adj &= ~mask;
494
495 mask >>= 1;
496 }
497
498 value = tegra_sor_readl(sor, SOR_PLL1);
499 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
500 value |= SOR_PLL1_TMDS_TERMADJ(adj);
501 tegra_sor_writel(sor, value, SOR_PLL1);
502
503 /* disable pad calibration logic */
504 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
505 value |= SOR_DP_PADCTL_PAD_CAL_PD;
506 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
507}
508
509static void tegra_sor_super_update(struct tegra_sor *sor) 629static void tegra_sor_super_update(struct tegra_sor *sor)
510{ 630{
511 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 631 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
@@ -897,31 +1017,31 @@ static void tegra_sor_mode_set(struct tegra_sor *sor,
897 */ 1017 */
898 1018
899 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 1019 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
900 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); 1020 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
901 1021
902 /* sync end = sync width - 1 */ 1022 /* sync end = sync width - 1 */
903 vse = mode->vsync_end - mode->vsync_start - 1; 1023 vse = mode->vsync_end - mode->vsync_start - 1;
904 hse = mode->hsync_end - mode->hsync_start - 1; 1024 hse = mode->hsync_end - mode->hsync_start - 1;
905 1025
906 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 1026 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
907 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); 1027 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
908 1028
909 /* blank end = sync end + back porch */ 1029 /* blank end = sync end + back porch */
910 vbe = vse + (mode->vtotal - mode->vsync_end); 1030 vbe = vse + (mode->vtotal - mode->vsync_end);
911 hbe = hse + (mode->htotal - mode->hsync_end); 1031 hbe = hse + (mode->htotal - mode->hsync_end);
912 1032
913 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 1033 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
914 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); 1034 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
915 1035
916 /* blank start = blank end + active */ 1036 /* blank start = blank end + active */
917 vbs = vbe + mode->vdisplay; 1037 vbs = vbe + mode->vdisplay;
918 hbs = hbe + mode->hdisplay; 1038 hbs = hbe + mode->hdisplay;
919 1039
920 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 1040 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
921 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); 1041 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
922 1042
923 /* XXX interlacing support */ 1043 /* XXX interlacing support */
924 tegra_sor_writel(sor, 0x001, SOR_HEAD_STATE5(dc->pipe)); 1044 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
925} 1045}
926 1046
927static int tegra_sor_detach(struct tegra_sor *sor) 1047static int tegra_sor_detach(struct tegra_sor *sor)
@@ -1003,10 +1123,10 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
1003 return err; 1123 return err;
1004 } 1124 }
1005 1125
1006 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1126 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1007 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 1127 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1008 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 1128 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1009 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1129 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1010 1130
1011 /* stop lane sequencer */ 1131 /* stop lane sequencer */
1012 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 1132 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
@@ -1026,20 +1146,20 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
1026 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 1146 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1027 return -ETIMEDOUT; 1147 return -ETIMEDOUT;
1028 1148
1029 value = tegra_sor_readl(sor, SOR_PLL2); 1149 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1030 value |= SOR_PLL2_PORT_POWERDOWN; 1150 value |= SOR_PLL2_PORT_POWERDOWN;
1031 tegra_sor_writel(sor, value, SOR_PLL2); 1151 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1032 1152
1033 usleep_range(20, 100); 1153 usleep_range(20, 100);
1034 1154
1035 value = tegra_sor_readl(sor, SOR_PLL0); 1155 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1036 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1156 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1037 tegra_sor_writel(sor, value, SOR_PLL0); 1157 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1038 1158
1039 value = tegra_sor_readl(sor, SOR_PLL2); 1159 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1040 value |= SOR_PLL2_SEQ_PLLCAPPD; 1160 value |= SOR_PLL2_SEQ_PLLCAPPD;
1041 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1161 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1042 tegra_sor_writel(sor, value, SOR_PLL2); 1162 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1043 1163
1044 usleep_range(20, 100); 1164 usleep_range(20, 100);
1045 1165
@@ -1105,12 +1225,133 @@ unlock:
1105 return err; 1225 return err;
1106} 1226}
1107 1227
1228#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1229
1230static const struct debugfs_reg32 tegra_sor_regs[] = {
1231 DEBUGFS_REG32(SOR_CTXSW),
1232 DEBUGFS_REG32(SOR_SUPER_STATE0),
1233 DEBUGFS_REG32(SOR_SUPER_STATE1),
1234 DEBUGFS_REG32(SOR_STATE0),
1235 DEBUGFS_REG32(SOR_STATE1),
1236 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1237 DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1238 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1239 DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1240 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1241 DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1242 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1243 DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1244 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1245 DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1246 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1247 DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1248 DEBUGFS_REG32(SOR_CRC_CNTRL),
1249 DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1250 DEBUGFS_REG32(SOR_CLK_CNTRL),
1251 DEBUGFS_REG32(SOR_CAP),
1252 DEBUGFS_REG32(SOR_PWR),
1253 DEBUGFS_REG32(SOR_TEST),
1254 DEBUGFS_REG32(SOR_PLL0),
1255 DEBUGFS_REG32(SOR_PLL1),
1256 DEBUGFS_REG32(SOR_PLL2),
1257 DEBUGFS_REG32(SOR_PLL3),
1258 DEBUGFS_REG32(SOR_CSTM),
1259 DEBUGFS_REG32(SOR_LVDS),
1260 DEBUGFS_REG32(SOR_CRCA),
1261 DEBUGFS_REG32(SOR_CRCB),
1262 DEBUGFS_REG32(SOR_BLANK),
1263 DEBUGFS_REG32(SOR_SEQ_CTL),
1264 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1265 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1266 DEBUGFS_REG32(SOR_SEQ_INST(1)),
1267 DEBUGFS_REG32(SOR_SEQ_INST(2)),
1268 DEBUGFS_REG32(SOR_SEQ_INST(3)),
1269 DEBUGFS_REG32(SOR_SEQ_INST(4)),
1270 DEBUGFS_REG32(SOR_SEQ_INST(5)),
1271 DEBUGFS_REG32(SOR_SEQ_INST(6)),
1272 DEBUGFS_REG32(SOR_SEQ_INST(7)),
1273 DEBUGFS_REG32(SOR_SEQ_INST(8)),
1274 DEBUGFS_REG32(SOR_SEQ_INST(9)),
1275 DEBUGFS_REG32(SOR_SEQ_INST(10)),
1276 DEBUGFS_REG32(SOR_SEQ_INST(11)),
1277 DEBUGFS_REG32(SOR_SEQ_INST(12)),
1278 DEBUGFS_REG32(SOR_SEQ_INST(13)),
1279 DEBUGFS_REG32(SOR_SEQ_INST(14)),
1280 DEBUGFS_REG32(SOR_SEQ_INST(15)),
1281 DEBUGFS_REG32(SOR_PWM_DIV),
1282 DEBUGFS_REG32(SOR_PWM_CTL),
1283 DEBUGFS_REG32(SOR_VCRC_A0),
1284 DEBUGFS_REG32(SOR_VCRC_A1),
1285 DEBUGFS_REG32(SOR_VCRC_B0),
1286 DEBUGFS_REG32(SOR_VCRC_B1),
1287 DEBUGFS_REG32(SOR_CCRC_A0),
1288 DEBUGFS_REG32(SOR_CCRC_A1),
1289 DEBUGFS_REG32(SOR_CCRC_B0),
1290 DEBUGFS_REG32(SOR_CCRC_B1),
1291 DEBUGFS_REG32(SOR_EDATA_A0),
1292 DEBUGFS_REG32(SOR_EDATA_A1),
1293 DEBUGFS_REG32(SOR_EDATA_B0),
1294 DEBUGFS_REG32(SOR_EDATA_B1),
1295 DEBUGFS_REG32(SOR_COUNT_A0),
1296 DEBUGFS_REG32(SOR_COUNT_A1),
1297 DEBUGFS_REG32(SOR_COUNT_B0),
1298 DEBUGFS_REG32(SOR_COUNT_B1),
1299 DEBUGFS_REG32(SOR_DEBUG_A0),
1300 DEBUGFS_REG32(SOR_DEBUG_A1),
1301 DEBUGFS_REG32(SOR_DEBUG_B0),
1302 DEBUGFS_REG32(SOR_DEBUG_B1),
1303 DEBUGFS_REG32(SOR_TRIG),
1304 DEBUGFS_REG32(SOR_MSCHECK),
1305 DEBUGFS_REG32(SOR_XBAR_CTRL),
1306 DEBUGFS_REG32(SOR_XBAR_POL),
1307 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1308 DEBUGFS_REG32(SOR_DP_LINKCTL1),
1309 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1310 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1311 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1312 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1313 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1314 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1315 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1316 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1317 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1318 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1319 DEBUGFS_REG32(SOR_DP_CONFIG0),
1320 DEBUGFS_REG32(SOR_DP_CONFIG1),
1321 DEBUGFS_REG32(SOR_DP_MN0),
1322 DEBUGFS_REG32(SOR_DP_MN1),
1323 DEBUGFS_REG32(SOR_DP_PADCTL0),
1324 DEBUGFS_REG32(SOR_DP_PADCTL1),
1325 DEBUGFS_REG32(SOR_DP_PADCTL2),
1326 DEBUGFS_REG32(SOR_DP_DEBUG0),
1327 DEBUGFS_REG32(SOR_DP_DEBUG1),
1328 DEBUGFS_REG32(SOR_DP_SPARE0),
1329 DEBUGFS_REG32(SOR_DP_SPARE1),
1330 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1331 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1332 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1333 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1334 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1335 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1336 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1337 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1338 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1339 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1340 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1341 DEBUGFS_REG32(SOR_DP_TPG),
1342 DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1343 DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1344 DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1345 DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1346};
1347
1108static int tegra_sor_show_regs(struct seq_file *s, void *data) 1348static int tegra_sor_show_regs(struct seq_file *s, void *data)
1109{ 1349{
1110 struct drm_info_node *node = s->private; 1350 struct drm_info_node *node = s->private;
1111 struct tegra_sor *sor = node->info_ent->data; 1351 struct tegra_sor *sor = node->info_ent->data;
1112 struct drm_crtc *crtc = sor->output.encoder.crtc; 1352 struct drm_crtc *crtc = sor->output.encoder.crtc;
1113 struct drm_device *drm = node->minor->dev; 1353 struct drm_device *drm = node->minor->dev;
1354 unsigned int i;
1114 int err = 0; 1355 int err = 0;
1115 1356
1116 drm_modeset_lock_all(drm); 1357 drm_modeset_lock_all(drm);
@@ -1120,126 +1361,12 @@ static int tegra_sor_show_regs(struct seq_file *s, void *data)
1120 goto unlock; 1361 goto unlock;
1121 } 1362 }
1122 1363
1123#define DUMP_REG(name) \ 1364 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1124 seq_printf(s, "%-38s %#05x %08x\n", #name, name, \ 1365 unsigned int offset = tegra_sor_regs[i].offset;
1125 tegra_sor_readl(sor, name)) 1366
1126 1367 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1127 DUMP_REG(SOR_CTXSW); 1368 offset, tegra_sor_readl(sor, offset));
1128 DUMP_REG(SOR_SUPER_STATE0); 1369 }
1129 DUMP_REG(SOR_SUPER_STATE1);
1130 DUMP_REG(SOR_STATE0);
1131 DUMP_REG(SOR_STATE1);
1132 DUMP_REG(SOR_HEAD_STATE0(0));
1133 DUMP_REG(SOR_HEAD_STATE0(1));
1134 DUMP_REG(SOR_HEAD_STATE1(0));
1135 DUMP_REG(SOR_HEAD_STATE1(1));
1136 DUMP_REG(SOR_HEAD_STATE2(0));
1137 DUMP_REG(SOR_HEAD_STATE2(1));
1138 DUMP_REG(SOR_HEAD_STATE3(0));
1139 DUMP_REG(SOR_HEAD_STATE3(1));
1140 DUMP_REG(SOR_HEAD_STATE4(0));
1141 DUMP_REG(SOR_HEAD_STATE4(1));
1142 DUMP_REG(SOR_HEAD_STATE5(0));
1143 DUMP_REG(SOR_HEAD_STATE5(1));
1144 DUMP_REG(SOR_CRC_CNTRL);
1145 DUMP_REG(SOR_DP_DEBUG_MVID);
1146 DUMP_REG(SOR_CLK_CNTRL);
1147 DUMP_REG(SOR_CAP);
1148 DUMP_REG(SOR_PWR);
1149 DUMP_REG(SOR_TEST);
1150 DUMP_REG(SOR_PLL0);
1151 DUMP_REG(SOR_PLL1);
1152 DUMP_REG(SOR_PLL2);
1153 DUMP_REG(SOR_PLL3);
1154 DUMP_REG(SOR_CSTM);
1155 DUMP_REG(SOR_LVDS);
1156 DUMP_REG(SOR_CRCA);
1157 DUMP_REG(SOR_CRCB);
1158 DUMP_REG(SOR_BLANK);
1159 DUMP_REG(SOR_SEQ_CTL);
1160 DUMP_REG(SOR_LANE_SEQ_CTL);
1161 DUMP_REG(SOR_SEQ_INST(0));
1162 DUMP_REG(SOR_SEQ_INST(1));
1163 DUMP_REG(SOR_SEQ_INST(2));
1164 DUMP_REG(SOR_SEQ_INST(3));
1165 DUMP_REG(SOR_SEQ_INST(4));
1166 DUMP_REG(SOR_SEQ_INST(5));
1167 DUMP_REG(SOR_SEQ_INST(6));
1168 DUMP_REG(SOR_SEQ_INST(7));
1169 DUMP_REG(SOR_SEQ_INST(8));
1170 DUMP_REG(SOR_SEQ_INST(9));
1171 DUMP_REG(SOR_SEQ_INST(10));
1172 DUMP_REG(SOR_SEQ_INST(11));
1173 DUMP_REG(SOR_SEQ_INST(12));
1174 DUMP_REG(SOR_SEQ_INST(13));
1175 DUMP_REG(SOR_SEQ_INST(14));
1176 DUMP_REG(SOR_SEQ_INST(15));
1177 DUMP_REG(SOR_PWM_DIV);
1178 DUMP_REG(SOR_PWM_CTL);
1179 DUMP_REG(SOR_VCRC_A0);
1180 DUMP_REG(SOR_VCRC_A1);
1181 DUMP_REG(SOR_VCRC_B0);
1182 DUMP_REG(SOR_VCRC_B1);
1183 DUMP_REG(SOR_CCRC_A0);
1184 DUMP_REG(SOR_CCRC_A1);
1185 DUMP_REG(SOR_CCRC_B0);
1186 DUMP_REG(SOR_CCRC_B1);
1187 DUMP_REG(SOR_EDATA_A0);
1188 DUMP_REG(SOR_EDATA_A1);
1189 DUMP_REG(SOR_EDATA_B0);
1190 DUMP_REG(SOR_EDATA_B1);
1191 DUMP_REG(SOR_COUNT_A0);
1192 DUMP_REG(SOR_COUNT_A1);
1193 DUMP_REG(SOR_COUNT_B0);
1194 DUMP_REG(SOR_COUNT_B1);
1195 DUMP_REG(SOR_DEBUG_A0);
1196 DUMP_REG(SOR_DEBUG_A1);
1197 DUMP_REG(SOR_DEBUG_B0);
1198 DUMP_REG(SOR_DEBUG_B1);
1199 DUMP_REG(SOR_TRIG);
1200 DUMP_REG(SOR_MSCHECK);
1201 DUMP_REG(SOR_XBAR_CTRL);
1202 DUMP_REG(SOR_XBAR_POL);
1203 DUMP_REG(SOR_DP_LINKCTL0);
1204 DUMP_REG(SOR_DP_LINKCTL1);
1205 DUMP_REG(SOR_LANE_DRIVE_CURRENT0);
1206 DUMP_REG(SOR_LANE_DRIVE_CURRENT1);
1207 DUMP_REG(SOR_LANE4_DRIVE_CURRENT0);
1208 DUMP_REG(SOR_LANE4_DRIVE_CURRENT1);
1209 DUMP_REG(SOR_LANE_PREEMPHASIS0);
1210 DUMP_REG(SOR_LANE_PREEMPHASIS1);
1211 DUMP_REG(SOR_LANE4_PREEMPHASIS0);
1212 DUMP_REG(SOR_LANE4_PREEMPHASIS1);
1213 DUMP_REG(SOR_LANE_POSTCURSOR0);
1214 DUMP_REG(SOR_LANE_POSTCURSOR1);
1215 DUMP_REG(SOR_DP_CONFIG0);
1216 DUMP_REG(SOR_DP_CONFIG1);
1217 DUMP_REG(SOR_DP_MN0);
1218 DUMP_REG(SOR_DP_MN1);
1219 DUMP_REG(SOR_DP_PADCTL0);
1220 DUMP_REG(SOR_DP_PADCTL1);
1221 DUMP_REG(SOR_DP_DEBUG0);
1222 DUMP_REG(SOR_DP_DEBUG1);
1223 DUMP_REG(SOR_DP_SPARE0);
1224 DUMP_REG(SOR_DP_SPARE1);
1225 DUMP_REG(SOR_DP_AUDIO_CTRL);
1226 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);
1227 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);
1228 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);
1229 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0);
1230 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1);
1231 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2);
1232 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3);
1233 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4);
1234 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5);
1235 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6);
1236 DUMP_REG(SOR_DP_TPG);
1237 DUMP_REG(SOR_DP_TPG_CONFIG);
1238 DUMP_REG(SOR_DP_LQ_CSTM0);
1239 DUMP_REG(SOR_DP_LQ_CSTM1);
1240 DUMP_REG(SOR_DP_LQ_CSTM2);
1241
1242#undef DUMP_REG
1243 1370
1244unlock: 1371unlock:
1245 drm_modeset_unlock_all(drm); 1372 drm_modeset_unlock_all(drm);
@@ -1251,57 +1378,46 @@ static const struct drm_info_list debugfs_files[] = {
1251 { "regs", tegra_sor_show_regs, 0, NULL }, 1378 { "regs", tegra_sor_show_regs, 0, NULL },
1252}; 1379};
1253 1380
1254static int tegra_sor_debugfs_init(struct tegra_sor *sor, 1381static int tegra_sor_late_register(struct drm_connector *connector)
1255 struct drm_minor *minor)
1256{ 1382{
1257 const char *name = sor->soc->supports_dp ? "sor1" : "sor"; 1383 struct tegra_output *output = connector_to_output(connector);
1258 unsigned int i; 1384 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1385 struct drm_minor *minor = connector->dev->primary;
1386 struct dentry *root = connector->debugfs_entry;
1387 struct tegra_sor *sor = to_sor(output);
1259 int err; 1388 int err;
1260 1389
1261 sor->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1262 if (!sor->debugfs)
1263 return -ENOMEM;
1264
1265 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1390 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1266 GFP_KERNEL); 1391 GFP_KERNEL);
1267 if (!sor->debugfs_files) { 1392 if (!sor->debugfs_files)
1268 err = -ENOMEM; 1393 return -ENOMEM;
1269 goto remove;
1270 }
1271 1394
1272 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 1395 for (i = 0; i < count; i++)
1273 sor->debugfs_files[i].data = sor; 1396 sor->debugfs_files[i].data = sor;
1274 1397
1275 err = drm_debugfs_create_files(sor->debugfs_files, 1398 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1276 ARRAY_SIZE(debugfs_files),
1277 sor->debugfs, minor);
1278 if (err < 0) 1399 if (err < 0)
1279 goto free; 1400 goto free;
1280 1401
1281 sor->minor = minor;
1282
1283 return 0; 1402 return 0;
1284 1403
1285free: 1404free:
1286 kfree(sor->debugfs_files); 1405 kfree(sor->debugfs_files);
1287 sor->debugfs_files = NULL; 1406 sor->debugfs_files = NULL;
1288remove: 1407
1289 debugfs_remove_recursive(sor->debugfs);
1290 sor->debugfs = NULL;
1291 return err; 1408 return err;
1292} 1409}
1293 1410
1294static void tegra_sor_debugfs_exit(struct tegra_sor *sor) 1411static void tegra_sor_early_unregister(struct drm_connector *connector)
1295{ 1412{
1296 drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), 1413 struct tegra_output *output = connector_to_output(connector);
1297 sor->minor); 1414 unsigned int count = ARRAY_SIZE(debugfs_files);
1298 sor->minor = NULL; 1415 struct tegra_sor *sor = to_sor(output);
1299 1416
1417 drm_debugfs_remove_files(sor->debugfs_files, count,
1418 connector->dev->primary);
1300 kfree(sor->debugfs_files); 1419 kfree(sor->debugfs_files);
1301 sor->debugfs_files = NULL; 1420 sor->debugfs_files = NULL;
1302
1303 debugfs_remove_recursive(sor->debugfs);
1304 sor->debugfs = NULL;
1305} 1421}
1306 1422
1307static void tegra_sor_connector_reset(struct drm_connector *connector) 1423static void tegra_sor_connector_reset(struct drm_connector *connector)
@@ -1354,6 +1470,8 @@ static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1354 .destroy = tegra_output_connector_destroy, 1470 .destroy = tegra_output_connector_destroy,
1355 .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 1471 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1356 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1472 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1473 .late_register = tegra_sor_late_register,
1474 .early_unregister = tegra_sor_early_unregister,
1357}; 1475};
1358 1476
1359static int tegra_sor_connector_get_modes(struct drm_connector *connector) 1477static int tegra_sor_connector_get_modes(struct drm_connector *connector)
@@ -1377,10 +1495,6 @@ static enum drm_mode_status
1377tegra_sor_connector_mode_valid(struct drm_connector *connector, 1495tegra_sor_connector_mode_valid(struct drm_connector *connector,
1378 struct drm_display_mode *mode) 1496 struct drm_display_mode *mode)
1379{ 1497{
1380 /* HDMI 2.0 modes are not yet supported */
1381 if (mode->clock > 340000)
1382 return MODE_NOCLOCK;
1383
1384 return MODE_OK; 1498 return MODE_OK;
1385} 1499}
1386 1500
@@ -1417,7 +1531,7 @@ static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1417 */ 1531 */
1418 if (dc) { 1532 if (dc) {
1419 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1533 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1420 value &= ~SOR_ENABLE; 1534 value &= ~SOR_ENABLE(0);
1421 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1535 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1422 1536
1423 tegra_dc_commit(dc); 1537 tegra_dc_commit(dc);
@@ -1433,9 +1547,9 @@ static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1433 dev_err(sor->dev, "failed to disable DP: %d\n", err); 1547 dev_err(sor->dev, "failed to disable DP: %d\n", err);
1434 } 1548 }
1435 1549
1436 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); 1550 err = tegra_io_pad_power_disable(sor->pad);
1437 if (err < 0) 1551 if (err < 0)
1438 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); 1552 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1439 1553
1440 if (output->panel) 1554 if (output->panel)
1441 drm_panel_unprepare(output->panel); 1555 drm_panel_unprepare(output->panel);
@@ -1533,40 +1647,40 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1533 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 1647 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1534 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1648 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1535 1649
1536 value = tegra_sor_readl(sor, SOR_PLL2); 1650 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1537 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1651 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1538 tegra_sor_writel(sor, value, SOR_PLL2); 1652 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1539 usleep_range(20, 100); 1653 usleep_range(20, 100);
1540 1654
1541 value = tegra_sor_readl(sor, SOR_PLL3); 1655 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1542 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 1656 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1543 tegra_sor_writel(sor, value, SOR_PLL3); 1657 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1544 1658
1545 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | 1659 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1546 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; 1660 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1547 tegra_sor_writel(sor, value, SOR_PLL0); 1661 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1548 1662
1549 value = tegra_sor_readl(sor, SOR_PLL2); 1663 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1550 value |= SOR_PLL2_SEQ_PLLCAPPD; 1664 value |= SOR_PLL2_SEQ_PLLCAPPD;
1551 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1665 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1552 value |= SOR_PLL2_LVDS_ENABLE; 1666 value |= SOR_PLL2_LVDS_ENABLE;
1553 tegra_sor_writel(sor, value, SOR_PLL2); 1667 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1554 1668
1555 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; 1669 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1556 tegra_sor_writel(sor, value, SOR_PLL1); 1670 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
1557 1671
1558 while (true) { 1672 while (true) {
1559 value = tegra_sor_readl(sor, SOR_PLL2); 1673 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1560 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) 1674 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1561 break; 1675 break;
1562 1676
1563 usleep_range(250, 1000); 1677 usleep_range(250, 1000);
1564 } 1678 }
1565 1679
1566 value = tegra_sor_readl(sor, SOR_PLL2); 1680 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1567 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 1681 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1568 value &= ~SOR_PLL2_PORT_POWERDOWN; 1682 value &= ~SOR_PLL2_PORT_POWERDOWN;
1569 tegra_sor_writel(sor, value, SOR_PLL2); 1683 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1570 1684
1571 /* 1685 /*
1572 * power up 1686 * power up
@@ -1579,49 +1693,49 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1579 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1693 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1580 1694
1581 /* step 1 */ 1695 /* step 1 */
1582 value = tegra_sor_readl(sor, SOR_PLL2); 1696 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1583 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | 1697 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1584 SOR_PLL2_BANDGAP_POWERDOWN; 1698 SOR_PLL2_BANDGAP_POWERDOWN;
1585 tegra_sor_writel(sor, value, SOR_PLL2); 1699 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1586 1700
1587 value = tegra_sor_readl(sor, SOR_PLL0); 1701 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1588 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1702 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1589 tegra_sor_writel(sor, value, SOR_PLL0); 1703 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1590 1704
1591 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1705 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1592 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 1706 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1593 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1707 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1594 1708
1595 /* step 2 */ 1709 /* step 2 */
1596 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); 1710 err = tegra_io_pad_power_enable(sor->pad);
1597 if (err < 0) 1711 if (err < 0)
1598 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); 1712 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
1599 1713
1600 usleep_range(5, 100); 1714 usleep_range(5, 100);
1601 1715
1602 /* step 3 */ 1716 /* step 3 */
1603 value = tegra_sor_readl(sor, SOR_PLL2); 1717 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1604 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1718 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1605 tegra_sor_writel(sor, value, SOR_PLL2); 1719 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1606 1720
1607 usleep_range(20, 100); 1721 usleep_range(20, 100);
1608 1722
1609 /* step 4 */ 1723 /* step 4 */
1610 value = tegra_sor_readl(sor, SOR_PLL0); 1724 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1611 value &= ~SOR_PLL0_VCOPD; 1725 value &= ~SOR_PLL0_VCOPD;
1612 value &= ~SOR_PLL0_PWR; 1726 value &= ~SOR_PLL0_PWR;
1613 tegra_sor_writel(sor, value, SOR_PLL0); 1727 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1614 1728
1615 value = tegra_sor_readl(sor, SOR_PLL2); 1729 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1616 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1730 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1617 tegra_sor_writel(sor, value, SOR_PLL2); 1731 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1618 1732
1619 usleep_range(200, 1000); 1733 usleep_range(200, 1000);
1620 1734
1621 /* step 5 */ 1735 /* step 5 */
1622 value = tegra_sor_readl(sor, SOR_PLL2); 1736 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1623 value &= ~SOR_PLL2_PORT_POWERDOWN; 1737 value &= ~SOR_PLL2_PORT_POWERDOWN;
1624 tegra_sor_writel(sor, value, SOR_PLL2); 1738 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1625 1739
1626 /* XXX not in TRM */ 1740 /* XXX not in TRM */
1627 for (value = 0, i = 0; i < 5; i++) 1741 for (value = 0, i = 0; i < 5; i++)
@@ -1637,7 +1751,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1637 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 1751 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1638 1752
1639 /* power DP lanes */ 1753 /* power DP lanes */
1640 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1754 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1641 1755
1642 if (link.num_lanes <= 2) 1756 if (link.num_lanes <= 2)
1643 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); 1757 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
@@ -1654,7 +1768,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1654 else 1768 else
1655 value |= SOR_DP_PADCTL_PD_TXD_0; 1769 value |= SOR_DP_PADCTL_PD_TXD_0;
1656 1770
1657 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1771 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1658 1772
1659 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1773 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1660 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1774 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
@@ -1698,9 +1812,9 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1698 tegra_sor_writel(sor, value, SOR_DP_TPG); 1812 tegra_sor_writel(sor, value, SOR_DP_TPG);
1699 1813
1700 /* enable pad calibration logic */ 1814 /* enable pad calibration logic */
1701 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1815 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1702 value |= SOR_DP_PADCTL_PAD_CAL_PD; 1816 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1703 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1817 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1704 1818
1705 err = drm_dp_link_probe(sor->aux, &link); 1819 err = drm_dp_link_probe(sor->aux, &link);
1706 if (err < 0) 1820 if (err < 0)
@@ -1773,7 +1887,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1773 tegra_sor_update(sor); 1887 tegra_sor_update(sor);
1774 1888
1775 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1889 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1776 value |= SOR_ENABLE; 1890 value |= SOR_ENABLE(0);
1777 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1891 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1778 1892
1779 tegra_dc_commit(dc); 1893 tegra_dc_commit(dc);
@@ -1805,6 +1919,18 @@ tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1805 1919
1806 info = &output->connector.display_info; 1920 info = &output->connector.display_info;
1807 1921
1922 /*
1923 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1924 * the pixel clock must be corrected accordingly.
1925 */
1926 if (pclk >= 340000000) {
1927 state->link_speed = 20;
1928 state->pclk = pclk / 2;
1929 } else {
1930 state->link_speed = 10;
1931 state->pclk = pclk;
1932 }
1933
1808 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 1934 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1809 pclk, 0); 1935 pclk, 0);
1810 if (err < 0) { 1936 if (err < 0) {
@@ -1955,6 +2081,81 @@ tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
1955 return NULL; 2081 return NULL;
1956} 2082}
1957 2083
2084static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2085{
2086 u32 value;
2087
2088 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2089 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2090 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2091 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2092}
2093
2094static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2095{
2096 struct i2c_adapter *ddc = sor->output.ddc;
2097
2098 drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2099 drm_scdc_set_scrambling(ddc, false);
2100
2101 tegra_sor_hdmi_disable_scrambling(sor);
2102}
2103
2104static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2105{
2106 if (sor->scdc_enabled) {
2107 cancel_delayed_work_sync(&sor->scdc);
2108 tegra_sor_hdmi_scdc_disable(sor);
2109 }
2110}
2111
2112static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2113{
2114 u32 value;
2115
2116 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2117 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2118 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2119 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2120}
2121
2122static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2123{
2124 struct i2c_adapter *ddc = sor->output.ddc;
2125
2126 drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2127 drm_scdc_set_scrambling(ddc, true);
2128
2129 tegra_sor_hdmi_enable_scrambling(sor);
2130}
2131
2132static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2133{
2134 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2135 struct i2c_adapter *ddc = sor->output.ddc;
2136
2137 if (!drm_scdc_get_scrambling_status(ddc)) {
2138 DRM_DEBUG_KMS("SCDC not scrambled\n");
2139 tegra_sor_hdmi_scdc_enable(sor);
2140 }
2141
2142 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2143}
2144
2145static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2146{
2147 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2148 struct drm_display_mode *mode;
2149
2150 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2151
2152 if (mode->clock >= 340000 && scdc->supported) {
2153 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2154 tegra_sor_hdmi_scdc_enable(sor);
2155 sor->scdc_enabled = true;
2156 }
2157}
2158
1958static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 2159static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1959{ 2160{
1960 struct tegra_output *output = encoder_to_output(encoder); 2161 struct tegra_output *output = encoder_to_output(encoder);
@@ -1963,6 +2164,8 @@ static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1963 u32 value; 2164 u32 value;
1964 int err; 2165 int err;
1965 2166
2167 tegra_sor_hdmi_scdc_stop(sor);
2168
1966 err = tegra_sor_detach(sor); 2169 err = tegra_sor_detach(sor);
1967 if (err < 0) 2170 if (err < 0)
1968 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2171 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
@@ -1972,8 +2175,12 @@ static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1972 2175
1973 /* disable display to SOR clock */ 2176 /* disable display to SOR clock */
1974 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2177 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1975 value &= ~SOR1_TIMING_CYA; 2178
1976 value &= ~SOR1_ENABLE; 2179 if (!sor->soc->has_nvdisplay)
2180 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2181 else
2182 value &= ~SOR_ENABLE(sor->index);
2183
1977 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2184 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1978 2185
1979 tegra_dc_commit(dc); 2186 tegra_dc_commit(dc);
@@ -1982,9 +2189,9 @@ static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1982 if (err < 0) 2189 if (err < 0)
1983 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2190 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1984 2191
1985 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI); 2192 err = tegra_io_pad_power_disable(sor->pad);
1986 if (err < 0) 2193 if (err < 0)
1987 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err); 2194 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1988 2195
1989 pm_runtime_put(sor->dev); 2196 pm_runtime_put(sor->dev);
1990} 2197}
@@ -1998,12 +2205,14 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
1998 struct tegra_sor *sor = to_sor(output); 2205 struct tegra_sor *sor = to_sor(output);
1999 struct tegra_sor_state *state; 2206 struct tegra_sor_state *state;
2000 struct drm_display_mode *mode; 2207 struct drm_display_mode *mode;
2208 unsigned long rate, pclk;
2001 unsigned int div, i; 2209 unsigned int div, i;
2002 u32 value; 2210 u32 value;
2003 int err; 2211 int err;
2004 2212
2005 state = to_sor_state(output->connector.state); 2213 state = to_sor_state(output->connector.state);
2006 mode = &encoder->crtc->state->adjusted_mode; 2214 mode = &encoder->crtc->state->adjusted_mode;
2215 pclk = mode->clock * 1000;
2007 2216
2008 pm_runtime_get_sync(sor->dev); 2217 pm_runtime_get_sync(sor->dev);
2009 2218
@@ -2016,44 +2225,44 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2016 2225
2017 div = clk_get_rate(sor->clk) / 1000000 * 4; 2226 div = clk_get_rate(sor->clk) / 1000000 * 4;
2018 2227
2019 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI); 2228 err = tegra_io_pad_power_enable(sor->pad);
2020 if (err < 0) 2229 if (err < 0)
2021 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err); 2230 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2022 2231
2023 usleep_range(20, 100); 2232 usleep_range(20, 100);
2024 2233
2025 value = tegra_sor_readl(sor, SOR_PLL2); 2234 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2026 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2235 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2027 tegra_sor_writel(sor, value, SOR_PLL2); 2236 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2028 2237
2029 usleep_range(20, 100); 2238 usleep_range(20, 100);
2030 2239
2031 value = tegra_sor_readl(sor, SOR_PLL3); 2240 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2032 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2241 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2033 tegra_sor_writel(sor, value, SOR_PLL3); 2242 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2034 2243
2035 value = tegra_sor_readl(sor, SOR_PLL0); 2244 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2036 value &= ~SOR_PLL0_VCOPD; 2245 value &= ~SOR_PLL0_VCOPD;
2037 value &= ~SOR_PLL0_PWR; 2246 value &= ~SOR_PLL0_PWR;
2038 tegra_sor_writel(sor, value, SOR_PLL0); 2247 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2039 2248
2040 value = tegra_sor_readl(sor, SOR_PLL2); 2249 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2041 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2250 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2042 tegra_sor_writel(sor, value, SOR_PLL2); 2251 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2043 2252
2044 usleep_range(200, 400); 2253 usleep_range(200, 400);
2045 2254
2046 value = tegra_sor_readl(sor, SOR_PLL2); 2255 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2047 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2256 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2048 value &= ~SOR_PLL2_PORT_POWERDOWN; 2257 value &= ~SOR_PLL2_PORT_POWERDOWN;
2049 tegra_sor_writel(sor, value, SOR_PLL2); 2258 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2050 2259
2051 usleep_range(20, 100); 2260 usleep_range(20, 100);
2052 2261
2053 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2262 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2054 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2263 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2055 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2264 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2056 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2265 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2057 2266
2058 while (true) { 2267 while (true) {
2059 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2268 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
@@ -2079,18 +2288,30 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2079 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2288 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2080 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2289 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2081 2290
2082 if (mode->clock < 340000) 2291 if (mode->clock < 340000) {
2292 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2083 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 2293 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2084 else 2294 } else {
2295 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2085 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 2296 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2297 }
2086 2298
2087 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2299 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2088 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2300 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2089 2301
2302 /* SOR pad PLL stabilization time */
2303 usleep_range(250, 1000);
2304
2305 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2306 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2307 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2308 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2309
2090 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2310 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2091 value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2311 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2092 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2312 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2093 value |= SOR_DP_SPARE_SEQ_ENABLE; 2313 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2314 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2094 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2315 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2095 2316
2096 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2317 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
@@ -2102,9 +2323,11 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2102 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2323 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2103 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2324 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2104 2325
2105 /* program the reference clock */ 2326 if (!sor->soc->has_nvdisplay) {
2106 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2327 /* program the reference clock */
2107 tegra_sor_writel(sor, value, SOR_REFCLK); 2328 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2329 tegra_sor_writel(sor, value, SOR_REFCLK);
2330 }
2108 2331
2109 /* XXX not in TRM */ 2332 /* XXX not in TRM */
2110 for (value = 0, i = 0; i < 5; i++) 2333 for (value = 0, i = 0; i < 5; i++)
@@ -2127,13 +2350,25 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2127 return; 2350 return;
2128 } 2351 }
2129 2352
2130 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2353 /* adjust clock rate for HDMI 2.0 modes */
2354 rate = clk_get_rate(sor->clk_parent);
2355
2356 if (mode->clock >= 340000)
2357 rate /= 2;
2131 2358
2132 /* XXX is this the proper check? */ 2359 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2133 if (mode->clock < 75000)
2134 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2135 2360
2136 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2361 clk_set_rate(sor->clk, rate);
2362
2363 if (!sor->soc->has_nvdisplay) {
2364 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2365
2366 /* XXX is this the proper check? */
2367 if (mode->clock < 75000)
2368 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2369
2370 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2371 }
2137 2372
2138 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2373 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2139 2374
@@ -2141,20 +2376,23 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2141 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2376 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2142 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2377 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2143 2378
2144 /* H_PULSE2 setup */ 2379 if (!dc->soc->has_nvdisplay) {
2145 pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) + 2380 /* H_PULSE2 setup */
2146 (mode->htotal - mode->hsync_end) - 10; 2381 pulse_start = h_ref_to_sync +
2382 (mode->hsync_end - mode->hsync_start) +
2383 (mode->htotal - mode->hsync_end) - 10;
2147 2384
2148 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2385 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2149 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2386 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2150 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2387 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2151 2388
2152 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2389 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2153 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2390 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2154 2391
2155 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2392 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2156 value |= H_PULSE2_ENABLE; 2393 value |= H_PULSE2_ENABLE;
2157 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2394 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2395 }
2158 2396
2159 /* infoframe setup */ 2397 /* infoframe setup */
2160 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2398 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
@@ -2171,9 +2409,9 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2171 tegra_sor_writel(sor, value, SOR_STATE1); 2409 tegra_sor_writel(sor, value, SOR_STATE1);
2172 2410
2173 /* power up pad calibration */ 2411 /* power up pad calibration */
2174 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2412 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2175 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2413 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2176 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2414 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2177 2415
2178 /* production settings */ 2416 /* production settings */
2179 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2417 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
@@ -2183,51 +2421,68 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2183 return; 2421 return;
2184 } 2422 }
2185 2423
2186 value = tegra_sor_readl(sor, SOR_PLL0); 2424 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2187 value &= ~SOR_PLL0_ICHPMP_MASK; 2425 value &= ~SOR_PLL0_ICHPMP_MASK;
2426 value &= ~SOR_PLL0_FILTER_MASK;
2188 value &= ~SOR_PLL0_VCOCAP_MASK; 2427 value &= ~SOR_PLL0_VCOCAP_MASK;
2189 value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2428 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2429 value |= SOR_PLL0_FILTER(settings->filter);
2190 value |= SOR_PLL0_VCOCAP(settings->vcocap); 2430 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2191 tegra_sor_writel(sor, value, SOR_PLL0); 2431 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2192
2193 tegra_sor_dp_term_calibrate(sor);
2194 2432
2195 value = tegra_sor_readl(sor, SOR_PLL1); 2433 /* XXX not in TRM */
2434 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2196 value &= ~SOR_PLL1_LOADADJ_MASK; 2435 value &= ~SOR_PLL1_LOADADJ_MASK;
2436 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2197 value |= SOR_PLL1_LOADADJ(settings->loadadj); 2437 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2198 tegra_sor_writel(sor, value, SOR_PLL1); 2438 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2439 value |= SOR_PLL1_TMDS_TERM;
2440 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2199 2441
2200 value = tegra_sor_readl(sor, SOR_PLL3); 2442 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2443 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2201 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2444 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2202 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref); 2445 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2203 tegra_sor_writel(sor, value, SOR_PLL3); 2446 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2204 2447 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2205 value = settings->drive_current[0] << 24 | 2448 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2206 settings->drive_current[1] << 16 | 2449 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2207 settings->drive_current[2] << 8 | 2450 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2208 settings->drive_current[3] << 0; 2451 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2452
2453 value = settings->drive_current[3] << 24 |
2454 settings->drive_current[2] << 16 |
2455 settings->drive_current[1] << 8 |
2456 settings->drive_current[0] << 0;
2209 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2457 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2210 2458
2211 value = settings->preemphasis[0] << 24 | 2459 value = settings->preemphasis[3] << 24 |
2212 settings->preemphasis[1] << 16 | 2460 settings->preemphasis[2] << 16 |
2213 settings->preemphasis[2] << 8 | 2461 settings->preemphasis[1] << 8 |
2214 settings->preemphasis[3] << 0; 2462 settings->preemphasis[0] << 0;
2215 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2463 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2216 2464
2217 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2465 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2218 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2466 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2219 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2467 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2220 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu); 2468 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2221 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2469 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2470
2471 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2472 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2473 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2474 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2222 2475
2223 /* power down pad calibration */ 2476 /* power down pad calibration */
2224 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2477 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2225 value |= SOR_DP_PADCTL_PAD_CAL_PD; 2478 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2226 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2479 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2227 2480
2228 /* miscellaneous display controller settings */ 2481 if (!dc->soc->has_nvdisplay) {
2229 value = VSYNC_H_POSITION(1); 2482 /* miscellaneous display controller settings */
2230 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2483 value = VSYNC_H_POSITION(1);
2484 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2485 }
2231 2486
2232 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2487 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2233 value &= ~DITHER_CONTROL_MASK; 2488 value &= ~DITHER_CONTROL_MASK;
@@ -2242,6 +2497,14 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2242 value |= BASE_COLOR_SIZE_888; 2497 value |= BASE_COLOR_SIZE_888;
2243 break; 2498 break;
2244 2499
2500 case 10:
2501 value |= BASE_COLOR_SIZE_101010;
2502 break;
2503
2504 case 12:
2505 value |= BASE_COLOR_SIZE_121212;
2506 break;
2507
2245 default: 2508 default:
2246 WARN(1, "%u bits-per-color not supported\n", state->bpc); 2509 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2247 value |= BASE_COLOR_SIZE_888; 2510 value |= BASE_COLOR_SIZE_888;
@@ -2250,40 +2513,65 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2250 2513
2251 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2514 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2252 2515
2516 /* XXX set display head owner */
2517 value = tegra_sor_readl(sor, SOR_STATE1);
2518 value &= ~SOR_STATE_ASY_OWNER_MASK;
2519 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2520 tegra_sor_writel(sor, value, SOR_STATE1);
2521
2253 err = tegra_sor_power_up(sor, 250); 2522 err = tegra_sor_power_up(sor, 250);
2254 if (err < 0) 2523 if (err < 0)
2255 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2524 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2256 2525
2257 /* configure dynamic range of output */ 2526 /* configure dynamic range of output */
2258 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); 2527 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2259 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2528 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2260 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2529 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2261 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); 2530 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2262 2531
2263 /* configure colorspace */ 2532 /* configure colorspace */
2264 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); 2533 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2265 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2534 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2266 value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2535 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2267 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); 2536 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2268 2537
2269 tegra_sor_mode_set(sor, mode, state); 2538 tegra_sor_mode_set(sor, mode, state);
2270 2539
2271 tegra_sor_update(sor); 2540 tegra_sor_update(sor);
2272 2541
2542 /* program preamble timing in SOR (XXX) */
2543 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2544 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2545 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2546
2273 err = tegra_sor_attach(sor); 2547 err = tegra_sor_attach(sor);
2274 if (err < 0) 2548 if (err < 0)
2275 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2549 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2276 2550
2277 /* enable display to SOR clock and generate HDMI preamble */ 2551 /* enable display to SOR clock and generate HDMI preamble */
2278 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2552 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2279 value |= SOR1_ENABLE | SOR1_TIMING_CYA; 2553
2554 if (!sor->soc->has_nvdisplay)
2555 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2556 else
2557 value |= SOR_ENABLE(sor->index);
2558
2280 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2559 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2281 2560
2561 if (dc->soc->has_nvdisplay) {
2562 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2563 value &= ~PROTOCOL_MASK;
2564 value |= PROTOCOL_SINGLE_TMDS_A;
2565 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2566 }
2567
2282 tegra_dc_commit(dc); 2568 tegra_dc_commit(dc);
2283 2569
2284 err = tegra_sor_wakeup(sor); 2570 err = tegra_sor_wakeup(sor);
2285 if (err < 0) 2571 if (err < 0)
2286 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2572 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2573
2574 tegra_sor_hdmi_scdc_start(sor);
2287} 2575}
2288 2576
2289static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2577static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
@@ -2344,13 +2632,7 @@ static int tegra_sor_init(struct host1x_client *client)
2344 return err; 2632 return err;
2345 } 2633 }
2346 2634
2347 sor->output.encoder.possible_crtcs = 0x3; 2635 tegra_output_find_possible_crtcs(&sor->output, drm);
2348
2349 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2350 err = tegra_sor_debugfs_init(sor, drm->primary);
2351 if (err < 0)
2352 dev_err(sor->dev, "debugfs setup failed: %d\n", err);
2353 }
2354 2636
2355 if (sor->aux) { 2637 if (sor->aux) {
2356 err = drm_dp_aux_attach(sor->aux, &sor->output); 2638 err = drm_dp_aux_attach(sor->aux, &sor->output);
@@ -2420,9 +2702,6 @@ static int tegra_sor_exit(struct host1x_client *client)
2420 clk_disable_unprepare(sor->clk_dp); 2702 clk_disable_unprepare(sor->clk_dp);
2421 clk_disable_unprepare(sor->clk); 2703 clk_disable_unprepare(sor->clk);
2422 2704
2423 if (IS_ENABLED(CONFIG_DEBUG_FS))
2424 tegra_sor_debugfs_exit(sor);
2425
2426 return 0; 2705 return 0;
2427} 2706}
2428 2707
@@ -2480,6 +2759,8 @@ static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2480 return err; 2759 return err;
2481 } 2760 }
2482 2761
2762 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
2763
2483 return 0; 2764 return 0;
2484} 2765}
2485 2766
@@ -2502,19 +2783,53 @@ static const u8 tegra124_sor_xbar_cfg[5] = {
2502 0, 1, 2, 3, 4 2783 0, 1, 2, 3, 4
2503}; 2784};
2504 2785
2786static const struct tegra_sor_regs tegra124_sor_regs = {
2787 .head_state0 = 0x05,
2788 .head_state1 = 0x07,
2789 .head_state2 = 0x09,
2790 .head_state3 = 0x0b,
2791 .head_state4 = 0x0d,
2792 .head_state5 = 0x0f,
2793 .pll0 = 0x17,
2794 .pll1 = 0x18,
2795 .pll2 = 0x19,
2796 .pll3 = 0x1a,
2797 .dp_padctl0 = 0x5c,
2798 .dp_padctl2 = 0x73,
2799};
2800
2505static const struct tegra_sor_soc tegra124_sor = { 2801static const struct tegra_sor_soc tegra124_sor = {
2506 .supports_edp = true, 2802 .supports_edp = true,
2507 .supports_lvds = true, 2803 .supports_lvds = true,
2508 .supports_hdmi = false, 2804 .supports_hdmi = false,
2509 .supports_dp = false, 2805 .supports_dp = false,
2806 .regs = &tegra124_sor_regs,
2807 .has_nvdisplay = false,
2510 .xbar_cfg = tegra124_sor_xbar_cfg, 2808 .xbar_cfg = tegra124_sor_xbar_cfg,
2511}; 2809};
2512 2810
2811static const struct tegra_sor_regs tegra210_sor_regs = {
2812 .head_state0 = 0x05,
2813 .head_state1 = 0x07,
2814 .head_state2 = 0x09,
2815 .head_state3 = 0x0b,
2816 .head_state4 = 0x0d,
2817 .head_state5 = 0x0f,
2818 .pll0 = 0x17,
2819 .pll1 = 0x18,
2820 .pll2 = 0x19,
2821 .pll3 = 0x1a,
2822 .dp_padctl0 = 0x5c,
2823 .dp_padctl2 = 0x73,
2824};
2825
2513static const struct tegra_sor_soc tegra210_sor = { 2826static const struct tegra_sor_soc tegra210_sor = {
2514 .supports_edp = true, 2827 .supports_edp = true,
2515 .supports_lvds = false, 2828 .supports_lvds = false,
2516 .supports_hdmi = false, 2829 .supports_hdmi = false,
2517 .supports_dp = false, 2830 .supports_dp = false,
2831 .regs = &tegra210_sor_regs,
2832 .has_nvdisplay = false,
2518 .xbar_cfg = tegra124_sor_xbar_cfg, 2833 .xbar_cfg = tegra124_sor_xbar_cfg,
2519}; 2834};
2520 2835
@@ -2528,13 +2843,60 @@ static const struct tegra_sor_soc tegra210_sor1 = {
2528 .supports_hdmi = true, 2843 .supports_hdmi = true,
2529 .supports_dp = true, 2844 .supports_dp = true,
2530 2845
2846 .regs = &tegra210_sor_regs,
2847 .has_nvdisplay = false,
2848
2531 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 2849 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
2532 .settings = tegra210_sor_hdmi_defaults, 2850 .settings = tegra210_sor_hdmi_defaults,
2533 2851
2534 .xbar_cfg = tegra210_sor_xbar_cfg, 2852 .xbar_cfg = tegra210_sor_xbar_cfg,
2535}; 2853};
2536 2854
2855static const struct tegra_sor_regs tegra186_sor_regs = {
2856 .head_state0 = 0x151,
2857 .head_state1 = 0x154,
2858 .head_state2 = 0x157,
2859 .head_state3 = 0x15a,
2860 .head_state4 = 0x15d,
2861 .head_state5 = 0x160,
2862 .pll0 = 0x163,
2863 .pll1 = 0x164,
2864 .pll2 = 0x165,
2865 .pll3 = 0x166,
2866 .dp_padctl0 = 0x168,
2867 .dp_padctl2 = 0x16a,
2868};
2869
2870static const struct tegra_sor_soc tegra186_sor = {
2871 .supports_edp = false,
2872 .supports_lvds = false,
2873 .supports_hdmi = false,
2874 .supports_dp = true,
2875
2876 .regs = &tegra186_sor_regs,
2877 .has_nvdisplay = true,
2878
2879 .xbar_cfg = tegra124_sor_xbar_cfg,
2880};
2881
2882static const struct tegra_sor_soc tegra186_sor1 = {
2883 .supports_edp = false,
2884 .supports_lvds = false,
2885 .supports_hdmi = true,
2886 .supports_dp = true,
2887
2888 .regs = &tegra186_sor_regs,
2889 .has_nvdisplay = true,
2890
2891 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
2892 .settings = tegra186_sor_hdmi_defaults,
2893
2894 .xbar_cfg = tegra124_sor_xbar_cfg,
2895};
2896
2537static const struct of_device_id tegra_sor_of_match[] = { 2897static const struct of_device_id tegra_sor_of_match[] = {
2898 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
2899 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
2538 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 2900 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
2539 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 2901 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
2540 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 2902 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
@@ -2542,6 +2904,29 @@ static const struct of_device_id tegra_sor_of_match[] = {
2542}; 2904};
2543MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 2905MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
2544 2906
2907static int tegra_sor_parse_dt(struct tegra_sor *sor)
2908{
2909 struct device_node *np = sor->dev->of_node;
2910 u32 value;
2911 int err;
2912
2913 if (sor->soc->has_nvdisplay) {
2914 err = of_property_read_u32(np, "nvidia,interface", &value);
2915 if (err < 0)
2916 return err;
2917
2918 sor->index = value;
2919
2920 /*
2921 * override the default that we already set for Tegra210 and
2922 * earlier
2923 */
2924 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
2925 }
2926
2927 return 0;
2928}
2929
2545static int tegra_sor_probe(struct platform_device *pdev) 2930static int tegra_sor_probe(struct platform_device *pdev)
2546{ 2931{
2547 struct device_node *np; 2932 struct device_node *np;
@@ -2577,6 +2962,7 @@ static int tegra_sor_probe(struct platform_device *pdev)
2577 if (!sor->aux) { 2962 if (!sor->aux) {
2578 if (sor->soc->supports_hdmi) { 2963 if (sor->soc->supports_hdmi) {
2579 sor->ops = &tegra_sor_hdmi_ops; 2964 sor->ops = &tegra_sor_hdmi_ops;
2965 sor->pad = TEGRA_IO_PAD_HDMI;
2580 } else if (sor->soc->supports_lvds) { 2966 } else if (sor->soc->supports_lvds) {
2581 dev_err(&pdev->dev, "LVDS not supported yet\n"); 2967 dev_err(&pdev->dev, "LVDS not supported yet\n");
2582 return -ENODEV; 2968 return -ENODEV;
@@ -2587,6 +2973,7 @@ static int tegra_sor_probe(struct platform_device *pdev)
2587 } else { 2973 } else {
2588 if (sor->soc->supports_edp) { 2974 if (sor->soc->supports_edp) {
2589 sor->ops = &tegra_sor_edp_ops; 2975 sor->ops = &tegra_sor_edp_ops;
2976 sor->pad = TEGRA_IO_PAD_LVDS;
2590 } else if (sor->soc->supports_dp) { 2977 } else if (sor->soc->supports_dp) {
2591 dev_err(&pdev->dev, "DisplayPort not supported yet\n"); 2978 dev_err(&pdev->dev, "DisplayPort not supported yet\n");
2592 return -ENODEV; 2979 return -ENODEV;
@@ -2596,6 +2983,10 @@ static int tegra_sor_probe(struct platform_device *pdev)
2596 } 2983 }
2597 } 2984 }
2598 2985
2986 err = tegra_sor_parse_dt(sor);
2987 if (err < 0)
2988 return err;
2989
2599 err = tegra_output_probe(&sor->output); 2990 err = tegra_output_probe(&sor->output);
2600 if (err < 0) { 2991 if (err < 0) {
2601 dev_err(&pdev->dev, "failed to probe output: %d\n", err); 2992 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
@@ -2656,6 +3047,8 @@ static int tegra_sor_probe(struct platform_device *pdev)
2656 name, err); 3047 name, err);
2657 goto remove; 3048 goto remove;
2658 } 3049 }
3050 } else {
3051 sor->clk_out = sor->clk;
2659 } 3052 }
2660 3053
2661 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 3054 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
diff --git a/drivers/gpu/drm/tegra/sor.h b/drivers/gpu/drm/tegra/sor.h
index 865c73b48968..fb0854d92a27 100644
--- a/drivers/gpu/drm/tegra/sor.h
+++ b/drivers/gpu/drm/tegra/sor.h
@@ -89,6 +89,8 @@
89#define SOR_PLL0 0x17 89#define SOR_PLL0 0x17
90#define SOR_PLL0_ICHPMP_MASK (0xf << 24) 90#define SOR_PLL0_ICHPMP_MASK (0xf << 24)
91#define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24) 91#define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24)
92#define SOR_PLL0_FILTER_MASK (0xf << 16)
93#define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16)
92#define SOR_PLL0_VCOCAP_MASK (0xf << 8) 94#define SOR_PLL0_VCOCAP_MASK (0xf << 8)
93#define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8) 95#define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8)
94#define SOR_PLL0_VCOCAP_RST SOR_PLL0_VCOCAP(3) 96#define SOR_PLL0_VCOCAP_RST SOR_PLL0_VCOCAP(3)
@@ -122,10 +124,16 @@
122#define SOR_PLL2_SEQ_PLL_PULLDOWN (1 << 16) 124#define SOR_PLL2_SEQ_PLL_PULLDOWN (1 << 16)
123 125
124#define SOR_PLL3 0x1a 126#define SOR_PLL3 0x1a
127#define SOR_PLL3_BG_TEMP_COEF_MASK (0xf << 28)
128#define SOR_PLL3_BG_TEMP_COEF(x) (((x) & 0xf) << 28)
125#define SOR_PLL3_BG_VREF_LEVEL_MASK (0xf << 24) 129#define SOR_PLL3_BG_VREF_LEVEL_MASK (0xf << 24)
126#define SOR_PLL3_BG_VREF_LEVEL(x) (((x) & 0xf) << 24) 130#define SOR_PLL3_BG_VREF_LEVEL(x) (((x) & 0xf) << 24)
127#define SOR_PLL3_PLL_VDD_MODE_1V8 (0 << 13) 131#define SOR_PLL3_PLL_VDD_MODE_1V8 (0 << 13)
128#define SOR_PLL3_PLL_VDD_MODE_3V3 (1 << 13) 132#define SOR_PLL3_PLL_VDD_MODE_3V3 (1 << 13)
133#define SOR_PLL3_AVDD10_LEVEL_MASK (0xf << 8)
134#define SOR_PLL3_AVDD10_LEVEL(x) (((x) & 0xf) << 8)
135#define SOR_PLL3_AVDD14_LEVEL_MASK (0xf << 4)
136#define SOR_PLL3_AVDD14_LEVEL(x) (((x) & 0xf) << 4)
129 137
130#define SOR_CSTM 0x1b 138#define SOR_CSTM 0x1b
131#define SOR_CSTM_ROTCLK_MASK (0xf << 24) 139#define SOR_CSTM_ROTCLK_MASK (0xf << 24)
@@ -334,6 +342,10 @@
334#define SOR_DP_LQ_CSTM1 0x70 342#define SOR_DP_LQ_CSTM1 0x70
335#define SOR_DP_LQ_CSTM2 0x71 343#define SOR_DP_LQ_CSTM2 0x71
336 344
345#define SOR_DP_PADCTL2 0x73
346#define SOR_DP_PADCTL_SPAREPLL_MASK (0xff << 24)
347#define SOR_DP_PADCTL_SPAREPLL(x) (((x) & 0xff) << 24)
348
337#define SOR_HDMI_AUDIO_INFOFRAME_CTRL 0x9a 349#define SOR_HDMI_AUDIO_INFOFRAME_CTRL 0x9a
338#define SOR_HDMI_AUDIO_INFOFRAME_STATUS 0x9b 350#define SOR_HDMI_AUDIO_INFOFRAME_STATUS 0x9b
339#define SOR_HDMI_AUDIO_INFOFRAME_HEADER 0x9c 351#define SOR_HDMI_AUDIO_INFOFRAME_HEADER 0x9c
@@ -370,4 +382,8 @@
370#define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124 382#define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124
371#define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125 383#define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125
372 384
385#define SOR_HDMI2_CTRL 0x13e
386#define SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 (1 << 1)
387#define SOR_HDMI2_CTRL_SCRAMBLE (1 << 0)
388
373#endif 389#endif
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index 18024183aa2b..f5794dd49f3b 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -115,7 +115,7 @@ static int vic_boot(struct vic *vic)
115} 115}
116 116
117static void *vic_falcon_alloc(struct falcon *falcon, size_t size, 117static void *vic_falcon_alloc(struct falcon *falcon, size_t size,
118 dma_addr_t *iova) 118 dma_addr_t *iova)
119{ 119{
120 struct tegra_drm *tegra = falcon->data; 120 struct tegra_drm *tegra = falcon->data;
121 121
@@ -138,13 +138,14 @@ static const struct falcon_ops vic_falcon_ops = {
138static int vic_init(struct host1x_client *client) 138static int vic_init(struct host1x_client *client)
139{ 139{
140 struct tegra_drm_client *drm = host1x_to_drm_client(client); 140 struct tegra_drm_client *drm = host1x_to_drm_client(client);
141 struct iommu_group *group = iommu_group_get(client->dev);
141 struct drm_device *dev = dev_get_drvdata(client->parent); 142 struct drm_device *dev = dev_get_drvdata(client->parent);
142 struct tegra_drm *tegra = dev->dev_private; 143 struct tegra_drm *tegra = dev->dev_private;
143 struct vic *vic = to_vic(drm); 144 struct vic *vic = to_vic(drm);
144 int err; 145 int err;
145 146
146 if (tegra->domain) { 147 if (group && tegra->domain) {
147 err = iommu_attach_device(tegra->domain, vic->dev); 148 err = iommu_attach_group(tegra->domain, group);
148 if (err < 0) { 149 if (err < 0) {
149 dev_err(vic->dev, "failed to attach to domain: %d\n", 150 dev_err(vic->dev, "failed to attach to domain: %d\n",
150 err); 151 err);
@@ -158,13 +159,13 @@ static int vic_init(struct host1x_client *client)
158 vic->falcon.data = tegra; 159 vic->falcon.data = tegra;
159 err = falcon_load_firmware(&vic->falcon); 160 err = falcon_load_firmware(&vic->falcon);
160 if (err < 0) 161 if (err < 0)
161 goto detach_device; 162 goto detach;
162 } 163 }
163 164
164 vic->channel = host1x_channel_request(client->dev); 165 vic->channel = host1x_channel_request(client->dev);
165 if (!vic->channel) { 166 if (!vic->channel) {
166 err = -ENOMEM; 167 err = -ENOMEM;
167 goto detach_device; 168 goto detach;
168 } 169 }
169 170
170 client->syncpts[0] = host1x_syncpt_request(client, 0); 171 client->syncpts[0] = host1x_syncpt_request(client, 0);
@@ -183,9 +184,9 @@ free_syncpt:
183 host1x_syncpt_free(client->syncpts[0]); 184 host1x_syncpt_free(client->syncpts[0]);
184free_channel: 185free_channel:
185 host1x_channel_put(vic->channel); 186 host1x_channel_put(vic->channel);
186detach_device: 187detach:
187 if (tegra->domain) 188 if (group && tegra->domain)
188 iommu_detach_device(tegra->domain, vic->dev); 189 iommu_detach_group(tegra->domain, group);
189 190
190 return err; 191 return err;
191} 192}
@@ -193,6 +194,7 @@ detach_device:
193static int vic_exit(struct host1x_client *client) 194static int vic_exit(struct host1x_client *client)
194{ 195{
195 struct tegra_drm_client *drm = host1x_to_drm_client(client); 196 struct tegra_drm_client *drm = host1x_to_drm_client(client);
197 struct iommu_group *group = iommu_group_get(client->dev);
196 struct drm_device *dev = dev_get_drvdata(client->parent); 198 struct drm_device *dev = dev_get_drvdata(client->parent);
197 struct tegra_drm *tegra = dev->dev_private; 199 struct tegra_drm *tegra = dev->dev_private;
198 struct vic *vic = to_vic(drm); 200 struct vic *vic = to_vic(drm);
@@ -206,7 +208,7 @@ static int vic_exit(struct host1x_client *client)
206 host1x_channel_put(vic->channel); 208 host1x_channel_put(vic->channel);
207 209
208 if (vic->domain) { 210 if (vic->domain) {
209 iommu_detach_device(vic->domain, vic->dev); 211 iommu_detach_group(vic->domain, group);
210 vic->domain = NULL; 212 vic->domain = NULL;
211 } 213 }
212 214
diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c
index 2e57c9cea696..88a3558b7916 100644
--- a/drivers/gpu/host1x/bus.c
+++ b/drivers/gpu/host1x/bus.c
@@ -211,8 +211,7 @@ int host1x_device_init(struct host1x_device *device)
211 dev_err(&device->dev, 211 dev_err(&device->dev,
212 "failed to initialize %s: %d\n", 212 "failed to initialize %s: %d\n",
213 dev_name(client->dev), err); 213 dev_name(client->dev), err);
214 mutex_unlock(&device->clients_lock); 214 goto teardown;
215 return err;
216 } 215 }
217 } 216 }
218 } 217 }
@@ -220,6 +219,14 @@ int host1x_device_init(struct host1x_device *device)
220 mutex_unlock(&device->clients_lock); 219 mutex_unlock(&device->clients_lock);
221 220
222 return 0; 221 return 0;
222
223teardown:
224 list_for_each_entry_continue_reverse(client, &device->clients, list)
225 if (client->ops->exit)
226 client->ops->exit(client);
227
228 mutex_unlock(&device->clients_lock);
229 return err;
223} 230}
224EXPORT_SYMBOL(host1x_device_init); 231EXPORT_SYMBOL(host1x_device_init);
225 232
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index bf67c3aeb634..03db71173f5d 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -218,20 +218,27 @@ static int host1x_probe(struct platform_device *pdev)
218 return err; 218 return err;
219 } 219 }
220 220
221 if (iommu_present(&platform_bus_type)) { 221 host->group = iommu_group_get(&pdev->dev);
222 if (host->group) {
222 struct iommu_domain_geometry *geometry; 223 struct iommu_domain_geometry *geometry;
223 unsigned long order; 224 unsigned long order;
224 225
225 host->domain = iommu_domain_alloc(&platform_bus_type); 226 host->domain = iommu_domain_alloc(&platform_bus_type);
226 if (!host->domain) 227 if (!host->domain) {
227 return -ENOMEM; 228 err = -ENOMEM;
228 229 goto put_group;
229 err = iommu_attach_device(host->domain, &pdev->dev); 230 }
230 if (err == -ENODEV) { 231
231 iommu_domain_free(host->domain); 232 err = iommu_attach_group(host->domain, host->group);
232 host->domain = NULL; 233 if (err) {
233 goto skip_iommu; 234 if (err == -ENODEV) {
234 } else if (err) { 235 iommu_domain_free(host->domain);
236 host->domain = NULL;
237 iommu_group_put(host->group);
238 host->group = NULL;
239 goto skip_iommu;
240 }
241
235 goto fail_free_domain; 242 goto fail_free_domain;
236 } 243 }
237 244
@@ -294,13 +301,15 @@ fail_unprepare_disable:
294fail_free_channels: 301fail_free_channels:
295 host1x_channel_list_free(&host->channel_list); 302 host1x_channel_list_free(&host->channel_list);
296fail_detach_device: 303fail_detach_device:
297 if (host->domain) { 304 if (host->group && host->domain) {
298 put_iova_domain(&host->iova); 305 put_iova_domain(&host->iova);
299 iommu_detach_device(host->domain, &pdev->dev); 306 iommu_detach_group(host->domain, host->group);
300 } 307 }
301fail_free_domain: 308fail_free_domain:
302 if (host->domain) 309 if (host->domain)
303 iommu_domain_free(host->domain); 310 iommu_domain_free(host->domain);
311put_group:
312 iommu_group_put(host->group);
304 313
305 return err; 314 return err;
306} 315}
@@ -317,8 +326,9 @@ static int host1x_remove(struct platform_device *pdev)
317 326
318 if (host->domain) { 327 if (host->domain) {
319 put_iova_domain(&host->iova); 328 put_iova_domain(&host->iova);
320 iommu_detach_device(host->domain, &pdev->dev); 329 iommu_detach_group(host->domain, host->group);
321 iommu_domain_free(host->domain); 330 iommu_domain_free(host->domain);
331 iommu_group_put(host->group);
322 } 332 }
323 333
324 return 0; 334 return 0;
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h
index 502769726480..43e9fabb43a1 100644
--- a/drivers/gpu/host1x/dev.h
+++ b/drivers/gpu/host1x/dev.h
@@ -117,6 +117,7 @@ struct host1x {
117 struct clk *clk; 117 struct clk *clk;
118 struct reset_control *rst; 118 struct reset_control *rst;
119 119
120 struct iommu_group *group;
120 struct iommu_domain *domain; 121 struct iommu_domain *domain;
121 struct iova_domain iova; 122 struct iova_domain iova;
122 dma_addr_t iova_end; 123 dma_addr_t iova_end;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3ad838d3f93f..e04613d30a13 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -178,7 +178,7 @@ extern "C" {
178#define DRM_FORMAT_MOD_VENDOR_NONE 0 178#define DRM_FORMAT_MOD_VENDOR_NONE 0
179#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 179#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
180#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 180#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
181#define DRM_FORMAT_MOD_VENDOR_NV 0x03 181#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
182#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 182#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
183#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 183#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
184#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 184#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
@@ -188,7 +188,7 @@ extern "C" {
188#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 188#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
189 189
190#define fourcc_mod_code(vendor, val) \ 190#define fourcc_mod_code(vendor, val) \
191 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) 191 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
192 192
193/* 193/*
194 * Format Modifier tokens: 194 * Format Modifier tokens:
@@ -338,29 +338,17 @@ extern "C" {
338 */ 338 */
339#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 339#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
340 340
341/* NVIDIA Tegra frame buffer modifiers */ 341/* NVIDIA frame buffer modifiers */
342
343/*
344 * Some modifiers take parameters, for example the number of vertical GOBs in
345 * a block. Reserve the lower 32 bits for parameters
346 */
347#define __fourcc_mod_tegra_mode_shift 32
348#define fourcc_mod_tegra_code(val, params) \
349 fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
350#define fourcc_mod_tegra_mod(m) \
351 (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
352#define fourcc_mod_tegra_param(m) \
353 (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
354 342
355/* 343/*
356 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 344 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
357 * 345 *
358 * Pixels are arranged in simple tiles of 16 x 16 bytes. 346 * Pixels are arranged in simple tiles of 16 x 16 bytes.
359 */ 347 */
360#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) 348#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
361 349
362/* 350/*
363 * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 351 * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
364 * 352 *
365 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 353 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
366 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 354 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
@@ -380,7 +368,21 @@ extern "C" {
380 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 368 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
381 * in full detail. 369 * in full detail.
382 */ 370 */
383#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) 371#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
372 fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
373
374#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
375 fourcc_mod_code(NVIDIA, 0x10)
376#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
377 fourcc_mod_code(NVIDIA, 0x11)
378#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
379 fourcc_mod_code(NVIDIA, 0x12)
380#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
381 fourcc_mod_code(NVIDIA, 0x13)
382#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
383 fourcc_mod_code(NVIDIA, 0x14)
384#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
385 fourcc_mod_code(NVIDIA, 0x15)
384 386
385/* 387/*
386 * Broadcom VC4 "T" format 388 * Broadcom VC4 "T" format
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 17:48:17 -0400