ARM: tegra: Enable the DFLL on the Jetson TK1

Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

1 files changed, 8 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index bd43ed6d6ec7..192111ac00b3 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1462,7 +1462,7 @@
                                 vin-ldo9-10-supply = <&vdd_5v0_sys>;
                                 vin-ldo11-supply = <&vdd_3v3_run>;
 
-                                sd0 {
+                                vdd_cpu: sd0 {
                                         regulator-name = "+VDD_CPU_AP";
                                         regulator-min-microvolt = <700000>;
                                         regulator-max-microvolt = <1400000>;
@@ -1694,6 +1694,13 @@
                 non-removable;
         };
 
+        /* CPU DFLL clock */
+        clock@0,70110000 {
+                status = "okay";
+                vdd-cpu-supply = <&vdd_cpu>;
+                nvidia,i2c-fs-rate = <400000>;
+        };
+
         ahub@0,70300000 {
                 i2s@0,70301100 {
                         status = "okay";