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authorDave Airlie <airlied@redhat.com>2017-09-27 17:12:44 -0400
committerDave Airlie <airlied@redhat.com>2017-09-27 17:12:44 -0400
commit9afafdbfbf5e8fca4dabd817939b61f1e766e64c (patch)
treebd888d5f06a260d1b31453dce4d502435ca48763
parent29baa82aa55f40d67cfc8138c944fd8880c27e8e (diff)
parentbb9d2d050503c69695557b8b741276686ca2a396 (diff)
Merge tag 'drm-intel-next-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel into drm-next
Getting started with v4.15 features: - Cannonlake workarounds (Rodrigo, Oscar) - Infoframe refactoring and fixes to enable infoframes for DP (Ville) - VBT definition updates (Jani) - Sparse warning fixes (Ville, Chris) - Crtc state usage fixes and cleanups (Ville) - DP vswing, pre-emph and buffer translation refactoring and fixes (Rodrigo) - Prevent IPS from interfering with CRC capture (Ville, Marta) - Enable Mesa to advertise ARB_timer_query (Nanley) - Refactor GT number into intel_device_info (Lionel) - Avoid eDP DP AUX CH timeouts harder (Manasi) - CDCLK check improvements (Ville) - Restore GPU clock boost on missed pageflip vblanks (Chris) - Fence register reservation API for vGPU (Changbin) - First batch of CCS fixes (Ville) - Finally, numerous GEM fixes, cleanups and improvements (Chris) * tag 'drm-intel-next-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel: (100 commits) drm/i915: Update DRIVER_DATE to 20170907 drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) drm/i915: Lift has-pinned-pages assert to caller of ____i915_gem_object_get_pages drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register drm/i915: Move device_info.has_snoop into the static tables drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm drm/i915: Re-enable GTT following a device reset drm/i915/cnp: Wa 1181: Fix Backlight issue drm/i915: Annotate user relocs with __user drm/i915: Constify load detect mode drm/i915/perf: Remove __user from u64 in drm_i915_perf_oa_config drm/i915: Silence sparse by using gfp_t drm/i915: io unmap functions want __iomem drm/i915: Add __rcu to radix tree slot pointer drm/i915: Wake up the device for the fbdev setup drm/i915: Add interface to reserve fence registers for vGPU drm/i915: Use correct path to trace include drm/i915: Fix the missing PPAT cache attributes on CNL drm/i915: Fix enum pipe vs. enum transcoder for the PCH transcoder ...
Diffstat
-rw-r--r--drivers/gpu/drm/i915/Makefile2
-rw-r--r--drivers/gpu/drm/i915/gvt/aperture_gm.c26
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c3
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h63
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c72
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c18
-rw-r--r--drivers/gpu/drm/i915/i915_gem_fence_reg.c51
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c134
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c8
-rw-r--r--drivers/gpu/drm/i915/i915_pci.c249
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h20
-rw-r--r--drivers/gpu/drm/i915/i915_trace.h2
-rw-r--r--drivers/gpu/drm/i915/intel_atomic_plane.c49
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c200
-rw-r--r--drivers/gpu/drm/i915/intel_cdclk.c272
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c22
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c295
-rw-r--r--drivers/gpu/drm/i915/intel_device_info.c2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c181
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c162
-rw-r--r--drivers/gpu/drm/i915/intel_dp_mst.c16
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h111
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.c22
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c12
-rw-r--r--drivers/gpu/drm/i915/intel_engine_cs.c62
-rw-r--r--drivers/gpu/drm/i915/intel_fbc.c17
-rw-r--r--drivers/gpu/drm/i915/intel_fbdev.c3
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c157
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c2
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c24
-rw-r--r--drivers/gpu/drm/i915/intel_pipe_crc.c65
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c177
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c79
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h12
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c85
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c40
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c27
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c14
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c2
-rw-r--r--drivers/gpu/drm/i915/intel_vbt_defs.h331
-rw-r--r--include/drm/i915_pciids.h152
-rw-r--r--include/uapi/drm/i915_drm.h6
42 files changed, 1945 insertions, 1302 deletions
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b53060..1cb8059a3a16 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -150,5 +150,3 @@ endif
150i915-y += intel_lpe_audio.o 150i915-y += intel_lpe_audio.o
151 151
152obj-$(CONFIG_DRM_I915) += i915.o 152obj-$(CONFIG_DRM_I915) += i915.o
153
154CFLAGS_i915_trace_points.o := -I$(src)
diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index ca3d1925beda..7c9ec4f4f36c 100644
--- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
+++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
@@ -173,8 +173,8 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu)
173 _clear_vgpu_fence(vgpu); 173 _clear_vgpu_fence(vgpu);
174 for (i = 0; i < vgpu_fence_sz(vgpu); i++) { 174 for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
175 reg = vgpu->fence.regs[i]; 175 reg = vgpu->fence.regs[i];
176 list_add_tail(&reg->link, 176 i915_unreserve_fence(reg);
177 &dev_priv->mm.fence_list); 177 vgpu->fence.regs[i] = NULL;
178 } 178 }
179 mutex_unlock(&dev_priv->drm.struct_mutex); 179 mutex_unlock(&dev_priv->drm.struct_mutex);
180 180
@@ -187,24 +187,19 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
187 struct drm_i915_private *dev_priv = gvt->dev_priv; 187 struct drm_i915_private *dev_priv = gvt->dev_priv;
188 struct drm_i915_fence_reg *reg; 188 struct drm_i915_fence_reg *reg;
189 int i; 189 int i;
190 struct list_head *pos, *q;
191 190
192 intel_runtime_pm_get(dev_priv); 191 intel_runtime_pm_get(dev_priv);
193 192
194 /* Request fences from host */ 193 /* Request fences from host */
195 mutex_lock(&dev_priv->drm.struct_mutex); 194 mutex_lock(&dev_priv->drm.struct_mutex);
196 i = 0; 195
197 list_for_each_safe(pos, q, &dev_priv->mm.fence_list) { 196 for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
198 reg = list_entry(pos, struct drm_i915_fence_reg, link); 197 reg = i915_reserve_fence(dev_priv);
199 if (reg->pin_count || reg->vma) 198 if (IS_ERR(reg))
200 continue; 199 goto out_free_fence;
201 list_del(pos); 200
202 vgpu->fence.regs[i] = reg; 201 vgpu->fence.regs[i] = reg;
203 if (++i == vgpu_fence_sz(vgpu))
204 break;
205 } 202 }
206 if (i != vgpu_fence_sz(vgpu))
207 goto out_free_fence;
208 203
209 _clear_vgpu_fence(vgpu); 204 _clear_vgpu_fence(vgpu);
210 205
@@ -212,13 +207,14 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
212 intel_runtime_pm_put(dev_priv); 207 intel_runtime_pm_put(dev_priv);
213 return 0; 208 return 0;
214out_free_fence: 209out_free_fence:
210 gvt_vgpu_err("Failed to alloc fences\n");
215 /* Return fences to host, if fail */ 211 /* Return fences to host, if fail */
216 for (i = 0; i < vgpu_fence_sz(vgpu); i++) { 212 for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
217 reg = vgpu->fence.regs[i]; 213 reg = vgpu->fence.regs[i];
218 if (!reg) 214 if (!reg)
219 continue; 215 continue;
220 list_add_tail(&reg->link, 216 i915_unreserve_fence(reg);
221 &dev_priv->mm.fence_list); 217 vgpu->fence.regs[i] = NULL;
222 } 218 }
223 mutex_unlock(&dev_priv->drm.struct_mutex); 219 mutex_unlock(&dev_priv->drm.struct_mutex);
224 intel_runtime_pm_put(dev_priv); 220 intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9f45cfeae775..ff70fc45ba7c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -239,7 +239,8 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
239 dev_priv->pch_type = PCH_KBP; 239 dev_priv->pch_type = PCH_KBP;
240 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n"); 240 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
241 WARN_ON(!IS_SKYLAKE(dev_priv) && 241 WARN_ON(!IS_SKYLAKE(dev_priv) &&
242 !IS_KABYLAKE(dev_priv)); 242 !IS_KABYLAKE(dev_priv) &&
243 !IS_COFFEELAKE(dev_priv));
243 } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) { 244 } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
244 dev_priv->pch_type = PCH_CNP; 245 dev_priv->pch_type = PCH_CNP;
245 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n"); 246 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b6b175aa5d25..b1fa81348ee9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -80,8 +80,8 @@
80 80
81#define DRIVER_NAME "i915" 81#define DRIVER_NAME "i915"
82#define DRIVER_DESC "Intel Graphics" 82#define DRIVER_DESC "Intel Graphics"
83#define DRIVER_DATE "20170818" 83#define DRIVER_DATE "20170907"
84#define DRIVER_TIMESTAMP 1503088845 84#define DRIVER_TIMESTAMP 1504772900
85 85
86/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 86/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
@@ -569,6 +569,24 @@ struct i915_hotplug {
569 (__i)++) \ 569 (__i)++) \
570 for_each_if (plane_state) 570 for_each_if (plane_state)
571 571
572#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
573 for ((__i) = 0; \
574 (__i) < (__state)->base.dev->mode_config.num_crtc && \
575 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
576 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
577 (__i)++) \
578 for_each_if (crtc)
579
580
581#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
582 for ((__i) = 0; \
583 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
584 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
585 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
586 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
587 (__i)++) \
588 for_each_if (plane)
589
572struct drm_i915_private; 590struct drm_i915_private;
573struct i915_mm_struct; 591struct i915_mm_struct;
574struct i915_mmu_object; 592struct i915_mmu_object;
@@ -841,6 +859,7 @@ struct intel_device_info {
841 u8 gen; 859 u8 gen;
842 u16 gen_mask; 860 u16 gen_mask;
843 enum intel_platform platform; 861 enum intel_platform platform;
862 u8 gt; /* GT number, 0 if undefined */
844 u8 ring_mask; /* Rings supported by the HW */ 863 u8 ring_mask; /* Rings supported by the HW */
845 u8 num_rings; 864 u8 num_rings;
846#define DEFINE_FLAG(name) u8 name:1 865#define DEFINE_FLAG(name) u8 name:1
@@ -1106,6 +1125,7 @@ struct intel_fbc {
1106 } fb; 1125 } fb;
1107 1126
1108 int cfb_size; 1127 int cfb_size;
1128 unsigned int gen9_wa_cfb_stride;
1109 } params; 1129 } params;
1110 1130
1111 struct intel_fbc_work { 1131 struct intel_fbc_work {
@@ -1464,6 +1484,11 @@ struct i915_gem_mm {
1464 struct llist_head free_list; 1484 struct llist_head free_list;
1465 struct work_struct free_work; 1485 struct work_struct free_work;
1466 1486
1487 /**
1488 * Small stash of WC pages
1489 */
1490 struct pagevec wc_stash;
1491
1467 /** Usable portion of the GTT for GEM */ 1492 /** Usable portion of the GTT for GEM */
1468 dma_addr_t stolen_base; /* limited to low memory (32-bit) */ 1493 dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1469 1494
@@ -1717,7 +1742,7 @@ struct intel_vbt_data {
1717 int crt_ddc_pin; 1742 int crt_ddc_pin;
1718 1743
1719 int child_dev_num; 1744 int child_dev_num;
1720 union child_device_config *child_dev; 1745 struct child_device_config *child_dev;
1721 1746
1722 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1747 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1723 struct sdvo_device_mapping sdvo_mappings[2]; 1748 struct sdvo_device_mapping sdvo_mappings[2];
@@ -2328,7 +2353,8 @@ struct drm_i915_private {
2328 struct mutex dpll_lock; 2353 struct mutex dpll_lock;
2329 2354
2330 unsigned int active_crtcs; 2355 unsigned int active_crtcs;
2331 unsigned int min_pixclk[I915_MAX_PIPES]; 2356 /* minimum acceptable cdclk for each pipe */
2357 int min_cdclk[I915_MAX_PIPES];
2332 2358
2333 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 2359 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2334 2360
@@ -2861,9 +2887,8 @@ intel_info(const struct drm_i915_private *dev_priv)
2861#define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33) 2887#define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2862#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) 2888#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2863#define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE) 2889#define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2864#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \ 2890#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2865 INTEL_DEVID(dev_priv) == 0x0152 || \ 2891 (dev_priv)->info.gt == 1)
2866 INTEL_DEVID(dev_priv) == 0x015a)
2867#define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW) 2892#define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2868#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW) 2893#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2869#define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL) 2894#define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
@@ -2885,11 +2910,11 @@ intel_info(const struct drm_i915_private *dev_priv)
2885#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ 2910#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2886 (INTEL_DEVID(dev_priv) & 0xf) == 0xe) 2911 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2887#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 2912#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2888 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) 2913 (dev_priv)->info.gt == 3)
2889#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ 2914#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2890 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) 2915 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2891#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 2916#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2892 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) 2917 (dev_priv)->info.gt == 3)
2893/* ULX machines are also considered ULT. */ 2918/* ULX machines are also considered ULT. */
2894#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ 2919#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2895 INTEL_DEVID(dev_priv) == 0x0A1E) 2920 INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2910,15 +2935,15 @@ intel_info(const struct drm_i915_private *dev_priv)
2910 INTEL_DEVID(dev_priv) == 0x5915 || \ 2935 INTEL_DEVID(dev_priv) == 0x5915 || \
2911 INTEL_DEVID(dev_priv) == 0x591E) 2936 INTEL_DEVID(dev_priv) == 0x591E)
2912#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 2937#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2913 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010) 2938 (dev_priv)->info.gt == 2)
2914#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 2939#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2915 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) 2940 (dev_priv)->info.gt == 3)
2916#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 2941#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2917 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030) 2942 (dev_priv)->info.gt == 4)
2918#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 2943#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2919 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010) 2944 (dev_priv)->info.gt == 2)
2920#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 2945#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2921 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) 2946 (dev_priv)->info.gt == 3)
2922#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 2947#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2923 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) 2948 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2924 2949
@@ -3647,6 +3672,9 @@ i915_vm_to_ppgtt(struct i915_address_space *vm)
3647/* i915_gem_fence_reg.c */ 3672/* i915_gem_fence_reg.c */
3648int __must_check i915_vma_get_fence(struct i915_vma *vma); 3673int __must_check i915_vma_get_fence(struct i915_vma *vma);
3649int __must_check i915_vma_put_fence(struct i915_vma *vma); 3674int __must_check i915_vma_put_fence(struct i915_vma *vma);
3675struct drm_i915_fence_reg *
3676i915_reserve_fence(struct drm_i915_private *dev_priv);
3677void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3650 3678
3651void i915_gem_revoke_fences(struct drm_i915_private *dev_priv); 3679void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3652void i915_gem_restore_fences(struct drm_i915_private *dev_priv); 3680void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
@@ -4332,11 +4360,4 @@ int remap_io_mapping(struct vm_area_struct *vma,
4332 unsigned long addr, unsigned long pfn, unsigned long size, 4360 unsigned long addr, unsigned long pfn, unsigned long size,
4333 struct io_mapping *iomap); 4361 struct io_mapping *iomap);
4334 4362
4335static inline bool
4336intel_engine_can_store_dword(struct intel_engine_cs *engine)
4337{
4338 return __intel_engine_can_store_dword(INTEL_GEN(engine->i915),
4339 engine->class);
4340}
4341
4342#endif 4363#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 19404c96eeb1..8f074c7f6253 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1013,17 +1013,20 @@ gtt_user_read(struct io_mapping *mapping,
1013 loff_t base, int offset, 1013 loff_t base, int offset,
1014 char __user *user_data, int length) 1014 char __user *user_data, int length)
1015{ 1015{
1016 void *vaddr; 1016 void __iomem *vaddr;
1017 unsigned long unwritten; 1017 unsigned long unwritten;
1018 1018
1019 /* We can use the cpu mem copy function because this is X86. */ 1019 /* We can use the cpu mem copy function because this is X86. */
1020 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); 1020 vaddr = io_mapping_map_atomic_wc(mapping, base);
1021 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); 1021 unwritten = __copy_to_user_inatomic(user_data,
1022 (void __force *)vaddr + offset,
1023 length);
1022 io_mapping_unmap_atomic(vaddr); 1024 io_mapping_unmap_atomic(vaddr);
1023 if (unwritten) { 1025 if (unwritten) {
1024 vaddr = (void __force *) 1026 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
1025 io_mapping_map_wc(mapping, base, PAGE_SIZE); 1027 unwritten = copy_to_user(user_data,
1026 unwritten = copy_to_user(user_data, vaddr + offset, length); 1028 (void __force *)vaddr + offset,
1029 length);
1027 io_mapping_unmap(vaddr); 1030 io_mapping_unmap(vaddr);
1028 } 1031 }
1029 return unwritten; 1032 return unwritten;
@@ -1189,18 +1192,18 @@ ggtt_write(struct io_mapping *mapping,
1189 loff_t base, int offset, 1192 loff_t base, int offset,
1190 char __user *user_data, int length) 1193 char __user *user_data, int length)
1191{ 1194{
1192 void *vaddr; 1195 void __iomem *vaddr;
1193 unsigned long unwritten; 1196 unsigned long unwritten;
1194 1197
1195 /* We can use the cpu mem copy function because this is X86. */ 1198 /* We can use the cpu mem copy function because this is X86. */
1196 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); 1199 vaddr = io_mapping_map_atomic_wc(mapping, base);
1197 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, 1200 unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,
1198 user_data, length); 1201 user_data, length);
1199 io_mapping_unmap_atomic(vaddr); 1202 io_mapping_unmap_atomic(vaddr);
1200 if (unwritten) { 1203 if (unwritten) {
1201 vaddr = (void __force *) 1204 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
1202 io_mapping_map_wc(mapping, base, PAGE_SIZE); 1205 unwritten = copy_from_user((void __force *)vaddr + offset,
1203 unwritten = copy_from_user(vaddr + offset, user_data, length); 1206 user_data, length);
1204 io_mapping_unmap(vaddr); 1207 io_mapping_unmap(vaddr);
1205 } 1208 }
1206 1209
@@ -2476,8 +2479,6 @@ static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2476{ 2479{
2477 struct sg_table *pages; 2480 struct sg_table *pages;
2478 2481
2479 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2480
2481 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { 2482 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2482 DRM_DEBUG("Attempting to obtain a purgeable object\n"); 2483 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2483 return -EFAULT; 2484 return -EFAULT;
@@ -2507,6 +2508,8 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2507 return err; 2508 return err;
2508 2509
2509 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) { 2510 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2511 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2512
2510 err = ____i915_gem_object_get_pages(obj); 2513 err = ____i915_gem_object_get_pages(obj);
2511 if (err) 2514 if (err)
2512 goto unlock; 2515 goto unlock;
@@ -2590,6 +2593,8 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2590 2593
2591 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { 2594 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2592 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) { 2595 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2596 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2597
2593 ret = ____i915_gem_object_get_pages(obj); 2598 ret = ____i915_gem_object_get_pages(obj);
2594 if (ret) 2599 if (ret)
2595 goto err_unlock; 2600 goto err_unlock;
@@ -3257,11 +3262,11 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
3257 struct i915_gem_context *ctx = lut->ctx; 3262 struct i915_gem_context *ctx = lut->ctx;
3258 struct i915_vma *vma; 3263 struct i915_vma *vma;
3259 3264
3265 GEM_BUG_ON(ctx->file_priv == ERR_PTR(-EBADF));
3260 if (ctx->file_priv != fpriv) 3266 if (ctx->file_priv != fpriv)
3261 continue; 3267 continue;
3262 3268
3263 vma = radix_tree_delete(&ctx->handles_vma, lut->handle); 3269 vma = radix_tree_delete(&ctx->handles_vma, lut->handle);
3264
3265 GEM_BUG_ON(vma->obj != obj); 3270 GEM_BUG_ON(vma->obj != obj);
3266 3271
3267 /* We allow the process to have multiple handles to the same 3272 /* We allow the process to have multiple handles to the same
@@ -3375,24 +3380,12 @@ static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3375 return 0; 3380 return 0;
3376} 3381}
3377 3382
3378static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms)
3379{
3380 return wait_for(intel_engine_is_idle(engine), timeout_ms);
3381}
3382
3383static int wait_for_engines(struct drm_i915_private *i915) 3383static int wait_for_engines(struct drm_i915_private *i915)
3384{ 3384{
3385 struct intel_engine_cs *engine; 3385 if (wait_for(intel_engines_are_idle(i915), 50)) {
3386 enum intel_engine_id id; 3386 DRM_ERROR("Failed to idle engines, declaring wedged!\n");
3387 3387 i915_gem_set_wedged(i915);
3388 for_each_engine(engine, i915, id) { 3388 return -EIO;
3389 if (GEM_WARN_ON(wait_for_engine(engine, 50))) {
3390 i915_gem_set_wedged(i915);
3391 return -EIO;
3392 }
3393
3394 GEM_BUG_ON(intel_engine_get_seqno(engine) !=
3395 intel_engine_last_submit(engine));
3396 } 3389 }
3397 3390
3398 return 0; 3391 return 0;
@@ -4426,6 +4419,7 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915,
4426 llist_for_each_entry_safe(obj, on, freed, freed) { 4419 llist_for_each_entry_safe(obj, on, freed, freed) {
4427 GEM_BUG_ON(obj->bind_count); 4420 GEM_BUG_ON(obj->bind_count);
4428 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); 4421 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4422 GEM_BUG_ON(!list_empty(&obj->lut_list));
4429 4423
4430 if (obj->ops->release) 4424 if (obj->ops->release)
4431 obj->ops->release(obj); 4425 obj->ops->release(obj);
@@ -4533,6 +4527,12 @@ static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4533 4527
4534void i915_gem_sanitize(struct drm_i915_private *i915) 4528void i915_gem_sanitize(struct drm_i915_private *i915)
4535{ 4529{
4530 if (i915_terminally_wedged(&i915->gpu_error)) {
4531 mutex_lock(&i915->drm.struct_mutex);
4532 i915_gem_unset_wedged(i915);
4533 mutex_unlock(&i915->drm.struct_mutex);
4534 }
4535
4536 /* 4536 /*
4537 * If we inherit context state from the BIOS or earlier occupants 4537 * If we inherit context state from the BIOS or earlier occupants
4538 * of the GPU, the GPU may be in an inconsistent state when we 4538 * of the GPU, the GPU may be in an inconsistent state when we
@@ -4572,7 +4572,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
4572 ret = i915_gem_wait_for_idle(dev_priv, 4572 ret = i915_gem_wait_for_idle(dev_priv,
4573 I915_WAIT_INTERRUPTIBLE | 4573 I915_WAIT_INTERRUPTIBLE |
4574 I915_WAIT_LOCKED); 4574 I915_WAIT_LOCKED);
4575 if (ret) 4575 if (ret && ret != -EIO)
4576 goto err_unlock; 4576 goto err_unlock;
4577 4577
4578 assert_kernel_context_is_current(dev_priv); 4578 assert_kernel_context_is_current(dev_priv);
@@ -4594,7 +4594,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
4594 * reset the GPU back to its idle, low power state. 4594 * reset the GPU back to its idle, low power state.
4595 */ 4595 */
4596 WARN_ON(dev_priv->gt.awake); 4596 WARN_ON(dev_priv->gt.awake);
4597 WARN_ON(!intel_engines_are_idle(dev_priv)); 4597 if (WARN_ON(!intel_engines_are_idle(dev_priv)))
4598 i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
4598 4599
4599 /* 4600 /*
4600 * Neither the BIOS, ourselves or any other kernel 4601 * Neither the BIOS, ourselves or any other kernel
@@ -4616,11 +4617,12 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
4616 * machine in an unusable condition. 4617 * machine in an unusable condition.
4617 */ 4618 */
4618 i915_gem_sanitize(dev_priv); 4619 i915_gem_sanitize(dev_priv);
4619 goto out_rpm_put; 4620
4621 intel_runtime_pm_put(dev_priv);
4622 return 0;
4620 4623
4621err_unlock: 4624err_unlock:
4622 mutex_unlock(&dev->struct_mutex); 4625 mutex_unlock(&dev->struct_mutex);
4623out_rpm_put:
4624 intel_runtime_pm_put(dev_priv); 4626 intel_runtime_pm_put(dev_priv);
4625 return ret; 4627 return ret;
4626} 4628}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 92437f455b43..ca0eab343644 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -268,6 +268,11 @@ static inline u64 gen8_noncanonical_addr(u64 address)
268 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0); 268 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
269} 269}
270 270
271static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
272{
273 return eb->engine->needs_cmd_parser && eb->batch_len;
274}
275
271static int eb_create(struct i915_execbuffer *eb) 276static int eb_create(struct i915_execbuffer *eb)
272{ 277{
273 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) { 278 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
@@ -1159,6 +1164,13 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb,
1159 if (unlikely(!cache->rq)) { 1164 if (unlikely(!cache->rq)) {
1160 int err; 1165 int err;
1161 1166
1167 /* If we need to copy for the cmdparser, we will stall anyway */
1168 if (eb_use_cmdparser(eb))
1169 return ERR_PTR(-EWOULDBLOCK);
1170
1171 if (!intel_engine_can_store_dword(eb->engine))
1172 return ERR_PTR(-ENODEV);
1173
1162 err = __reloc_gpu_alloc(eb, vma, len); 1174 err = __reloc_gpu_alloc(eb, vma, len);
1163 if (unlikely(err)) 1175 if (unlikely(err))
1164 return ERR_PTR(err); 1176 return ERR_PTR(err);
@@ -1183,9 +1195,7 @@ relocate_entry(struct i915_vma *vma,
1183 1195
1184 if (!eb->reloc_cache.vaddr && 1196 if (!eb->reloc_cache.vaddr &&
1185 (DBG_FORCE_RELOC == FORCE_GPU_RELOC || 1197 (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
1186 !reservation_object_test_signaled_rcu(vma->resv, true)) && 1198 !reservation_object_test_signaled_rcu(vma->resv, true))) {
1187 __intel_engine_can_store_dword(eb->reloc_cache.gen,
1188 eb->engine->class)) {
1189 const unsigned int gen = eb->reloc_cache.gen; 1199 const unsigned int gen = eb->reloc_cache.gen;
1190 unsigned int len; 1200 unsigned int len;
1191 u32 *batch; 1201 u32 *batch;
@@ -2291,7 +2301,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
2291 goto err_vma; 2301 goto err_vma;
2292 } 2302 }
2293 2303
2294 if (eb.engine->needs_cmd_parser && eb.batch_len) { 2304 if (eb_use_cmdparser(&eb)) {
2295 struct i915_vma *vma; 2305 struct i915_vma *vma;
2296 2306
2297 vma = eb_parse(&eb, drm_is_current_master(file)); 2307 vma = eb_parse(&eb, drm_is_current_master(file));
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 5fe2cd8c8f28..2783d63bd1ad 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -360,6 +360,57 @@ i915_vma_get_fence(struct i915_vma *vma)
360} 360}
361 361
362/** 362/**
363 * i915_reserve_fence - Reserve a fence for vGPU
364 * @dev_priv: i915 device private
365 *
366 * This function walks the fence regs looking for a free one and remove
367 * it from the fence_list. It is used to reserve fence for vGPU to use.
368 */
369struct drm_i915_fence_reg *
370i915_reserve_fence(struct drm_i915_private *dev_priv)
371{
372 struct drm_i915_fence_reg *fence;
373 int count;
374 int ret;
375
376 lockdep_assert_held(&dev_priv->drm.struct_mutex);
377
378 /* Keep at least one fence available for the display engine. */
379 count = 0;
380 list_for_each_entry(fence, &dev_priv->mm.fence_list, link)
381 count += !fence->pin_count;
382 if (count <= 1)
383 return ERR_PTR(-ENOSPC);
384
385 fence = fence_find(dev_priv);
386 if (IS_ERR(fence))
387 return fence;
388
389 if (fence->vma) {
390 /* Force-remove fence from VMA */
391 ret = fence_update(fence, NULL);
392 if (ret)
393 return ERR_PTR(ret);
394 }
395
396 list_del(&fence->link);
397 return fence;
398}
399
400/**
401 * i915_unreserve_fence - Reclaim a reserved fence
402 * @fence: the fence reg
403 *
404 * This function add a reserved fence register from vGPU to the fence_list.
405 */
406void i915_unreserve_fence(struct drm_i915_fence_reg *fence)
407{
408 lockdep_assert_held(&fence->i915->drm.struct_mutex);
409
410 list_add(&fence->link, &fence->i915->mm.fence_list);
411}
412
413/**
363 * i915_gem_revoke_fences - revoke fence state 414 * i915_gem_revoke_fences - revoke fence state
364 * @dev_priv: i915 device private 415 * @dev_priv: i915 device private
365 * 416 *
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e2410eb5d96e..40d446ba0b85 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -356,39 +356,86 @@ static gen6_pte_t iris_pte_encode(dma_addr_t addr,
356 356
357static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp) 357static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp)
358{ 358{
359 struct page *page; 359 struct pagevec *pvec = &vm->free_pages;
360 360
361 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) 361 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1)))
362 i915_gem_shrink_all(vm->i915); 362 i915_gem_shrink_all(vm->i915);
363 363
364 if (vm->free_pages.nr) 364 if (likely(pvec->nr))
365 return vm->free_pages.pages[--vm->free_pages.nr]; 365 return pvec->pages[--pvec->nr];
366
367 if (!vm->pt_kmap_wc)
368 return alloc_page(gfp);
369
370 /* A placeholder for a specific mutex to guard the WC stash */
371 lockdep_assert_held(&vm->i915->drm.struct_mutex);
372
373 /* Look in our global stash of WC pages... */
374 pvec = &vm->i915->mm.wc_stash;
375 if (likely(pvec->nr))
376 return pvec->pages[--pvec->nr];
366 377
367 page = alloc_page(gfp); 378 /* Otherwise batch allocate pages to amoritize cost of set_pages_wc. */
368 if (!page) 379 do {
380 struct page *page;
381
382 page = alloc_page(gfp);
383 if (unlikely(!page))
384 break;
385
386 pvec->pages[pvec->nr++] = page;
387 } while (pagevec_space(pvec));
388
389 if (unlikely(!pvec->nr))
369 return NULL; 390 return NULL;
370 391
371 if (vm->pt_kmap_wc) 392 set_pages_array_wc(pvec->pages, pvec->nr);
372 set_pages_array_wc(&page, 1);
373 393
374 return page; 394 return pvec->pages[--pvec->nr];
375} 395}
376 396
377static void vm_free_pages_release(struct i915_address_space *vm) 397static void vm_free_pages_release(struct i915_address_space *vm,
398 bool immediate)
378{ 399{
379 GEM_BUG_ON(!pagevec_count(&vm->free_pages)); 400 struct pagevec *pvec = &vm->free_pages;
401
402 GEM_BUG_ON(!pagevec_count(pvec));
403
404 if (vm->pt_kmap_wc) {
405 struct pagevec *stash = &vm->i915->mm.wc_stash;
380 406
381 if (vm->pt_kmap_wc) 407 /* When we use WC, first fill up the global stash and then
382 set_pages_array_wb(vm->free_pages.pages, 408 * only if full immediately free the overflow.
383 pagevec_count(&vm->free_pages)); 409 */
410
411 lockdep_assert_held(&vm->i915->drm.struct_mutex);
412 if (pagevec_space(stash)) {
413 do {
414 stash->pages[stash->nr++] =
415 pvec->pages[--pvec->nr];
416 if (!pvec->nr)
417 return;
418 } while (pagevec_space(stash));
419
420 /* As we have made some room in the VM's free_pages,
421 * we can wait for it to fill again. Unless we are
422 * inside i915_address_space_fini() and must
423 * immediately release the pages!
424 */
425 if (!immediate)
426 return;
427 }
428
429 set_pages_array_wb(pvec->pages, pvec->nr);
430 }
384 431
385 __pagevec_release(&vm->free_pages); 432 __pagevec_release(pvec);
386} 433}
387 434
388static void vm_free_page(struct i915_address_space *vm, struct page *page) 435static void vm_free_page(struct i915_address_space *vm, struct page *page)
389{ 436{
390 if (!pagevec_add(&vm->free_pages, page)) 437 if (!pagevec_add(&vm->free_pages, page))
391 vm_free_pages_release(vm); 438 vm_free_pages_release(vm, false);
392} 439}
393 440
394static int __setup_page_dma(struct i915_address_space *vm, 441static int __setup_page_dma(struct i915_address_space *vm,
@@ -452,12 +499,31 @@ static void fill_page_dma_32(struct i915_address_space *vm,
452static int 499static int
453setup_scratch_page(struct i915_address_space *vm, gfp_t gfp) 500setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
454{ 501{
455 return __setup_page_dma(vm, &vm->scratch_page, gfp | __GFP_ZERO); 502 struct page *page;
503 dma_addr_t addr;
504
505 page = alloc_page(gfp | __GFP_ZERO);
506 if (unlikely(!page))
507 return -ENOMEM;
508
509 addr = dma_map_page(vm->dma, page, 0, PAGE_SIZE,
510 PCI_DMA_BIDIRECTIONAL);
511 if (unlikely(dma_mapping_error(vm->dma, addr))) {
512 __free_page(page);
513 return -ENOMEM;
514 }
515
516 vm->scratch_page.page = page;
517 vm->scratch_page.daddr = addr;
518 return 0;
456} 519}
457 520
458static void cleanup_scratch_page(struct i915_address_space *vm) 521static void cleanup_scratch_page(struct i915_address_space *vm)
459{ 522{
460 cleanup_page_dma(vm, &vm->scratch_page); 523 struct i915_page_dma *p = &vm->scratch_page;
524
525 dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
526 __free_page(p->page);
461} 527}
462 528
463static struct i915_page_table *alloc_pt(struct i915_address_space *vm) 529static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
@@ -1337,18 +1403,18 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1337 1ULL << 48 : 1403 1ULL << 48 :
1338 1ULL << 32; 1404 1ULL << 32;
1339 1405
1340 ret = gen8_init_scratch(&ppgtt->base);
1341 if (ret) {
1342 ppgtt->base.total = 0;
1343 return ret;
1344 }
1345
1346 /* There are only few exceptions for gen >=6. chv and bxt. 1406 /* There are only few exceptions for gen >=6. chv and bxt.
1347 * And we are not sure about the latter so play safe for now. 1407 * And we are not sure about the latter so play safe for now.
1348 */ 1408 */
1349 if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) 1409 if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
1350 ppgtt->base.pt_kmap_wc = true; 1410 ppgtt->base.pt_kmap_wc = true;
1351 1411
1412 ret = gen8_init_scratch(&ppgtt->base);
1413 if (ret) {
1414 ppgtt->base.total = 0;
1415 return ret;
1416 }
1417
1352 if (use_4lvl(vm)) { 1418 if (use_4lvl(vm)) {
1353 ret = setup_px(&ppgtt->base, &ppgtt->pml4); 1419 ret = setup_px(&ppgtt->base, &ppgtt->pml4);
1354 if (ret) 1420 if (ret)
@@ -1872,7 +1938,7 @@ static void i915_address_space_init(struct i915_address_space *vm,
1872static void i915_address_space_fini(struct i915_address_space *vm) 1938static void i915_address_space_fini(struct i915_address_space *vm)
1873{ 1939{
1874 if (pagevec_count(&vm->free_pages)) 1940 if (pagevec_count(&vm->free_pages))
1875 vm_free_pages_release(vm); 1941 vm_free_pages_release(vm, true);
1876 1942
1877 i915_gem_timeline_fini(&vm->timeline); 1943 i915_gem_timeline_fini(&vm->timeline);
1878 drm_mm_takedown(&vm->mm); 1944 drm_mm_takedown(&vm->mm);
@@ -1885,12 +1951,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
1885 * called on driver load and after a GPU reset, so you can place 1951 * called on driver load and after a GPU reset, so you can place
1886 * workarounds here even if they get overwritten by GPU reset. 1952 * workarounds here even if they get overwritten by GPU reset.
1887 */ 1953 */
1888 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */ 1954 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
1889 if (IS_BROADWELL(dev_priv)) 1955 if (IS_BROADWELL(dev_priv))
1890 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); 1956 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
1891 else if (IS_CHERRYVIEW(dev_priv)) 1957 else if (IS_CHERRYVIEW(dev_priv))
1892 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); 1958 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
1893 else if (IS_GEN9_BC(dev_priv)) 1959 else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
1894 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); 1960 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
1895 else if (IS_GEN9_LP(dev_priv)) 1961 else if (IS_GEN9_LP(dev_priv))
1896 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); 1962 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
@@ -2598,6 +2664,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
2598{ 2664{
2599 struct i915_ggtt *ggtt = &dev_priv->ggtt; 2665 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2600 struct i915_vma *vma, *vn; 2666 struct i915_vma *vma, *vn;
2667 struct pagevec *pvec;
2601 2668
2602 ggtt->base.closed = true; 2669 ggtt->base.closed = true;
2603 2670
@@ -2621,6 +2688,13 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
2621 } 2688 }
2622 2689
2623 ggtt->base.cleanup(&ggtt->base); 2690 ggtt->base.cleanup(&ggtt->base);
2691
2692 pvec = &dev_priv->mm.wc_stash;
2693 if (pvec->nr) {
2694 set_pages_array_wb(pvec->pages, pvec->nr);
2695 __pagevec_release(pvec);
2696 }
2697
2624 mutex_unlock(&dev_priv->drm.struct_mutex); 2698 mutex_unlock(&dev_priv->drm.struct_mutex);
2625 2699
2626 arch_phys_wc_del(ggtt->mtrr); 2700 arch_phys_wc_del(ggtt->mtrr);
@@ -2716,13 +2790,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
2716 phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; 2790 phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
2717 2791
2718 /* 2792 /*
2719 * On BXT writes larger than 64 bit to the GTT pagetable range will be 2793 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
2720 * dropped. For WC mappings in general we have 64 byte burst writes 2794 * will be dropped. For WC mappings in general we have 64 byte burst
2721 * when the WC buffer is flushed, so we can't use it, but have to 2795 * writes when the WC buffer is flushed, so we can't use it, but have to
2722 * resort to an uncached mapping. The WC issue is easily caught by the 2796 * resort to an uncached mapping. The WC issue is easily caught by the
2723 * readback check when writing GTT PTE entries. 2797 * readback check when writing GTT PTE entries.
2724 */ 2798 */
2725 if (IS_GEN9_LP(dev_priv)) 2799 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
2726 ggtt->gsm = ioremap_nocache(phys_addr, size); 2800 ggtt->gsm = ioremap_nocache(phys_addr, size);
2727 else 2801 else
2728 ggtt->gsm = ioremap_wc(phys_addr, size); 2802 ggtt->gsm = ioremap_wc(phys_addr, size);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b63893eeca73..2fe92d2e0f62 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -336,7 +336,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
336 __gen6_mask_pm_irq(dev_priv, mask); 336 __gen6_mask_pm_irq(dev_priv, mask);
337} 337}
338 338
339void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) 339static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
340{ 340{
341 i915_reg_t reg = gen6_pm_iir(dev_priv); 341 i915_reg_t reg = gen6_pm_iir(dev_priv);
342 342
@@ -347,7 +347,7 @@ void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
347 POSTING_READ(reg); 347 POSTING_READ(reg);
348} 348}
349 349
350void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask) 350static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
351{ 351{
352 lockdep_assert_held(&dev_priv->irq_lock); 352 lockdep_assert_held(&dev_priv->irq_lock);
353 353
@@ -357,7 +357,7 @@ void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
357 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */ 357 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
358} 358}
359 359
360void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask) 360static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
361{ 361{
362 lockdep_assert_held(&dev_priv->irq_lock); 362 lockdep_assert_held(&dev_priv->irq_lock);
363 363
@@ -405,7 +405,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
405 synchronize_irq(dev_priv->drm.irq); 405 synchronize_irq(dev_priv->drm.irq);
406 406
407 /* Now that we will not be generating any more work, flush any 407 /* Now that we will not be generating any more work, flush any
408 * outsanding tasks. As we are called on the RPS idle path, 408 * outstanding tasks. As we are called on the RPS idle path,
409 * we will reset the GPU to minimum frequencies, so the current 409 * we will reset the GPU to minimum frequencies, so the current
410 * state of the worker can be discarded. 410 * state of the worker can be discarded.
411 */ 411 */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 09d97e0990b7..881b5d6708aa 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -63,22 +63,23 @@
63 .hws_needs_physical = 1, \ 63 .hws_needs_physical = 1, \
64 .unfenced_needs_alignment = 1, \ 64 .unfenced_needs_alignment = 1, \
65 .ring_mask = RENDER_RING, \ 65 .ring_mask = RENDER_RING, \
66 .has_snoop = true, \
66 GEN_DEFAULT_PIPEOFFSETS, \ 67 GEN_DEFAULT_PIPEOFFSETS, \
67 CURSOR_OFFSETS 68 CURSOR_OFFSETS
68 69
69static const struct intel_device_info intel_i830_info = { 70static const struct intel_device_info intel_i830_info __initconst = {
70 GEN2_FEATURES, 71 GEN2_FEATURES,
71 .platform = INTEL_I830, 72 .platform = INTEL_I830,
72 .is_mobile = 1, .cursor_needs_physical = 1, 73 .is_mobile = 1, .cursor_needs_physical = 1,
73 .num_pipes = 2, /* legal, last one wins */ 74 .num_pipes = 2, /* legal, last one wins */
74}; 75};
75 76
76static const struct intel_device_info intel_i845g_info = { 77static const struct intel_device_info intel_i845g_info __initconst = {
77 GEN2_FEATURES, 78 GEN2_FEATURES,
78 .platform = INTEL_I845G, 79 .platform = INTEL_I845G,
79}; 80};
80 81
81static const struct intel_device_info intel_i85x_info = { 82static const struct intel_device_info intel_i85x_info __initconst = {
82 GEN2_FEATURES, 83 GEN2_FEATURES,
83 .platform = INTEL_I85X, .is_mobile = 1, 84 .platform = INTEL_I85X, .is_mobile = 1,
84 .num_pipes = 2, /* legal, last one wins */ 85 .num_pipes = 2, /* legal, last one wins */
@@ -86,7 +87,7 @@ static const struct intel_device_info intel_i85x_info = {
86 .has_fbc = 1, 87 .has_fbc = 1,
87}; 88};
88 89
89static const struct intel_device_info intel_i865g_info = { 90static const struct intel_device_info intel_i865g_info __initconst = {
90 GEN2_FEATURES, 91 GEN2_FEATURES,
91 .platform = INTEL_I865G, 92 .platform = INTEL_I865G,
92}; 93};
@@ -95,10 +96,11 @@ static const struct intel_device_info intel_i865g_info = {
95 .gen = 3, .num_pipes = 2, \ 96 .gen = 3, .num_pipes = 2, \
96 .has_gmch_display = 1, \ 97 .has_gmch_display = 1, \
97 .ring_mask = RENDER_RING, \ 98 .ring_mask = RENDER_RING, \
99 .has_snoop = true, \
98 GEN_DEFAULT_PIPEOFFSETS, \ 100 GEN_DEFAULT_PIPEOFFSETS, \
99 CURSOR_OFFSETS 101 CURSOR_OFFSETS
100 102
101static const struct intel_device_info intel_i915g_info = { 103static const struct intel_device_info intel_i915g_info __initconst = {
102 GEN3_FEATURES, 104 GEN3_FEATURES,
103 .platform = INTEL_I915G, .cursor_needs_physical = 1, 105 .platform = INTEL_I915G, .cursor_needs_physical = 1,
104 .has_overlay = 1, .overlay_needs_physical = 1, 106 .has_overlay = 1, .overlay_needs_physical = 1,
@@ -106,7 +108,7 @@ static const struct intel_device_info intel_i915g_info = {
106 .unfenced_needs_alignment = 1, 108 .unfenced_needs_alignment = 1,
107}; 109};
108 110
109static const struct intel_device_info intel_i915gm_info = { 111static const struct intel_device_info intel_i915gm_info __initconst = {
110 GEN3_FEATURES, 112 GEN3_FEATURES,
111 .platform = INTEL_I915GM, 113 .platform = INTEL_I915GM,
112 .is_mobile = 1, 114 .is_mobile = 1,
@@ -118,7 +120,7 @@ static const struct intel_device_info intel_i915gm_info = {
118 .unfenced_needs_alignment = 1, 120 .unfenced_needs_alignment = 1,
119}; 121};
120 122
121static const struct intel_device_info intel_i945g_info = { 123static const struct intel_device_info intel_i945g_info __initconst = {
122 GEN3_FEATURES, 124 GEN3_FEATURES,
123 .platform = INTEL_I945G, 125 .platform = INTEL_I945G,
124 .has_hotplug = 1, .cursor_needs_physical = 1, 126 .has_hotplug = 1, .cursor_needs_physical = 1,
@@ -127,7 +129,7 @@ static const struct intel_device_info intel_i945g_info = {
127 .unfenced_needs_alignment = 1, 129 .unfenced_needs_alignment = 1,
128}; 130};
129 131
130static const struct intel_device_info intel_i945gm_info = { 132static const struct intel_device_info intel_i945gm_info __initconst = {
131 GEN3_FEATURES, 133 GEN3_FEATURES,
132 .platform = INTEL_I945GM, .is_mobile = 1, 134 .platform = INTEL_I945GM, .is_mobile = 1,
133 .has_hotplug = 1, .cursor_needs_physical = 1, 135 .has_hotplug = 1, .cursor_needs_physical = 1,
@@ -138,14 +140,14 @@ static const struct intel_device_info intel_i945gm_info = {
138 .unfenced_needs_alignment = 1, 140 .unfenced_needs_alignment = 1,
139}; 141};
140 142
141static const struct intel_device_info intel_g33_info = { 143static const struct intel_device_info intel_g33_info __initconst = {
142 GEN3_FEATURES, 144 GEN3_FEATURES,
143 .platform = INTEL_G33, 145 .platform = INTEL_G33,
144 .has_hotplug = 1, 146 .has_hotplug = 1,
145 .has_overlay = 1, 147 .has_overlay = 1,
146}; 148};
147 149
148static const struct intel_device_info intel_pineview_info = { 150static const struct intel_device_info intel_pineview_info __initconst = {
149 GEN3_FEATURES, 151 GEN3_FEATURES,
150 .platform = INTEL_PINEVIEW, .is_mobile = 1, 152 .platform = INTEL_PINEVIEW, .is_mobile = 1,
151 .has_hotplug = 1, 153 .has_hotplug = 1,
@@ -157,17 +159,18 @@ static const struct intel_device_info intel_pineview_info = {
157 .has_hotplug = 1, \ 159 .has_hotplug = 1, \
158 .has_gmch_display = 1, \ 160 .has_gmch_display = 1, \
159 .ring_mask = RENDER_RING, \ 161 .ring_mask = RENDER_RING, \
162 .has_snoop = true, \
160 GEN_DEFAULT_PIPEOFFSETS, \ 163 GEN_DEFAULT_PIPEOFFSETS, \
161 CURSOR_OFFSETS 164 CURSOR_OFFSETS
162 165
163static const struct intel_device_info intel_i965g_info = { 166static const struct intel_device_info intel_i965g_info __initconst = {
164 GEN4_FEATURES, 167 GEN4_FEATURES,
165 .platform = INTEL_I965G, 168 .platform = INTEL_I965G,
166 .has_overlay = 1, 169 .has_overlay = 1,
167 .hws_needs_physical = 1, 170 .hws_needs_physical = 1,
168}; 171};
169 172
170static const struct intel_device_info intel_i965gm_info = { 173static const struct intel_device_info intel_i965gm_info __initconst = {
171 GEN4_FEATURES, 174 GEN4_FEATURES,
172 .platform = INTEL_I965GM, 175 .platform = INTEL_I965GM,
173 .is_mobile = 1, .has_fbc = 1, 176 .is_mobile = 1, .has_fbc = 1,
@@ -176,14 +179,14 @@ static const struct intel_device_info intel_i965gm_info = {
176 .hws_needs_physical = 1, 179 .hws_needs_physical = 1,
177}; 180};
178 181
179static const struct intel_device_info intel_g45_info = { 182static const struct intel_device_info intel_g45_info __initconst = {
180 GEN4_FEATURES, 183 GEN4_FEATURES,
181 .platform = INTEL_G45, 184 .platform = INTEL_G45,
182 .has_pipe_cxsr = 1, 185 .has_pipe_cxsr = 1,
183 .ring_mask = RENDER_RING | BSD_RING, 186 .ring_mask = RENDER_RING | BSD_RING,
184}; 187};
185 188
186static const struct intel_device_info intel_gm45_info = { 189static const struct intel_device_info intel_gm45_info __initconst = {
187 GEN4_FEATURES, 190 GEN4_FEATURES,
188 .platform = INTEL_GM45, 191 .platform = INTEL_GM45,
189 .is_mobile = 1, .has_fbc = 1, 192 .is_mobile = 1, .has_fbc = 1,
@@ -197,15 +200,16 @@ static const struct intel_device_info intel_gm45_info = {
197 .has_hotplug = 1, \ 200 .has_hotplug = 1, \
198 .has_gmbus_irq = 1, \ 201 .has_gmbus_irq = 1, \
199 .ring_mask = RENDER_RING | BSD_RING, \ 202 .ring_mask = RENDER_RING | BSD_RING, \
203 .has_snoop = true, \
200 GEN_DEFAULT_PIPEOFFSETS, \ 204 GEN_DEFAULT_PIPEOFFSETS, \
201 CURSOR_OFFSETS 205 CURSOR_OFFSETS
202 206
203static const struct intel_device_info intel_ironlake_d_info = { 207static const struct intel_device_info intel_ironlake_d_info __initconst = {
204 GEN5_FEATURES, 208 GEN5_FEATURES,
205 .platform = INTEL_IRONLAKE, 209 .platform = INTEL_IRONLAKE,
206}; 210};
207 211
208static const struct intel_device_info intel_ironlake_m_info = { 212static const struct intel_device_info intel_ironlake_m_info __initconst = {
209 GEN5_FEATURES, 213 GEN5_FEATURES,
210 .platform = INTEL_IRONLAKE, 214 .platform = INTEL_IRONLAKE,
211 .is_mobile = 1, .has_fbc = 1, 215 .is_mobile = 1, .has_fbc = 1,
@@ -224,15 +228,34 @@ static const struct intel_device_info intel_ironlake_m_info = {
224 GEN_DEFAULT_PIPEOFFSETS, \ 228 GEN_DEFAULT_PIPEOFFSETS, \
225 CURSOR_OFFSETS 229 CURSOR_OFFSETS
226 230
227static const struct intel_device_info intel_sandybridge_d_info = { 231#define SNB_D_PLATFORM \
228 GEN6_FEATURES, 232 GEN6_FEATURES, \
229 .platform = INTEL_SANDYBRIDGE, 233 .platform = INTEL_SANDYBRIDGE
234
235static const struct intel_device_info intel_sandybridge_d_gt1_info __initconst = {
236 SNB_D_PLATFORM,
237 .gt = 1,
230}; 238};
231 239
232static const struct intel_device_info intel_sandybridge_m_info = { 240static const struct intel_device_info intel_sandybridge_d_gt2_info __initconst = {
233 GEN6_FEATURES, 241 SNB_D_PLATFORM,
234 .platform = INTEL_SANDYBRIDGE, 242 .gt = 2,
235 .is_mobile = 1, 243};
244
245#define SNB_M_PLATFORM \
246 GEN6_FEATURES, \
247 .platform = INTEL_SANDYBRIDGE, \
248 .is_mobile = 1
249
250
251static const struct intel_device_info intel_sandybridge_m_gt1_info __initconst = {
252 SNB_M_PLATFORM,
253 .gt = 1,
254};
255
256static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = {
257 SNB_M_PLATFORM,
258 .gt = 2,
236}; 259};
237 260
238#define GEN7_FEATURES \ 261#define GEN7_FEATURES \
@@ -249,27 +272,46 @@ static const struct intel_device_info intel_sandybridge_m_info = {
249 GEN_DEFAULT_PIPEOFFSETS, \ 272 GEN_DEFAULT_PIPEOFFSETS, \
250 IVB_CURSOR_OFFSETS 273 IVB_CURSOR_OFFSETS
251 274
252static const struct intel_device_info intel_ivybridge_d_info = { 275#define IVB_D_PLATFORM \
253 GEN7_FEATURES, 276 GEN7_FEATURES, \
254 .platform = INTEL_IVYBRIDGE, 277 .platform = INTEL_IVYBRIDGE, \
255 .has_l3_dpf = 1, 278 .has_l3_dpf = 1
279
280static const struct intel_device_info intel_ivybridge_d_gt1_info __initconst = {
281 IVB_D_PLATFORM,
282 .gt = 1,
256}; 283};
257 284
258static const struct intel_device_info intel_ivybridge_m_info = { 285static const struct intel_device_info intel_ivybridge_d_gt2_info __initconst = {
259 GEN7_FEATURES, 286 IVB_D_PLATFORM,
260 .platform = INTEL_IVYBRIDGE, 287 .gt = 2,
261 .is_mobile = 1, 288};
262 .has_l3_dpf = 1, 289
290#define IVB_M_PLATFORM \
291 GEN7_FEATURES, \
292 .platform = INTEL_IVYBRIDGE, \
293 .is_mobile = 1, \
294 .has_l3_dpf = 1
295
296static const struct intel_device_info intel_ivybridge_m_gt1_info __initconst = {
297 IVB_M_PLATFORM,
298 .gt = 1,
299};
300
301static const struct intel_device_info intel_ivybridge_m_gt2_info __initconst = {
302 IVB_M_PLATFORM,
303 .gt = 2,
263}; 304};
264 305
265static const struct intel_device_info intel_ivybridge_q_info = { 306static const struct intel_device_info intel_ivybridge_q_info __initconst = {
266 GEN7_FEATURES, 307 GEN7_FEATURES,
267 .platform = INTEL_IVYBRIDGE, 308 .platform = INTEL_IVYBRIDGE,
309 .gt = 2,
268 .num_pipes = 0, /* legal, last one wins */ 310 .num_pipes = 0, /* legal, last one wins */
269 .has_l3_dpf = 1, 311 .has_l3_dpf = 1,
270}; 312};
271 313
272static const struct intel_device_info intel_valleyview_info = { 314static const struct intel_device_info intel_valleyview_info __initconst = {
273 .platform = INTEL_VALLEYVIEW, 315 .platform = INTEL_VALLEYVIEW,
274 .gen = 7, 316 .gen = 7,
275 .is_lp = 1, 317 .is_lp = 1,
@@ -282,6 +324,7 @@ static const struct intel_device_info intel_valleyview_info = {
282 .has_hotplug = 1, 324 .has_hotplug = 1,
283 .has_aliasing_ppgtt = 1, 325 .has_aliasing_ppgtt = 1,
284 .has_full_ppgtt = 1, 326 .has_full_ppgtt = 1,
327 .has_snoop = true,
285 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 328 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
286 .display_mmio_offset = VLV_DISPLAY_BASE, 329 .display_mmio_offset = VLV_DISPLAY_BASE,
287 GEN_DEFAULT_PIPEOFFSETS, 330 GEN_DEFAULT_PIPEOFFSETS,
@@ -299,10 +342,24 @@ static const struct intel_device_info intel_valleyview_info = {
299 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 342 .has_rc6p = 0 /* RC6p removed-by HSW */, \
300 .has_runtime_pm = 1 343 .has_runtime_pm = 1
301 344
302static const struct intel_device_info intel_haswell_info = { 345#define HSW_PLATFORM \
303 HSW_FEATURES, 346 HSW_FEATURES, \
304 .platform = INTEL_HASWELL, 347 .platform = INTEL_HASWELL, \
305 .has_l3_dpf = 1, 348 .has_l3_dpf = 1
349
350static const struct intel_device_info intel_haswell_gt1_info __initconst = {
351 HSW_PLATFORM,
352 .gt = 1,
353};
354
355static const struct intel_device_info intel_haswell_gt2_info __initconst = {
356 HSW_PLATFORM,
357 .gt = 2,
358};
359
360static const struct intel_device_info intel_haswell_gt3_info __initconst = {
361 HSW_PLATFORM,
362 .gt = 3,
306}; 363};
307 364
308#define BDW_FEATURES \ 365#define BDW_FEATURES \
@@ -318,16 +375,31 @@ static const struct intel_device_info intel_haswell_info = {
318 .gen = 8, \ 375 .gen = 8, \
319 .platform = INTEL_BROADWELL 376 .platform = INTEL_BROADWELL
320 377
321static const struct intel_device_info intel_broadwell_info = { 378static const struct intel_device_info intel_broadwell_gt1_info __initconst = {
322 BDW_PLATFORM, 379 BDW_PLATFORM,
380 .gt = 1,
323}; 381};
324 382
325static const struct intel_device_info intel_broadwell_gt3_info = { 383static const struct intel_device_info intel_broadwell_gt2_info __initconst = {
326 BDW_PLATFORM, 384 BDW_PLATFORM,
385 .gt = 2,
386};
387
388static const struct intel_device_info intel_broadwell_rsvd_info __initconst = {
389 BDW_PLATFORM,
390 .gt = 3,
391 /* According to the device ID those devices are GT3, they were
392 * previously treated as not GT3, keep it like that.
393 */
394};
395
396static const struct intel_device_info intel_broadwell_gt3_info __initconst = {
397 BDW_PLATFORM,
398 .gt = 3,
327 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 399 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
328}; 400};
329 401
330static const struct intel_device_info intel_cherryview_info = { 402static const struct intel_device_info intel_cherryview_info __initconst = {
331 .gen = 8, .num_pipes = 3, 403 .gen = 8, .num_pipes = 3,
332 .has_hotplug = 1, 404 .has_hotplug = 1,
333 .is_lp = 1, 405 .is_lp = 1,
@@ -344,6 +416,7 @@ static const struct intel_device_info intel_cherryview_info = {
344 .has_aliasing_ppgtt = 1, 416 .has_aliasing_ppgtt = 1,
345 .has_full_ppgtt = 1, 417 .has_full_ppgtt = 1,
346 .has_reset_engine = 1, 418 .has_reset_engine = 1,
419 .has_snoop = true,
347 .display_mmio_offset = VLV_DISPLAY_BASE, 420 .display_mmio_offset = VLV_DISPLAY_BASE,
348 GEN_CHV_PIPEOFFSETS, 421 GEN_CHV_PIPEOFFSETS,
349 CURSOR_OFFSETS, 422 CURSOR_OFFSETS,
@@ -358,13 +431,29 @@ static const struct intel_device_info intel_cherryview_info = {
358 .has_guc = 1, \ 431 .has_guc = 1, \
359 .ddb_size = 896 432 .ddb_size = 896
360 433
361static const struct intel_device_info intel_skylake_info = { 434static const struct intel_device_info intel_skylake_gt1_info __initconst = {
362 SKL_PLATFORM, 435 SKL_PLATFORM,
436 .gt = 1,
363}; 437};
364 438
365static const struct intel_device_info intel_skylake_gt3_info = { 439static const struct intel_device_info intel_skylake_gt2_info __initconst = {
366 SKL_PLATFORM, 440 SKL_PLATFORM,
367 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 441 .gt = 2,
442};
443
444#define SKL_GT3_PLUS_PLATFORM \
445 SKL_PLATFORM, \
446 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
447
448
449static const struct intel_device_info intel_skylake_gt3_info __initconst = {
450 SKL_GT3_PLUS_PLATFORM,
451 .gt = 3,
452};
453
454static const struct intel_device_info intel_skylake_gt4_info __initconst = {
455 SKL_GT3_PLUS_PLATFORM,
456 .gt = 4,
368}; 457};
369 458
370#define GEN9_LP_FEATURES \ 459#define GEN9_LP_FEATURES \
@@ -390,18 +479,18 @@ static const struct intel_device_info intel_skylake_gt3_info = {
390 .has_full_ppgtt = 1, \ 479 .has_full_ppgtt = 1, \
391 .has_full_48bit_ppgtt = 1, \ 480 .has_full_48bit_ppgtt = 1, \
392 .has_reset_engine = 1, \ 481 .has_reset_engine = 1, \
482 .has_snoop = true, \
393 GEN_DEFAULT_PIPEOFFSETS, \ 483 GEN_DEFAULT_PIPEOFFSETS, \
394 IVB_CURSOR_OFFSETS, \ 484 IVB_CURSOR_OFFSETS, \
395 BDW_COLORS 485 BDW_COLORS
396 486
397static const struct intel_device_info intel_broxton_info = { 487static const struct intel_device_info intel_broxton_info __initconst = {
398 GEN9_LP_FEATURES, 488 GEN9_LP_FEATURES,
399 .platform = INTEL_BROXTON, 489 .platform = INTEL_BROXTON,
400 .ddb_size = 512, 490 .ddb_size = 512,
401 .has_reset_engine = false,
402}; 491};
403 492
404static const struct intel_device_info intel_geminilake_info = { 493static const struct intel_device_info intel_geminilake_info __initconst = {
405 GEN9_LP_FEATURES, 494 GEN9_LP_FEATURES,
406 .platform = INTEL_GEMINILAKE, 495 .platform = INTEL_GEMINILAKE,
407 .ddb_size = 1024, 496 .ddb_size = 1024,
@@ -416,12 +505,19 @@ static const struct intel_device_info intel_geminilake_info = {
416 .has_guc = 1, \ 505 .has_guc = 1, \
417 .ddb_size = 896 506 .ddb_size = 896
418 507
419static const struct intel_device_info intel_kabylake_info = { 508static const struct intel_device_info intel_kabylake_gt1_info __initconst = {
420 KBL_PLATFORM, 509 KBL_PLATFORM,
510 .gt = 1,
421}; 511};
422 512
423static const struct intel_device_info intel_kabylake_gt3_info = { 513static const struct intel_device_info intel_kabylake_gt2_info __initconst = {
424 KBL_PLATFORM, 514 KBL_PLATFORM,
515 .gt = 2,
516};
517
518static const struct intel_device_info intel_kabylake_gt3_info __initconst = {
519 KBL_PLATFORM,
520 .gt = 3,
425 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 521 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
426}; 522};
427 523
@@ -434,20 +530,28 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
434 .has_guc = 1, \ 530 .has_guc = 1, \
435 .ddb_size = 896 531 .ddb_size = 896
436 532
437static const struct intel_device_info intel_coffeelake_info = { 533static const struct intel_device_info intel_coffeelake_gt1_info __initconst = {
534 CFL_PLATFORM,
535 .gt = 1,
536};
537
538static const struct intel_device_info intel_coffeelake_gt2_info __initconst = {
438 CFL_PLATFORM, 539 CFL_PLATFORM,
540 .gt = 2,
439}; 541};
440 542
441static const struct intel_device_info intel_coffeelake_gt3_info = { 543static const struct intel_device_info intel_coffeelake_gt3_info __initconst = {
442 CFL_PLATFORM, 544 CFL_PLATFORM,
545 .gt = 3,
443 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 546 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
444}; 547};
445 548
446static const struct intel_device_info intel_cannonlake_info = { 549static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
447 BDW_FEATURES, 550 BDW_FEATURES,
448 .is_alpha_support = 1, 551 .is_alpha_support = 1,
449 .platform = INTEL_CANNONLAKE, 552 .platform = INTEL_CANNONLAKE,
450 .gen = 10, 553 .gen = 10,
554 .gt = 2,
451 .ddb_size = 1024, 555 .ddb_size = 1024,
452 .has_csr = 1, 556 .has_csr = 1,
453 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } 557 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
@@ -476,31 +580,40 @@ static const struct pci_device_id pciidlist[] = {
476 INTEL_PINEVIEW_IDS(&intel_pineview_info), 580 INTEL_PINEVIEW_IDS(&intel_pineview_info),
477 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 581 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
478 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 582 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
479 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), 583 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
480 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), 584 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
585 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
586 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
481 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 587 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
482 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 588 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
483 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 589 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
484 INTEL_HSW_IDS(&intel_haswell_info), 590 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
591 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
592 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
593 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
594 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
485 INTEL_VLV_IDS(&intel_valleyview_info), 595 INTEL_VLV_IDS(&intel_valleyview_info),
486 INTEL_BDW_GT12_IDS(&intel_broadwell_info), 596 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
597 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
487 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 598 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
488 INTEL_BDW_RSVD_IDS(&intel_broadwell_info), 599 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
489 INTEL_CHV_IDS(&intel_cherryview_info), 600 INTEL_CHV_IDS(&intel_cherryview_info),
490 INTEL_SKL_GT1_IDS(&intel_skylake_info), 601 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
491 INTEL_SKL_GT2_IDS(&intel_skylake_info), 602 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
492 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 603 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
493 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), 604 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
494 INTEL_BXT_IDS(&intel_broxton_info), 605 INTEL_BXT_IDS(&intel_broxton_info),
495 INTEL_GLK_IDS(&intel_geminilake_info), 606 INTEL_GLK_IDS(&intel_geminilake_info),
496 INTEL_KBL_GT1_IDS(&intel_kabylake_info), 607 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
497 INTEL_KBL_GT2_IDS(&intel_kabylake_info), 608 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
498 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 609 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
499 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 610 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
500 INTEL_CFL_S_IDS(&intel_coffeelake_info), 611 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
501 INTEL_CFL_H_IDS(&intel_coffeelake_info), 612 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
502 INTEL_CFL_U_IDS(&intel_coffeelake_gt3_info), 613 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
503 INTEL_CNL_IDS(&intel_cannonlake_info), 614 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
615 INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
616 INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
504 {0, 0, 0} 617 {0, 0, 0}
505}; 618};
506MODULE_DEVICE_TABLE(pci, pciidlist); 619MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed7cd9ee2c2a..2eff98cdcfad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2373,6 +2373,7 @@ enum i915_power_well_id {
2373 2373
2374#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 2374#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2375#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28) 2375#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
2376#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
2376 2377
2377#if 0 2378#if 0
2378#define PRB0_TAIL _MMIO(0x2030) 2379#define PRB0_TAIL _MMIO(0x2030)
@@ -2491,6 +2492,7 @@ enum i915_power_well_id {
2491# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 2492# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2492#define _3D_CHICKEN3 _MMIO(0x2090) 2493#define _3D_CHICKEN3 _MMIO(0x2090)
2493#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 2494#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2495#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2494#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 2496#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2495#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ 2497#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
2496#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 2498#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
@@ -2938,6 +2940,9 @@ enum i915_power_well_id {
2938#define ILK_DPFC_CHICKEN _MMIO(0x43224) 2940#define ILK_DPFC_CHICKEN _MMIO(0x43224)
2939#define ILK_DPFC_DISABLE_DUMMY0 (1<<8) 2941#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
2940#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23) 2942#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
2943#define GLK_SKIP_SEG_EN (1<<12)
2944#define GLK_SKIP_SEG_COUNT_MASK (3<<10)
2945#define GLK_SKIP_SEG_COUNT(x) ((x)<<10)
2941#define ILK_FBC_RT_BASE _MMIO(0x2128) 2946#define ILK_FBC_RT_BASE _MMIO(0x2128)
2942#define ILK_FBC_RT_VALID (1<<0) 2947#define ILK_FBC_RT_VALID (1<<0)
2943#define SNB_FBC_FRONT_BUFFER (1<<1) 2948#define SNB_FBC_FRONT_BUFFER (1<<1)
@@ -3807,6 +3812,12 @@ enum {
3807#define PWM1_GATING_DIS (1 << 13) 3812#define PWM1_GATING_DIS (1 << 13)
3808 3813
3809/* 3814/*
3815 * GEN10 clock gating regs
3816 */
3817#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
3818#define SARBUNIT_CLKGATE_DIS (1 << 5)
3819
3820/*
3810 * Display engine regs 3821 * Display engine regs
3811 */ 3822 */
3812 3823
@@ -6916,6 +6927,10 @@ enum {
6916#define GLK_CL1_PWR_DOWN (1 << 11) 6927#define GLK_CL1_PWR_DOWN (1 << 11)
6917#define GLK_CL0_PWR_DOWN (1 << 10) 6928#define GLK_CL0_PWR_DOWN (1 << 10)
6918 6929
6930#define CHICKEN_MISC_4 _MMIO(0x4208c)
6931#define FBC_STRIDE_OVERRIDE (1 << 13)
6932#define FBC_STRIDE_MASK 0x1FFF
6933
6919#define _CHICKEN_PIPESL_1_A 0x420b0 6934#define _CHICKEN_PIPESL_1_A 0x420b0
6920#define _CHICKEN_PIPESL_1_B 0x420b4 6935#define _CHICKEN_PIPESL_1_B 0x420b4
6921#define HSW_FBCQ_DIS (1 << 22) 6936#define HSW_FBCQ_DIS (1 << 22)
@@ -7017,6 +7032,7 @@ enum {
7017 7032
7018/* GEN8 chicken */ 7033/* GEN8 chicken */
7019#define HDC_CHICKEN0 _MMIO(0x7300) 7034#define HDC_CHICKEN0 _MMIO(0x7300)
7035#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
7020#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) 7036#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
7021#define HDC_FENCE_DEST_SLM_DISABLE (1<<14) 7037#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
7022#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) 7038#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
@@ -7470,6 +7486,7 @@ enum {
7470#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 7486#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
7471#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 7487#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
7472#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 7488#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
7489#define CNP_PWM_CGE_GATING_DISABLE (1<<13)
7473#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 7490#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
7474 7491
7475/* CPU: FDI_TX */ 7492/* CPU: FDI_TX */
@@ -8044,10 +8061,12 @@ enum {
8044#define FLOW_CONTROL_ENABLE (1<<15) 8061#define FLOW_CONTROL_ENABLE (1<<15)
8045#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) 8062#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
8046#define STALL_DOP_GATING_DISABLE (1<<5) 8063#define STALL_DOP_GATING_DISABLE (1<<5)
8064#define THROTTLE_12_5 (7<<2)
8047 8065
8048#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 8066#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
8049#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 8067#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
8050#define DOP_CLOCK_GATING_DISABLE (1<<0) 8068#define DOP_CLOCK_GATING_DISABLE (1<<0)
8069#define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
8051 8070
8052#define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 8071#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
8053#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 8072#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
@@ -8059,6 +8078,7 @@ enum {
8059#define HSW_SAMPLE_C_PERFORMANCE (1<<9) 8078#define HSW_SAMPLE_C_PERFORMANCE (1<<9)
8060#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 8079#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
8061#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) 8080#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
8081#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
8062#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 8082#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
8063 8083
8064#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) 8084#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 6fd5c57e21f6..92f4c5bb7aa7 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -1031,5 +1031,5 @@ TRACE_EVENT(switch_mm,
1031 1031
1032/* This part must be outside protection */ 1032/* This part must be outside protection */
1033#undef TRACE_INCLUDE_PATH 1033#undef TRACE_INCLUDE_PATH
1034#define TRACE_INCLUDE_PATH . 1034#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915
1035#include <trace/define_trace.h> 1035#include <trace/define_trace.h>
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index ee76fab7bb6f..8e6dc159f64d 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -107,7 +107,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
107 drm_atomic_helper_plane_destroy_state(plane, state); 107 drm_atomic_helper_plane_destroy_state(plane, state);
108} 108}
109 109
110int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state, 110int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
111 struct intel_crtc_state *crtc_state,
112 const struct intel_plane_state *old_plane_state,
111 struct intel_plane_state *intel_state) 113 struct intel_plane_state *intel_state)
112{ 114{
113 struct drm_plane *plane = intel_state->base.plane; 115 struct drm_plane *plane = intel_state->base.plane;
@@ -124,7 +126,7 @@ int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
124 * anything driver-specific we need to test in that case, so 126 * anything driver-specific we need to test in that case, so
125 * just return success. 127 * just return success.
126 */ 128 */
127 if (!intel_state->base.crtc && !plane->state->crtc) 129 if (!intel_state->base.crtc && !old_plane_state->base.crtc)
128 return 0; 130 return 0;
129 131
130 /* Clip all planes to CRTC size, or 0x0 if CRTC is disabled */ 132 /* Clip all planes to CRTC size, or 0x0 if CRTC is disabled */
@@ -194,16 +196,21 @@ int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
194 else 196 else
195 crtc_state->active_planes &= ~BIT(intel_plane->id); 197 crtc_state->active_planes &= ~BIT(intel_plane->id);
196 198
197 return intel_plane_atomic_calc_changes(&crtc_state->base, state); 199 return intel_plane_atomic_calc_changes(old_crtc_state,
200 &crtc_state->base,
201 old_plane_state,
202 state);
198} 203}
199 204
200static int intel_plane_atomic_check(struct drm_plane *plane, 205static int intel_plane_atomic_check(struct drm_plane *plane,
201 struct drm_plane_state *state) 206 struct drm_plane_state *new_plane_state)
202{ 207{
203 struct drm_crtc *crtc = state->crtc; 208 struct drm_atomic_state *state = new_plane_state->state;
204 struct drm_crtc_state *drm_crtc_state; 209 const struct drm_plane_state *old_plane_state =
205 210 drm_atomic_get_old_plane_state(state, plane);
206 crtc = crtc ? crtc : plane->state->crtc; 211 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
212 const struct drm_crtc_state *old_crtc_state;
213 struct drm_crtc_state *new_crtc_state;
207 214
208 /* 215 /*
209 * Both crtc and plane->crtc could be NULL if we're updating a 216 * Both crtc and plane->crtc could be NULL if we're updating a
@@ -214,29 +221,33 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
214 if (!crtc) 221 if (!crtc)
215 return 0; 222 return 0;
216 223
217 drm_crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 224 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
218 if (WARN_ON(!drm_crtc_state)) 225 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
219 return -EINVAL;
220 226
221 return intel_plane_atomic_check_with_state(to_intel_crtc_state(drm_crtc_state), 227 return intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state),
222 to_intel_plane_state(state)); 228 to_intel_crtc_state(new_crtc_state),
229 to_intel_plane_state(old_plane_state),
230 to_intel_plane_state(new_plane_state));
223} 231}
224 232
225static void intel_plane_atomic_update(struct drm_plane *plane, 233static void intel_plane_atomic_update(struct drm_plane *plane,
226 struct drm_plane_state *old_state) 234 struct drm_plane_state *old_state)
227{ 235{
236 struct intel_atomic_state *state = to_intel_atomic_state(old_state->state);
228 struct intel_plane *intel_plane = to_intel_plane(plane); 237 struct intel_plane *intel_plane = to_intel_plane(plane);
229 struct intel_plane_state *intel_state = 238 const struct intel_plane_state *new_plane_state =
230 to_intel_plane_state(plane->state); 239 intel_atomic_get_new_plane_state(state, intel_plane);
231 struct drm_crtc *crtc = plane->state->crtc ?: old_state->crtc; 240 struct drm_crtc *crtc = new_plane_state->base.crtc ?: old_state->crtc;
241
242 if (new_plane_state->base.visible) {
243 const struct intel_crtc_state *new_crtc_state =
244 intel_atomic_get_new_crtc_state(state, to_intel_crtc(crtc));
232 245
233 if (intel_state->base.visible) {
234 trace_intel_update_plane(plane, 246 trace_intel_update_plane(plane,
235 to_intel_crtc(crtc)); 247 to_intel_crtc(crtc));
236 248
237 intel_plane->update_plane(intel_plane, 249 intel_plane->update_plane(intel_plane,
238 to_intel_crtc_state(crtc->state), 250 new_crtc_state, new_plane_state);
239 intel_state);
240 } else { 251 } else {
241 trace_intel_disable_plane(plane, 252 trace_intel_disable_plane(plane,
242 to_intel_crtc(crtc)); 253 to_intel_crtc(crtc));
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 183e87e8ea31..5949750a35ee 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -452,24 +452,24 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
452 } 452 }
453} 453}
454 454
455static const union child_device_config * 455static const struct child_device_config *
456child_device_ptr(const struct bdb_general_definitions *p_defs, int i) 456child_device_ptr(const struct bdb_general_definitions *defs, int i)
457{ 457{
458 return (const void *) &p_defs->devices[i * p_defs->child_dev_size]; 458 return (const void *) &defs->devices[i * defs->child_dev_size];
459} 459}
460 460
461static void 461static void
462parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, 462parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
463 const struct bdb_header *bdb) 463 const struct bdb_header *bdb)
464{ 464{
465 struct sdvo_device_mapping *p_mapping; 465 struct sdvo_device_mapping *mapping;
466 const struct bdb_general_definitions *p_defs; 466 const struct bdb_general_definitions *defs;
467 const struct old_child_dev_config *child; /* legacy */ 467 const struct child_device_config *child;
468 int i, child_device_num, count; 468 int i, child_device_num, count;
469 u16 block_size; 469 u16 block_size;
470 470
471 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); 471 defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
472 if (!p_defs) { 472 if (!defs) {
473 DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n"); 473 DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
474 return; 474 return;
475 } 475 }
@@ -479,18 +479,17 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
479 * device size matches that of the *legacy* child device config 479 * device size matches that of the *legacy* child device config
480 * struct. Thus, SDVO mapping will be skipped for newer VBT. 480 * struct. Thus, SDVO mapping will be skipped for newer VBT.
481 */ 481 */
482 if (p_defs->child_dev_size != sizeof(*child)) { 482 if (defs->child_dev_size != LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
483 DRM_DEBUG_KMS("Unsupported child device size for SDVO mapping.\n"); 483 DRM_DEBUG_KMS("Unsupported child device size for SDVO mapping.\n");
484 return; 484 return;
485 } 485 }
486 /* get the block size of general definitions */ 486 /* get the block size of general definitions */
487 block_size = get_blocksize(p_defs); 487 block_size = get_blocksize(defs);
488 /* get the number of child device */ 488 /* get the number of child device */
489 child_device_num = (block_size - sizeof(*p_defs)) / 489 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
490 p_defs->child_dev_size;
491 count = 0; 490 count = 0;
492 for (i = 0; i < child_device_num; i++) { 491 for (i = 0; i < child_device_num; i++) {
493 child = &child_device_ptr(p_defs, i)->old; 492 child = child_device_ptr(defs, i);
494 if (!child->device_type) { 493 if (!child->device_type) {
495 /* skip the device block if device type is invalid */ 494 /* skip the device block if device type is invalid */
496 continue; 495 continue;
@@ -514,20 +513,20 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
514 child->slave_addr, 513 child->slave_addr,
515 (child->dvo_port == DEVICE_PORT_DVOB) ? 514 (child->dvo_port == DEVICE_PORT_DVOB) ?
516 "SDVOB" : "SDVOC"); 515 "SDVOB" : "SDVOC");
517 p_mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1]; 516 mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1];
518 if (!p_mapping->initialized) { 517 if (!mapping->initialized) {
519 p_mapping->dvo_port = child->dvo_port; 518 mapping->dvo_port = child->dvo_port;
520 p_mapping->slave_addr = child->slave_addr; 519 mapping->slave_addr = child->slave_addr;
521 p_mapping->dvo_wiring = child->dvo_wiring; 520 mapping->dvo_wiring = child->dvo_wiring;
522 p_mapping->ddc_pin = child->ddc_pin; 521 mapping->ddc_pin = child->ddc_pin;
523 p_mapping->i2c_pin = child->i2c_pin; 522 mapping->i2c_pin = child->i2c_pin;
524 p_mapping->initialized = 1; 523 mapping->initialized = 1;
525 DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", 524 DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
526 p_mapping->dvo_port, 525 mapping->dvo_port,
527 p_mapping->slave_addr, 526 mapping->slave_addr,
528 p_mapping->dvo_wiring, 527 mapping->dvo_wiring,
529 p_mapping->ddc_pin, 528 mapping->ddc_pin,
530 p_mapping->i2c_pin); 529 mapping->i2c_pin);
531 } else { 530 } else {
532 DRM_DEBUG_KMS("Maybe one SDVO port is shared by " 531 DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
533 "two SDVO device.\n"); 532 "two SDVO device.\n");
@@ -577,7 +576,7 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
577{ 576{
578 const struct bdb_edp *edp; 577 const struct bdb_edp *edp;
579 const struct edp_power_seq *edp_pps; 578 const struct edp_power_seq *edp_pps;
580 const struct edp_link_params *edp_link_params; 579 const struct edp_fast_link_params *edp_link_params;
581 int panel_type = dev_priv->vbt.panel_type; 580 int panel_type = dev_priv->vbt.panel_type;
582 581
583 edp = find_section(bdb, BDB_EDP); 582 edp = find_section(bdb, BDB_EDP);
@@ -601,7 +600,7 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
601 600
602 /* Get the eDP sequencing and link info */ 601 /* Get the eDP sequencing and link info */
603 edp_pps = &edp->power_seqs[panel_type]; 602 edp_pps = &edp->power_seqs[panel_type];
604 edp_link_params = &edp->link_params[panel_type]; 603 edp_link_params = &edp->fast_link_params[panel_type];
605 604
606 dev_priv->vbt.edp.pps = *edp_pps; 605 dev_priv->vbt.edp.pps = *edp_pps;
607 606
@@ -1113,7 +1112,7 @@ static void sanitize_aux_ch(struct drm_i915_private *dev_priv,
1113static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, 1112static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
1114 const struct bdb_header *bdb) 1113 const struct bdb_header *bdb)
1115{ 1114{
1116 union child_device_config *it, *child = NULL; 1115 struct child_device_config *it, *child = NULL;
1117 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; 1116 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1118 uint8_t hdmi_level_shift; 1117 uint8_t hdmi_level_shift;
1119 int i, j; 1118 int i, j;
@@ -1141,7 +1140,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
1141 if (dvo_ports[port][j] == -1) 1140 if (dvo_ports[port][j] == -1)
1142 break; 1141 break;
1143 1142
1144 if (it->common.dvo_port == dvo_ports[port][j]) { 1143 if (it->dvo_port == dvo_ports[port][j]) {
1145 if (child) { 1144 if (child) {
1146 DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n", 1145 DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n",
1147 port_name(port)); 1146 port_name(port));
@@ -1154,14 +1153,14 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
1154 if (!child) 1153 if (!child)
1155 return; 1154 return;
1156 1155
1157 aux_channel = child->common.aux_channel; 1156 aux_channel = child->aux_channel;
1158 ddc_pin = child->common.ddc_pin; 1157 ddc_pin = child->ddc_pin;
1159 1158
1160 is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; 1159 is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
1161 is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; 1160 is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
1162 is_crt = child->common.device_type & DEVICE_TYPE_ANALOG_OUTPUT; 1161 is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT;
1163 is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; 1162 is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
1164 is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR); 1163 is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
1165 1164
1166 info->supports_dvi = is_dvi; 1165 info->supports_dvi = is_dvi;
1167 info->supports_hdmi = is_hdmi; 1166 info->supports_hdmi = is_hdmi;
@@ -1210,7 +1209,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
1210 1209
1211 if (bdb->version >= 158) { 1210 if (bdb->version >= 158) {
1212 /* The VBT HDMI level shift values match the table we have. */ 1211 /* The VBT HDMI level shift values match the table we have. */
1213 hdmi_level_shift = child->raw[7] & 0xF; 1212 hdmi_level_shift = child->hdmi_level_shifter_value;
1214 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n", 1213 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
1215 port_name(port), 1214 port_name(port),
1216 hdmi_level_shift); 1215 hdmi_level_shift);
@@ -1218,11 +1217,11 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
1218 } 1217 }
1219 1218
1220 /* Parse the I_boost config for SKL and above */ 1219 /* Parse the I_boost config for SKL and above */
1221 if (bdb->version >= 196 && child->common.iboost) { 1220 if (bdb->version >= 196 && child->iboost) {
1222 info->dp_boost_level = translate_iboost(child->common.iboost_level & 0xF); 1221 info->dp_boost_level = translate_iboost(child->dp_iboost_level);
1223 DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n", 1222 DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n",
1224 port_name(port), info->dp_boost_level); 1223 port_name(port), info->dp_boost_level);
1225 info->hdmi_boost_level = translate_iboost(child->common.iboost_level >> 4); 1224 info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level);
1226 DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n", 1225 DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
1227 port_name(port), info->hdmi_boost_level); 1226 port_name(port), info->hdmi_boost_level);
1228 } 1227 }
@@ -1250,15 +1249,15 @@ static void
1250parse_device_mapping(struct drm_i915_private *dev_priv, 1249parse_device_mapping(struct drm_i915_private *dev_priv,
1251 const struct bdb_header *bdb) 1250 const struct bdb_header *bdb)
1252{ 1251{
1253 const struct bdb_general_definitions *p_defs; 1252 const struct bdb_general_definitions *defs;
1254 const union child_device_config *p_child; 1253 const struct child_device_config *child;
1255 union child_device_config *child_dev_ptr; 1254 struct child_device_config *child_dev_ptr;
1256 int i, child_device_num, count; 1255 int i, child_device_num, count;
1257 u8 expected_size; 1256 u8 expected_size;
1258 u16 block_size; 1257 u16 block_size;
1259 1258
1260 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); 1259 defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
1261 if (!p_defs) { 1260 if (!defs) {
1262 DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n"); 1261 DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
1263 return; 1262 return;
1264 } 1263 }
@@ -1267,41 +1266,39 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
1267 } else if (bdb->version < 111) { 1266 } else if (bdb->version < 111) {
1268 expected_size = 27; 1267 expected_size = 27;
1269 } else if (bdb->version < 195) { 1268 } else if (bdb->version < 195) {
1270 BUILD_BUG_ON(sizeof(struct old_child_dev_config) != 33); 1269 expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
1271 expected_size = sizeof(struct old_child_dev_config);
1272 } else if (bdb->version == 195) { 1270 } else if (bdb->version == 195) {
1273 expected_size = 37; 1271 expected_size = 37;
1274 } else if (bdb->version <= 197) { 1272 } else if (bdb->version <= 197) {
1275 expected_size = 38; 1273 expected_size = 38;
1276 } else { 1274 } else {
1277 expected_size = 38; 1275 expected_size = 38;
1278 BUILD_BUG_ON(sizeof(*p_child) < 38); 1276 BUILD_BUG_ON(sizeof(*child) < 38);
1279 DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n", 1277 DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n",
1280 bdb->version, expected_size); 1278 bdb->version, expected_size);
1281 } 1279 }
1282 1280
1283 /* Flag an error for unexpected size, but continue anyway. */ 1281 /* Flag an error for unexpected size, but continue anyway. */
1284 if (p_defs->child_dev_size != expected_size) 1282 if (defs->child_dev_size != expected_size)
1285 DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n", 1283 DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n",
1286 p_defs->child_dev_size, expected_size, bdb->version); 1284 defs->child_dev_size, expected_size, bdb->version);
1287 1285
1288 /* The legacy sized child device config is the minimum we need. */ 1286 /* The legacy sized child device config is the minimum we need. */
1289 if (p_defs->child_dev_size < sizeof(struct old_child_dev_config)) { 1287 if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
1290 DRM_DEBUG_KMS("Child device config size %u is too small.\n", 1288 DRM_DEBUG_KMS("Child device config size %u is too small.\n",
1291 p_defs->child_dev_size); 1289 defs->child_dev_size);
1292 return; 1290 return;
1293 } 1291 }
1294 1292
1295 /* get the block size of general definitions */ 1293 /* get the block size of general definitions */
1296 block_size = get_blocksize(p_defs); 1294 block_size = get_blocksize(defs);
1297 /* get the number of child device */ 1295 /* get the number of child device */
1298 child_device_num = (block_size - sizeof(*p_defs)) / 1296 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
1299 p_defs->child_dev_size;
1300 count = 0; 1297 count = 0;
1301 /* get the number of child device that is present */ 1298 /* get the number of child device that is present */
1302 for (i = 0; i < child_device_num; i++) { 1299 for (i = 0; i < child_device_num; i++) {
1303 p_child = child_device_ptr(p_defs, i); 1300 child = child_device_ptr(defs, i);
1304 if (!p_child->common.device_type) { 1301 if (!child->device_type) {
1305 /* skip the device block if device type is invalid */ 1302 /* skip the device block if device type is invalid */
1306 continue; 1303 continue;
1307 } 1304 }
@@ -1311,7 +1308,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
1311 DRM_DEBUG_KMS("no child dev is parsed from VBT\n"); 1308 DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
1312 return; 1309 return;
1313 } 1310 }
1314 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL); 1311 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL);
1315 if (!dev_priv->vbt.child_dev) { 1312 if (!dev_priv->vbt.child_dev) {
1316 DRM_DEBUG_KMS("No memory space for child device\n"); 1313 DRM_DEBUG_KMS("No memory space for child device\n");
1317 return; 1314 return;
@@ -1320,8 +1317,8 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
1320 dev_priv->vbt.child_dev_num = count; 1317 dev_priv->vbt.child_dev_num = count;
1321 count = 0; 1318 count = 0;
1322 for (i = 0; i < child_device_num; i++) { 1319 for (i = 0; i < child_device_num; i++) {
1323 p_child = child_device_ptr(p_defs, i); 1320 child = child_device_ptr(defs, i);
1324 if (!p_child->common.device_type) { 1321 if (!child->device_type) {
1325 /* skip the device block if device type is invalid */ 1322 /* skip the device block if device type is invalid */
1326 continue; 1323 continue;
1327 } 1324 }
@@ -1334,8 +1331,8 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
1334 * (child_dev_size) of the child device. Accessing the data must 1331 * (child_dev_size) of the child device. Accessing the data must
1335 * depend on VBT version. 1332 * depend on VBT version.
1336 */ 1333 */
1337 memcpy(child_dev_ptr, p_child, 1334 memcpy(child_dev_ptr, child,
1338 min_t(size_t, p_defs->child_dev_size, sizeof(*p_child))); 1335 min_t(size_t, defs->child_dev_size, sizeof(*child)));
1339 1336
1340 /* 1337 /*
1341 * copied full block, now init values when they are not 1338 * copied full block, now init values when they are not
@@ -1343,12 +1340,12 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
1343 */ 1340 */
1344 if (bdb->version < 196) { 1341 if (bdb->version < 196) {
1345 /* Set default values for bits added from v196 */ 1342 /* Set default values for bits added from v196 */
1346 child_dev_ptr->common.iboost = 0; 1343 child_dev_ptr->iboost = 0;
1347 child_dev_ptr->common.hpd_invert = 0; 1344 child_dev_ptr->hpd_invert = 0;
1348 } 1345 }
1349 1346
1350 if (bdb->version < 192) 1347 if (bdb->version < 192)
1351 child_dev_ptr->common.lspcon = 0; 1348 child_dev_ptr->lspcon = 0;
1352 } 1349 }
1353 return; 1350 return;
1354} 1351}
@@ -1559,7 +1556,7 @@ out:
1559 */ 1556 */
1560bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv) 1557bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
1561{ 1558{
1562 union child_device_config *p_child; 1559 const struct child_device_config *child;
1563 int i; 1560 int i;
1564 1561
1565 if (!dev_priv->vbt.int_tv_support) 1562 if (!dev_priv->vbt.int_tv_support)
@@ -1569,11 +1566,11 @@ bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
1569 return true; 1566 return true;
1570 1567
1571 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 1568 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1572 p_child = dev_priv->vbt.child_dev + i; 1569 child = dev_priv->vbt.child_dev + i;
1573 /* 1570 /*
1574 * If the device type is not TV, continue. 1571 * If the device type is not TV, continue.
1575 */ 1572 */
1576 switch (p_child->old.device_type) { 1573 switch (child->device_type) {
1577 case DEVICE_TYPE_INT_TV: 1574 case DEVICE_TYPE_INT_TV:
1578 case DEVICE_TYPE_TV: 1575 case DEVICE_TYPE_TV:
1579 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE: 1576 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
@@ -1584,7 +1581,7 @@ bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
1584 /* Only when the addin_offset is non-zero, it is regarded 1581 /* Only when the addin_offset is non-zero, it is regarded
1585 * as present. 1582 * as present.
1586 */ 1583 */
1587 if (p_child->old.addin_offset) 1584 if (child->addin_offset)
1588 return true; 1585 return true;
1589 } 1586 }
1590 1587
@@ -1601,14 +1598,14 @@ bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
1601 */ 1598 */
1602bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin) 1599bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)
1603{ 1600{
1601 const struct child_device_config *child;
1604 int i; 1602 int i;
1605 1603
1606 if (!dev_priv->vbt.child_dev_num) 1604 if (!dev_priv->vbt.child_dev_num)
1607 return true; 1605 return true;
1608 1606
1609 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 1607 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1610 union child_device_config *uchild = dev_priv->vbt.child_dev + i; 1608 child = dev_priv->vbt.child_dev + i;
1611 struct old_child_dev_config *child = &uchild->old;
1612 1609
1613 /* If the device type is not LFP, continue. 1610 /* If the device type is not LFP, continue.
1614 * We have to check both the new identifiers as well as the 1611 * We have to check both the new identifiers as well as the
@@ -1650,6 +1647,7 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)
1650 */ 1647 */
1651bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port) 1648bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port)
1652{ 1649{
1650 const struct child_device_config *child;
1653 static const struct { 1651 static const struct {
1654 u16 dp, hdmi; 1652 u16 dp, hdmi;
1655 } port_mapping[] = { 1653 } port_mapping[] = {
@@ -1668,12 +1666,12 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por
1668 return false; 1666 return false;
1669 1667
1670 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 1668 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1671 const union child_device_config *p_child = 1669 child = dev_priv->vbt.child_dev + i;
1672 &dev_priv->vbt.child_dev[i]; 1670
1673 if ((p_child->common.dvo_port == port_mapping[port].dp || 1671 if ((child->dvo_port == port_mapping[port].dp ||
1674 p_child->common.dvo_port == port_mapping[port].hdmi) && 1672 child->dvo_port == port_mapping[port].hdmi) &&
1675 (p_child->common.device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING | 1673 (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
1676 DEVICE_TYPE_DISPLAYPORT_OUTPUT))) 1674 DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
1677 return true; 1675 return true;
1678 } 1676 }
1679 1677
@@ -1689,7 +1687,7 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por
1689 */ 1687 */
1690bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port) 1688bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
1691{ 1689{
1692 union child_device_config *p_child; 1690 const struct child_device_config *child;
1693 static const short port_mapping[] = { 1691 static const short port_mapping[] = {
1694 [PORT_B] = DVO_PORT_DPB, 1692 [PORT_B] = DVO_PORT_DPB,
1695 [PORT_C] = DVO_PORT_DPC, 1693 [PORT_C] = DVO_PORT_DPC,
@@ -1705,10 +1703,10 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
1705 return false; 1703 return false;
1706 1704
1707 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 1705 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1708 p_child = dev_priv->vbt.child_dev + i; 1706 child = dev_priv->vbt.child_dev + i;
1709 1707
1710 if (p_child->common.dvo_port == port_mapping[port] && 1708 if (child->dvo_port == port_mapping[port] &&
1711 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 1709 (child->device_type & DEVICE_TYPE_eDP_BITS) ==
1712 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 1710 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
1713 return true; 1711 return true;
1714 } 1712 }
@@ -1716,7 +1714,7 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
1716 return false; 1714 return false;
1717} 1715}
1718 1716
1719static bool child_dev_is_dp_dual_mode(const union child_device_config *p_child, 1717static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
1720 enum port port) 1718 enum port port)
1721{ 1719{
1722 static const struct { 1720 static const struct {
@@ -1735,16 +1733,16 @@ static bool child_dev_is_dp_dual_mode(const union child_device_config *p_child,
1735 if (port == PORT_A || port >= ARRAY_SIZE(port_mapping)) 1733 if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
1736 return false; 1734 return false;
1737 1735
1738 if ((p_child->common.device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) != 1736 if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
1739 (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS)) 1737 (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
1740 return false; 1738 return false;
1741 1739
1742 if (p_child->common.dvo_port == port_mapping[port].dp) 1740 if (child->dvo_port == port_mapping[port].dp)
1743 return true; 1741 return true;
1744 1742
1745 /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ 1743 /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */
1746 if (p_child->common.dvo_port == port_mapping[port].hdmi && 1744 if (child->dvo_port == port_mapping[port].hdmi &&
1747 p_child->common.aux_channel != 0) 1745 child->aux_channel != 0)
1748 return true; 1746 return true;
1749 1747
1750 return false; 1748 return false;
@@ -1753,13 +1751,13 @@ static bool child_dev_is_dp_dual_mode(const union child_device_config *p_child,
1753bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, 1751bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv,
1754 enum port port) 1752 enum port port)
1755{ 1753{
1754 const struct child_device_config *child;
1756 int i; 1755 int i;
1757 1756
1758 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 1757 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1759 const union child_device_config *p_child = 1758 child = dev_priv->vbt.child_dev + i;
1760 &dev_priv->vbt.child_dev[i];
1761 1759
1762 if (child_dev_is_dp_dual_mode(p_child, port)) 1760 if (child_dev_is_dp_dual_mode(child, port))
1763 return true; 1761 return true;
1764 } 1762 }
1765 1763
@@ -1776,17 +1774,17 @@ bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv,
1776bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, 1774bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
1777 enum port *port) 1775 enum port *port)
1778{ 1776{
1779 union child_device_config *p_child; 1777 const struct child_device_config *child;
1780 u8 dvo_port; 1778 u8 dvo_port;
1781 int i; 1779 int i;
1782 1780
1783 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 1781 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1784 p_child = dev_priv->vbt.child_dev + i; 1782 child = dev_priv->vbt.child_dev + i;
1785 1783
1786 if (!(p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT)) 1784 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
1787 continue; 1785 continue;
1788 1786
1789 dvo_port = p_child->common.dvo_port; 1787 dvo_port = child->dvo_port;
1790 1788
1791 switch (dvo_port) { 1789 switch (dvo_port) {
1792 case DVO_PORT_MIPIA: 1790 case DVO_PORT_MIPIA:
@@ -1816,16 +1814,19 @@ bool
1816intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, 1814intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
1817 enum port port) 1815 enum port port)
1818{ 1816{
1817 const struct child_device_config *child;
1819 int i; 1818 int i;
1820 1819
1821 if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv))) 1820 if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
1822 return false; 1821 return false;
1823 1822
1824 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 1823 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1825 if (!dev_priv->vbt.child_dev[i].common.hpd_invert) 1824 child = dev_priv->vbt.child_dev + i;
1825
1826 if (!child->hpd_invert)
1826 continue; 1827 continue;
1827 1828
1828 switch (dev_priv->vbt.child_dev[i].common.dvo_port) { 1829 switch (child->dvo_port) {
1829 case DVO_PORT_DPA: 1830 case DVO_PORT_DPA:
1830 case DVO_PORT_HDMIA: 1831 case DVO_PORT_HDMIA:
1831 if (port == PORT_A) 1832 if (port == PORT_A)
@@ -1860,16 +1861,19 @@ bool
1860intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, 1861intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
1861 enum port port) 1862 enum port port)
1862{ 1863{
1864 const struct child_device_config *child;
1863 int i; 1865 int i;
1864 1866
1865 if (!HAS_LSPCON(dev_priv)) 1867 if (!HAS_LSPCON(dev_priv))
1866 return false; 1868 return false;
1867 1869
1868 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 1870 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1869 if (!dev_priv->vbt.child_dev[i].common.lspcon) 1871 child = dev_priv->vbt.child_dev + i;
1872
1873 if (!child->lspcon)
1870 continue; 1874 continue;
1871 1875
1872 switch (dev_priv->vbt.child_dev[i].common.dvo_port) { 1876 switch (child->dvo_port) {
1873 case DVO_PORT_DPA: 1877 case DVO_PORT_DPA:
1874 case DVO_PORT_HDMIA: 1878 case DVO_PORT_HDMIA:
1875 if (port == PORT_A) 1879 if (port == PORT_A)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 1241e5891b29..d32911816fc2 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -417,24 +417,21 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
417 cdclk_state->cdclk = 540000; 417 cdclk_state->cdclk = 540000;
418} 418}
419 419
420static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, 420static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
421 int max_pixclk)
422{ 421{
423 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 422 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
424 333333 : 320000; 423 333333 : 320000;
425 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
426 424
427 /* 425 /*
428 * We seem to get an unstable or solid color picture at 200MHz. 426 * We seem to get an unstable or solid color picture at 200MHz.
429 * Not sure what's wrong. For now use 200MHz only when all pipes 427 * Not sure what's wrong. For now use 200MHz only when all pipes
430 * are off. 428 * are off.
431 */ 429 */
432 if (!IS_CHERRYVIEW(dev_priv) && 430 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
433 max_pixclk > freq_320*limit/100)
434 return 400000; 431 return 400000;
435 else if (max_pixclk > 266667*limit/100) 432 else if (min_cdclk > 266667)
436 return freq_320; 433 return freq_320;
437 else if (max_pixclk > 0) 434 else if (min_cdclk > 0)
438 return 266667; 435 return 266667;
439 else 436 else
440 return 200000; 437 return 200000;
@@ -612,13 +609,13 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
612 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); 609 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
613} 610}
614 611
615static int bdw_calc_cdclk(int max_pixclk) 612static int bdw_calc_cdclk(int min_cdclk)
616{ 613{
617 if (max_pixclk > 540000) 614 if (min_cdclk > 540000)
618 return 675000; 615 return 675000;
619 else if (max_pixclk > 450000) 616 else if (min_cdclk > 450000)
620 return 540000; 617 return 540000;
621 else if (max_pixclk > 337500) 618 else if (min_cdclk > 337500)
622 return 450000; 619 return 450000;
623 else 620 else
624 return 337500; 621 return 337500;
@@ -724,23 +721,23 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
724 cdclk, dev_priv->cdclk.hw.cdclk); 721 cdclk, dev_priv->cdclk.hw.cdclk);
725} 722}
726 723
727static int skl_calc_cdclk(int max_pixclk, int vco) 724static int skl_calc_cdclk(int min_cdclk, int vco)
728{ 725{
729 if (vco == 8640000) { 726 if (vco == 8640000) {
730 if (max_pixclk > 540000) 727 if (min_cdclk > 540000)
731 return 617143; 728 return 617143;
732 else if (max_pixclk > 432000) 729 else if (min_cdclk > 432000)
733 return 540000; 730 return 540000;
734 else if (max_pixclk > 308571) 731 else if (min_cdclk > 308571)
735 return 432000; 732 return 432000;
736 else 733 else
737 return 308571; 734 return 308571;
738 } else { 735 } else {
739 if (max_pixclk > 540000) 736 if (min_cdclk > 540000)
740 return 675000; 737 return 675000;
741 else if (max_pixclk > 450000) 738 else if (min_cdclk > 450000)
742 return 540000; 739 return 540000;
743 else if (max_pixclk > 337500) 740 else if (min_cdclk > 337500)
744 return 450000; 741 return 450000;
745 else 742 else
746 return 337500; 743 return 337500;
@@ -1075,31 +1072,25 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1075 skl_set_cdclk(dev_priv, &cdclk_state); 1072 skl_set_cdclk(dev_priv, &cdclk_state);
1076} 1073}
1077 1074
1078static int bxt_calc_cdclk(int max_pixclk) 1075static int bxt_calc_cdclk(int min_cdclk)
1079{ 1076{
1080 if (max_pixclk > 576000) 1077 if (min_cdclk > 576000)
1081 return 624000; 1078 return 624000;
1082 else if (max_pixclk > 384000) 1079 else if (min_cdclk > 384000)
1083 return 576000; 1080 return 576000;
1084 else if (max_pixclk > 288000) 1081 else if (min_cdclk > 288000)
1085 return 384000; 1082 return 384000;
1086 else if (max_pixclk > 144000) 1083 else if (min_cdclk > 144000)
1087 return 288000; 1084 return 288000;
1088 else 1085 else
1089 return 144000; 1086 return 144000;
1090} 1087}
1091 1088
1092static int glk_calc_cdclk(int max_pixclk) 1089static int glk_calc_cdclk(int min_cdclk)
1093{ 1090{
1094 /* 1091 if (min_cdclk > 158400)
1095 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1096 * as a temporary workaround. Use a higher cdclk instead. (Note that
1097 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1098 * cdclk.)
1099 */
1100 if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
1101 return 316800; 1092 return 316800;
1102 else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100)) 1093 else if (min_cdclk > 79200)
1103 return 158400; 1094 return 158400;
1104 else 1095 else
1105 return 79200; 1096 return 79200;
@@ -1420,11 +1411,11 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1420 bxt_set_cdclk(dev_priv, &cdclk_state); 1411 bxt_set_cdclk(dev_priv, &cdclk_state);
1421} 1412}
1422 1413
1423static int cnl_calc_cdclk(int max_pixclk) 1414static int cnl_calc_cdclk(int min_cdclk)
1424{ 1415{
1425 if (max_pixclk > 336000) 1416 if (min_cdclk > 336000)
1426 return 528000; 1417 return 528000;
1427 else if (max_pixclk > 168000) 1418 else if (min_cdclk > 168000)
1428 return 336000; 1419 return 336000;
1429 else 1420 else
1430 return 168000; 1421 return 168000;
@@ -1732,104 +1723,119 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
1732 dev_priv->display.set_cdclk(dev_priv, cdclk_state); 1723 dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1733} 1724}
1734 1725
1735static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, 1726static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
1736 int pixel_rate) 1727 int pixel_rate)
1728{
1729 if (INTEL_GEN(dev_priv) >= 10)
1730 /*
1731 * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
1732 * once DDI clock voltage requirements are
1733 * handled correctly.
1734 */
1735 return pixel_rate;
1736 else if (IS_GEMINILAKE(dev_priv))
1737 /*
1738 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1739 * as a temporary workaround. Use a higher cdclk instead. (Note that
1740 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1741 * cdclk.)
1742 */
1743 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
1744 else if (IS_GEN9(dev_priv) ||
1745 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1746 return pixel_rate;
1747 else if (IS_CHERRYVIEW(dev_priv))
1748 return DIV_ROUND_UP(pixel_rate * 100, 95);
1749 else
1750 return DIV_ROUND_UP(pixel_rate * 100, 90);
1751}
1752
1753int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
1737{ 1754{
1738 struct drm_i915_private *dev_priv = 1755 struct drm_i915_private *dev_priv =
1739 to_i915(crtc_state->base.crtc->dev); 1756 to_i915(crtc_state->base.crtc->dev);
1757 int min_cdclk;
1758
1759 if (!crtc_state->base.enable)
1760 return 0;
1761
1762 min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
1740 1763
1741 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 1764 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1742 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) 1765 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1743 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); 1766 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
1744 1767
1745 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 1768 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1746 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 1769 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1747 * there may be audio corruption or screen corruption." This cdclk 1770 * there may be audio corruption or screen corruption." This cdclk
1748 * restriction for GLK is 316.8 MHz and since GLK can output two 1771 * restriction for GLK is 316.8 MHz.
1749 * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.
1750 */ 1772 */
1751 if (intel_crtc_has_dp_encoder(crtc_state) && 1773 if (intel_crtc_has_dp_encoder(crtc_state) &&
1752 crtc_state->has_audio && 1774 crtc_state->has_audio &&
1753 crtc_state->port_clock >= 540000 && 1775 crtc_state->port_clock >= 540000 &&
1754 crtc_state->lane_count == 4) { 1776 crtc_state->lane_count == 4) {
1755 if (IS_CANNONLAKE(dev_priv)) 1777 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1756 pixel_rate = max(316800, pixel_rate); 1778 /* Display WA #1145: glk,cnl */
1757 else if (IS_GEMINILAKE(dev_priv)) 1779 min_cdclk = max(316800, min_cdclk);
1758 pixel_rate = max(2 * 316800, pixel_rate); 1780 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
1759 else 1781 /* Display WA #1144: skl,bxt */
1760 pixel_rate = max(432000, pixel_rate); 1782 min_cdclk = max(432000, min_cdclk);
1783 }
1761 } 1784 }
1762 1785
1763 /* According to BSpec, "The CD clock frequency must be at least twice 1786 /* According to BSpec, "The CD clock frequency must be at least twice
1764 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 1787 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1765 * The check for GLK has to be adjusted as the platform can output
1766 * two pixels per clock.
1767 */ 1788 */
1768 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) { 1789 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
1769 if (IS_GEMINILAKE(dev_priv)) 1790 min_cdclk = max(2 * 96000, min_cdclk);
1770 pixel_rate = max(2 * 2 * 96000, pixel_rate); 1791
1771 else 1792 if (min_cdclk > dev_priv->max_cdclk_freq) {
1772 pixel_rate = max(2 * 96000, pixel_rate); 1793 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
1794 min_cdclk, dev_priv->max_cdclk_freq);
1795 return -EINVAL;
1773 } 1796 }
1774 1797
1775 return pixel_rate; 1798 return min_cdclk;
1776} 1799}
1777 1800
1778/* compute the max rate for new configuration */ 1801static int intel_compute_min_cdclk(struct drm_atomic_state *state)
1779static int intel_max_pixel_rate(struct drm_atomic_state *state)
1780{ 1802{
1781 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 1803 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1782 struct drm_i915_private *dev_priv = to_i915(state->dev); 1804 struct drm_i915_private *dev_priv = to_i915(state->dev);
1783 struct drm_crtc *crtc; 1805 struct intel_crtc *crtc;
1784 struct drm_crtc_state *cstate;
1785 struct intel_crtc_state *crtc_state; 1806 struct intel_crtc_state *crtc_state;
1786 unsigned int max_pixel_rate = 0, i; 1807 int min_cdclk, i;
1787 enum pipe pipe; 1808 enum pipe pipe;
1788 1809
1789 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, 1810 memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
1790 sizeof(intel_state->min_pixclk)); 1811 sizeof(intel_state->min_cdclk));
1791 1812
1792 for_each_new_crtc_in_state(state, crtc, cstate, i) { 1813 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
1793 int pixel_rate; 1814 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
1815 if (min_cdclk < 0)
1816 return min_cdclk;
1794 1817
1795 crtc_state = to_intel_crtc_state(cstate); 1818 intel_state->min_cdclk[i] = min_cdclk;
1796 if (!crtc_state->base.enable) {
1797 intel_state->min_pixclk[i] = 0;
1798 continue;
1799 }
1800
1801 pixel_rate = crtc_state->pixel_rate;
1802
1803 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1804 pixel_rate =
1805 bdw_adjust_min_pipe_pixel_rate(crtc_state,
1806 pixel_rate);
1807
1808 intel_state->min_pixclk[i] = pixel_rate;
1809 } 1819 }
1810 1820
1821 min_cdclk = 0;
1811 for_each_pipe(dev_priv, pipe) 1822 for_each_pipe(dev_priv, pipe)
1812 max_pixel_rate = max(intel_state->min_pixclk[pipe], 1823 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
1813 max_pixel_rate);
1814 1824
1815 return max_pixel_rate; 1825 return min_cdclk;
1816} 1826}
1817 1827
1818static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) 1828static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1819{ 1829{
1820 struct drm_i915_private *dev_priv = to_i915(state->dev); 1830 struct drm_i915_private *dev_priv = to_i915(state->dev);
1821 int max_pixclk = intel_max_pixel_rate(state); 1831 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1822 struct intel_atomic_state *intel_state = 1832 int min_cdclk, cdclk;
1823 to_intel_atomic_state(state);
1824 int cdclk;
1825 1833
1826 cdclk = vlv_calc_cdclk(dev_priv, max_pixclk); 1834 min_cdclk = intel_compute_min_cdclk(state);
1835 if (min_cdclk < 0)
1836 return min_cdclk;
1827 1837
1828 if (cdclk > dev_priv->max_cdclk_freq) { 1838 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
1829 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1830 cdclk, dev_priv->max_cdclk_freq);
1831 return -EINVAL;
1832 }
1833 1839
1834 intel_state->cdclk.logical.cdclk = cdclk; 1840 intel_state->cdclk.logical.cdclk = cdclk;
1835 1841
@@ -1847,22 +1853,18 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1847 1853
1848static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) 1854static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1849{ 1855{
1850 struct drm_i915_private *dev_priv = to_i915(state->dev);
1851 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 1856 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1852 int max_pixclk = intel_max_pixel_rate(state); 1857 int min_cdclk, cdclk;
1853 int cdclk; 1858
1859 min_cdclk = intel_compute_min_cdclk(state);
1860 if (min_cdclk < 0)
1861 return min_cdclk;
1854 1862
1855 /* 1863 /*
1856 * FIXME should also account for plane ratio 1864 * FIXME should also account for plane ratio
1857 * once 64bpp pixel formats are supported. 1865 * once 64bpp pixel formats are supported.
1858 */ 1866 */
1859 cdclk = bdw_calc_cdclk(max_pixclk); 1867 cdclk = bdw_calc_cdclk(min_cdclk);
1860
1861 if (cdclk > dev_priv->max_cdclk_freq) {
1862 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1863 cdclk, dev_priv->max_cdclk_freq);
1864 return -EINVAL;
1865 }
1866 1868
1867 intel_state->cdclk.logical.cdclk = cdclk; 1869 intel_state->cdclk.logical.cdclk = cdclk;
1868 1870
@@ -1880,10 +1882,13 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1880 1882
1881static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) 1883static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1882{ 1884{
1883 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1884 struct drm_i915_private *dev_priv = to_i915(state->dev); 1885 struct drm_i915_private *dev_priv = to_i915(state->dev);
1885 const int max_pixclk = intel_max_pixel_rate(state); 1886 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1886 int cdclk, vco; 1887 int min_cdclk, cdclk, vco;
1888
1889 min_cdclk = intel_compute_min_cdclk(state);
1890 if (min_cdclk < 0)
1891 return min_cdclk;
1887 1892
1888 vco = intel_state->cdclk.logical.vco; 1893 vco = intel_state->cdclk.logical.vco;
1889 if (!vco) 1894 if (!vco)
@@ -1893,13 +1898,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1893 * FIXME should also account for plane ratio 1898 * FIXME should also account for plane ratio
1894 * once 64bpp pixel formats are supported. 1899 * once 64bpp pixel formats are supported.
1895 */ 1900 */
1896 cdclk = skl_calc_cdclk(max_pixclk, vco); 1901 cdclk = skl_calc_cdclk(min_cdclk, vco);
1897
1898 if (cdclk > dev_priv->max_cdclk_freq) {
1899 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1900 cdclk, dev_priv->max_cdclk_freq);
1901 return -EINVAL;
1902 }
1903 1902
1904 intel_state->cdclk.logical.vco = vco; 1903 intel_state->cdclk.logical.vco = vco;
1905 intel_state->cdclk.logical.cdclk = cdclk; 1904 intel_state->cdclk.logical.cdclk = cdclk;
@@ -1920,25 +1919,21 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1920static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) 1919static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1921{ 1920{
1922 struct drm_i915_private *dev_priv = to_i915(state->dev); 1921 struct drm_i915_private *dev_priv = to_i915(state->dev);
1923 int max_pixclk = intel_max_pixel_rate(state); 1922 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1924 struct intel_atomic_state *intel_state = 1923 int min_cdclk, cdclk, vco;
1925 to_intel_atomic_state(state); 1924
1926 int cdclk, vco; 1925 min_cdclk = intel_compute_min_cdclk(state);
1926 if (min_cdclk < 0)
1927 return min_cdclk;
1927 1928
1928 if (IS_GEMINILAKE(dev_priv)) { 1929 if (IS_GEMINILAKE(dev_priv)) {
1929 cdclk = glk_calc_cdclk(max_pixclk); 1930 cdclk = glk_calc_cdclk(min_cdclk);
1930 vco = glk_de_pll_vco(dev_priv, cdclk); 1931 vco = glk_de_pll_vco(dev_priv, cdclk);
1931 } else { 1932 } else {
1932 cdclk = bxt_calc_cdclk(max_pixclk); 1933 cdclk = bxt_calc_cdclk(min_cdclk);
1933 vco = bxt_de_pll_vco(dev_priv, cdclk); 1934 vco = bxt_de_pll_vco(dev_priv, cdclk);
1934 } 1935 }
1935 1936
1936 if (cdclk > dev_priv->max_cdclk_freq) {
1937 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1938 cdclk, dev_priv->max_cdclk_freq);
1939 return -EINVAL;
1940 }
1941
1942 intel_state->cdclk.logical.vco = vco; 1937 intel_state->cdclk.logical.vco = vco;
1943 intel_state->cdclk.logical.cdclk = cdclk; 1938 intel_state->cdclk.logical.cdclk = cdclk;
1944 1939
@@ -1964,19 +1959,15 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1964static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state) 1959static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
1965{ 1960{
1966 struct drm_i915_private *dev_priv = to_i915(state->dev); 1961 struct drm_i915_private *dev_priv = to_i915(state->dev);
1967 struct intel_atomic_state *intel_state = 1962 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1968 to_intel_atomic_state(state); 1963 int min_cdclk, cdclk, vco;
1969 int max_pixclk = intel_max_pixel_rate(state);
1970 int cdclk, vco;
1971 1964
1972 cdclk = cnl_calc_cdclk(max_pixclk); 1965 min_cdclk = intel_compute_min_cdclk(state);
1973 vco = cnl_cdclk_pll_vco(dev_priv, cdclk); 1966 if (min_cdclk < 0)
1967 return min_cdclk;
1974 1968
1975 if (cdclk > dev_priv->max_cdclk_freq) { 1969 cdclk = cnl_calc_cdclk(min_cdclk);
1976 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", 1970 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
1977 cdclk, dev_priv->max_cdclk_freq);
1978 return -EINVAL;
1979 }
1980 1971
1981 intel_state->cdclk.logical.vco = vco; 1972 intel_state->cdclk.logical.vco = vco;
1982 intel_state->cdclk.logical.cdclk = cdclk; 1973 intel_state->cdclk.logical.cdclk = cdclk;
@@ -1999,14 +1990,21 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
1999{ 1990{
2000 int max_cdclk_freq = dev_priv->max_cdclk_freq; 1991 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2001 1992
2002 if (IS_GEMINILAKE(dev_priv)) 1993 if (INTEL_GEN(dev_priv) >= 10)
1994 /*
1995 * FIXME: Allow '2 * max_cdclk_freq'
1996 * once DDI clock voltage requirements are
1997 * handled correctly.
1998 */
1999 return max_cdclk_freq;
2000 else if (IS_GEMINILAKE(dev_priv))
2003 /* 2001 /*
2004 * FIXME: Limiting to 99% as a temporary workaround. See 2002 * FIXME: Limiting to 99% as a temporary workaround. See
2005 * glk_calc_cdclk() for details. 2003 * intel_min_cdclk() for details.
2006 */ 2004 */
2007 return 2 * max_cdclk_freq * 99 / 100; 2005 return 2 * max_cdclk_freq * 99 / 100;
2008 else if (INTEL_INFO(dev_priv)->gen >= 9 || 2006 else if (IS_GEN9(dev_priv) ||
2009 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 2007 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2010 return max_cdclk_freq; 2008 return max_cdclk_freq;
2011 else if (IS_CHERRYVIEW(dev_priv)) 2009 else if (IS_CHERRYVIEW(dev_priv))
2012 return max_cdclk_freq*95/100; 2010 return max_cdclk_freq*95/100;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 70e0ff41070c..a77dd80a97f2 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -143,7 +143,7 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
143/* Note: The caller is required to filter out dpms modes not supported by the 143/* Note: The caller is required to filter out dpms modes not supported by the
144 * platform. */ 144 * platform. */
145static void intel_crt_set_dpms(struct intel_encoder *encoder, 145static void intel_crt_set_dpms(struct intel_encoder *encoder,
146 struct intel_crtc_state *crtc_state, 146 const struct intel_crtc_state *crtc_state,
147 int mode) 147 int mode)
148{ 148{
149 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 149 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -194,28 +194,28 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
194} 194}
195 195
196static void intel_disable_crt(struct intel_encoder *encoder, 196static void intel_disable_crt(struct intel_encoder *encoder,
197 struct intel_crtc_state *old_crtc_state, 197 const struct intel_crtc_state *old_crtc_state,
198 struct drm_connector_state *old_conn_state) 198 const struct drm_connector_state *old_conn_state)
199{ 199{
200 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 200 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
201} 201}
202 202
203static void pch_disable_crt(struct intel_encoder *encoder, 203static void pch_disable_crt(struct intel_encoder *encoder,
204 struct intel_crtc_state *old_crtc_state, 204 const struct intel_crtc_state *old_crtc_state,
205 struct drm_connector_state *old_conn_state) 205 const struct drm_connector_state *old_conn_state)
206{ 206{
207} 207}
208 208
209static void pch_post_disable_crt(struct intel_encoder *encoder, 209static void pch_post_disable_crt(struct intel_encoder *encoder,
210 struct intel_crtc_state *old_crtc_state, 210 const struct intel_crtc_state *old_crtc_state,
211 struct drm_connector_state *old_conn_state) 211 const struct drm_connector_state *old_conn_state)
212{ 212{
213 intel_disable_crt(encoder, old_crtc_state, old_conn_state); 213 intel_disable_crt(encoder, old_crtc_state, old_conn_state);
214} 214}
215 215
216static void hsw_post_disable_crt(struct intel_encoder *encoder, 216static void hsw_post_disable_crt(struct intel_encoder *encoder,
217 struct intel_crtc_state *old_crtc_state, 217 const struct intel_crtc_state *old_crtc_state,
218 struct drm_connector_state *old_conn_state) 218 const struct drm_connector_state *old_conn_state)
219{ 219{
220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
221 221
@@ -228,8 +228,8 @@ static void hsw_post_disable_crt(struct intel_encoder *encoder,
228} 228}
229 229
230static void intel_enable_crt(struct intel_encoder *encoder, 230static void intel_enable_crt(struct intel_encoder *encoder,
231 struct intel_crtc_state *pipe_config, 231 const struct intel_crtc_state *pipe_config,
232 struct drm_connector_state *conn_state) 232 const struct drm_connector_state *conn_state)
233{ 233{
234 intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON); 234 intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);
235} 235}
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4b4fd1f8110b..1da3bb2cc4b4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -588,6 +588,67 @@ skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
588 } 588 }
589} 589}
590 590
591static const struct cnl_ddi_buf_trans *
592cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
593{
594 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
595
596 if (voltage == VOLTAGE_INFO_0_85V) {
597 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
598 return cnl_ddi_translations_hdmi_0_85V;
599 } else if (voltage == VOLTAGE_INFO_0_95V) {
600 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
601 return cnl_ddi_translations_hdmi_0_95V;
602 } else if (voltage == VOLTAGE_INFO_1_05V) {
603 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
604 return cnl_ddi_translations_hdmi_1_05V;
605 } else
606 MISSING_CASE(voltage);
607 return NULL;
608}
609
610static const struct cnl_ddi_buf_trans *
611cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
612{
613 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
614
615 if (voltage == VOLTAGE_INFO_0_85V) {
616 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
617 return cnl_ddi_translations_dp_0_85V;
618 } else if (voltage == VOLTAGE_INFO_0_95V) {
619 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
620 return cnl_ddi_translations_dp_0_95V;
621 } else if (voltage == VOLTAGE_INFO_1_05V) {
622 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
623 return cnl_ddi_translations_dp_1_05V;
624 } else
625 MISSING_CASE(voltage);
626 return NULL;
627}
628
629static const struct cnl_ddi_buf_trans *
630cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
631{
632 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
633
634 if (dev_priv->vbt.edp.low_vswing) {
635 if (voltage == VOLTAGE_INFO_0_85V) {
636 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
637 return cnl_ddi_translations_edp_0_85V;
638 } else if (voltage == VOLTAGE_INFO_0_95V) {
639 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
640 return cnl_ddi_translations_edp_0_95V;
641 } else if (voltage == VOLTAGE_INFO_1_05V) {
642 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
643 return cnl_ddi_translations_edp_1_05V;
644 } else
645 MISSING_CASE(voltage);
646 return NULL;
647 } else {
648 return cnl_get_buf_trans_dp(dev_priv, n_entries);
649 }
650}
651
591static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) 652static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
592{ 653{
593 int n_hdmi_entries; 654 int n_hdmi_entries;
@@ -599,7 +660,10 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
599 if (IS_GEN9_LP(dev_priv)) 660 if (IS_GEN9_LP(dev_priv))
600 return hdmi_level; 661 return hdmi_level;
601 662
602 if (IS_GEN9_BC(dev_priv)) { 663 if (IS_CANNONLAKE(dev_priv)) {
664 cnl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
665 hdmi_default_entry = n_hdmi_entries - 1;
666 } else if (IS_GEN9_BC(dev_priv)) {
603 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); 667 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
604 hdmi_default_entry = 8; 668 hdmi_default_entry = 8;
605 } else if (IS_BROADWELL(dev_priv)) { 669 } else if (IS_BROADWELL(dev_priv)) {
@@ -688,9 +752,6 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
688 enum port port = intel_ddi_get_encoder_port(encoder); 752 enum port port = intel_ddi_get_encoder_port(encoder);
689 const struct ddi_buf_trans *ddi_translations; 753 const struct ddi_buf_trans *ddi_translations;
690 754
691 if (IS_GEN9_LP(dev_priv))
692 return;
693
694 switch (encoder->type) { 755 switch (encoder->type) {
695 case INTEL_OUTPUT_EDP: 756 case INTEL_OUTPUT_EDP:
696 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, 757 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
@@ -741,9 +802,6 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
741 enum port port = intel_ddi_get_encoder_port(encoder); 802 enum port port = intel_ddi_get_encoder_port(encoder);
742 const struct ddi_buf_trans *ddi_translations_hdmi; 803 const struct ddi_buf_trans *ddi_translations_hdmi;
743 804
744 if (IS_GEN9_LP(dev_priv))
745 return;
746
747 hdmi_level = intel_ddi_hdmi_level(dev_priv, port); 805 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
748 806
749 if (IS_GEN9_BC(dev_priv)) { 807 if (IS_GEN9_BC(dev_priv)) {
@@ -785,7 +843,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
785 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 843 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
786} 844}
787 845
788static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll) 846static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
789{ 847{
790 switch (pll->id) { 848 switch (pll->id) {
791 case DPLL_ID_WRPLL1: 849 case DPLL_ID_WRPLL1:
@@ -1821,10 +1879,17 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1821 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1822 int n_entries; 1880 int n_entries;
1823 1881
1824 if (encoder->type == INTEL_OUTPUT_EDP) 1882 if (IS_CANNONLAKE(dev_priv)) {
1825 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries); 1883 if (encoder->type == INTEL_OUTPUT_EDP)
1826 else 1884 cnl_get_buf_trans_edp(dev_priv, &n_entries);
1827 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries); 1885 else
1886 cnl_get_buf_trans_dp(dev_priv, &n_entries);
1887 } else {
1888 if (encoder->type == INTEL_OUTPUT_EDP)
1889 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1890 else
1891 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1892 }
1828 1893
1829 if (WARN_ON(n_entries < 1)) 1894 if (WARN_ON(n_entries < 1))
1830 n_entries = 1; 1895 n_entries = 1;
@@ -1835,90 +1900,23 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1835 DP_TRAIN_VOLTAGE_SWING_MASK; 1900 DP_TRAIN_VOLTAGE_SWING_MASK;
1836} 1901}
1837 1902
1838static const struct cnl_ddi_buf_trans *
1839cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
1840 u32 voltage, int *n_entries)
1841{
1842 if (voltage == VOLTAGE_INFO_0_85V) {
1843 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1844 return cnl_ddi_translations_hdmi_0_85V;
1845 } else if (voltage == VOLTAGE_INFO_0_95V) {
1846 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1847 return cnl_ddi_translations_hdmi_0_95V;
1848 } else if (voltage == VOLTAGE_INFO_1_05V) {
1849 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1850 return cnl_ddi_translations_hdmi_1_05V;
1851 }
1852 return NULL;
1853}
1854
1855static const struct cnl_ddi_buf_trans *
1856cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
1857 u32 voltage, int *n_entries)
1858{
1859 if (voltage == VOLTAGE_INFO_0_85V) {
1860 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1861 return cnl_ddi_translations_dp_0_85V;
1862 } else if (voltage == VOLTAGE_INFO_0_95V) {
1863 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1864 return cnl_ddi_translations_dp_0_95V;
1865 } else if (voltage == VOLTAGE_INFO_1_05V) {
1866 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1867 return cnl_ddi_translations_dp_1_05V;
1868 }
1869 return NULL;
1870}
1871
1872static const struct cnl_ddi_buf_trans *
1873cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
1874 u32 voltage, int *n_entries)
1875{
1876 if (dev_priv->vbt.edp.low_vswing) {
1877 if (voltage == VOLTAGE_INFO_0_85V) {
1878 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1879 return cnl_ddi_translations_edp_0_85V;
1880 } else if (voltage == VOLTAGE_INFO_0_95V) {
1881 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1882 return cnl_ddi_translations_edp_0_95V;
1883 } else if (voltage == VOLTAGE_INFO_1_05V) {
1884 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1885 return cnl_ddi_translations_edp_1_05V;
1886 }
1887 return NULL;
1888 } else {
1889 return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
1890 }
1891}
1892
1893static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, 1903static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1894 u32 level, enum port port, int type) 1904 u32 level, enum port port, int type)
1895{ 1905{
1896 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 1906 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
1897 u32 n_entries, val, voltage; 1907 u32 n_entries, val;
1898 int ln; 1908 int ln;
1899 1909
1900 /*
1901 * Values for each port type are listed in
1902 * voltage swing programming tables.
1903 * Vccio voltage found in PORT_COMP_DW3.
1904 */
1905 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1906
1907 if (type == INTEL_OUTPUT_HDMI) { 1910 if (type == INTEL_OUTPUT_HDMI) {
1908 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, 1911 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
1909 voltage, &n_entries);
1910 } else if (type == INTEL_OUTPUT_DP) { 1912 } else if (type == INTEL_OUTPUT_DP) {
1911 ddi_translations = cnl_get_buf_trans_dp(dev_priv, 1913 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
1912 voltage, &n_entries);
1913 } else if (type == INTEL_OUTPUT_EDP) { 1914 } else if (type == INTEL_OUTPUT_EDP) {
1914 ddi_translations = cnl_get_buf_trans_edp(dev_priv, 1915 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
1915 voltage, &n_entries);
1916 } 1916 }
1917 1917
1918 if (ddi_translations == NULL) { 1918 if (WARN_ON(ddi_translations == NULL))
1919 MISSING_CASE(voltage);
1920 return; 1919 return;
1921 }
1922 1920
1923 if (level >= n_entries) { 1921 if (level >= n_entries) {
1924 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); 1922 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
@@ -2054,33 +2052,46 @@ static uint32_t translate_signal_level(int signal_levels)
2054 return 0; 2052 return 0;
2055} 2053}
2056 2054
2057uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 2055static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2058{ 2056{
2059 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2060 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2061 struct intel_encoder *encoder = &dport->base;
2062 uint8_t train_set = intel_dp->train_set[0]; 2057 uint8_t train_set = intel_dp->train_set[0];
2063 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2058 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2064 DP_TRAIN_PRE_EMPHASIS_MASK); 2059 DP_TRAIN_PRE_EMPHASIS_MASK);
2060
2061 return translate_signal_level(signal_levels);
2062}
2063
2064u32 bxt_signal_levels(struct intel_dp *intel_dp)
2065{
2066 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2067 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2068 struct intel_encoder *encoder = &dport->base;
2065 enum port port = dport->port; 2069 enum port port = dport->port;
2066 uint32_t level; 2070 u32 level = intel_ddi_dp_level(intel_dp);
2067 2071
2068 level = translate_signal_level(signal_levels); 2072 if (IS_CANNONLAKE(dev_priv))
2073 cnl_ddi_vswing_sequence(encoder, level);
2074 else
2075 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2076
2077 return 0;
2078}
2079
2080uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2081{
2082 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2083 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2084 struct intel_encoder *encoder = &dport->base;
2085 uint32_t level = intel_ddi_dp_level(intel_dp);
2069 2086
2070 if (IS_GEN9_BC(dev_priv)) 2087 if (IS_GEN9_BC(dev_priv))
2071 skl_ddi_set_iboost(encoder, level); 2088 skl_ddi_set_iboost(encoder, level);
2072 else if (IS_GEN9_LP(dev_priv)) 2089
2073 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2074 else if (IS_CANNONLAKE(dev_priv)) {
2075 cnl_ddi_vswing_sequence(encoder, level);
2076 /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
2077 return 0;
2078 }
2079 return DDI_BUF_TRANS_SELECT(level); 2090 return DDI_BUF_TRANS_SELECT(level);
2080} 2091}
2081 2092
2082static void intel_ddi_clk_select(struct intel_encoder *encoder, 2093static void intel_ddi_clk_select(struct intel_encoder *encoder,
2083 struct intel_shared_dpll *pll) 2094 const struct intel_shared_dpll *pll)
2084{ 2095{
2085 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2096 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2086 enum port port = intel_ddi_get_encoder_port(encoder); 2097 enum port port = intel_ddi_get_encoder_port(encoder);
@@ -2129,6 +2140,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2129 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2140 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2130 enum port port = intel_ddi_get_encoder_port(encoder); 2141 enum port port = intel_ddi_get_encoder_port(encoder);
2131 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 2142 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2143 uint32_t level = intel_ddi_dp_level(intel_dp);
2132 2144
2133 WARN_ON(link_mst && (port == PORT_A || port == PORT_E)); 2145 WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2134 2146
@@ -2141,7 +2153,13 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2141 2153
2142 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 2154 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2143 2155
2144 intel_prepare_dp_ddi_buffers(encoder); 2156 if (IS_CANNONLAKE(dev_priv))
2157 cnl_ddi_vswing_sequence(encoder, level);
2158 else if (IS_GEN9_LP(dev_priv))
2159 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2160 else
2161 intel_prepare_dp_ddi_buffers(encoder);
2162
2145 intel_ddi_init_dp_buf_reg(encoder); 2163 intel_ddi_init_dp_buf_reg(encoder);
2146 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2164 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2147 intel_dp_start_link_train(intel_dp); 2165 intel_dp_start_link_train(intel_dp);
@@ -2150,14 +2168,14 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2150} 2168}
2151 2169
2152static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 2170static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2153 bool has_hdmi_sink, 2171 bool has_infoframe,
2154 const struct intel_crtc_state *crtc_state, 2172 const struct intel_crtc_state *crtc_state,
2155 const struct drm_connector_state *conn_state, 2173 const struct drm_connector_state *conn_state,
2156 struct intel_shared_dpll *pll) 2174 const struct intel_shared_dpll *pll)
2157{ 2175{
2158 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 2176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2177 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2159 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2160 struct drm_encoder *drm_encoder = &encoder->base;
2161 enum port port = intel_ddi_get_encoder_port(encoder); 2179 enum port port = intel_ddi_get_encoder_port(encoder);
2162 int level = intel_ddi_hdmi_level(dev_priv, port); 2180 int level = intel_ddi_hdmi_level(dev_priv, port);
2163 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 2181 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
@@ -2167,23 +2185,25 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2167 2185
2168 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 2186 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2169 2187
2170 intel_prepare_hdmi_ddi_buffers(encoder); 2188 if (IS_CANNONLAKE(dev_priv))
2171 if (IS_GEN9_BC(dev_priv)) 2189 cnl_ddi_vswing_sequence(encoder, level);
2172 skl_ddi_set_iboost(encoder, level);
2173 else if (IS_GEN9_LP(dev_priv)) 2190 else if (IS_GEN9_LP(dev_priv))
2174 bxt_ddi_vswing_sequence(dev_priv, level, port, 2191 bxt_ddi_vswing_sequence(dev_priv, level, port,
2175 INTEL_OUTPUT_HDMI); 2192 INTEL_OUTPUT_HDMI);
2176 else if (IS_CANNONLAKE(dev_priv)) 2193 else
2177 cnl_ddi_vswing_sequence(encoder, level); 2194 intel_prepare_hdmi_ddi_buffers(encoder);
2195
2196 if (IS_GEN9_BC(dev_priv))
2197 skl_ddi_set_iboost(encoder, level);
2178 2198
2179 intel_hdmi->set_infoframes(drm_encoder, 2199 intel_dig_port->set_infoframes(&encoder->base,
2180 has_hdmi_sink, 2200 has_infoframe,
2181 crtc_state, conn_state); 2201 crtc_state, conn_state);
2182} 2202}
2183 2203
2184static void intel_ddi_pre_enable(struct intel_encoder *encoder, 2204static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2185 struct intel_crtc_state *pipe_config, 2205 const struct intel_crtc_state *pipe_config,
2186 struct drm_connector_state *conn_state) 2206 const struct drm_connector_state *conn_state)
2187{ 2207{
2188 int type = encoder->type; 2208 int type = encoder->type;
2189 2209
@@ -2197,21 +2217,20 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2197 } 2217 }
2198 if (type == INTEL_OUTPUT_HDMI) { 2218 if (type == INTEL_OUTPUT_HDMI) {
2199 intel_ddi_pre_enable_hdmi(encoder, 2219 intel_ddi_pre_enable_hdmi(encoder,
2200 pipe_config->has_hdmi_sink, 2220 pipe_config->has_infoframe,
2201 pipe_config, conn_state, 2221 pipe_config, conn_state,
2202 pipe_config->shared_dpll); 2222 pipe_config->shared_dpll);
2203 } 2223 }
2204} 2224}
2205 2225
2206static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, 2226static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2207 struct intel_crtc_state *old_crtc_state, 2227 const struct intel_crtc_state *old_crtc_state,
2208 struct drm_connector_state *old_conn_state) 2228 const struct drm_connector_state *old_conn_state)
2209{ 2229{
2210 struct drm_encoder *encoder = &intel_encoder->base; 2230 struct drm_encoder *encoder = &intel_encoder->base;
2211 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 2231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2212 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2232 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2213 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2233 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2214 struct intel_dp *intel_dp = NULL;
2215 int type = intel_encoder->type; 2234 int type = intel_encoder->type;
2216 uint32_t val; 2235 uint32_t val;
2217 bool wait = false; 2236 bool wait = false;
@@ -2219,7 +2238,8 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2219 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */ 2238 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
2220 2239
2221 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { 2240 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2222 intel_dp = enc_to_intel_dp(encoder); 2241 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2242
2223 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2243 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2224 } 2244 }
2225 2245
@@ -2238,7 +2258,14 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2238 if (wait) 2258 if (wait)
2239 intel_wait_ddi_buf_idle(dev_priv, port); 2259 intel_wait_ddi_buf_idle(dev_priv, port);
2240 2260
2241 if (intel_dp) { 2261 if (type == INTEL_OUTPUT_HDMI) {
2262 dig_port->set_infoframes(encoder, false,
2263 old_crtc_state, old_conn_state);
2264 }
2265
2266 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2267 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2268
2242 intel_edp_panel_vdd_on(intel_dp); 2269 intel_edp_panel_vdd_on(intel_dp);
2243 intel_edp_panel_off(intel_dp); 2270 intel_edp_panel_off(intel_dp);
2244 } 2271 }
@@ -2263,8 +2290,8 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2263} 2290}
2264 2291
2265void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, 2292void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2266 struct intel_crtc_state *old_crtc_state, 2293 const struct intel_crtc_state *old_crtc_state,
2267 struct drm_connector_state *old_conn_state) 2294 const struct drm_connector_state *old_conn_state)
2268{ 2295{
2269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2270 uint32_t val; 2297 uint32_t val;
@@ -2296,8 +2323,8 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2296} 2323}
2297 2324
2298static void intel_enable_ddi(struct intel_encoder *intel_encoder, 2325static void intel_enable_ddi(struct intel_encoder *intel_encoder,
2299 struct intel_crtc_state *pipe_config, 2326 const struct intel_crtc_state *pipe_config,
2300 struct drm_connector_state *conn_state) 2327 const struct drm_connector_state *conn_state)
2301{ 2328{
2302 struct drm_encoder *encoder = &intel_encoder->base; 2329 struct drm_encoder *encoder = &intel_encoder->base;
2303 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 2330 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
@@ -2328,7 +2355,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder,
2328 intel_dp_stop_link_train(intel_dp); 2355 intel_dp_stop_link_train(intel_dp);
2329 2356
2330 intel_edp_backlight_on(pipe_config, conn_state); 2357 intel_edp_backlight_on(pipe_config, conn_state);
2331 intel_psr_enable(intel_dp); 2358 intel_psr_enable(intel_dp, pipe_config);
2332 intel_edp_drrs_enable(intel_dp, pipe_config); 2359 intel_edp_drrs_enable(intel_dp, pipe_config);
2333 } 2360 }
2334 2361
@@ -2337,8 +2364,8 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder,
2337} 2364}
2338 2365
2339static void intel_disable_ddi(struct intel_encoder *intel_encoder, 2366static void intel_disable_ddi(struct intel_encoder *intel_encoder,
2340 struct intel_crtc_state *old_crtc_state, 2367 const struct intel_crtc_state *old_crtc_state,
2341 struct drm_connector_state *old_conn_state) 2368 const struct drm_connector_state *old_conn_state)
2342{ 2369{
2343 struct drm_encoder *encoder = &intel_encoder->base; 2370 struct drm_encoder *encoder = &intel_encoder->base;
2344 int type = intel_encoder->type; 2371 int type = intel_encoder->type;
@@ -2356,14 +2383,14 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder,
2356 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2383 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2357 2384
2358 intel_edp_drrs_disable(intel_dp, old_crtc_state); 2385 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2359 intel_psr_disable(intel_dp); 2386 intel_psr_disable(intel_dp, old_crtc_state);
2360 intel_edp_backlight_off(old_conn_state); 2387 intel_edp_backlight_off(old_conn_state);
2361 } 2388 }
2362} 2389}
2363 2390
2364static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder, 2391static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2365 struct intel_crtc_state *pipe_config, 2392 const struct intel_crtc_state *pipe_config,
2366 struct drm_connector_state *conn_state) 2393 const struct drm_connector_state *conn_state)
2367{ 2394{
2368 uint8_t mask = pipe_config->lane_lat_optim_mask; 2395 uint8_t mask = pipe_config->lane_lat_optim_mask;
2369 2396
@@ -2435,7 +2462,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
2435 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2436 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2463 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2437 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2464 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2438 struct intel_hdmi *intel_hdmi; 2465 struct intel_digital_port *intel_dig_port;
2439 u32 temp, flags = 0; 2466 u32 temp, flags = 0;
2440 2467
2441 /* XXX: DSI transcoder paranoia */ 2468 /* XXX: DSI transcoder paranoia */
@@ -2474,9 +2501,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
2474 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 2501 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2475 case TRANS_DDI_MODE_SELECT_HDMI: 2502 case TRANS_DDI_MODE_SELECT_HDMI:
2476 pipe_config->has_hdmi_sink = true; 2503 pipe_config->has_hdmi_sink = true;
2477 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 2504 intel_dig_port = enc_to_dig_port(&encoder->base);
2478 2505
2479 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 2506 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
2480 pipe_config->has_infoframe = true; 2507 pipe_config->has_infoframe = true;
2481 2508
2482 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) == 2509 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
@@ -2729,6 +2756,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
2729 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2756 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2730 intel_encoder->cloneable = 0; 2757 intel_encoder->cloneable = 0;
2731 2758
2759 intel_infoframe_init(intel_dig_port);
2760
2732 if (init_dp) { 2761 if (init_dp) {
2733 if (!intel_ddi_init_dp_connector(intel_dig_port)) 2762 if (!intel_ddi_init_dp_connector(intel_dig_port))
2734 goto err; 2763 goto err;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 5f91ddc78c7a..b17f7045c8f8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -412,7 +412,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
412 else if (INTEL_INFO(dev_priv)->gen >= 9) 412 else if (INTEL_INFO(dev_priv)->gen >= 9)
413 gen9_sseu_info_init(dev_priv); 413 gen9_sseu_info_init(dev_priv);
414 414
415 info->has_snoop = !info->has_llc; 415 WARN_ON(info->has_snoop != !info->has_llc);
416 416
417 DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask); 417 DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
418 DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask)); 418 DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4b34fa6954f9..f780f39e0758 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3770,8 +3770,8 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
3770 if (!gpu_reset_clobbers_display(dev_priv)) { 3770 if (!gpu_reset_clobbers_display(dev_priv)) {
3771 /* for testing only restore the display */ 3771 /* for testing only restore the display */
3772 ret = __intel_display_resume(dev, state, ctx); 3772 ret = __intel_display_resume(dev, state, ctx);
3773 if (ret) 3773 if (ret)
3774 DRM_ERROR("Restoring old state failed with %i\n", ret); 3774 DRM_ERROR("Restoring old state failed with %i\n", ret);
3775 } else { 3775 } else {
3776 /* 3776 /*
3777 * The display has been reset as well, 3777 * The display has been reset as well,
@@ -3804,15 +3804,14 @@ unlock:
3804 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); 3804 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3805} 3805}
3806 3806
3807static void intel_update_pipe_config(struct intel_crtc *crtc, 3807static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3808 struct intel_crtc_state *old_crtc_state) 3808 const struct intel_crtc_state *new_crtc_state)
3809{ 3809{
3810 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3810 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3811 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3811 struct intel_crtc_state *pipe_config =
3812 to_intel_crtc_state(crtc->base.state);
3813 3812
3814 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ 3813 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3815 crtc->base.mode = crtc->base.state->mode; 3814 crtc->base.mode = new_crtc_state->base.mode;
3816 3815
3817 /* 3816 /*
3818 * Update pipe size and adjust fitter if needed: the reason for this is 3817 * Update pipe size and adjust fitter if needed: the reason for this is
@@ -3824,17 +3823,17 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
3824 */ 3823 */
3825 3824
3826 I915_WRITE(PIPESRC(crtc->pipe), 3825 I915_WRITE(PIPESRC(crtc->pipe),
3827 ((pipe_config->pipe_src_w - 1) << 16) | 3826 ((new_crtc_state->pipe_src_w - 1) << 16) |
3828 (pipe_config->pipe_src_h - 1)); 3827 (new_crtc_state->pipe_src_h - 1));
3829 3828
3830 /* on skylake this is done by detaching scalers */ 3829 /* on skylake this is done by detaching scalers */
3831 if (INTEL_GEN(dev_priv) >= 9) { 3830 if (INTEL_GEN(dev_priv) >= 9) {
3832 skl_detach_scalers(crtc); 3831 skl_detach_scalers(crtc);
3833 3832
3834 if (pipe_config->pch_pfit.enabled) 3833 if (new_crtc_state->pch_pfit.enabled)
3835 skylake_pfit_enable(crtc); 3834 skylake_pfit_enable(crtc);
3836 } else if (HAS_PCH_SPLIT(dev_priv)) { 3835 } else if (HAS_PCH_SPLIT(dev_priv)) {
3837 if (pipe_config->pch_pfit.enabled) 3836 if (new_crtc_state->pch_pfit.enabled)
3838 ironlake_pfit_enable(crtc); 3837 ironlake_pfit_enable(crtc);
3839 else if (old_crtc_state->pch_pfit.enabled) 3838 else if (old_crtc_state->pch_pfit.enabled)
3840 ironlake_pfit_disable(crtc, true); 3839 ironlake_pfit_disable(crtc, true);
@@ -5118,7 +5117,8 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5118 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 5117 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5119 struct drm_atomic_state *old_state = old_crtc_state->base.state; 5118 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5120 struct intel_crtc_state *pipe_config = 5119 struct intel_crtc_state *pipe_config =
5121 to_intel_crtc_state(crtc->base.state); 5120 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5121 crtc);
5122 struct drm_plane *primary = crtc->base.primary; 5122 struct drm_plane *primary = crtc->base.primary;
5123 struct drm_plane_state *old_pri_state = 5123 struct drm_plane_state *old_pri_state =
5124 drm_atomic_get_existing_plane_state(old_state, primary); 5124 drm_atomic_get_existing_plane_state(old_state, primary);
@@ -5130,7 +5130,8 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5130 5130
5131 if (old_pri_state) { 5131 if (old_pri_state) {
5132 struct intel_plane_state *primary_state = 5132 struct intel_plane_state *primary_state =
5133 to_intel_plane_state(primary->state); 5133 intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5134 to_intel_plane(primary));
5134 struct intel_plane_state *old_primary_state = 5135 struct intel_plane_state *old_primary_state =
5135 to_intel_plane_state(old_pri_state); 5136 to_intel_plane_state(old_pri_state);
5136 5137
@@ -5159,7 +5160,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5159 5160
5160 if (old_pri_state) { 5161 if (old_pri_state) {
5161 struct intel_plane_state *primary_state = 5162 struct intel_plane_state *primary_state =
5162 to_intel_plane_state(primary->state); 5163 intel_atomic_get_new_plane_state(old_intel_state,
5164 to_intel_plane(primary));
5163 struct intel_plane_state *old_primary_state = 5165 struct intel_plane_state *old_primary_state =
5164 to_intel_plane_state(old_pri_state); 5166 to_intel_plane_state(old_pri_state);
5165 5167
@@ -6038,7 +6040,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6038 intel_crtc->enabled_power_domains = 0; 6040 intel_crtc->enabled_power_domains = 0;
6039 6041
6040 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); 6042 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6041 dev_priv->min_pixclk[intel_crtc->pipe] = 0; 6043 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6042} 6044}
6043 6045
6044/* 6046/*
@@ -6283,6 +6285,9 @@ retry:
6283static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, 6285static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6284 struct intel_crtc_state *pipe_config) 6286 struct intel_crtc_state *pipe_config)
6285{ 6287{
6288 if (pipe_config->ips_force_disable)
6289 return false;
6290
6286 if (pipe_config->pipe_bpp > 24) 6291 if (pipe_config->pipe_bpp > 24)
6287 return false; 6292 return false;
6288 6293
@@ -9039,7 +9044,7 @@ static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9039 u32 temp; 9044 u32 temp;
9040 9045
9041 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 9046 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9042 id = temp >> (port * 2); 9047 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9043 9048
9044 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) 9049 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9045 return; 9050 return;
@@ -9753,7 +9758,7 @@ static void i9xx_disable_cursor(struct intel_plane *plane,
9753 9758
9754 9759
9755/* VESA 640x480x72Hz mode to set on the pipe */ 9760/* VESA 640x480x72Hz mode to set on the pipe */
9756static struct drm_display_mode load_detect_mode = { 9761static const struct drm_display_mode load_detect_mode = {
9757 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 9762 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9758 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 9763 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9759}; 9764};
@@ -9788,7 +9793,7 @@ intel_framebuffer_pitch_for_width(int width, int bpp)
9788} 9793}
9789 9794
9790static u32 9795static u32
9791intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) 9796intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9792{ 9797{
9793 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); 9798 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9794 return PAGE_ALIGN(pitch * mode->vdisplay); 9799 return PAGE_ALIGN(pitch * mode->vdisplay);
@@ -9796,7 +9801,7 @@ intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9796 9801
9797static struct drm_framebuffer * 9802static struct drm_framebuffer *
9798intel_framebuffer_create_for_mode(struct drm_device *dev, 9803intel_framebuffer_create_for_mode(struct drm_device *dev,
9799 struct drm_display_mode *mode, 9804 const struct drm_display_mode *mode,
9800 int depth, int bpp) 9805 int depth, int bpp)
9801{ 9806{
9802 struct drm_framebuffer *fb; 9807 struct drm_framebuffer *fb;
@@ -9823,7 +9828,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev,
9823 9828
9824static struct drm_framebuffer * 9829static struct drm_framebuffer *
9825mode_fits_in_fbdev(struct drm_device *dev, 9830mode_fits_in_fbdev(struct drm_device *dev,
9826 struct drm_display_mode *mode) 9831 const struct drm_display_mode *mode)
9827{ 9832{
9828#ifdef CONFIG_DRM_FBDEV_EMULATION 9833#ifdef CONFIG_DRM_FBDEV_EMULATION
9829 struct drm_i915_private *dev_priv = to_i915(dev); 9834 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -9856,7 +9861,7 @@ mode_fits_in_fbdev(struct drm_device *dev,
9856 9861
9857static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, 9862static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9858 struct drm_crtc *crtc, 9863 struct drm_crtc *crtc,
9859 struct drm_display_mode *mode, 9864 const struct drm_display_mode *mode,
9860 struct drm_framebuffer *fb, 9865 struct drm_framebuffer *fb,
9861 int x, int y) 9866 int x, int y)
9862{ 9867{
@@ -9890,7 +9895,7 @@ static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9890} 9895}
9891 9896
9892int intel_get_load_detect_pipe(struct drm_connector *connector, 9897int intel_get_load_detect_pipe(struct drm_connector *connector,
9893 struct drm_display_mode *mode, 9898 const struct drm_display_mode *mode,
9894 struct intel_load_detect_pipe *old, 9899 struct intel_load_detect_pipe *old,
9895 struct drm_modeset_acquire_ctx *ctx) 9900 struct drm_modeset_acquire_ctx *ctx)
9896{ 9901{
@@ -10337,7 +10342,7 @@ static bool intel_wm_need_update(struct drm_plane *plane,
10337 return false; 10342 return false;
10338} 10343}
10339 10344
10340static bool needs_scaling(struct intel_plane_state *state) 10345static bool needs_scaling(const struct intel_plane_state *state)
10341{ 10346{
10342 int src_w = drm_rect_width(&state->base.src) >> 16; 10347 int src_w = drm_rect_width(&state->base.src) >> 16;
10343 int src_h = drm_rect_height(&state->base.src) >> 16; 10348 int src_h = drm_rect_height(&state->base.src) >> 16;
@@ -10347,7 +10352,9 @@ static bool needs_scaling(struct intel_plane_state *state)
10347 return (src_w != dst_w || src_h != dst_h); 10352 return (src_w != dst_w || src_h != dst_h);
10348} 10353}
10349 10354
10350int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, 10355int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10356 struct drm_crtc_state *crtc_state,
10357 const struct intel_plane_state *old_plane_state,
10351 struct drm_plane_state *plane_state) 10358 struct drm_plane_state *plane_state)
10352{ 10359{
10353 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); 10360 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
@@ -10356,10 +10363,8 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10356 struct intel_plane *plane = to_intel_plane(plane_state->plane); 10363 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10357 struct drm_device *dev = crtc->dev; 10364 struct drm_device *dev = crtc->dev;
10358 struct drm_i915_private *dev_priv = to_i915(dev); 10365 struct drm_i915_private *dev_priv = to_i915(dev);
10359 struct intel_plane_state *old_plane_state =
10360 to_intel_plane_state(plane->base.state);
10361 bool mode_changed = needs_modeset(crtc_state); 10366 bool mode_changed = needs_modeset(crtc_state);
10362 bool was_crtc_enabled = crtc->state->active; 10367 bool was_crtc_enabled = old_crtc_state->base.active;
10363 bool is_crtc_enabled = crtc_state->active; 10368 bool is_crtc_enabled = crtc_state->active;
10364 bool turn_off, turn_on, visible, was_visible; 10369 bool turn_off, turn_on, visible, was_visible;
10365 struct drm_framebuffer *fb = plane_state->fb; 10370 struct drm_framebuffer *fb = plane_state->fb;
@@ -10850,7 +10855,7 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10850 struct intel_dpll_hw_state dpll_hw_state; 10855 struct intel_dpll_hw_state dpll_hw_state;
10851 struct intel_shared_dpll *shared_dpll; 10856 struct intel_shared_dpll *shared_dpll;
10852 struct intel_crtc_wm_state wm_state; 10857 struct intel_crtc_wm_state wm_state;
10853 bool force_thru; 10858 bool force_thru, ips_force_disable;
10854 10859
10855 /* FIXME: before the switch to atomic started, a new pipe_config was 10860 /* FIXME: before the switch to atomic started, a new pipe_config was
10856 * kzalloc'd. Code that depends on any field being zero should be 10861 * kzalloc'd. Code that depends on any field being zero should be
@@ -10861,6 +10866,7 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10861 shared_dpll = crtc_state->shared_dpll; 10866 shared_dpll = crtc_state->shared_dpll;
10862 dpll_hw_state = crtc_state->dpll_hw_state; 10867 dpll_hw_state = crtc_state->dpll_hw_state;
10863 force_thru = crtc_state->pch_pfit.force_thru; 10868 force_thru = crtc_state->pch_pfit.force_thru;
10869 ips_force_disable = crtc_state->ips_force_disable;
10864 if (IS_G4X(dev_priv) || 10870 if (IS_G4X(dev_priv) ||
10865 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 10871 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10866 wm_state = crtc_state->wm; 10872 wm_state = crtc_state->wm;
@@ -10874,6 +10880,7 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10874 crtc_state->shared_dpll = shared_dpll; 10880 crtc_state->shared_dpll = shared_dpll;
10875 crtc_state->dpll_hw_state = dpll_hw_state; 10881 crtc_state->dpll_hw_state = dpll_hw_state;
10876 crtc_state->pch_pfit.force_thru = force_thru; 10882 crtc_state->pch_pfit.force_thru = force_thru;
10883 crtc_state->ips_force_disable = ips_force_disable;
10877 if (IS_G4X(dev_priv) || 10884 if (IS_G4X(dev_priv) ||
10878 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 10885 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10879 crtc_state->wm = wm_state; 10886 crtc_state->wm = wm_state;
@@ -12206,7 +12213,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
12206 unsigned int cmask = drm_crtc_mask(crtc); 12213 unsigned int cmask = drm_crtc_mask(crtc);
12207 12214
12208 intel_crtc = to_intel_crtc(crtc); 12215 intel_crtc = to_intel_crtc(crtc);
12209 cstate = to_intel_crtc_state(crtc->state); 12216 cstate = to_intel_crtc_state(new_crtc_state);
12210 pipe = intel_crtc->pipe; 12217 pipe = intel_crtc->pipe;
12211 12218
12212 if (updated & cmask || !cstate->base.active) 12219 if (updated & cmask || !cstate->base.active)
@@ -12334,7 +12341,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12334 intel_check_cpu_fifo_underruns(dev_priv); 12341 intel_check_cpu_fifo_underruns(dev_priv);
12335 intel_check_pch_fifo_underruns(dev_priv); 12342 intel_check_pch_fifo_underruns(dev_priv);
12336 12343
12337 if (!crtc->state->active) { 12344 if (!new_crtc_state->active) {
12338 /* 12345 /*
12339 * Make sure we don't call initial_watermarks 12346 * Make sure we don't call initial_watermarks
12340 * for ILK-style watermark updates. 12347 * for ILK-style watermark updates.
@@ -12343,7 +12350,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12343 */ 12350 */
12344 if (INTEL_GEN(dev_priv) >= 9) 12351 if (INTEL_GEN(dev_priv) >= 9)
12345 dev_priv->display.initial_watermarks(intel_state, 12352 dev_priv->display.initial_watermarks(intel_state,
12346 to_intel_crtc_state(crtc->state)); 12353 to_intel_crtc_state(new_crtc_state));
12347 } 12354 }
12348 } 12355 }
12349 } 12356 }
@@ -12556,8 +12563,8 @@ static int intel_atomic_commit(struct drm_device *dev,
12556 intel_atomic_track_fbs(state); 12563 intel_atomic_track_fbs(state);
12557 12564
12558 if (intel_state->modeset) { 12565 if (intel_state->modeset) {
12559 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, 12566 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12560 sizeof(intel_state->min_pixclk)); 12567 sizeof(intel_state->min_cdclk));
12561 dev_priv->active_crtcs = intel_state->active_crtcs; 12568 dev_priv->active_crtcs = intel_state->active_crtcs;
12562 dev_priv->cdclk.logical = intel_state->cdclk.logical; 12569 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12563 dev_priv->cdclk.actual = intel_state->cdclk.actual; 12570 dev_priv->cdclk.actual = intel_state->cdclk.actual;
@@ -12586,6 +12593,58 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
12586 .set_crc_source = intel_crtc_set_crc_source, 12593 .set_crc_source = intel_crtc_set_crc_source,
12587}; 12594};
12588 12595
12596struct wait_rps_boost {
12597 struct wait_queue_entry wait;
12598
12599 struct drm_crtc *crtc;
12600 struct drm_i915_gem_request *request;
12601};
12602
12603static int do_rps_boost(struct wait_queue_entry *_wait,
12604 unsigned mode, int sync, void *key)
12605{
12606 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12607 struct drm_i915_gem_request *rq = wait->request;
12608
12609 gen6_rps_boost(rq, NULL);
12610 i915_gem_request_put(rq);
12611
12612 drm_crtc_vblank_put(wait->crtc);
12613
12614 list_del(&wait->wait.entry);
12615 kfree(wait);
12616 return 1;
12617}
12618
12619static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12620 struct dma_fence *fence)
12621{
12622 struct wait_rps_boost *wait;
12623
12624 if (!dma_fence_is_i915(fence))
12625 return;
12626
12627 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12628 return;
12629
12630 if (drm_crtc_vblank_get(crtc))
12631 return;
12632
12633 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12634 if (!wait) {
12635 drm_crtc_vblank_put(crtc);
12636 return;
12637 }
12638
12639 wait->request = to_request(dma_fence_get(fence));
12640 wait->crtc = crtc;
12641
12642 wait->wait.func = do_rps_boost;
12643 wait->wait.flags = 0;
12644
12645 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12646}
12647
12589/** 12648/**
12590 * intel_prepare_plane_fb - Prepare fb for usage on plane 12649 * intel_prepare_plane_fb - Prepare fb for usage on plane
12591 * @plane: drm plane to prepare for 12650 * @plane: drm plane to prepare for
@@ -12683,12 +12742,22 @@ intel_prepare_plane_fb(struct drm_plane *plane,
12683 return ret; 12742 return ret;
12684 12743
12685 if (!new_state->fence) { /* implicit fencing */ 12744 if (!new_state->fence) { /* implicit fencing */
12745 struct dma_fence *fence;
12746
12686 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, 12747 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12687 obj->resv, NULL, 12748 obj->resv, NULL,
12688 false, I915_FENCE_TIMEOUT, 12749 false, I915_FENCE_TIMEOUT,
12689 GFP_KERNEL); 12750 GFP_KERNEL);
12690 if (ret < 0) 12751 if (ret < 0)
12691 return ret; 12752 return ret;
12753
12754 fence = reservation_object_get_excl_rcu(obj->resv);
12755 if (fence) {
12756 add_rps_boost_after_vblank(new_state->crtc, fence);
12757 dma_fence_put(fence);
12758 }
12759 } else {
12760 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12692 } 12761 }
12693 12762
12694 return 0; 12763 return 0;
@@ -12805,29 +12874,29 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12805 struct drm_device *dev = crtc->dev; 12874 struct drm_device *dev = crtc->dev;
12806 struct drm_i915_private *dev_priv = to_i915(dev); 12875 struct drm_i915_private *dev_priv = to_i915(dev);
12807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12808 struct intel_crtc_state *intel_cstate =
12809 to_intel_crtc_state(crtc->state);
12810 struct intel_crtc_state *old_intel_cstate = 12877 struct intel_crtc_state *old_intel_cstate =
12811 to_intel_crtc_state(old_crtc_state); 12878 to_intel_crtc_state(old_crtc_state);
12812 struct intel_atomic_state *old_intel_state = 12879 struct intel_atomic_state *old_intel_state =
12813 to_intel_atomic_state(old_crtc_state->state); 12880 to_intel_atomic_state(old_crtc_state->state);
12814 bool modeset = needs_modeset(crtc->state); 12881 struct intel_crtc_state *intel_cstate =
12882 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12883 bool modeset = needs_modeset(&intel_cstate->base);
12815 12884
12816 if (!modeset && 12885 if (!modeset &&
12817 (intel_cstate->base.color_mgmt_changed || 12886 (intel_cstate->base.color_mgmt_changed ||
12818 intel_cstate->update_pipe)) { 12887 intel_cstate->update_pipe)) {
12819 intel_color_set_csc(crtc->state); 12888 intel_color_set_csc(&intel_cstate->base);
12820 intel_color_load_luts(crtc->state); 12889 intel_color_load_luts(&intel_cstate->base);
12821 } 12890 }
12822 12891
12823 /* Perform vblank evasion around commit operation */ 12892 /* Perform vblank evasion around commit operation */
12824 intel_pipe_update_start(intel_crtc); 12893 intel_pipe_update_start(intel_cstate);
12825 12894
12826 if (modeset) 12895 if (modeset)
12827 goto out; 12896 goto out;
12828 12897
12829 if (intel_cstate->update_pipe) 12898 if (intel_cstate->update_pipe)
12830 intel_update_pipe_config(intel_crtc, old_intel_cstate); 12899 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12831 else if (INTEL_GEN(dev_priv) >= 9) 12900 else if (INTEL_GEN(dev_priv) >= 9)
12832 skl_detach_scalers(intel_crtc); 12901 skl_detach_scalers(intel_crtc);
12833 12902
@@ -12841,8 +12910,12 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12841 struct drm_crtc_state *old_crtc_state) 12910 struct drm_crtc_state *old_crtc_state)
12842{ 12911{
12843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12913 struct intel_atomic_state *old_intel_state =
12914 to_intel_atomic_state(old_crtc_state->state);
12915 struct intel_crtc_state *new_crtc_state =
12916 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12844 12917
12845 intel_pipe_update_end(intel_crtc); 12918 intel_pipe_update_end(new_crtc_state);
12846} 12919}
12847 12920
12848/** 12921/**
@@ -13029,6 +13102,8 @@ intel_legacy_cursor_update(struct drm_plane *plane,
13029 new_plane_state->crtc_h = crtc_h; 13102 new_plane_state->crtc_h = crtc_h;
13030 13103
13031 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), 13104 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13105 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13106 to_intel_plane_state(plane->state),
13032 to_intel_plane_state(new_plane_state)); 13107 to_intel_plane_state(new_plane_state));
13033 if (ret) 13108 if (ret)
13034 goto out_free; 13109 goto out_free;
@@ -13600,7 +13675,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13600 13675
13601 } else if (HAS_PCH_SPLIT(dev_priv)) { 13676 } else if (HAS_PCH_SPLIT(dev_priv)) {
13602 int found; 13677 int found;
13603 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); 13678 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13604 13679
13605 if (has_edp_a(dev_priv)) 13680 if (has_edp_a(dev_priv))
13606 intel_dp_init(dev_priv, DP_A, PORT_A); 13681 intel_dp_init(dev_priv, DP_A, PORT_A);
@@ -13643,14 +13718,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13643 * trust the port type the VBT declares as we've seen at least 13718 * trust the port type the VBT declares as we've seen at least
13644 * HDMI ports that the VBT claim are DP or eDP. 13719 * HDMI ports that the VBT claim are DP or eDP.
13645 */ 13720 */
13646 has_edp = intel_dp_is_edp(dev_priv, PORT_B); 13721 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13647 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 13722 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13648 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) 13723 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13649 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); 13724 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13650 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 13725 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13651 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 13726 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13652 13727
13653 has_edp = intel_dp_is_edp(dev_priv, PORT_C); 13728 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13654 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 13729 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13655 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) 13730 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13656 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); 13731 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
@@ -14967,7 +15042,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
14967 for_each_intel_crtc(dev, crtc) { 15042 for_each_intel_crtc(dev, crtc) {
14968 struct intel_crtc_state *crtc_state = 15043 struct intel_crtc_state *crtc_state =
14969 to_intel_crtc_state(crtc->base.state); 15044 to_intel_crtc_state(crtc->base.state);
14970 int pixclk = 0; 15045 int min_cdclk = 0;
14971 15046
14972 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); 15047 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
14973 if (crtc_state->base.active) { 15048 if (crtc_state->base.active) {
@@ -14988,22 +15063,18 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
14988 15063
14989 intel_crtc_compute_pixel_rate(crtc_state); 15064 intel_crtc_compute_pixel_rate(crtc_state);
14990 15065
14991 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || 15066 if (dev_priv->display.modeset_calc_cdclk) {
14992 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 15067 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
14993 pixclk = crtc_state->pixel_rate; 15068 if (WARN_ON(min_cdclk < 0))
14994 else 15069 min_cdclk = 0;
14995 WARN_ON(dev_priv->display.modeset_calc_cdclk); 15070 }
14996
14997 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
14998 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
14999 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15000 15071
15001 drm_calc_timestamping_constants(&crtc->base, 15072 drm_calc_timestamping_constants(&crtc->base,
15002 &crtc_state->base.adjusted_mode); 15073 &crtc_state->base.adjusted_mode);
15003 update_scanline_offset(crtc); 15074 update_scanline_offset(crtc);
15004 } 15075 }
15005 15076
15006 dev_priv->min_pixclk[crtc->pipe] = pixclk; 15077 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15007 15078
15008 intel_pipe_config_sanity_check(dev_priv, crtc_state); 15079 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15009 } 15080 }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 64134947c0aa..887953c0f495 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -103,13 +103,13 @@ static const int cnl_rates[] = { 162000, 216000, 270000,
103static const int default_rates[] = { 162000, 270000, 540000 }; 103static const int default_rates[] = { 162000, 270000, 540000 };
104 104
105/** 105/**
106 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 106 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
107 * @intel_dp: DP struct 107 * @intel_dp: DP struct
108 * 108 *
109 * If a CPU or PCH DP output is attached to an eDP panel, this function 109 * If a CPU or PCH DP output is attached to an eDP panel, this function
110 * will return true, and false otherwise. 110 * will return true, and false otherwise.
111 */ 111 */
112static bool is_edp(struct intel_dp *intel_dp) 112bool intel_dp_is_edp(struct intel_dp *intel_dp)
113{ 113{
114 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 114 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
115 115
@@ -388,7 +388,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
388 388
389 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); 389 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
390 390
391 if (is_edp(intel_dp) && fixed_mode) { 391 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
392 if (mode->hdisplay > fixed_mode->hdisplay) 392 if (mode->hdisplay > fixed_mode->hdisplay)
393 return MODE_PANEL; 393 return MODE_PANEL;
394 394
@@ -597,7 +597,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
597 lockdep_assert_held(&dev_priv->pps_mutex); 597 lockdep_assert_held(&dev_priv->pps_mutex);
598 598
599 /* We should never land here with regular DP ports */ 599 /* We should never land here with regular DP ports */
600 WARN_ON(!is_edp(intel_dp)); 600 WARN_ON(!intel_dp_is_edp(intel_dp));
601 601
602 WARN_ON(intel_dp->active_pipe != INVALID_PIPE && 602 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
603 intel_dp->active_pipe != intel_dp->pps_pipe); 603 intel_dp->active_pipe != intel_dp->pps_pipe);
@@ -644,7 +644,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
644 lockdep_assert_held(&dev_priv->pps_mutex); 644 lockdep_assert_held(&dev_priv->pps_mutex);
645 645
646 /* We should never land here with regular DP ports */ 646 /* We should never land here with regular DP ports */
647 WARN_ON(!is_edp(intel_dp)); 647 WARN_ON(!intel_dp_is_edp(intel_dp));
648 648
649 /* 649 /*
650 * TODO: BXT has 2 PPS instances. The correct port->PPS instance 650 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
@@ -847,7 +847,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
847 struct drm_device *dev = intel_dp_to_dev(intel_dp); 847 struct drm_device *dev = intel_dp_to_dev(intel_dp);
848 struct drm_i915_private *dev_priv = to_i915(dev); 848 struct drm_i915_private *dev_priv = to_i915(dev);
849 849
850 if (!is_edp(intel_dp) || code != SYS_RESTART) 850 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
851 return 0; 851 return 0;
852 852
853 pps_lock(intel_dp); 853 pps_lock(intel_dp);
@@ -907,7 +907,7 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
907 struct drm_device *dev = intel_dp_to_dev(intel_dp); 907 struct drm_device *dev = intel_dp_to_dev(intel_dp);
908 struct drm_i915_private *dev_priv = to_i915(dev); 908 struct drm_i915_private *dev_priv = to_i915(dev);
909 909
910 if (!is_edp(intel_dp)) 910 if (!intel_dp_is_edp(intel_dp))
911 return; 911 return;
912 912
913 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 913 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
@@ -1681,7 +1681,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
1681 else 1681 else
1682 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; 1682 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1683 1683
1684 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1684 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1685 struct drm_display_mode *panel_mode = 1685 struct drm_display_mode *panel_mode =
1686 intel_connector->panel.alt_fixed_mode; 1686 intel_connector->panel.alt_fixed_mode;
1687 struct drm_display_mode *req_mode = &pipe_config->base.mode; 1687 struct drm_display_mode *req_mode = &pipe_config->base.mode;
@@ -1736,7 +1736,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
1736 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 1736 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1737 * bpc in between. */ 1737 * bpc in between. */
1738 bpp = intel_dp_compute_bpp(intel_dp, pipe_config); 1738 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1739 if (is_edp(intel_dp)) { 1739 if (intel_dp_is_edp(intel_dp)) {
1740 1740
1741 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1741 /* Get bpp from vbt only for panels that dont have bpp in edid */
1742 if (intel_connector->base.display_info.bpc == 0 && 1742 if (intel_connector->base.display_info.bpc == 0 &&
@@ -1829,7 +1829,7 @@ found:
1829 * DPLL0 VCO may need to be adjusted to get the correct 1829 * DPLL0 VCO may need to be adjusted to get the correct
1830 * clock for eDP. This will affect cdclk as well. 1830 * clock for eDP. This will affect cdclk as well.
1831 */ 1831 */
1832 if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) { 1832 if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1833 int vco; 1833 int vco;
1834 1834
1835 switch (pipe_config->port_clock / 2) { 1835 switch (pipe_config->port_clock / 2) {
@@ -1861,7 +1861,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
1861} 1861}
1862 1862
1863static void intel_dp_prepare(struct intel_encoder *encoder, 1863static void intel_dp_prepare(struct intel_encoder *encoder,
1864 struct intel_crtc_state *pipe_config) 1864 const struct intel_crtc_state *pipe_config)
1865{ 1865{
1866 struct drm_device *dev = encoder->base.dev; 1866 struct drm_device *dev = encoder->base.dev;
1867 struct drm_i915_private *dev_priv = to_i915(dev); 1867 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -2069,7 +2069,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2069 2069
2070 lockdep_assert_held(&dev_priv->pps_mutex); 2070 lockdep_assert_held(&dev_priv->pps_mutex);
2071 2071
2072 if (!is_edp(intel_dp)) 2072 if (!intel_dp_is_edp(intel_dp))
2073 return false; 2073 return false;
2074 2074
2075 cancel_delayed_work(&intel_dp->panel_vdd_work); 2075 cancel_delayed_work(&intel_dp->panel_vdd_work);
@@ -2119,7 +2119,7 @@ void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2119{ 2119{
2120 bool vdd; 2120 bool vdd;
2121 2121
2122 if (!is_edp(intel_dp)) 2122 if (!intel_dp_is_edp(intel_dp))
2123 return; 2123 return;
2124 2124
2125 pps_lock(intel_dp); 2125 pps_lock(intel_dp);
@@ -2203,7 +2203,7 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2203 2203
2204 lockdep_assert_held(&dev_priv->pps_mutex); 2204 lockdep_assert_held(&dev_priv->pps_mutex);
2205 2205
2206 if (!is_edp(intel_dp)) 2206 if (!intel_dp_is_edp(intel_dp))
2207 return; 2207 return;
2208 2208
2209 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", 2209 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
@@ -2226,7 +2226,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
2226 2226
2227 lockdep_assert_held(&dev_priv->pps_mutex); 2227 lockdep_assert_held(&dev_priv->pps_mutex);
2228 2228
2229 if (!is_edp(intel_dp)) 2229 if (!intel_dp_is_edp(intel_dp))
2230 return; 2230 return;
2231 2231
2232 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", 2232 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
@@ -2267,7 +2267,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
2267 2267
2268void intel_edp_panel_on(struct intel_dp *intel_dp) 2268void intel_edp_panel_on(struct intel_dp *intel_dp)
2269{ 2269{
2270 if (!is_edp(intel_dp)) 2270 if (!intel_dp_is_edp(intel_dp))
2271 return; 2271 return;
2272 2272
2273 pps_lock(intel_dp); 2273 pps_lock(intel_dp);
@@ -2285,7 +2285,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
2285 2285
2286 lockdep_assert_held(&dev_priv->pps_mutex); 2286 lockdep_assert_held(&dev_priv->pps_mutex);
2287 2287
2288 if (!is_edp(intel_dp)) 2288 if (!intel_dp_is_edp(intel_dp))
2289 return; 2289 return;
2290 2290
2291 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", 2291 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
@@ -2316,7 +2316,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
2316 2316
2317void intel_edp_panel_off(struct intel_dp *intel_dp) 2317void intel_edp_panel_off(struct intel_dp *intel_dp)
2318{ 2318{
2319 if (!is_edp(intel_dp)) 2319 if (!intel_dp_is_edp(intel_dp))
2320 return; 2320 return;
2321 2321
2322 pps_lock(intel_dp); 2322 pps_lock(intel_dp);
@@ -2360,7 +2360,7 @@ void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2360{ 2360{
2361 struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder); 2361 struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2362 2362
2363 if (!is_edp(intel_dp)) 2363 if (!intel_dp_is_edp(intel_dp))
2364 return; 2364 return;
2365 2365
2366 DRM_DEBUG_KMS("\n"); 2366 DRM_DEBUG_KMS("\n");
@@ -2377,7 +2377,7 @@ static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2377 u32 pp; 2377 u32 pp;
2378 i915_reg_t pp_ctrl_reg; 2378 i915_reg_t pp_ctrl_reg;
2379 2379
2380 if (!is_edp(intel_dp)) 2380 if (!intel_dp_is_edp(intel_dp))
2381 return; 2381 return;
2382 2382
2383 pps_lock(intel_dp); 2383 pps_lock(intel_dp);
@@ -2401,7 +2401,7 @@ void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2401{ 2401{
2402 struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder); 2402 struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2403 2403
2404 if (!is_edp(intel_dp)) 2404 if (!intel_dp_is_edp(intel_dp))
2405 return; 2405 return;
2406 2406
2407 DRM_DEBUG_KMS("\n"); 2407 DRM_DEBUG_KMS("\n");
@@ -2461,7 +2461,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2461#define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 2461#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2462 2462
2463static void ironlake_edp_pll_on(struct intel_dp *intel_dp, 2463static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2464 struct intel_crtc_state *pipe_config) 2464 const struct intel_crtc_state *pipe_config)
2465{ 2465{
2466 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 2466 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2467 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2467 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2666,7 +2666,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
2666 intel_dotclock_calculate(pipe_config->port_clock, 2666 intel_dotclock_calculate(pipe_config->port_clock,
2667 &pipe_config->dp_m_n); 2667 &pipe_config->dp_m_n);
2668 2668
2669 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && 2669 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2670 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 2670 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2671 /* 2671 /*
2672 * This is a big fat ugly hack. 2672 * This is a big fat ugly hack.
@@ -2688,8 +2688,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
2688} 2688}
2689 2689
2690static void intel_disable_dp(struct intel_encoder *encoder, 2690static void intel_disable_dp(struct intel_encoder *encoder,
2691 struct intel_crtc_state *old_crtc_state, 2691 const struct intel_crtc_state *old_crtc_state,
2692 struct drm_connector_state *old_conn_state) 2692 const struct drm_connector_state *old_conn_state)
2693{ 2693{
2694 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2694 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2695 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2695 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2698,7 +2698,7 @@ static void intel_disable_dp(struct intel_encoder *encoder,
2698 intel_audio_codec_disable(encoder); 2698 intel_audio_codec_disable(encoder);
2699 2699
2700 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) 2700 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2701 intel_psr_disable(intel_dp); 2701 intel_psr_disable(intel_dp, old_crtc_state);
2702 2702
2703 /* Make sure the panel is off before trying to change the mode. But also 2703 /* Make sure the panel is off before trying to change the mode. But also
2704 * ensure that we have vdd while we switch off the panel. */ 2704 * ensure that we have vdd while we switch off the panel. */
@@ -2713,8 +2713,8 @@ static void intel_disable_dp(struct intel_encoder *encoder,
2713} 2713}
2714 2714
2715static void ilk_post_disable_dp(struct intel_encoder *encoder, 2715static void ilk_post_disable_dp(struct intel_encoder *encoder,
2716 struct intel_crtc_state *old_crtc_state, 2716 const struct intel_crtc_state *old_crtc_state,
2717 struct drm_connector_state *old_conn_state) 2717 const struct drm_connector_state *old_conn_state)
2718{ 2718{
2719 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2719 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2720 enum port port = dp_to_dig_port(intel_dp)->port; 2720 enum port port = dp_to_dig_port(intel_dp)->port;
@@ -2727,8 +2727,8 @@ static void ilk_post_disable_dp(struct intel_encoder *encoder,
2727} 2727}
2728 2728
2729static void vlv_post_disable_dp(struct intel_encoder *encoder, 2729static void vlv_post_disable_dp(struct intel_encoder *encoder,
2730 struct intel_crtc_state *old_crtc_state, 2730 const struct intel_crtc_state *old_crtc_state,
2731 struct drm_connector_state *old_conn_state) 2731 const struct drm_connector_state *old_conn_state)
2732{ 2732{
2733 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2733 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2734 2734
@@ -2736,8 +2736,8 @@ static void vlv_post_disable_dp(struct intel_encoder *encoder,
2736} 2736}
2737 2737
2738static void chv_post_disable_dp(struct intel_encoder *encoder, 2738static void chv_post_disable_dp(struct intel_encoder *encoder,
2739 struct intel_crtc_state *old_crtc_state, 2739 const struct intel_crtc_state *old_crtc_state,
2740 struct drm_connector_state *old_conn_state) 2740 const struct drm_connector_state *old_conn_state)
2741{ 2741{
2742 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2742 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2743 struct drm_device *dev = encoder->base.dev; 2743 struct drm_device *dev = encoder->base.dev;
@@ -2842,7 +2842,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
2842} 2842}
2843 2843
2844static void intel_dp_enable_port(struct intel_dp *intel_dp, 2844static void intel_dp_enable_port(struct intel_dp *intel_dp,
2845 struct intel_crtc_state *old_crtc_state) 2845 const struct intel_crtc_state *old_crtc_state)
2846{ 2846{
2847 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2847 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2848 struct drm_i915_private *dev_priv = to_i915(dev); 2848 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -2866,8 +2866,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
2866} 2866}
2867 2867
2868static void intel_enable_dp(struct intel_encoder *encoder, 2868static void intel_enable_dp(struct intel_encoder *encoder,
2869 struct intel_crtc_state *pipe_config, 2869 const struct intel_crtc_state *pipe_config,
2870 struct drm_connector_state *conn_state) 2870 const struct drm_connector_state *conn_state)
2871{ 2871{
2872 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2872 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2873 struct drm_device *dev = encoder->base.dev; 2873 struct drm_device *dev = encoder->base.dev;
@@ -2914,26 +2914,26 @@ static void intel_enable_dp(struct intel_encoder *encoder,
2914} 2914}
2915 2915
2916static void g4x_enable_dp(struct intel_encoder *encoder, 2916static void g4x_enable_dp(struct intel_encoder *encoder,
2917 struct intel_crtc_state *pipe_config, 2917 const struct intel_crtc_state *pipe_config,
2918 struct drm_connector_state *conn_state) 2918 const struct drm_connector_state *conn_state)
2919{ 2919{
2920 intel_enable_dp(encoder, pipe_config, conn_state); 2920 intel_enable_dp(encoder, pipe_config, conn_state);
2921 intel_edp_backlight_on(pipe_config, conn_state); 2921 intel_edp_backlight_on(pipe_config, conn_state);
2922} 2922}
2923 2923
2924static void vlv_enable_dp(struct intel_encoder *encoder, 2924static void vlv_enable_dp(struct intel_encoder *encoder,
2925 struct intel_crtc_state *pipe_config, 2925 const struct intel_crtc_state *pipe_config,
2926 struct drm_connector_state *conn_state) 2926 const struct drm_connector_state *conn_state)
2927{ 2927{
2928 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2928 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2929 2929
2930 intel_edp_backlight_on(pipe_config, conn_state); 2930 intel_edp_backlight_on(pipe_config, conn_state);
2931 intel_psr_enable(intel_dp); 2931 intel_psr_enable(intel_dp, pipe_config);
2932} 2932}
2933 2933
2934static void g4x_pre_enable_dp(struct intel_encoder *encoder, 2934static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2935 struct intel_crtc_state *pipe_config, 2935 const struct intel_crtc_state *pipe_config,
2936 struct drm_connector_state *conn_state) 2936 const struct drm_connector_state *conn_state)
2937{ 2937{
2938 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2938 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2939 enum port port = dp_to_dig_port(intel_dp)->port; 2939 enum port port = dp_to_dig_port(intel_dp)->port;
@@ -3040,7 +3040,7 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
3040 3040
3041 intel_dp->active_pipe = crtc->pipe; 3041 intel_dp->active_pipe = crtc->pipe;
3042 3042
3043 if (!is_edp(intel_dp)) 3043 if (!intel_dp_is_edp(intel_dp))
3044 return; 3044 return;
3045 3045
3046 /* now it's all ours */ 3046 /* now it's all ours */
@@ -3055,8 +3055,8 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
3055} 3055}
3056 3056
3057static void vlv_pre_enable_dp(struct intel_encoder *encoder, 3057static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3058 struct intel_crtc_state *pipe_config, 3058 const struct intel_crtc_state *pipe_config,
3059 struct drm_connector_state *conn_state) 3059 const struct drm_connector_state *conn_state)
3060{ 3060{
3061 vlv_phy_pre_encoder_enable(encoder); 3061 vlv_phy_pre_encoder_enable(encoder);
3062 3062
@@ -3064,8 +3064,8 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3064} 3064}
3065 3065
3066static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, 3066static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3067 struct intel_crtc_state *pipe_config, 3067 const struct intel_crtc_state *pipe_config,
3068 struct drm_connector_state *conn_state) 3068 const struct drm_connector_state *conn_state)
3069{ 3069{
3070 intel_dp_prepare(encoder, pipe_config); 3070 intel_dp_prepare(encoder, pipe_config);
3071 3071
@@ -3073,8 +3073,8 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3073} 3073}
3074 3074
3075static void chv_pre_enable_dp(struct intel_encoder *encoder, 3075static void chv_pre_enable_dp(struct intel_encoder *encoder,
3076 struct intel_crtc_state *pipe_config, 3076 const struct intel_crtc_state *pipe_config,
3077 struct drm_connector_state *conn_state) 3077 const struct drm_connector_state *conn_state)
3078{ 3078{
3079 chv_phy_pre_encoder_enable(encoder); 3079 chv_phy_pre_encoder_enable(encoder);
3080 3080
@@ -3085,8 +3085,8 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder,
3085} 3085}
3086 3086
3087static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, 3087static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3088 struct intel_crtc_state *pipe_config, 3088 const struct intel_crtc_state *pipe_config,
3089 struct drm_connector_state *conn_state) 3089 const struct drm_connector_state *conn_state)
3090{ 3090{
3091 intel_dp_prepare(encoder, pipe_config); 3091 intel_dp_prepare(encoder, pipe_config);
3092 3092
@@ -3094,8 +3094,8 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3094} 3094}
3095 3095
3096static void chv_dp_post_pll_disable(struct intel_encoder *encoder, 3096static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3097 struct intel_crtc_state *pipe_config, 3097 const struct intel_crtc_state *pipe_config,
3098 struct drm_connector_state *conn_state) 3098 const struct drm_connector_state *conn_state)
3099{ 3099{
3100 chv_phy_post_pll_disable(encoder); 3100 chv_phy_post_pll_disable(encoder);
3101} 3101}
@@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3506 uint32_t signal_levels, mask = 0; 3506 uint32_t signal_levels, mask = 0;
3507 uint8_t train_set = intel_dp->train_set[0]; 3507 uint8_t train_set = intel_dp->train_set[0];
3508 3508
3509 if (HAS_DDI(dev_priv)) { 3509 if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3510 signal_levels = bxt_signal_levels(intel_dp);
3511 } else if (HAS_DDI(dev_priv)) {
3510 signal_levels = ddi_signal_levels(intel_dp); 3512 signal_levels = ddi_signal_levels(intel_dp);
3511 3513 mask = DDI_BUF_EMP_MASK;
3512 if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
3513 signal_levels = 0;
3514 else
3515 mask = DDI_BUF_EMP_MASK;
3516 } else if (IS_CHERRYVIEW(dev_priv)) { 3514 } else if (IS_CHERRYVIEW(dev_priv)) {
3517 signal_levels = chv_signal_levels(intel_dp); 3515 signal_levels = chv_signal_levels(intel_dp);
3518 } else if (IS_VALLEYVIEW(dev_priv)) { 3516 } else if (IS_VALLEYVIEW(dev_priv)) {
@@ -3784,7 +3782,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
3784 return false; 3782 return false;
3785 3783
3786 /* Don't clobber cached eDP rates. */ 3784 /* Don't clobber cached eDP rates. */
3787 if (!is_edp(intel_dp)) { 3785 if (!intel_dp_is_edp(intel_dp)) {
3788 intel_dp_set_sink_rates(intel_dp); 3786 intel_dp_set_sink_rates(intel_dp);
3789 intel_dp_set_common_rates(intel_dp); 3787 intel_dp_set_common_rates(intel_dp);
3790 } 3788 }
@@ -3806,7 +3804,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
3806 * downstream port information. So, an early return here saves 3804 * downstream port information. So, an early return here saves
3807 * time from performing other operations which are not required. 3805 * time from performing other operations which are not required.
3808 */ 3806 */
3809 if (!is_edp(intel_dp) && !intel_dp->sink_count) 3807 if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3810 return false; 3808 return false;
3811 3809
3812 if (!drm_dp_is_branch(intel_dp->dpcd)) 3810 if (!drm_dp_is_branch(intel_dp->dpcd))
@@ -4396,7 +4394,7 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4396 if (!intel_dp_get_dpcd(intel_dp)) 4394 if (!intel_dp_get_dpcd(intel_dp))
4397 return connector_status_disconnected; 4395 return connector_status_disconnected;
4398 4396
4399 if (is_edp(intel_dp)) 4397 if (intel_dp_is_edp(intel_dp))
4400 return connector_status_connected; 4398 return connector_status_connected;
4401 4399
4402 /* if there's no downstream port, we're done */ 4400 /* if there's no downstream port, we're done */
@@ -4712,7 +4710,7 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
4712 intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain); 4710 intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4713 4711
4714 /* Can't disconnect eDP, but you can close the lid... */ 4712 /* Can't disconnect eDP, but you can close the lid... */
4715 if (is_edp(intel_dp)) 4713 if (intel_dp_is_edp(intel_dp))
4716 status = edp_detect(intel_dp); 4714 status = edp_detect(intel_dp);
4717 else if (intel_digital_port_connected(to_i915(dev), 4715 else if (intel_digital_port_connected(to_i915(dev),
4718 dp_to_dig_port(intel_dp))) 4716 dp_to_dig_port(intel_dp)))
@@ -4792,7 +4790,7 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
4792 intel_dp->aux.i2c_defer_count = 0; 4790 intel_dp->aux.i2c_defer_count = 0;
4793 4791
4794 intel_dp_set_edid(intel_dp); 4792 intel_dp_set_edid(intel_dp);
4795 if (is_edp(intel_dp) || intel_connector->detect_edid) 4793 if (intel_dp_is_edp(intel_dp) || intel_connector->detect_edid)
4796 status = connector_status_connected; 4794 status = connector_status_connected;
4797 intel_dp->detect_done = true; 4795 intel_dp->detect_done = true;
4798 4796
@@ -4876,7 +4874,7 @@ static int intel_dp_get_modes(struct drm_connector *connector)
4876 } 4874 }
4877 4875
4878 /* if eDP has no EDID, fall back to fixed mode */ 4876 /* if eDP has no EDID, fall back to fixed mode */
4879 if (is_edp(intel_attached_dp(connector)) && 4877 if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4880 intel_connector->panel.fixed_mode) { 4878 intel_connector->panel.fixed_mode) {
4881 struct drm_display_mode *mode; 4879 struct drm_display_mode *mode;
4882 4880
@@ -4927,8 +4925,10 @@ intel_dp_connector_destroy(struct drm_connector *connector)
4927 if (!IS_ERR_OR_NULL(intel_connector->edid)) 4925 if (!IS_ERR_OR_NULL(intel_connector->edid))
4928 kfree(intel_connector->edid); 4926 kfree(intel_connector->edid);
4929 4927
4930 /* Can't call is_edp() since the encoder may have been destroyed 4928 /*
4931 * already. */ 4929 * Can't call intel_dp_is_edp() since the encoder may have been
4930 * destroyed already.
4931 */
4932 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4932 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4933 intel_panel_fini(&intel_connector->panel); 4933 intel_panel_fini(&intel_connector->panel);
4934 4934
@@ -4942,7 +4942,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4942 struct intel_dp *intel_dp = &intel_dig_port->dp; 4942 struct intel_dp *intel_dp = &intel_dig_port->dp;
4943 4943
4944 intel_dp_mst_encoder_cleanup(intel_dig_port); 4944 intel_dp_mst_encoder_cleanup(intel_dig_port);
4945 if (is_edp(intel_dp)) { 4945 if (intel_dp_is_edp(intel_dp)) {
4946 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4946 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4947 /* 4947 /*
4948 * vdd might still be enabled do to the delayed vdd off. 4948 * vdd might still be enabled do to the delayed vdd off.
@@ -4968,7 +4968,7 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4968{ 4968{
4969 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4969 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4970 4970
4971 if (!is_edp(intel_dp)) 4971 if (!intel_dp_is_edp(intel_dp))
4972 return; 4972 return;
4973 4973
4974 /* 4974 /*
@@ -5036,7 +5036,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
5036 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5036 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5037 intel_dp->active_pipe = vlv_active_pipe(intel_dp); 5037 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5038 5038
5039 if (is_edp(intel_dp)) { 5039 if (intel_dp_is_edp(intel_dp)) {
5040 /* Reinit the power sequencer, in case BIOS did something with it. */ 5040 /* Reinit the power sequencer, in case BIOS did something with it. */
5041 intel_dp_pps_init(encoder->dev, intel_dp); 5041 intel_dp_pps_init(encoder->dev, intel_dp);
5042 intel_edp_panel_vdd_sanitize(intel_dp); 5042 intel_edp_panel_vdd_sanitize(intel_dp);
@@ -5137,7 +5137,7 @@ put_power:
5137} 5137}
5138 5138
5139/* check the VBT to see whether the eDP is on another port */ 5139/* check the VBT to see whether the eDP is on another port */
5140bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port) 5140bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5141{ 5141{
5142 /* 5142 /*
5143 * eDP not supported on g4x. so bail out early just 5143 * eDP not supported on g4x. so bail out early just
@@ -5160,7 +5160,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
5160 intel_attach_force_audio_property(connector); 5160 intel_attach_force_audio_property(connector);
5161 intel_attach_broadcast_rgb_property(connector); 5161 intel_attach_broadcast_rgb_property(connector);
5162 5162
5163 if (is_edp(intel_dp)) { 5163 if (intel_dp_is_edp(intel_dp)) {
5164 u32 allowed_scalers; 5164 u32 allowed_scalers;
5165 5165
5166 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 5166 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
@@ -5448,7 +5448,7 @@ static void intel_dp_pps_init(struct drm_device *dev,
5448 * The caller of this function needs to take a lock on dev_priv->drrs. 5448 * The caller of this function needs to take a lock on dev_priv->drrs.
5449 */ 5449 */
5450static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, 5450static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5451 struct intel_crtc_state *crtc_state, 5451 const struct intel_crtc_state *crtc_state,
5452 int refresh_rate) 5452 int refresh_rate)
5453{ 5453{
5454 struct intel_encoder *encoder; 5454 struct intel_encoder *encoder;
@@ -5545,7 +5545,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5545 * Initializes frontbuffer_bits and drrs.dp 5545 * Initializes frontbuffer_bits and drrs.dp
5546 */ 5546 */
5547void intel_edp_drrs_enable(struct intel_dp *intel_dp, 5547void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5548 struct intel_crtc_state *crtc_state) 5548 const struct intel_crtc_state *crtc_state)
5549{ 5549{
5550 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5550 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5551 struct drm_i915_private *dev_priv = to_i915(dev); 5551 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -5576,7 +5576,7 @@ unlock:
5576 * 5576 *
5577 */ 5577 */
5578void intel_edp_drrs_disable(struct intel_dp *intel_dp, 5578void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5579 struct intel_crtc_state *old_crtc_state) 5579 const struct intel_crtc_state *old_crtc_state)
5580{ 5580{
5581 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5581 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5582 struct drm_i915_private *dev_priv = to_i915(dev); 5582 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -5826,7 +5826,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5826 struct edid *edid; 5826 struct edid *edid;
5827 enum pipe pipe = INVALID_PIPE; 5827 enum pipe pipe = INVALID_PIPE;
5828 5828
5829 if (!is_edp(intel_dp)) 5829 if (!intel_dp_is_edp(intel_dp))
5830 return true; 5830 return true;
5831 5831
5832 /* 5832 /*
@@ -6042,7 +6042,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6042 intel_dp->DP = I915_READ(intel_dp->output_reg); 6042 intel_dp->DP = I915_READ(intel_dp->output_reg);
6043 intel_dp->attached_connector = intel_connector; 6043 intel_dp->attached_connector = intel_connector;
6044 6044
6045 if (intel_dp_is_edp(dev_priv, port)) 6045 if (intel_dp_is_port_edp(dev_priv, port))
6046 type = DRM_MODE_CONNECTOR_eDP; 6046 type = DRM_MODE_CONNECTOR_eDP;
6047 else 6047 else
6048 type = DRM_MODE_CONNECTOR_DisplayPort; 6048 type = DRM_MODE_CONNECTOR_DisplayPort;
@@ -6060,7 +6060,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6060 6060
6061 /* eDP only on port B and/or C on vlv/chv */ 6061 /* eDP only on port B and/or C on vlv/chv */
6062 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 6062 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6063 is_edp(intel_dp) && port != PORT_B && port != PORT_C)) 6063 intel_dp_is_edp(intel_dp) &&
6064 port != PORT_B && port != PORT_C))
6064 return false; 6065 return false;
6065 6066
6066 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 6067 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
@@ -6088,7 +6089,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6088 intel_connector->get_hw_state = intel_connector_get_hw_state; 6089 intel_connector->get_hw_state = intel_connector_get_hw_state;
6089 6090
6090 /* init MST on ports that can support it */ 6091 /* init MST on ports that can support it */
6091 if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) && 6092 if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6092 (port == PORT_B || port == PORT_C || port == PORT_D)) 6093 (port == PORT_B || port == PORT_C || port == PORT_D))
6093 intel_dp_mst_encoder_init(intel_dig_port, 6094 intel_dp_mst_encoder_init(intel_dig_port,
6094 intel_connector->base.base.id); 6095 intel_connector->base.base.id);
@@ -6186,6 +6187,9 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
6186 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 6187 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6187 dev_priv->hotplug.irq_port[port] = intel_dig_port; 6188 dev_priv->hotplug.irq_port[port] = intel_dig_port;
6188 6189
6190 if (port != PORT_A)
6191 intel_infoframe_init(intel_dig_port);
6192
6189 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) 6193 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6190 goto err_init_connector; 6194 goto err_init_connector;
6191 6195
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 93fc8ab9bb31..8e3aad0ea60b 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -123,8 +123,8 @@ static int intel_dp_mst_atomic_check(struct drm_connector *connector,
123} 123}
124 124
125static void intel_mst_disable_dp(struct intel_encoder *encoder, 125static void intel_mst_disable_dp(struct intel_encoder *encoder,
126 struct intel_crtc_state *old_crtc_state, 126 const struct intel_crtc_state *old_crtc_state,
127 struct drm_connector_state *old_conn_state) 127 const struct drm_connector_state *old_conn_state)
128{ 128{
129 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); 129 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
130 struct intel_digital_port *intel_dig_port = intel_mst->primary; 130 struct intel_digital_port *intel_dig_port = intel_mst->primary;
@@ -146,8 +146,8 @@ static void intel_mst_disable_dp(struct intel_encoder *encoder,
146} 146}
147 147
148static void intel_mst_post_disable_dp(struct intel_encoder *encoder, 148static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
149 struct intel_crtc_state *old_crtc_state, 149 const struct intel_crtc_state *old_crtc_state,
150 struct drm_connector_state *old_conn_state) 150 const struct drm_connector_state *old_conn_state)
151{ 151{
152 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); 152 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
153 struct intel_digital_port *intel_dig_port = intel_mst->primary; 153 struct intel_digital_port *intel_dig_port = intel_mst->primary;
@@ -176,8 +176,8 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
176} 176}
177 177
178static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, 178static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
179 struct intel_crtc_state *pipe_config, 179 const struct intel_crtc_state *pipe_config,
180 struct drm_connector_state *conn_state) 180 const struct drm_connector_state *conn_state)
181{ 181{
182 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); 182 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
183 struct intel_digital_port *intel_dig_port = intel_mst->primary; 183 struct intel_digital_port *intel_dig_port = intel_mst->primary;
@@ -219,8 +219,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
219} 219}
220 220
221static void intel_mst_enable_dp(struct intel_encoder *encoder, 221static void intel_mst_enable_dp(struct intel_encoder *encoder,
222 struct intel_crtc_state *pipe_config, 222 const struct intel_crtc_state *pipe_config,
223 struct drm_connector_state *conn_state) 223 const struct drm_connector_state *conn_state)
224{ 224{
225 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); 225 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
226 struct intel_digital_port *intel_dig_port = intel_mst->primary; 226 struct intel_digital_port *intel_dig_port = intel_mst->primary;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fa47285918f4..463ed152e6b1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -220,23 +220,23 @@ struct intel_encoder {
220 struct intel_crtc_state *, 220 struct intel_crtc_state *,
221 struct drm_connector_state *); 221 struct drm_connector_state *);
222 void (*pre_pll_enable)(struct intel_encoder *, 222 void (*pre_pll_enable)(struct intel_encoder *,
223 struct intel_crtc_state *, 223 const struct intel_crtc_state *,
224 struct drm_connector_state *); 224 const struct drm_connector_state *);
225 void (*pre_enable)(struct intel_encoder *, 225 void (*pre_enable)(struct intel_encoder *,
226 struct intel_crtc_state *, 226 const struct intel_crtc_state *,
227 struct drm_connector_state *); 227 const struct drm_connector_state *);
228 void (*enable)(struct intel_encoder *, 228 void (*enable)(struct intel_encoder *,
229 struct intel_crtc_state *, 229 const struct intel_crtc_state *,
230 struct drm_connector_state *); 230 const struct drm_connector_state *);
231 void (*disable)(struct intel_encoder *, 231 void (*disable)(struct intel_encoder *,
232 struct intel_crtc_state *, 232 const struct intel_crtc_state *,
233 struct drm_connector_state *); 233 const struct drm_connector_state *);
234 void (*post_disable)(struct intel_encoder *, 234 void (*post_disable)(struct intel_encoder *,
235 struct intel_crtc_state *, 235 const struct intel_crtc_state *,
236 struct drm_connector_state *); 236 const struct drm_connector_state *);
237 void (*post_pll_disable)(struct intel_encoder *, 237 void (*post_pll_disable)(struct intel_encoder *,
238 struct intel_crtc_state *, 238 const struct intel_crtc_state *,
239 struct drm_connector_state *); 239 const struct drm_connector_state *);
240 /* Read out the current hw state of this connector, returning true if 240 /* Read out the current hw state of this connector, returning true if
241 * the encoder is active. If the encoder is enabled it also set the pipe 241 * the encoder is active. If the encoder is enabled it also set the pipe
242 * it is connected to in the pipe parameter. */ 242 * it is connected to in the pipe parameter. */
@@ -384,7 +384,8 @@ struct intel_atomic_state {
384 unsigned int active_pipe_changes; 384 unsigned int active_pipe_changes;
385 385
386 unsigned int active_crtcs; 386 unsigned int active_crtcs;
387 unsigned int min_pixclk[I915_MAX_PIPES]; 387 /* minimum acceptable cdclk for each pipe */
388 int min_cdclk[I915_MAX_PIPES];
388 389
389 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; 390 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
390 391
@@ -753,6 +754,7 @@ struct intel_crtc_state {
753 struct intel_link_m_n fdi_m_n; 754 struct intel_link_m_n fdi_m_n;
754 755
755 bool ips_enabled; 756 bool ips_enabled;
757 bool ips_force_disable;
756 758
757 bool enable_fbc; 759 bool enable_fbc;
758 760
@@ -909,16 +911,6 @@ struct intel_hdmi {
909 bool has_audio; 911 bool has_audio;
910 bool rgb_quant_range_selectable; 912 bool rgb_quant_range_selectable;
911 struct intel_connector *attached_connector; 913 struct intel_connector *attached_connector;
912 void (*write_infoframe)(struct drm_encoder *encoder,
913 const struct intel_crtc_state *crtc_state,
914 enum hdmi_infoframe_type type,
915 const void *frame, ssize_t len);
916 void (*set_infoframes)(struct drm_encoder *encoder,
917 bool enable,
918 const struct intel_crtc_state *crtc_state,
919 const struct drm_connector_state *conn_state);
920 bool (*infoframe_enabled)(struct drm_encoder *encoder,
921 const struct intel_crtc_state *pipe_config);
922}; 914};
923 915
924struct intel_dp_mst_encoder; 916struct intel_dp_mst_encoder;
@@ -1069,6 +1061,17 @@ struct intel_digital_port {
1069 bool release_cl2_override; 1061 bool release_cl2_override;
1070 uint8_t max_lanes; 1062 uint8_t max_lanes;
1071 enum intel_display_power_domain ddi_io_power_domain; 1063 enum intel_display_power_domain ddi_io_power_domain;
1064
1065 void (*write_infoframe)(struct drm_encoder *encoder,
1066 const struct intel_crtc_state *crtc_state,
1067 enum hdmi_infoframe_type type,
1068 const void *frame, ssize_t len);
1069 void (*set_infoframes)(struct drm_encoder *encoder,
1070 bool enable,
1071 const struct intel_crtc_state *crtc_state,
1072 const struct drm_connector_state *conn_state);
1073 bool (*infoframe_enabled)(struct drm_encoder *encoder,
1074 const struct intel_crtc_state *pipe_config);
1072}; 1075};
1073 1076
1074struct intel_dp_mst_encoder { 1077struct intel_dp_mst_encoder {
@@ -1189,6 +1192,30 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1189 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 1192 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1190} 1193}
1191 1194
1195static inline struct intel_plane_state *
1196intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1197 struct intel_plane *plane)
1198{
1199 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1200 &plane->base));
1201}
1202
1203static inline struct intel_crtc_state *
1204intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1205 struct intel_crtc *crtc)
1206{
1207 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1208 &crtc->base));
1209}
1210
1211static inline struct intel_crtc_state *
1212intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1213 struct intel_crtc *crtc)
1214{
1215 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1216 &crtc->base));
1217}
1218
1192/* intel_fifo_underrun.c */ 1219/* intel_fifo_underrun.c */
1193bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 1220bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1194 enum pipe pipe, bool enable); 1221 enum pipe pipe, bool enable);
@@ -1205,11 +1232,8 @@ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1205/* i915_irq.c */ 1232/* i915_irq.c */
1206void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1233void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1207void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1234void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1208void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1209void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); 1235void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1210void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); 1236void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1211void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1212void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1213void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); 1237void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1214void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); 1238void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1215void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); 1239void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
@@ -1246,8 +1270,8 @@ void intel_crt_reset(struct drm_encoder *encoder);
1246 1270
1247/* intel_ddi.c */ 1271/* intel_ddi.c */
1248void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, 1272void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1249 struct intel_crtc_state *old_crtc_state, 1273 const struct intel_crtc_state *old_crtc_state,
1250 struct drm_connector_state *old_conn_state); 1274 const struct drm_connector_state *old_conn_state);
1251void hsw_fdi_link_train(struct intel_crtc *crtc, 1275void hsw_fdi_link_train(struct intel_crtc *crtc,
1252 const struct intel_crtc_state *crtc_state); 1276 const struct intel_crtc_state *crtc_state);
1253void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); 1277void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
@@ -1272,6 +1296,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
1272 struct intel_crtc_state *pipe_config); 1296 struct intel_crtc_state *pipe_config);
1273void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, 1297void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1274 bool state); 1298 bool state);
1299u32 bxt_signal_levels(struct intel_dp *intel_dp);
1275uint32_t ddi_signal_levels(struct intel_dp *intel_dp); 1300uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1276u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); 1301u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1277 1302
@@ -1290,6 +1315,7 @@ void intel_audio_init(struct drm_i915_private *dev_priv);
1290void intel_audio_deinit(struct drm_i915_private *dev_priv); 1315void intel_audio_deinit(struct drm_i915_private *dev_priv);
1291 1316
1292/* intel_cdclk.c */ 1317/* intel_cdclk.c */
1318int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1293void skl_init_cdclk(struct drm_i915_private *dev_priv); 1319void skl_init_cdclk(struct drm_i915_private *dev_priv);
1294void skl_uninit_cdclk(struct drm_i915_private *dev_priv); 1320void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1295void cnl_init_cdclk(struct drm_i915_private *dev_priv); 1321void cnl_init_cdclk(struct drm_i915_private *dev_priv);
@@ -1377,7 +1403,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1377 struct intel_digital_port *dport, 1403 struct intel_digital_port *dport,
1378 unsigned int expected_mask); 1404 unsigned int expected_mask);
1379int intel_get_load_detect_pipe(struct drm_connector *connector, 1405int intel_get_load_detect_pipe(struct drm_connector *connector,
1380 struct drm_display_mode *mode, 1406 const struct drm_display_mode *mode,
1381 struct intel_load_detect_pipe *old, 1407 struct intel_load_detect_pipe *old,
1382 struct drm_modeset_acquire_ctx *ctx); 1408 struct drm_modeset_acquire_ctx *ctx);
1383void intel_release_load_detect_pipe(struct drm_connector *connector, 1409void intel_release_load_detect_pipe(struct drm_connector *connector,
@@ -1401,7 +1427,9 @@ int intel_plane_atomic_set_property(struct drm_plane *plane,
1401 struct drm_plane_state *state, 1427 struct drm_plane_state *state,
1402 struct drm_property *property, 1428 struct drm_property *property,
1403 uint64_t val); 1429 uint64_t val);
1404int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, 1430int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1431 struct drm_crtc_state *crtc_state,
1432 const struct intel_plane_state *old_plane_state,
1405 struct drm_plane_state *plane_state); 1433 struct drm_plane_state *plane_state);
1406 1434
1407void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 1435void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
@@ -1499,7 +1527,8 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1499bool intel_dp_compute_config(struct intel_encoder *encoder, 1527bool intel_dp_compute_config(struct intel_encoder *encoder,
1500 struct intel_crtc_state *pipe_config, 1528 struct intel_crtc_state *pipe_config,
1501 struct drm_connector_state *conn_state); 1529 struct drm_connector_state *conn_state);
1502bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port); 1530bool intel_dp_is_edp(struct intel_dp *intel_dp);
1531bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1503enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, 1532enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1504 bool long_hpd); 1533 bool long_hpd);
1505void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 1534void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
@@ -1518,9 +1547,9 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1518uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); 1547uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1519void intel_plane_destroy(struct drm_plane *plane); 1548void intel_plane_destroy(struct drm_plane *plane);
1520void intel_edp_drrs_enable(struct intel_dp *intel_dp, 1549void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1521 struct intel_crtc_state *crtc_state); 1550 const struct intel_crtc_state *crtc_state);
1522void intel_edp_drrs_disable(struct intel_dp *intel_dp, 1551void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1523 struct intel_crtc_state *crtc_state); 1552 const struct intel_crtc_state *crtc_state);
1524void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, 1553void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1525 unsigned int frontbuffer_bits); 1554 unsigned int frontbuffer_bits);
1526void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, 1555void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
@@ -1648,6 +1677,7 @@ void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1648 bool high_tmds_clock_ratio, 1677 bool high_tmds_clock_ratio,
1649 bool scrambling); 1678 bool scrambling);
1650void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); 1679void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1680void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1651 1681
1652 1682
1653/* intel_lvds.c */ 1683/* intel_lvds.c */
@@ -1719,8 +1749,10 @@ static inline void intel_backlight_device_unregister(struct intel_connector *con
1719 1749
1720 1750
1721/* intel_psr.c */ 1751/* intel_psr.c */
1722void intel_psr_enable(struct intel_dp *intel_dp); 1752void intel_psr_enable(struct intel_dp *intel_dp,
1723void intel_psr_disable(struct intel_dp *intel_dp); 1753 const struct intel_crtc_state *crtc_state);
1754void intel_psr_disable(struct intel_dp *intel_dp,
1755 const struct intel_crtc_state *old_crtc_state);
1724void intel_psr_invalidate(struct drm_i915_private *dev_priv, 1756void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1725 unsigned frontbuffer_bits); 1757 unsigned frontbuffer_bits);
1726void intel_psr_flush(struct drm_i915_private *dev_priv, 1758void intel_psr_flush(struct drm_i915_private *dev_priv,
@@ -1844,7 +1876,6 @@ void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1844void gen6_rps_idle(struct drm_i915_private *dev_priv); 1876void gen6_rps_idle(struct drm_i915_private *dev_priv);
1845void gen6_rps_boost(struct drm_i915_gem_request *rq, 1877void gen6_rps_boost(struct drm_i915_gem_request *rq,
1846 struct intel_rps_client *rps); 1878 struct intel_rps_client *rps);
1847void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1848void g4x_wm_get_hw_state(struct drm_device *dev); 1879void g4x_wm_get_hw_state(struct drm_device *dev);
1849void vlv_wm_get_hw_state(struct drm_device *dev); 1880void vlv_wm_get_hw_state(struct drm_device *dev);
1850void ilk_wm_get_hw_state(struct drm_device *dev); 1881void ilk_wm_get_hw_state(struct drm_device *dev);
@@ -1884,8 +1915,8 @@ struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1884 enum pipe pipe, int plane); 1915 enum pipe pipe, int plane);
1885int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 1916int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1886 struct drm_file *file_priv); 1917 struct drm_file *file_priv);
1887void intel_pipe_update_start(struct intel_crtc *crtc); 1918void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
1888void intel_pipe_update_end(struct intel_crtc *crtc); 1919void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
1889 1920
1890/* intel_tv.c */ 1921/* intel_tv.c */
1891void intel_tv_init(struct drm_i915_private *dev_priv); 1922void intel_tv_init(struct drm_i915_private *dev_priv);
@@ -1957,7 +1988,9 @@ struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1957void intel_plane_destroy_state(struct drm_plane *plane, 1988void intel_plane_destroy_state(struct drm_plane *plane,
1958 struct drm_plane_state *state); 1989 struct drm_plane_state *state);
1959extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; 1990extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1960int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state, 1991int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
1992 struct intel_crtc_state *crtc_state,
1993 const struct intel_plane_state *old_plane_state,
1961 struct intel_plane_state *intel_state); 1994 struct intel_plane_state *intel_state);
1962 1995
1963/* intel_color.c */ 1996/* intel_color.c */
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 7442891762be..fc25d7d2d942 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -731,7 +731,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
731} 731}
732 732
733static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 733static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
734 struct intel_crtc_state *pipe_config); 734 const struct intel_crtc_state *pipe_config);
735static void intel_dsi_unprepare(struct intel_encoder *encoder); 735static void intel_dsi_unprepare(struct intel_encoder *encoder);
736 736
737static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 737static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
@@ -783,8 +783,8 @@ static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
783 */ 783 */
784 784
785static void intel_dsi_pre_enable(struct intel_encoder *encoder, 785static void intel_dsi_pre_enable(struct intel_encoder *encoder,
786 struct intel_crtc_state *pipe_config, 786 const struct intel_crtc_state *pipe_config,
787 struct drm_connector_state *conn_state) 787 const struct drm_connector_state *conn_state)
788{ 788{
789 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 789 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
790 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 790 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -878,8 +878,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
878 * the pre_enable hook. 878 * the pre_enable hook.
879 */ 879 */
880static void intel_dsi_enable_nop(struct intel_encoder *encoder, 880static void intel_dsi_enable_nop(struct intel_encoder *encoder,
881 struct intel_crtc_state *pipe_config, 881 const struct intel_crtc_state *pipe_config,
882 struct drm_connector_state *conn_state) 882 const struct drm_connector_state *conn_state)
883{ 883{
884 DRM_DEBUG_KMS("\n"); 884 DRM_DEBUG_KMS("\n");
885} 885}
@@ -889,8 +889,8 @@ static void intel_dsi_enable_nop(struct intel_encoder *encoder,
889 * the post_disable hook. 889 * the post_disable hook.
890 */ 890 */
891static void intel_dsi_disable(struct intel_encoder *encoder, 891static void intel_dsi_disable(struct intel_encoder *encoder,
892 struct intel_crtc_state *old_crtc_state, 892 const struct intel_crtc_state *old_crtc_state,
893 struct drm_connector_state *old_conn_state) 893 const struct drm_connector_state *old_conn_state)
894{ 894{
895 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 895 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
896 enum port port; 896 enum port port;
@@ -925,8 +925,8 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
925} 925}
926 926
927static void intel_dsi_post_disable(struct intel_encoder *encoder, 927static void intel_dsi_post_disable(struct intel_encoder *encoder,
928 struct intel_crtc_state *pipe_config, 928 const struct intel_crtc_state *pipe_config,
929 struct drm_connector_state *conn_state) 929 const struct drm_connector_state *conn_state)
930{ 930{
931 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 931 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
932 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 932 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -1066,7 +1066,7 @@ out_put_power:
1066} 1066}
1067 1067
1068static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1068static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1069 struct intel_crtc_state *pipe_config) 1069 struct intel_crtc_state *pipe_config)
1070{ 1070{
1071 struct drm_device *dev = encoder->base.dev; 1071 struct drm_device *dev = encoder->base.dev;
1072 struct drm_i915_private *dev_priv = to_i915(dev); 1072 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1370,7 +1370,7 @@ static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1370} 1370}
1371 1371
1372static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1372static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1373 struct intel_crtc_state *pipe_config) 1373 const struct intel_crtc_state *pipe_config)
1374{ 1374{
1375 struct drm_encoder *encoder = &intel_encoder->base; 1375 struct drm_encoder *encoder = &intel_encoder->base;
1376 struct drm_device *dev = encoder->dev; 1376 struct drm_device *dev = encoder->dev;
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index c0a027274c06..5c562e1f56ae 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -175,8 +175,8 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
175} 175}
176 176
177static void intel_disable_dvo(struct intel_encoder *encoder, 177static void intel_disable_dvo(struct intel_encoder *encoder,
178 struct intel_crtc_state *old_crtc_state, 178 const struct intel_crtc_state *old_crtc_state,
179 struct drm_connector_state *old_conn_state) 179 const struct drm_connector_state *old_conn_state)
180{ 180{
181 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 181 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
182 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 182 struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
@@ -189,8 +189,8 @@ static void intel_disable_dvo(struct intel_encoder *encoder,
189} 189}
190 190
191static void intel_enable_dvo(struct intel_encoder *encoder, 191static void intel_enable_dvo(struct intel_encoder *encoder,
192 struct intel_crtc_state *pipe_config, 192 const struct intel_crtc_state *pipe_config,
193 struct drm_connector_state *conn_state) 193 const struct drm_connector_state *conn_state)
194{ 194{
195 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 195 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
196 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 196 struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
@@ -258,8 +258,8 @@ static bool intel_dvo_compute_config(struct intel_encoder *encoder,
258} 258}
259 259
260static void intel_dvo_pre_enable(struct intel_encoder *encoder, 260static void intel_dvo_pre_enable(struct intel_encoder *encoder,
261 struct intel_crtc_state *pipe_config, 261 const struct intel_crtc_state *pipe_config,
262 struct drm_connector_state *conn_state) 262 const struct drm_connector_state *conn_state)
263{ 263{
264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
265 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 265 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 9ab596941372..b8e9a234af2d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1065,6 +1065,51 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
1065 return 0; 1065 return 0;
1066} 1066}
1067 1067
1068static int cnl_init_workarounds(struct intel_engine_cs *engine)
1069{
1070 struct drm_i915_private *dev_priv = engine->i915;
1071 int ret;
1072
1073 /* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */
1074 if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
1075 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1076 GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
1077
1078 /* WaForceContextSaveRestoreNonCoherent:cnl */
1079 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
1080 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
1081
1082 /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
1083 if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
1084 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
1085
1086 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
1087 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1088 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1089
1090 /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
1091 if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0))
1092 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1093 GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
1094
1095 /* WaInPlaceDecompressionHang:cnl */
1096 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1097 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1098
1099 /* WaPushConstantDereferenceHoldDisable:cnl */
1100 WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
1101
1102 /* FtrEnableFastAnisoL1BankingFix: cnl */
1103 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
1104
1105 /* WaEnablePreemptionGranularityControlByUMD:cnl */
1106 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1107 if (ret)
1108 return ret;
1109
1110 return 0;
1111}
1112
1068static int kbl_init_workarounds(struct intel_engine_cs *engine) 1113static int kbl_init_workarounds(struct intel_engine_cs *engine)
1069{ 1114{
1070 struct drm_i915_private *dev_priv = engine->i915; 1115 struct drm_i915_private *dev_priv = engine->i915;
@@ -1185,6 +1230,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
1185 err = glk_init_workarounds(engine); 1230 err = glk_init_workarounds(engine);
1186 else if (IS_COFFEELAKE(dev_priv)) 1231 else if (IS_COFFEELAKE(dev_priv))
1187 err = cfl_init_workarounds(engine); 1232 err = cfl_init_workarounds(engine);
1233 else if (IS_CANNONLAKE(dev_priv))
1234 err = cnl_init_workarounds(engine);
1188 else 1235 else
1189 err = 0; 1236 err = 0;
1190 if (err) 1237 if (err)
@@ -1335,6 +1382,21 @@ void intel_engines_mark_idle(struct drm_i915_private *i915)
1335 } 1382 }
1336} 1383}
1337 1384
1385bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1386{
1387 switch (INTEL_GEN(engine->i915)) {
1388 case 2:
1389 return false; /* uses physical not virtual addresses */
1390 case 3:
1391 /* maybe only uses physical not virtual addresses */
1392 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1393 case 6:
1394 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1395 default:
1396 return true;
1397 }
1398}
1399
1338#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1400#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1339#include "selftests/mock_engine.c" 1401#include "selftests/mock_engine.c"
1340#endif 1402#endif
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 8c8ead2276e0..58a772de6672 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -291,6 +291,19 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
291 u32 dpfc_ctl; 291 u32 dpfc_ctl;
292 int threshold = dev_priv->fbc.threshold; 292 int threshold = dev_priv->fbc.threshold;
293 293
294 /* Display WA #0529: skl, kbl, bxt. */
295 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
296 u32 val = I915_READ(CHICKEN_MISC_4);
297
298 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
299
300 if (i915_gem_object_get_tiling(params->vma->obj) !=
301 I915_TILING_X)
302 val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
303
304 I915_WRITE(CHICKEN_MISC_4, val);
305 }
306
294 dpfc_ctl = 0; 307 dpfc_ctl = 0;
295 if (IS_IVYBRIDGE(dev_priv)) 308 if (IS_IVYBRIDGE(dev_priv))
296 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane); 309 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
@@ -881,6 +894,10 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
881 params->fb.stride = cache->fb.stride; 894 params->fb.stride = cache->fb.stride;
882 895
883 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); 896 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
897
898 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
899 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
900 32 * fbc->threshold) * 8;
884} 901}
885 902
886static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1, 903static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 262e75c00dd2..f2bb8116227c 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -206,6 +206,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
206 } 206 }
207 207
208 mutex_lock(&dev->struct_mutex); 208 mutex_lock(&dev->struct_mutex);
209 intel_runtime_pm_get(dev_priv);
209 210
210 /* Pin the GGTT vma for our access via info->screen_base. 211 /* Pin the GGTT vma for our access via info->screen_base.
211 * This also validates that any existing fb inherited from the 212 * This also validates that any existing fb inherited from the
@@ -269,6 +270,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
269 fb->width, fb->height, i915_ggtt_offset(vma)); 270 fb->width, fb->height, i915_ggtt_offset(vma));
270 ifbdev->vma = vma; 271 ifbdev->vma = vma;
271 272
273 intel_runtime_pm_put(dev_priv);
272 mutex_unlock(&dev->struct_mutex); 274 mutex_unlock(&dev->struct_mutex);
273 vga_switcheroo_client_fb_set(pdev, info); 275 vga_switcheroo_client_fb_set(pdev, info);
274 return 0; 276 return 0;
@@ -276,6 +278,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
276out_unpin: 278out_unpin:
277 intel_unpin_fb_vma(vma); 279 intel_unpin_fb_vma(vma);
278out_unlock: 280out_unlock:
281 intel_runtime_pm_put(dev_priv);
279 mutex_unlock(&dev->struct_mutex); 282 mutex_unlock(&dev->struct_mutex);
280 return ret; 283 return ret;
281} 284}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index e8abea7594ec..e6f8f30ce7bd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -434,7 +434,7 @@ static void intel_write_infoframe(struct drm_encoder *encoder,
434 const struct intel_crtc_state *crtc_state, 434 const struct intel_crtc_state *crtc_state,
435 union hdmi_infoframe *frame) 435 union hdmi_infoframe *frame)
436{ 436{
437 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 437 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
438 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 438 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
439 ssize_t len; 439 ssize_t len;
440 440
@@ -450,7 +450,7 @@ static void intel_write_infoframe(struct drm_encoder *encoder,
450 buffer[3] = 0; 450 buffer[3] = 0;
451 len++; 451 len++;
452 452
453 intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); 453 intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
454} 454}
455 455
456static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 456static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
@@ -945,6 +945,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
945 struct intel_crtc_state *pipe_config) 945 struct intel_crtc_state *pipe_config)
946{ 946{
947 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 947 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
948 struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
948 struct drm_device *dev = encoder->base.dev; 949 struct drm_device *dev = encoder->base.dev;
949 struct drm_i915_private *dev_priv = to_i915(dev); 950 struct drm_i915_private *dev_priv = to_i915(dev);
950 u32 tmp, flags = 0; 951 u32 tmp, flags = 0;
@@ -965,7 +966,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
965 if (tmp & HDMI_MODE_SELECT_HDMI) 966 if (tmp & HDMI_MODE_SELECT_HDMI)
966 pipe_config->has_hdmi_sink = true; 967 pipe_config->has_hdmi_sink = true;
967 968
968 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 969 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
969 pipe_config->has_infoframe = true; 970 pipe_config->has_infoframe = true;
970 971
971 if (tmp & SDVO_AUDIO_ENABLE) 972 if (tmp & SDVO_AUDIO_ENABLE)
@@ -991,8 +992,8 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
991} 992}
992 993
993static void intel_enable_hdmi_audio(struct intel_encoder *encoder, 994static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
994 struct intel_crtc_state *pipe_config, 995 const struct intel_crtc_state *pipe_config,
995 struct drm_connector_state *conn_state) 996 const struct drm_connector_state *conn_state)
996{ 997{
997 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 998 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
998 999
@@ -1003,8 +1004,8 @@ static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1003} 1004}
1004 1005
1005static void g4x_enable_hdmi(struct intel_encoder *encoder, 1006static void g4x_enable_hdmi(struct intel_encoder *encoder,
1006 struct intel_crtc_state *pipe_config, 1007 const struct intel_crtc_state *pipe_config,
1007 struct drm_connector_state *conn_state) 1008 const struct drm_connector_state *conn_state)
1008{ 1009{
1009 struct drm_device *dev = encoder->base.dev; 1010 struct drm_device *dev = encoder->base.dev;
1010 struct drm_i915_private *dev_priv = to_i915(dev); 1011 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1025,8 +1026,8 @@ static void g4x_enable_hdmi(struct intel_encoder *encoder,
1025} 1026}
1026 1027
1027static void ibx_enable_hdmi(struct intel_encoder *encoder, 1028static void ibx_enable_hdmi(struct intel_encoder *encoder,
1028 struct intel_crtc_state *pipe_config, 1029 const struct intel_crtc_state *pipe_config,
1029 struct drm_connector_state *conn_state) 1030 const struct drm_connector_state *conn_state)
1030{ 1031{
1031 struct drm_device *dev = encoder->base.dev; 1032 struct drm_device *dev = encoder->base.dev;
1032 struct drm_i915_private *dev_priv = to_i915(dev); 1033 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1075,8 +1076,8 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder,
1075} 1076}
1076 1077
1077static void cpt_enable_hdmi(struct intel_encoder *encoder, 1078static void cpt_enable_hdmi(struct intel_encoder *encoder,
1078 struct intel_crtc_state *pipe_config, 1079 const struct intel_crtc_state *pipe_config,
1079 struct drm_connector_state *conn_state) 1080 const struct drm_connector_state *conn_state)
1080{ 1081{
1081 struct drm_device *dev = encoder->base.dev; 1082 struct drm_device *dev = encoder->base.dev;
1082 struct drm_i915_private *dev_priv = to_i915(dev); 1083 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1130,18 +1131,20 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
1130} 1131}
1131 1132
1132static void vlv_enable_hdmi(struct intel_encoder *encoder, 1133static void vlv_enable_hdmi(struct intel_encoder *encoder,
1133 struct intel_crtc_state *pipe_config, 1134 const struct intel_crtc_state *pipe_config,
1134 struct drm_connector_state *conn_state) 1135 const struct drm_connector_state *conn_state)
1135{ 1136{
1136} 1137}
1137 1138
1138static void intel_disable_hdmi(struct intel_encoder *encoder, 1139static void intel_disable_hdmi(struct intel_encoder *encoder,
1139 struct intel_crtc_state *old_crtc_state, 1140 const struct intel_crtc_state *old_crtc_state,
1140 struct drm_connector_state *old_conn_state) 1141 const struct drm_connector_state *old_conn_state)
1141{ 1142{
1142 struct drm_device *dev = encoder->base.dev; 1143 struct drm_device *dev = encoder->base.dev;
1143 struct drm_i915_private *dev_priv = to_i915(dev); 1144 struct drm_i915_private *dev_priv = to_i915(dev);
1144 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1145 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1146 struct intel_digital_port *intel_dig_port =
1147 hdmi_to_dig_port(intel_hdmi);
1145 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 1148 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1146 u32 temp; 1149 u32 temp;
1147 1150
@@ -1184,14 +1187,15 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
1184 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1187 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1185 } 1188 }
1186 1189
1187 intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state); 1190 intel_dig_port->set_infoframes(&encoder->base, false,
1191 old_crtc_state, old_conn_state);
1188 1192
1189 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 1193 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1190} 1194}
1191 1195
1192static void g4x_disable_hdmi(struct intel_encoder *encoder, 1196static void g4x_disable_hdmi(struct intel_encoder *encoder,
1193 struct intel_crtc_state *old_crtc_state, 1197 const struct intel_crtc_state *old_crtc_state,
1194 struct drm_connector_state *old_conn_state) 1198 const struct drm_connector_state *old_conn_state)
1195{ 1199{
1196 if (old_crtc_state->has_audio) 1200 if (old_crtc_state->has_audio)
1197 intel_audio_codec_disable(encoder); 1201 intel_audio_codec_disable(encoder);
@@ -1200,16 +1204,16 @@ static void g4x_disable_hdmi(struct intel_encoder *encoder,
1200} 1204}
1201 1205
1202static void pch_disable_hdmi(struct intel_encoder *encoder, 1206static void pch_disable_hdmi(struct intel_encoder *encoder,
1203 struct intel_crtc_state *old_crtc_state, 1207 const struct intel_crtc_state *old_crtc_state,
1204 struct drm_connector_state *old_conn_state) 1208 const struct drm_connector_state *old_conn_state)
1205{ 1209{
1206 if (old_crtc_state->has_audio) 1210 if (old_crtc_state->has_audio)
1207 intel_audio_codec_disable(encoder); 1211 intel_audio_codec_disable(encoder);
1208} 1212}
1209 1213
1210static void pch_post_disable_hdmi(struct intel_encoder *encoder, 1214static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1211 struct intel_crtc_state *old_crtc_state, 1215 const struct intel_crtc_state *old_crtc_state,
1212 struct drm_connector_state *old_conn_state) 1216 const struct drm_connector_state *old_conn_state)
1213{ 1217{
1214 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 1218 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1215} 1219}
@@ -1314,7 +1318,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
1314 return status; 1318 return status;
1315} 1319}
1316 1320
1317static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) 1321static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
1318{ 1322{
1319 struct drm_i915_private *dev_priv = 1323 struct drm_i915_private *dev_priv =
1320 to_i915(crtc_state->base.crtc->dev); 1324 to_i915(crtc_state->base.crtc->dev);
@@ -1642,24 +1646,24 @@ static int intel_hdmi_get_modes(struct drm_connector *connector)
1642} 1646}
1643 1647
1644static void intel_hdmi_pre_enable(struct intel_encoder *encoder, 1648static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1645 struct intel_crtc_state *pipe_config, 1649 const struct intel_crtc_state *pipe_config,
1646 struct drm_connector_state *conn_state) 1650 const struct drm_connector_state *conn_state)
1647{ 1651{
1648 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1652 struct intel_digital_port *intel_dig_port =
1653 enc_to_dig_port(&encoder->base);
1649 1654
1650 intel_hdmi_prepare(encoder, pipe_config); 1655 intel_hdmi_prepare(encoder, pipe_config);
1651 1656
1652 intel_hdmi->set_infoframes(&encoder->base, 1657 intel_dig_port->set_infoframes(&encoder->base,
1653 pipe_config->has_hdmi_sink, 1658 pipe_config->has_infoframe,
1654 pipe_config, conn_state); 1659 pipe_config, conn_state);
1655} 1660}
1656 1661
1657static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, 1662static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1658 struct intel_crtc_state *pipe_config, 1663 const struct intel_crtc_state *pipe_config,
1659 struct drm_connector_state *conn_state) 1664 const struct drm_connector_state *conn_state)
1660{ 1665{
1661 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1666 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1662 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1663 struct drm_device *dev = encoder->base.dev; 1667 struct drm_device *dev = encoder->base.dev;
1664 struct drm_i915_private *dev_priv = to_i915(dev); 1668 struct drm_i915_private *dev_priv = to_i915(dev);
1665 1669
@@ -1669,9 +1673,9 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1669 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 1673 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1670 0x2b247878); 1674 0x2b247878);
1671 1675
1672 intel_hdmi->set_infoframes(&encoder->base, 1676 dport->set_infoframes(&encoder->base,
1673 pipe_config->has_hdmi_sink, 1677 pipe_config->has_infoframe,
1674 pipe_config, conn_state); 1678 pipe_config, conn_state);
1675 1679
1676 g4x_enable_hdmi(encoder, pipe_config, conn_state); 1680 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1677 1681
@@ -1679,8 +1683,8 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1679} 1683}
1680 1684
1681static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 1685static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1682 struct intel_crtc_state *pipe_config, 1686 const struct intel_crtc_state *pipe_config,
1683 struct drm_connector_state *conn_state) 1687 const struct drm_connector_state *conn_state)
1684{ 1688{
1685 intel_hdmi_prepare(encoder, pipe_config); 1689 intel_hdmi_prepare(encoder, pipe_config);
1686 1690
@@ -1688,8 +1692,8 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1688} 1692}
1689 1693
1690static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 1694static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1691 struct intel_crtc_state *pipe_config, 1695 const struct intel_crtc_state *pipe_config,
1692 struct drm_connector_state *conn_state) 1696 const struct drm_connector_state *conn_state)
1693{ 1697{
1694 intel_hdmi_prepare(encoder, pipe_config); 1698 intel_hdmi_prepare(encoder, pipe_config);
1695 1699
@@ -1697,23 +1701,23 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1697} 1701}
1698 1702
1699static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, 1703static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1700 struct intel_crtc_state *old_crtc_state, 1704 const struct intel_crtc_state *old_crtc_state,
1701 struct drm_connector_state *old_conn_state) 1705 const struct drm_connector_state *old_conn_state)
1702{ 1706{
1703 chv_phy_post_pll_disable(encoder); 1707 chv_phy_post_pll_disable(encoder);
1704} 1708}
1705 1709
1706static void vlv_hdmi_post_disable(struct intel_encoder *encoder, 1710static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1707 struct intel_crtc_state *old_crtc_state, 1711 const struct intel_crtc_state *old_crtc_state,
1708 struct drm_connector_state *old_conn_state) 1712 const struct drm_connector_state *old_conn_state)
1709{ 1713{
1710 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1714 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1711 vlv_phy_reset_lanes(encoder); 1715 vlv_phy_reset_lanes(encoder);
1712} 1716}
1713 1717
1714static void chv_hdmi_post_disable(struct intel_encoder *encoder, 1718static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1715 struct intel_crtc_state *old_crtc_state, 1719 const struct intel_crtc_state *old_crtc_state,
1716 struct drm_connector_state *old_conn_state) 1720 const struct drm_connector_state *old_conn_state)
1717{ 1721{
1718 struct drm_device *dev = encoder->base.dev; 1722 struct drm_device *dev = encoder->base.dev;
1719 struct drm_i915_private *dev_priv = to_i915(dev); 1723 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1727,11 +1731,10 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1727} 1731}
1728 1732
1729static void chv_hdmi_pre_enable(struct intel_encoder *encoder, 1733static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1730 struct intel_crtc_state *pipe_config, 1734 const struct intel_crtc_state *pipe_config,
1731 struct drm_connector_state *conn_state) 1735 const struct drm_connector_state *conn_state)
1732{ 1736{
1733 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1737 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1734 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1735 struct drm_device *dev = encoder->base.dev; 1738 struct drm_device *dev = encoder->base.dev;
1736 struct drm_i915_private *dev_priv = to_i915(dev); 1739 struct drm_i915_private *dev_priv = to_i915(dev);
1737 1740
@@ -1741,9 +1744,9 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1741 /* Use 800mV-0dB */ 1744 /* Use 800mV-0dB */
1742 chv_set_phy_signal_level(encoder, 128, 102, false); 1745 chv_set_phy_signal_level(encoder, 128, 102, false);
1743 1746
1744 intel_hdmi->set_infoframes(&encoder->base, 1747 dport->set_infoframes(&encoder->base,
1745 pipe_config->has_hdmi_sink, 1748 pipe_config->has_infoframe,
1746 pipe_config, conn_state); 1749 pipe_config, conn_state);
1747 1750
1748 g4x_enable_hdmi(encoder, pipe_config, conn_state); 1751 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1749 1752
@@ -1958,6 +1961,34 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1958 return ddc_pin; 1961 return ddc_pin;
1959} 1962}
1960 1963
1964void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
1965{
1966 struct drm_i915_private *dev_priv =
1967 to_i915(intel_dig_port->base.base.dev);
1968
1969 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1970 intel_dig_port->write_infoframe = vlv_write_infoframe;
1971 intel_dig_port->set_infoframes = vlv_set_infoframes;
1972 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
1973 } else if (IS_G4X(dev_priv)) {
1974 intel_dig_port->write_infoframe = g4x_write_infoframe;
1975 intel_dig_port->set_infoframes = g4x_set_infoframes;
1976 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
1977 } else if (HAS_DDI(dev_priv)) {
1978 intel_dig_port->write_infoframe = hsw_write_infoframe;
1979 intel_dig_port->set_infoframes = hsw_set_infoframes;
1980 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
1981 } else if (HAS_PCH_IBX(dev_priv)) {
1982 intel_dig_port->write_infoframe = ibx_write_infoframe;
1983 intel_dig_port->set_infoframes = ibx_set_infoframes;
1984 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
1985 } else {
1986 intel_dig_port->write_infoframe = cpt_write_infoframe;
1987 intel_dig_port->set_infoframes = cpt_set_infoframes;
1988 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
1989 }
1990}
1991
1961void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1992void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1962 struct intel_connector *intel_connector) 1993 struct intel_connector *intel_connector)
1963{ 1994{
@@ -1993,28 +2024,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1993 return; 2024 return;
1994 intel_encoder->hpd_pin = intel_hpd_pin(port); 2025 intel_encoder->hpd_pin = intel_hpd_pin(port);
1995 2026
1996 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1997 intel_hdmi->write_infoframe = vlv_write_infoframe;
1998 intel_hdmi->set_infoframes = vlv_set_infoframes;
1999 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2000 } else if (IS_G4X(dev_priv)) {
2001 intel_hdmi->write_infoframe = g4x_write_infoframe;
2002 intel_hdmi->set_infoframes = g4x_set_infoframes;
2003 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2004 } else if (HAS_DDI(dev_priv)) {
2005 intel_hdmi->write_infoframe = hsw_write_infoframe;
2006 intel_hdmi->set_infoframes = hsw_set_infoframes;
2007 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2008 } else if (HAS_PCH_IBX(dev_priv)) {
2009 intel_hdmi->write_infoframe = ibx_write_infoframe;
2010 intel_hdmi->set_infoframes = ibx_set_infoframes;
2011 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2012 } else {
2013 intel_hdmi->write_infoframe = cpt_write_infoframe;
2014 intel_hdmi->set_infoframes = cpt_set_infoframes;
2015 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2016 }
2017
2018 if (HAS_DDI(dev_priv)) 2027 if (HAS_DDI(dev_priv))
2019 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2028 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2020 else 2029 else
@@ -2113,5 +2122,7 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv,
2113 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 2122 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2114 intel_dig_port->max_lanes = 4; 2123 intel_dig_port->max_lanes = 4;
2115 2124
2125 intel_infoframe_init(intel_dig_port);
2126
2116 intel_hdmi_init_connector(intel_dig_port, intel_connector); 2127 intel_hdmi_init_connector(intel_dig_port, intel_connector);
2117} 2128}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6f972e6ec663..d89e1b8e1cc5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1175,6 +1175,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1175 return -EINVAL; 1175 return -EINVAL;
1176 1176
1177 switch (INTEL_GEN(engine->i915)) { 1177 switch (INTEL_GEN(engine->i915)) {
1178 case 10:
1179 return 0;
1178 case 9: 1180 case 9:
1179 wa_bb_fn[0] = gen9_init_indirectctx_bb; 1181 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1180 wa_bb_fn[1] = gen9_init_perctx_bb; 1182 wa_bb_fn[1] = gen9_init_perctx_bb;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 8e215777c7f4..a9813aea89d8 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -229,8 +229,8 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
229} 229}
230 230
231static void intel_pre_enable_lvds(struct intel_encoder *encoder, 231static void intel_pre_enable_lvds(struct intel_encoder *encoder,
232 struct intel_crtc_state *pipe_config, 232 const struct intel_crtc_state *pipe_config,
233 struct drm_connector_state *conn_state) 233 const struct drm_connector_state *conn_state)
234{ 234{
235 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 235 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
236 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 236 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -306,8 +306,8 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
306 * Sets the power state for the panel. 306 * Sets the power state for the panel.
307 */ 307 */
308static void intel_enable_lvds(struct intel_encoder *encoder, 308static void intel_enable_lvds(struct intel_encoder *encoder,
309 struct intel_crtc_state *pipe_config, 309 const struct intel_crtc_state *pipe_config,
310 struct drm_connector_state *conn_state) 310 const struct drm_connector_state *conn_state)
311{ 311{
312 struct drm_device *dev = encoder->base.dev; 312 struct drm_device *dev = encoder->base.dev;
313 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 313 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
@@ -324,8 +324,8 @@ static void intel_enable_lvds(struct intel_encoder *encoder,
324} 324}
325 325
326static void intel_disable_lvds(struct intel_encoder *encoder, 326static void intel_disable_lvds(struct intel_encoder *encoder,
327 struct intel_crtc_state *old_crtc_state, 327 const struct intel_crtc_state *old_crtc_state,
328 struct drm_connector_state *old_conn_state) 328 const struct drm_connector_state *old_conn_state)
329{ 329{
330 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 330 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -339,8 +339,8 @@ static void intel_disable_lvds(struct intel_encoder *encoder,
339} 339}
340 340
341static void gmch_disable_lvds(struct intel_encoder *encoder, 341static void gmch_disable_lvds(struct intel_encoder *encoder,
342 struct intel_crtc_state *old_crtc_state, 342 const struct intel_crtc_state *old_crtc_state,
343 struct drm_connector_state *old_conn_state) 343 const struct drm_connector_state *old_conn_state)
344 344
345{ 345{
346 intel_panel_disable_backlight(old_conn_state); 346 intel_panel_disable_backlight(old_conn_state);
@@ -349,15 +349,15 @@ static void gmch_disable_lvds(struct intel_encoder *encoder,
349} 349}
350 350
351static void pch_disable_lvds(struct intel_encoder *encoder, 351static void pch_disable_lvds(struct intel_encoder *encoder,
352 struct intel_crtc_state *old_crtc_state, 352 const struct intel_crtc_state *old_crtc_state,
353 struct drm_connector_state *old_conn_state) 353 const struct drm_connector_state *old_conn_state)
354{ 354{
355 intel_panel_disable_backlight(old_conn_state); 355 intel_panel_disable_backlight(old_conn_state);
356} 356}
357 357
358static void pch_post_disable_lvds(struct intel_encoder *encoder, 358static void pch_post_disable_lvds(struct intel_encoder *encoder,
359 struct intel_crtc_state *old_crtc_state, 359 const struct intel_crtc_state *old_crtc_state,
360 struct drm_connector_state *old_conn_state) 360 const struct drm_connector_state *old_conn_state)
361{ 361{
362 intel_disable_lvds(encoder, old_crtc_state, old_conn_state); 362 intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
363} 363}
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 8fbd2bd0877f..96043a51c1bf 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -506,8 +506,8 @@ static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
506 return 0; 506 return 0;
507} 507}
508 508
509static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv, 509static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
510 bool enable) 510 bool enable)
511{ 511{
512 struct drm_device *dev = &dev_priv->drm; 512 struct drm_device *dev = &dev_priv->drm;
513 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); 513 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
@@ -533,10 +533,24 @@ retry:
533 goto put_state; 533 goto put_state;
534 } 534 }
535 535
536 pipe_config->pch_pfit.force_thru = enable; 536 if (HAS_IPS(dev_priv)) {
537 if (pipe_config->cpu_transcoder == TRANSCODER_EDP && 537 /*
538 pipe_config->pch_pfit.enabled != enable) 538 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
539 pipe_config->base.connectors_changed = true; 539 * enabled and disabled dynamically based on package C states,
540 * user space can't make reliable use of the CRCs, so let's just
541 * completely disable it.
542 */
543 pipe_config->ips_force_disable = enable;
544 if (pipe_config->ips_enabled == enable)
545 pipe_config->base.connectors_changed = true;
546 }
547
548 if (IS_HASWELL(dev_priv)) {
549 pipe_config->pch_pfit.force_thru = enable;
550 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
551 pipe_config->pch_pfit.enabled != enable)
552 pipe_config->base.connectors_changed = true;
553 }
540 554
541 ret = drm_atomic_commit(state); 555 ret = drm_atomic_commit(state);
542 556
@@ -570,8 +584,9 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
570 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; 584 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
571 break; 585 break;
572 case INTEL_PIPE_CRC_SOURCE_PF: 586 case INTEL_PIPE_CRC_SOURCE_PF:
573 if (IS_HASWELL(dev_priv) && pipe == PIPE_A) 587 if ((IS_HASWELL(dev_priv) ||
574 hsw_trans_edp_pipe_A_crc_wa(dev_priv, true); 588 IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
589 hsw_pipe_A_crc_wa(dev_priv, true);
575 590
576 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; 591 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
577 break; 592 break;
@@ -606,7 +621,6 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
606 enum intel_pipe_crc_source source) 621 enum intel_pipe_crc_source source)
607{ 622{
608 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 623 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
609 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
610 enum intel_display_power_domain power_domain; 624 enum intel_display_power_domain power_domain;
611 u32 val = 0; /* shut up gcc */ 625 u32 val = 0; /* shut up gcc */
612 int ret; 626 int ret;
@@ -643,14 +657,6 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
643 goto out; 657 goto out;
644 } 658 }
645 659
646 /*
647 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
648 * enabled and disabled dynamically based on package C states,
649 * user space can't make reliable use of the CRCs, so let's just
650 * completely disable it.
651 */
652 hsw_disable_ips(crtc);
653
654 spin_lock_irq(&pipe_crc->lock); 660 spin_lock_irq(&pipe_crc->lock);
655 kfree(pipe_crc->entries); 661 kfree(pipe_crc->entries);
656 pipe_crc->entries = entries; 662 pipe_crc->entries = entries;
@@ -691,10 +697,9 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
691 g4x_undo_pipe_scramble_reset(dev_priv, pipe); 697 g4x_undo_pipe_scramble_reset(dev_priv, pipe);
692 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 698 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
693 vlv_undo_pipe_scramble_reset(dev_priv, pipe); 699 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
694 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A) 700 else if ((IS_HASWELL(dev_priv) ||
695 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); 701 IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
696 702 hsw_pipe_A_crc_wa(dev_priv, false);
697 hsw_enable_ips(crtc);
698 } 703 }
699 704
700 ret = 0; 705 ret = 0;
@@ -914,7 +919,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
914{ 919{
915 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 920 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
916 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; 921 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
918 enum intel_display_power_domain power_domain; 922 enum intel_display_power_domain power_domain;
919 enum intel_pipe_crc_source source; 923 enum intel_pipe_crc_source source;
920 u32 val = 0; /* shut up gcc */ 924 u32 val = 0; /* shut up gcc */
@@ -935,16 +939,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
935 if (ret != 0) 939 if (ret != 0)
936 goto out; 940 goto out;
937 941
938 if (source) {
939 /*
940 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
941 * enabled and disabled dynamically based on package C states,
942 * user space can't make reliable use of the CRCs, so let's just
943 * completely disable it.
944 */
945 hsw_disable_ips(intel_crtc);
946 }
947
948 I915_WRITE(PIPE_CRC_CTL(crtc->index), val); 942 I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
949 POSTING_READ(PIPE_CRC_CTL(crtc->index)); 943 POSTING_READ(PIPE_CRC_CTL(crtc->index));
950 944
@@ -953,10 +947,9 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
953 g4x_undo_pipe_scramble_reset(dev_priv, crtc->index); 947 g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
954 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 948 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
955 vlv_undo_pipe_scramble_reset(dev_priv, crtc->index); 949 vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
956 else if (IS_HASWELL(dev_priv) && crtc->index == PIPE_A) 950 else if ((IS_HASWELL(dev_priv) ||
957 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); 951 IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
958 952 hsw_pipe_A_crc_wa(dev_priv, false);
959 hsw_enable_ips(intel_crtc);
960 } 953 }
961 954
962 pipe_crc->skipped = 0; 955 pipe_crc->skipped = 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed662937ec3c..0201816a4229 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -125,6 +125,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
125 125
126static void glk_init_clock_gating(struct drm_i915_private *dev_priv) 126static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
127{ 127{
128 u32 val;
128 gen9_init_clock_gating(dev_priv); 129 gen9_init_clock_gating(dev_priv);
129 130
130 /* 131 /*
@@ -144,6 +145,11 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
144 I915_WRITE(CHICKEN_MISC_2, val); 145 I915_WRITE(CHICKEN_MISC_2, val);
145 } 146 }
146 147
148 /* Display WA #1133: WaFbcSkipSegments:glk */
149 val = I915_READ(ILK_DPFC_CHICKEN);
150 val &= ~GLK_SKIP_SEG_COUNT_MASK;
151 val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
152 I915_WRITE(ILK_DPFC_CHICKEN, val);
147} 153}
148 154
149static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) 155static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
@@ -1322,21 +1328,21 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1322 int num_active_planes = hweight32(crtc_state->active_planes & 1328 int num_active_planes = hweight32(crtc_state->active_planes &
1323 ~BIT(PLANE_CURSOR)); 1329 ~BIT(PLANE_CURSOR));
1324 const struct g4x_pipe_wm *raw; 1330 const struct g4x_pipe_wm *raw;
1325 struct intel_plane_state *plane_state; 1331 const struct intel_plane_state *old_plane_state;
1332 const struct intel_plane_state *new_plane_state;
1326 struct intel_plane *plane; 1333 struct intel_plane *plane;
1327 enum plane_id plane_id; 1334 enum plane_id plane_id;
1328 int i, level; 1335 int i, level;
1329 unsigned int dirty = 0; 1336 unsigned int dirty = 0;
1330 1337
1331 for_each_intel_plane_in_state(state, plane, plane_state, i) { 1338 for_each_oldnew_intel_plane_in_state(state, plane,
1332 const struct intel_plane_state *old_plane_state = 1339 old_plane_state,
1333 to_intel_plane_state(plane->base.state); 1340 new_plane_state, i) {
1334 1341 if (new_plane_state->base.crtc != &crtc->base &&
1335 if (plane_state->base.crtc != &crtc->base &&
1336 old_plane_state->base.crtc != &crtc->base) 1342 old_plane_state->base.crtc != &crtc->base)
1337 continue; 1343 continue;
1338 1344
1339 if (g4x_raw_plane_wm_compute(crtc_state, plane_state)) 1345 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1340 dirty |= BIT(plane->id); 1346 dirty |= BIT(plane->id);
1341 } 1347 }
1342 1348
@@ -1831,21 +1837,21 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1831 int num_active_planes = hweight32(crtc_state->active_planes & 1837 int num_active_planes = hweight32(crtc_state->active_planes &
1832 ~BIT(PLANE_CURSOR)); 1838 ~BIT(PLANE_CURSOR));
1833 bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base); 1839 bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1834 struct intel_plane_state *plane_state; 1840 const struct intel_plane_state *old_plane_state;
1841 const struct intel_plane_state *new_plane_state;
1835 struct intel_plane *plane; 1842 struct intel_plane *plane;
1836 enum plane_id plane_id; 1843 enum plane_id plane_id;
1837 int level, ret, i; 1844 int level, ret, i;
1838 unsigned int dirty = 0; 1845 unsigned int dirty = 0;
1839 1846
1840 for_each_intel_plane_in_state(state, plane, plane_state, i) { 1847 for_each_oldnew_intel_plane_in_state(state, plane,
1841 const struct intel_plane_state *old_plane_state = 1848 old_plane_state,
1842 to_intel_plane_state(plane->base.state); 1849 new_plane_state, i) {
1843 1850 if (new_plane_state->base.crtc != &crtc->base &&
1844 if (plane_state->base.crtc != &crtc->base &&
1845 old_plane_state->base.crtc != &crtc->base) 1851 old_plane_state->base.crtc != &crtc->base)
1846 continue; 1852 continue;
1847 1853
1848 if (vlv_raw_plane_wm_compute(crtc_state, plane_state)) 1854 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1849 dirty |= BIT(plane->id); 1855 dirty |= BIT(plane->id);
1850 } 1856 }
1851 1857
@@ -1864,7 +1870,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1864 /* cursor changes don't warrant a FIFO recompute */ 1870 /* cursor changes don't warrant a FIFO recompute */
1865 if (dirty & ~BIT(PLANE_CURSOR)) { 1871 if (dirty & ~BIT(PLANE_CURSOR)) {
1866 const struct intel_crtc_state *old_crtc_state = 1872 const struct intel_crtc_state *old_crtc_state =
1867 to_intel_crtc_state(crtc->base.state); 1873 intel_atomic_get_old_crtc_state(state, crtc);
1868 const struct vlv_fifo_state *old_fifo_state = 1874 const struct vlv_fifo_state *old_fifo_state =
1869 &old_crtc_state->wm.vlv.fifo_state; 1875 &old_crtc_state->wm.vlv.fifo_state;
1870 1876
@@ -6169,6 +6175,7 @@ void gen6_rps_boost(struct drm_i915_gem_request *rq,
6169 struct intel_rps_client *rps) 6175 struct intel_rps_client *rps)
6170{ 6176{
6171 struct drm_i915_private *i915 = rq->i915; 6177 struct drm_i915_private *i915 = rq->i915;
6178 unsigned long flags;
6172 bool boost; 6179 bool boost;
6173 6180
6174 /* This is intentionally racy! We peek at the state here, then 6181 /* This is intentionally racy! We peek at the state here, then
@@ -6178,13 +6185,13 @@ void gen6_rps_boost(struct drm_i915_gem_request *rq,
6178 return; 6185 return;
6179 6186
6180 boost = false; 6187 boost = false;
6181 spin_lock_irq(&rq->lock); 6188 spin_lock_irqsave(&rq->lock, flags);
6182 if (!rq->waitboost && !i915_gem_request_completed(rq)) { 6189 if (!rq->waitboost && !i915_gem_request_completed(rq)) {
6183 atomic_inc(&i915->rps.num_waiters); 6190 atomic_inc(&i915->rps.num_waiters);
6184 rq->waitboost = true; 6191 rq->waitboost = true;
6185 boost = true; 6192 boost = true;
6186 } 6193 }
6187 spin_unlock_irq(&rq->lock); 6194 spin_unlock_irqrestore(&rq->lock, flags);
6188 if (!boost) 6195 if (!boost)
6189 return; 6196 return;
6190 6197
@@ -7980,7 +7987,7 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
7980 */ 7987 */
7981} 7988}
7982 7989
7983static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv) 7990static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
7984{ 7991{
7985 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 7992 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7986 7993
@@ -8263,7 +8270,56 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
8263 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 8270 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
8264} 8271}
8265 8272
8266static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) 8273static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
8274{
8275 if (!HAS_PCH_CNP(dev_priv))
8276 return;
8277
8278 /* Wa #1181 */
8279 I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
8280}
8281
8282static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
8283{
8284 u32 val;
8285 cnp_init_clock_gating(dev_priv);
8286
8287 /* This is not an Wa. Enable for better image quality */
8288 I915_WRITE(_3D_CHICKEN3,
8289 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
8290
8291 /* WaEnableChickenDCPR:cnl */
8292 I915_WRITE(GEN8_CHICKEN_DCPR_1,
8293 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
8294
8295 /* WaFbcWakeMemOn:cnl */
8296 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
8297 DISP_FBC_MEMORY_WAKE);
8298
8299 /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
8300 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
8301 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
8302 I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
8303 SARBUNIT_CLKGATE_DIS);
8304
8305 /* Display WA #1133: WaFbcSkipSegments:cnl */
8306 val = I915_READ(ILK_DPFC_CHICKEN);
8307 val &= ~GLK_SKIP_SEG_COUNT_MASK;
8308 val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
8309 I915_WRITE(ILK_DPFC_CHICKEN, val);
8310}
8311
8312static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
8313{
8314 cnp_init_clock_gating(dev_priv);
8315 gen9_init_clock_gating(dev_priv);
8316
8317 /* WaFbcNukeOnHostModify:cfl */
8318 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8319 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8320}
8321
8322static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
8267{ 8323{
8268 gen9_init_clock_gating(dev_priv); 8324 gen9_init_clock_gating(dev_priv);
8269 8325
@@ -8277,12 +8333,12 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
8277 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | 8333 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8278 GEN6_GAMUNIT_CLOCK_GATE_DISABLE); 8334 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
8279 8335
8280 /* WaFbcNukeOnHostModify:kbl,cfl */ 8336 /* WaFbcNukeOnHostModify:kbl */
8281 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | 8337 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8282 ILK_DPFC_NUKE_ON_ANY_MODIFICATION); 8338 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8283} 8339}
8284 8340
8285static void skylake_init_clock_gating(struct drm_i915_private *dev_priv) 8341static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
8286{ 8342{
8287 gen9_init_clock_gating(dev_priv); 8343 gen9_init_clock_gating(dev_priv);
8288 8344
@@ -8295,7 +8351,7 @@ static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
8295 ILK_DPFC_NUKE_ON_ANY_MODIFICATION); 8351 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8296} 8352}
8297 8353
8298static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) 8354static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
8299{ 8355{
8300 enum pipe pipe; 8356 enum pipe pipe;
8301 8357
@@ -8353,7 +8409,7 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
8353 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); 8409 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
8354} 8410}
8355 8411
8356static void haswell_init_clock_gating(struct drm_i915_private *dev_priv) 8412static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
8357{ 8413{
8358 ilk_init_lp_watermarks(dev_priv); 8414 ilk_init_lp_watermarks(dev_priv);
8359 8415
@@ -8407,7 +8463,7 @@ static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
8407 lpt_init_clock_gating(dev_priv); 8463 lpt_init_clock_gating(dev_priv);
8408} 8464}
8409 8465
8410static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv) 8466static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
8411{ 8467{
8412 uint32_t snpcr; 8468 uint32_t snpcr;
8413 8469
@@ -8504,7 +8560,7 @@ static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
8504 gen6_check_mch_setup(dev_priv); 8560 gen6_check_mch_setup(dev_priv);
8505} 8561}
8506 8562
8507static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv) 8563static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
8508{ 8564{
8509 /* WaDisableEarlyCull:vlv */ 8565 /* WaDisableEarlyCull:vlv */
8510 I915_WRITE(_3D_CHICKEN3, 8566 I915_WRITE(_3D_CHICKEN3,
@@ -8584,7 +8640,7 @@ static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
8584 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 8640 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
8585} 8641}
8586 8642
8587static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv) 8643static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
8588{ 8644{
8589 /* WaVSRefCountFullforceMissDisable:chv */ 8645 /* WaVSRefCountFullforceMissDisable:chv */
8590 /* WaDSRefCountFullforceMissDisable:chv */ 8646 /* WaDSRefCountFullforceMissDisable:chv */
@@ -8644,7 +8700,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
8644 g4x_disable_trickle_feed(dev_priv); 8700 g4x_disable_trickle_feed(dev_priv);
8645} 8701}
8646 8702
8647static void crestline_init_clock_gating(struct drm_i915_private *dev_priv) 8703static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
8648{ 8704{
8649 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 8705 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8650 I915_WRITE(RENCLK_GATE_D2, 0); 8706 I915_WRITE(RENCLK_GATE_D2, 0);
@@ -8658,7 +8714,7 @@ static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
8658 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 8714 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8659} 8715}
8660 8716
8661static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv) 8717static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
8662{ 8718{
8663 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 8719 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8664 I965_RCC_CLOCK_GATE_DISABLE | 8720 I965_RCC_CLOCK_GATE_DISABLE |
@@ -8743,34 +8799,38 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
8743 */ 8799 */
8744void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) 8800void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
8745{ 8801{
8746 if (IS_SKYLAKE(dev_priv)) 8802 if (IS_CANNONLAKE(dev_priv))
8747 dev_priv->display.init_clock_gating = skylake_init_clock_gating; 8803 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
8748 else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) 8804 else if (IS_COFFEELAKE(dev_priv))
8749 dev_priv->display.init_clock_gating = kabylake_init_clock_gating; 8805 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
8806 else if (IS_SKYLAKE(dev_priv))
8807 dev_priv->display.init_clock_gating = skl_init_clock_gating;
8808 else if (IS_KABYLAKE(dev_priv))
8809 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
8750 else if (IS_BROXTON(dev_priv)) 8810 else if (IS_BROXTON(dev_priv))
8751 dev_priv->display.init_clock_gating = bxt_init_clock_gating; 8811 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
8752 else if (IS_GEMINILAKE(dev_priv)) 8812 else if (IS_GEMINILAKE(dev_priv))
8753 dev_priv->display.init_clock_gating = glk_init_clock_gating; 8813 dev_priv->display.init_clock_gating = glk_init_clock_gating;
8754 else if (IS_BROADWELL(dev_priv)) 8814 else if (IS_BROADWELL(dev_priv))
8755 dev_priv->display.init_clock_gating = broadwell_init_clock_gating; 8815 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
8756 else if (IS_CHERRYVIEW(dev_priv)) 8816 else if (IS_CHERRYVIEW(dev_priv))
8757 dev_priv->display.init_clock_gating = cherryview_init_clock_gating; 8817 dev_priv->display.init_clock_gating = chv_init_clock_gating;
8758 else if (IS_HASWELL(dev_priv)) 8818 else if (IS_HASWELL(dev_priv))
8759 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 8819 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
8760 else if (IS_IVYBRIDGE(dev_priv)) 8820 else if (IS_IVYBRIDGE(dev_priv))
8761 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 8821 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
8762 else if (IS_VALLEYVIEW(dev_priv)) 8822 else if (IS_VALLEYVIEW(dev_priv))
8763 dev_priv->display.init_clock_gating = valleyview_init_clock_gating; 8823 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
8764 else if (IS_GEN6(dev_priv)) 8824 else if (IS_GEN6(dev_priv))
8765 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 8825 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8766 else if (IS_GEN5(dev_priv)) 8826 else if (IS_GEN5(dev_priv))
8767 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 8827 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
8768 else if (IS_G4X(dev_priv)) 8828 else if (IS_G4X(dev_priv))
8769 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 8829 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8770 else if (IS_I965GM(dev_priv)) 8830 else if (IS_I965GM(dev_priv))
8771 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 8831 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
8772 else if (IS_I965G(dev_priv)) 8832 else if (IS_I965G(dev_priv))
8773 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 8833 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
8774 else if (IS_GEN3(dev_priv)) 8834 else if (IS_GEN3(dev_priv))
8775 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 8835 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8776 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) 8836 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
@@ -9132,43 +9192,6 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
9132 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 9192 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
9133} 9193}
9134 9194
9135struct request_boost {
9136 struct work_struct work;
9137 struct drm_i915_gem_request *req;
9138};
9139
9140static void __intel_rps_boost_work(struct work_struct *work)
9141{
9142 struct request_boost *boost = container_of(work, struct request_boost, work);
9143 struct drm_i915_gem_request *req = boost->req;
9144
9145 if (!i915_gem_request_completed(req))
9146 gen6_rps_boost(req, NULL);
9147
9148 i915_gem_request_put(req);
9149 kfree(boost);
9150}
9151
9152void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
9153{
9154 struct request_boost *boost;
9155
9156 if (req == NULL || INTEL_GEN(req->i915) < 6)
9157 return;
9158
9159 if (i915_gem_request_completed(req))
9160 return;
9161
9162 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
9163 if (boost == NULL)
9164 return;
9165
9166 boost->req = i915_gem_request_get(req);
9167
9168 INIT_WORK(&boost->work, __intel_rps_boost_work);
9169 queue_work(req->i915->wq, &boost->work);
9170}
9171
9172void intel_pm_setup(struct drm_i915_private *dev_priv) 9195void intel_pm_setup(struct drm_i915_private *dev_priv)
9173{ 9196{
9174 mutex_init(&dev_priv->rps.hw_lock); 9197 mutex_init(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 1b31ab002dae..f62ab05d3d62 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -103,28 +103,26 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
103 POSTING_READ(ctl_reg); 103 POSTING_READ(ctl_reg);
104} 104}
105 105
106static void vlv_psr_setup_vsc(struct intel_dp *intel_dp) 106static void vlv_psr_setup_vsc(struct intel_dp *intel_dp,
107 const struct intel_crtc_state *crtc_state)
107{ 108{
108 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 109 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
109 struct drm_device *dev = intel_dig_port->base.base.dev; 110 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
110 struct drm_i915_private *dev_priv = to_i915(dev);
111 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
112 enum pipe pipe = to_intel_crtc(crtc)->pipe;
113 uint32_t val; 111 uint32_t val;
114 112
115 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */ 113 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
116 val = I915_READ(VLV_VSCSDP(pipe)); 114 val = I915_READ(VLV_VSCSDP(crtc->pipe));
117 val &= ~VLV_EDP_PSR_SDP_FREQ_MASK; 115 val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
118 val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME; 116 val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
119 I915_WRITE(VLV_VSCSDP(pipe), val); 117 I915_WRITE(VLV_VSCSDP(crtc->pipe), val);
120} 118}
121 119
122static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp) 120static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp,
121 const struct intel_crtc_state *crtc_state)
123{ 122{
124 struct edp_vsc_psr psr_vsc;
125 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 123 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
126 struct drm_device *dev = intel_dig_port->base.base.dev; 124 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
127 struct drm_i915_private *dev_priv = to_i915(dev); 125 struct edp_vsc_psr psr_vsc;
128 126
129 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ 127 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
130 memset(&psr_vsc, 0, sizeof(psr_vsc)); 128 memset(&psr_vsc, 0, sizeof(psr_vsc));
@@ -145,7 +143,8 @@ static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
145 intel_psr_write_vsc(intel_dp, &psr_vsc); 143 intel_psr_write_vsc(intel_dp, &psr_vsc);
146} 144}
147 145
148static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) 146static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
147 const struct intel_crtc_state *crtc_state)
149{ 148{
150 struct edp_vsc_psr psr_vsc; 149 struct edp_vsc_psr psr_vsc;
151 150
@@ -233,16 +232,15 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
233 I915_WRITE(aux_ctl_reg, aux_ctl); 232 I915_WRITE(aux_ctl_reg, aux_ctl);
234} 233}
235 234
236static void vlv_psr_enable_source(struct intel_dp *intel_dp) 235static void vlv_psr_enable_source(struct intel_dp *intel_dp,
236 const struct intel_crtc_state *crtc_state)
237{ 237{
238 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 238 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
239 struct drm_device *dev = dig_port->base.base.dev; 239 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
240 struct drm_i915_private *dev_priv = to_i915(dev); 240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
241 struct drm_crtc *crtc = dig_port->base.base.crtc;
242 enum pipe pipe = to_intel_crtc(crtc)->pipe;
243 241
244 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */ 242 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
245 I915_WRITE(VLV_PSRCTL(pipe), 243 I915_WRITE(VLV_PSRCTL(crtc->pipe),
246 VLV_EDP_PSR_MODE_SW_TIMER | 244 VLV_EDP_PSR_MODE_SW_TIMER |
247 VLV_EDP_PSR_SRC_TRANSMITTER_STATE | 245 VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
248 VLV_EDP_PSR_ENABLE); 246 VLV_EDP_PSR_ENABLE);
@@ -485,16 +483,17 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
485/** 483/**
486 * intel_psr_enable - Enable PSR 484 * intel_psr_enable - Enable PSR
487 * @intel_dp: Intel DP 485 * @intel_dp: Intel DP
486 * @crtc_state: new CRTC state
488 * 487 *
489 * This function can only be called after the pipe is fully trained and enabled. 488 * This function can only be called after the pipe is fully trained and enabled.
490 */ 489 */
491void intel_psr_enable(struct intel_dp *intel_dp) 490void intel_psr_enable(struct intel_dp *intel_dp,
491 const struct intel_crtc_state *crtc_state)
492{ 492{
493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
494 struct drm_device *dev = intel_dig_port->base.base.dev; 494 struct drm_device *dev = intel_dig_port->base.base.dev;
495 struct drm_i915_private *dev_priv = to_i915(dev); 495 struct drm_i915_private *dev_priv = to_i915(dev);
496 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 496 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
497 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
498 u32 chicken; 497 u32 chicken;
499 498
500 if (!HAS_PSR(dev_priv)) { 499 if (!HAS_PSR(dev_priv)) {
@@ -520,11 +519,13 @@ void intel_psr_enable(struct intel_dp *intel_dp)
520 519
521 if (HAS_DDI(dev_priv)) { 520 if (HAS_DDI(dev_priv)) {
522 if (dev_priv->psr.psr2_support) { 521 if (dev_priv->psr.psr2_support) {
523 skl_psr_setup_su_vsc(intel_dp); 522 skl_psr_setup_su_vsc(intel_dp, crtc_state);
523
524 chicken = PSR2_VSC_ENABLE_PROG_HEADER; 524 chicken = PSR2_VSC_ENABLE_PROG_HEADER;
525 if (dev_priv->psr.y_cord_support) 525 if (dev_priv->psr.y_cord_support)
526 chicken |= PSR2_ADD_VERTICAL_LINE_COUNT; 526 chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
527 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); 527 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
528
528 I915_WRITE(EDP_PSR_DEBUG_CTL, 529 I915_WRITE(EDP_PSR_DEBUG_CTL,
529 EDP_PSR_DEBUG_MASK_MEMUP | 530 EDP_PSR_DEBUG_MASK_MEMUP |
530 EDP_PSR_DEBUG_MASK_HPD | 531 EDP_PSR_DEBUG_MASK_HPD |
@@ -533,7 +534,8 @@ void intel_psr_enable(struct intel_dp *intel_dp)
533 EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); 534 EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
534 } else { 535 } else {
535 /* set up vsc header for psr1 */ 536 /* set up vsc header for psr1 */
536 hsw_psr_setup_vsc(intel_dp); 537 hsw_psr_setup_vsc(intel_dp, crtc_state);
538
537 /* 539 /*
538 * Per Spec: Avoid continuous PSR exit by masking MEMUP 540 * Per Spec: Avoid continuous PSR exit by masking MEMUP
539 * and HPD. also mask LPSP to avoid dependency on other 541 * and HPD. also mask LPSP to avoid dependency on other
@@ -553,7 +555,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
553 if (INTEL_GEN(dev_priv) >= 9) 555 if (INTEL_GEN(dev_priv) >= 9)
554 intel_psr_activate(intel_dp); 556 intel_psr_activate(intel_dp);
555 } else { 557 } else {
556 vlv_psr_setup_vsc(intel_dp); 558 vlv_psr_setup_vsc(intel_dp, crtc_state);
557 559
558 /* Enable PSR on the panel */ 560 /* Enable PSR on the panel */
559 vlv_psr_enable_sink(intel_dp); 561 vlv_psr_enable_sink(intel_dp);
@@ -564,7 +566,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
564 * but let it on inactive state. So we might do this prior 566 * but let it on inactive state. So we might do this prior
565 * to active transition, i.e. here. 567 * to active transition, i.e. here.
566 */ 568 */
567 vlv_psr_enable_source(intel_dp); 569 vlv_psr_enable_source(intel_dp, crtc_state);
568 } 570 }
569 571
570 /* 572 /*
@@ -585,37 +587,38 @@ unlock:
585 mutex_unlock(&dev_priv->psr.lock); 587 mutex_unlock(&dev_priv->psr.lock);
586} 588}
587 589
588static void vlv_psr_disable(struct intel_dp *intel_dp) 590static void vlv_psr_disable(struct intel_dp *intel_dp,
591 const struct intel_crtc_state *old_crtc_state)
589{ 592{
590 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 593 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
591 struct drm_device *dev = intel_dig_port->base.base.dev; 594 struct drm_device *dev = intel_dig_port->base.base.dev;
592 struct drm_i915_private *dev_priv = to_i915(dev); 595 struct drm_i915_private *dev_priv = to_i915(dev);
593 struct intel_crtc *intel_crtc = 596 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
594 to_intel_crtc(intel_dig_port->base.base.crtc);
595 uint32_t val; 597 uint32_t val;
596 598
597 if (dev_priv->psr.active) { 599 if (dev_priv->psr.active) {
598 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */ 600 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
599 if (intel_wait_for_register(dev_priv, 601 if (intel_wait_for_register(dev_priv,
600 VLV_PSRSTAT(intel_crtc->pipe), 602 VLV_PSRSTAT(crtc->pipe),
601 VLV_EDP_PSR_IN_TRANS, 603 VLV_EDP_PSR_IN_TRANS,
602 0, 604 0,
603 1)) 605 1))
604 WARN(1, "PSR transition took longer than expected\n"); 606 WARN(1, "PSR transition took longer than expected\n");
605 607
606 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); 608 val = I915_READ(VLV_PSRCTL(crtc->pipe));
607 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; 609 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
608 val &= ~VLV_EDP_PSR_ENABLE; 610 val &= ~VLV_EDP_PSR_ENABLE;
609 val &= ~VLV_EDP_PSR_MODE_MASK; 611 val &= ~VLV_EDP_PSR_MODE_MASK;
610 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); 612 I915_WRITE(VLV_PSRCTL(crtc->pipe), val);
611 613
612 dev_priv->psr.active = false; 614 dev_priv->psr.active = false;
613 } else { 615 } else {
614 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)); 616 WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe));
615 } 617 }
616} 618}
617 619
618static void hsw_psr_disable(struct intel_dp *intel_dp) 620static void hsw_psr_disable(struct intel_dp *intel_dp,
621 const struct intel_crtc_state *old_crtc_state)
619{ 622{
620 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 623 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
621 struct drm_device *dev = intel_dig_port->base.base.dev; 624 struct drm_device *dev = intel_dig_port->base.base.dev;
@@ -664,10 +667,12 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
664/** 667/**
665 * intel_psr_disable - Disable PSR 668 * intel_psr_disable - Disable PSR
666 * @intel_dp: Intel DP 669 * @intel_dp: Intel DP
670 * @old_crtc_state: old CRTC state
667 * 671 *
668 * This function needs to be called before disabling pipe. 672 * This function needs to be called before disabling pipe.
669 */ 673 */
670void intel_psr_disable(struct intel_dp *intel_dp) 674void intel_psr_disable(struct intel_dp *intel_dp,
675 const struct intel_crtc_state *old_crtc_state)
671{ 676{
672 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 677 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
673 struct drm_device *dev = intel_dig_port->base.base.dev; 678 struct drm_device *dev = intel_dig_port->base.base.dev;
@@ -681,9 +686,9 @@ void intel_psr_disable(struct intel_dp *intel_dp)
681 686
682 /* Disable PSR on Source */ 687 /* Disable PSR on Source */
683 if (HAS_DDI(dev_priv)) 688 if (HAS_DDI(dev_priv))
684 hsw_psr_disable(intel_dp); 689 hsw_psr_disable(intel_dp, old_crtc_state);
685 else 690 else
686 vlv_psr_disable(intel_dp); 691 vlv_psr_disable(intel_dp, old_crtc_state);
687 692
688 /* Disable PSR on Sink */ 693 /* Disable PSR on Sink */
689 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 694 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 02d8974bf9ab..79c0021f3700 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -735,16 +735,6 @@ bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
735void intel_engines_mark_idle(struct drm_i915_private *i915); 735void intel_engines_mark_idle(struct drm_i915_private *i915);
736void intel_engines_reset_default_submission(struct drm_i915_private *i915); 736void intel_engines_reset_default_submission(struct drm_i915_private *i915);
737 737
738static inline bool 738bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
739__intel_engine_can_store_dword(unsigned int gen, unsigned int class)
740{
741 if (gen <= 2)
742 return false; /* uses physical not virtual addresses */
743
744 if (gen == 6 && class == VIDEO_DECODE_CLASS)
745 return false; /* b0rked */
746
747 return true;
748}
749 739
750#endif /* _INTEL_RINGBUFFER_H_ */ 740#endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b66d8e136aa3..a3bfb9f27e7a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2707,30 +2707,67 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2707 usleep_range(10, 30); /* 10 us delay per Bspec */ 2707 usleep_range(10, 30); /* 10 us delay per Bspec */
2708} 2708}
2709 2709
2710#define CNL_PROCMON_IDX(val) \ 2710enum {
2711 (((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT) 2711 PROCMON_0_85V_DOT_0,
2712#define NUM_CNL_PROCMON \ 2712 PROCMON_0_95V_DOT_0,
2713 (CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1) 2713 PROCMON_0_95V_DOT_1,
2714 PROCMON_1_05V_DOT_0,
2715 PROCMON_1_05V_DOT_1,
2716};
2714 2717
2715static const struct cnl_procmon { 2718static const struct cnl_procmon {
2716 u32 dw1, dw9, dw10; 2719 u32 dw1, dw9, dw10;
2717} cnl_procmon_values[NUM_CNL_PROCMON] = { 2720} cnl_procmon_values[] = {
2718 [CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] = 2721 [PROCMON_0_85V_DOT_0] =
2719 { .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, 2722 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
2720 [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] = 2723 [PROCMON_0_95V_DOT_0] =
2721 { .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, 2724 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
2722 [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] = 2725 [PROCMON_0_95V_DOT_1] =
2723 { .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, 2726 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
2724 [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] = 2727 [PROCMON_1_05V_DOT_0] =
2725 { .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, 2728 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
2726 [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] = 2729 [PROCMON_1_05V_DOT_1] =
2727 { .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, 2730 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
2728}; 2731};
2729 2732
2733static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
2734{
2735 const struct cnl_procmon *procmon;
2736 u32 val;
2737
2738 val = I915_READ(CNL_PORT_COMP_DW3);
2739 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
2740 default:
2741 MISSING_CASE(val);
2742 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
2743 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
2744 break;
2745 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
2746 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
2747 break;
2748 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
2749 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
2750 break;
2751 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
2752 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
2753 break;
2754 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
2755 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
2756 break;
2757 }
2758
2759 val = I915_READ(CNL_PORT_COMP_DW1);
2760 val &= ~((0xff << 16) | 0xff);
2761 val |= procmon->dw1;
2762 I915_WRITE(CNL_PORT_COMP_DW1, val);
2763
2764 I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
2765 I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
2766}
2767
2730static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) 2768static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
2731{ 2769{
2732 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2770 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2733 const struct cnl_procmon *procmon;
2734 struct i915_power_well *well; 2771 struct i915_power_well *well;
2735 u32 val; 2772 u32 val;
2736 2773
@@ -2746,18 +2783,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
2746 val &= ~CNL_COMP_PWR_DOWN; 2783 val &= ~CNL_COMP_PWR_DOWN;
2747 I915_WRITE(CHICKEN_MISC_2, val); 2784 I915_WRITE(CHICKEN_MISC_2, val);
2748 2785
2749 val = I915_READ(CNL_PORT_COMP_DW3); 2786 cnl_set_procmon_ref_values(dev_priv);
2750 procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
2751
2752 WARN_ON(procmon->dw10 == 0);
2753
2754 val = I915_READ(CNL_PORT_COMP_DW1);
2755 val &= ~((0xff << 16) | 0xff);
2756 val |= procmon->dw1;
2757 I915_WRITE(CNL_PORT_COMP_DW1, val);
2758
2759 I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
2760 I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
2761 2787
2762 val = I915_READ(CNL_PORT_COMP_DW0); 2788 val = I915_READ(CNL_PORT_COMP_DW0);
2763 val |= COMP_INIT; 2789 val |= COMP_INIT;
@@ -2784,9 +2810,6 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
2784 gen9_dbuf_enable(dev_priv); 2810 gen9_dbuf_enable(dev_priv);
2785} 2811}
2786 2812
2787#undef CNL_PROCMON_IDX
2788#undef NUM_CNL_PROCMON
2789
2790static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) 2813static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
2791{ 2814{
2792 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2815 struct i915_power_domains *power_domains = &dev_priv->power_domains;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 29a3b0f5bec7..7437944b388f 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -201,11 +201,8 @@ to_intel_sdvo_connector(struct drm_connector *connector)
201 return container_of(connector, struct intel_sdvo_connector, base.base); 201 return container_of(connector, struct intel_sdvo_connector, base.base);
202} 202}
203 203
204static struct intel_sdvo_connector_state * 204#define to_intel_sdvo_connector_state(conn_state) \
205to_intel_sdvo_connector_state(struct drm_connector_state *conn_state) 205 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
206{
207 return container_of(conn_state, struct intel_sdvo_connector_state, base.base);
208}
209 206
210static bool 207static bool
211intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 208intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
@@ -998,7 +995,7 @@ static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
998} 995}
999 996
1000static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 997static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1001 struct intel_crtc_state *pipe_config) 998 const struct intel_crtc_state *pipe_config)
1002{ 999{
1003 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1000 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1004 union hdmi_infoframe frame; 1001 union hdmi_infoframe frame;
@@ -1032,7 +1029,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1032} 1029}
1033 1030
1034static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1031static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1035 struct drm_connector_state *conn_state) 1032 const struct drm_connector_state *conn_state)
1036{ 1033{
1037 struct intel_sdvo_tv_format format; 1034 struct intel_sdvo_tv_format format;
1038 uint32_t format_map; 1035 uint32_t format_map;
@@ -1202,9 +1199,9 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1202 } while (0) 1199 } while (0)
1203 1200
1204static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1201static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1205 struct intel_sdvo_connector_state *sdvo_state) 1202 const struct intel_sdvo_connector_state *sdvo_state)
1206{ 1203{
1207 struct drm_connector_state *conn_state = &sdvo_state->base.base; 1204 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
1208 struct intel_sdvo_connector *intel_sdvo_conn = 1205 struct intel_sdvo_connector *intel_sdvo_conn =
1209 to_intel_sdvo_connector(conn_state->connector); 1206 to_intel_sdvo_connector(conn_state->connector);
1210 uint16_t val; 1207 uint16_t val;
@@ -1258,14 +1255,15 @@ static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1258} 1255}
1259 1256
1260static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, 1257static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
1261 struct intel_crtc_state *crtc_state, 1258 const struct intel_crtc_state *crtc_state,
1262 struct drm_connector_state *conn_state) 1259 const struct drm_connector_state *conn_state)
1263{ 1260{
1264 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 1261 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1262 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1266 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; 1263 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1267 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(conn_state); 1264 const struct intel_sdvo_connector_state *sdvo_state =
1268 struct drm_display_mode *mode = &crtc_state->base.mode; 1265 to_intel_sdvo_connector_state(conn_state);
1266 const struct drm_display_mode *mode = &crtc_state->base.mode;
1269 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1267 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1270 u32 sdvox; 1268 u32 sdvox;
1271 struct intel_sdvo_in_out_map in_out; 1269 struct intel_sdvo_in_out_map in_out;
@@ -1507,8 +1505,8 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
1507} 1505}
1508 1506
1509static void intel_disable_sdvo(struct intel_encoder *encoder, 1507static void intel_disable_sdvo(struct intel_encoder *encoder,
1510 struct intel_crtc_state *old_crtc_state, 1508 const struct intel_crtc_state *old_crtc_state,
1511 struct drm_connector_state *conn_state) 1509 const struct drm_connector_state *conn_state)
1512{ 1510{
1513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1514 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1512 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
@@ -1552,21 +1550,21 @@ static void intel_disable_sdvo(struct intel_encoder *encoder,
1552} 1550}
1553 1551
1554static void pch_disable_sdvo(struct intel_encoder *encoder, 1552static void pch_disable_sdvo(struct intel_encoder *encoder,
1555 struct intel_crtc_state *old_crtc_state, 1553 const struct intel_crtc_state *old_crtc_state,
1556 struct drm_connector_state *old_conn_state) 1554 const struct drm_connector_state *old_conn_state)
1557{ 1555{
1558} 1556}
1559 1557
1560static void pch_post_disable_sdvo(struct intel_encoder *encoder, 1558static void pch_post_disable_sdvo(struct intel_encoder *encoder,
1561 struct intel_crtc_state *old_crtc_state, 1559 const struct intel_crtc_state *old_crtc_state,
1562 struct drm_connector_state *old_conn_state) 1560 const struct drm_connector_state *old_conn_state)
1563{ 1561{
1564 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state); 1562 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
1565} 1563}
1566 1564
1567static void intel_enable_sdvo(struct intel_encoder *encoder, 1565static void intel_enable_sdvo(struct intel_encoder *encoder,
1568 struct intel_crtc_state *pipe_config, 1566 const struct intel_crtc_state *pipe_config,
1569 struct drm_connector_state *conn_state) 1567 const struct drm_connector_state *conn_state)
1570{ 1568{
1571 struct drm_device *dev = encoder->base.dev; 1569 struct drm_device *dev = encoder->base.dev;
1572 struct drm_i915_private *dev_priv = to_i915(dev); 1570 struct drm_i915_private *dev_priv = to_i915(dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 524933b01483..b0d6e3e28d07 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -70,8 +70,7 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
70 70
71/** 71/**
72 * intel_pipe_update_start() - start update of a set of display registers 72 * intel_pipe_update_start() - start update of a set of display registers
73 * @crtc: the crtc of which the registers are going to be updated 73 * @new_crtc_state: the new crtc state
74 * @start_vbl_count: vblank counter return pointer used for error checking
75 * 74 *
76 * Mark the start of an update to pipe registers that should be updated 75 * Mark the start of an update to pipe registers that should be updated
77 * atomically regarding vblank. If the next vblank will happens within 76 * atomically regarding vblank. If the next vblank will happens within
@@ -79,18 +78,18 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
79 * 78 *
80 * After a successful call to this function, interrupts will be disabled 79 * After a successful call to this function, interrupts will be disabled
81 * until a subsequent call to intel_pipe_update_end(). That is done to 80 * until a subsequent call to intel_pipe_update_end(). That is done to
82 * avoid random delays. The value written to @start_vbl_count should be 81 * avoid random delays.
83 * supplied to intel_pipe_update_end() for error checking.
84 */ 82 */
85void intel_pipe_update_start(struct intel_crtc *crtc) 83void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
86{ 84{
85 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
87 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 86 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
88 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 87 const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
89 long timeout = msecs_to_jiffies_timeout(1); 88 long timeout = msecs_to_jiffies_timeout(1);
90 int scanline, min, max, vblank_start; 89 int scanline, min, max, vblank_start;
91 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 90 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
92 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 91 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
93 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI); 92 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
94 DEFINE_WAIT(wait); 93 DEFINE_WAIT(wait);
95 94
96 vblank_start = adjusted_mode->crtc_vblank_start; 95 vblank_start = adjusted_mode->crtc_vblank_start;
@@ -170,15 +169,15 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
170 169
171/** 170/**
172 * intel_pipe_update_end() - end update of a set of display registers 171 * intel_pipe_update_end() - end update of a set of display registers
173 * @crtc: the crtc of which the registers were updated 172 * @new_crtc_state: the new crtc state
174 * @start_vbl_count: start vblank counter (used for error checking)
175 * 173 *
176 * Mark the end of an update started with intel_pipe_update_start(). This 174 * Mark the end of an update started with intel_pipe_update_start(). This
177 * re-enables interrupts and verifies the update was actually completed 175 * re-enables interrupts and verifies the update was actually completed
178 * before a vblank using the value of @start_vbl_count. 176 * before a vblank.
179 */ 177 */
180void intel_pipe_update_end(struct intel_crtc *crtc) 178void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
181{ 179{
180 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
182 enum pipe pipe = crtc->pipe; 181 enum pipe pipe = crtc->pipe;
183 int scanline_end = intel_get_crtc_scanline(crtc); 182 int scanline_end = intel_get_crtc_scanline(crtc);
184 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); 183 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
@@ -191,14 +190,14 @@ void intel_pipe_update_end(struct intel_crtc *crtc)
191 * Would be slightly nice to just grab the vblank count and arm the 190 * Would be slightly nice to just grab the vblank count and arm the
192 * event outside of the critical section - the spinlock might spin for a 191 * event outside of the critical section - the spinlock might spin for a
193 * while ... */ 192 * while ... */
194 if (crtc->base.state->event) { 193 if (new_crtc_state->base.event) {
195 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); 194 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
196 195
197 spin_lock(&crtc->base.dev->event_lock); 196 spin_lock(&crtc->base.dev->event_lock);
198 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event); 197 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
199 spin_unlock(&crtc->base.dev->event_lock); 198 spin_unlock(&crtc->base.dev->event_lock);
200 199
201 crtc->base.state->event = NULL; 200 new_crtc_state->base.event = NULL;
202 } 201 }
203 202
204 local_irq_enable(); 203 local_irq_enable();
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 906893c006d8..0cc999fa09c5 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -814,8 +814,8 @@ intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
814 814
815static void 815static void
816intel_enable_tv(struct intel_encoder *encoder, 816intel_enable_tv(struct intel_encoder *encoder,
817 struct intel_crtc_state *pipe_config, 817 const struct intel_crtc_state *pipe_config,
818 struct drm_connector_state *conn_state) 818 const struct drm_connector_state *conn_state)
819{ 819{
820 struct drm_device *dev = encoder->base.dev; 820 struct drm_device *dev = encoder->base.dev;
821 struct drm_i915_private *dev_priv = to_i915(dev); 821 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -829,8 +829,8 @@ intel_enable_tv(struct intel_encoder *encoder,
829 829
830static void 830static void
831intel_disable_tv(struct intel_encoder *encoder, 831intel_disable_tv(struct intel_encoder *encoder,
832 struct intel_crtc_state *old_crtc_state, 832 const struct intel_crtc_state *old_crtc_state,
833 struct drm_connector_state *old_conn_state) 833 const struct drm_connector_state *old_conn_state)
834{ 834{
835 struct drm_device *dev = encoder->base.dev; 835 struct drm_device *dev = encoder->base.dev;
836 struct drm_i915_private *dev_priv = to_i915(dev); 836 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -838,7 +838,7 @@ intel_disable_tv(struct intel_encoder *encoder,
838 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); 838 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
839} 839}
840 840
841static const struct tv_mode *intel_tv_mode_find(struct drm_connector_state *conn_state) 841static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
842{ 842{
843 int format = conn_state->tv.mode; 843 int format = conn_state->tv.mode;
844 844
@@ -976,8 +976,8 @@ static void set_color_conversion(struct drm_i915_private *dev_priv,
976} 976}
977 977
978static void intel_tv_pre_enable(struct intel_encoder *encoder, 978static void intel_tv_pre_enable(struct intel_encoder *encoder,
979 struct intel_crtc_state *pipe_config, 979 const struct intel_crtc_state *pipe_config,
980 struct drm_connector_state *conn_state) 980 const struct drm_connector_state *conn_state)
981{ 981{
982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
983 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 983 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1d7b879cc68c..0529af7cfbb8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1251,7 +1251,7 @@ static const struct register_whitelist {
1251} whitelist[] = { 1251} whitelist[] = {
1252 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), 1252 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1253 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), 1253 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1254 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, 1254 .size = 8, .gen_bitmask = GEN_RANGE(4, 10) },
1255}; 1255};
1256 1256
1257int i915_reg_read_ioctl(struct drm_device *dev, 1257int i915_reg_read_ioctl(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index a92e7762f596..404569c9fdfc 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -149,16 +149,19 @@ struct bdb_general_features {
149 u8 ssc_freq:1; 149 u8 ssc_freq:1;
150 u8 enable_lfp_on_override:1; 150 u8 enable_lfp_on_override:1;
151 u8 disable_ssc_ddt:1; 151 u8 disable_ssc_ddt:1;
152 u8 rsvd7:1; 152 u8 underscan_vga_timings:1;
153 u8 display_clock_mode:1; 153 u8 display_clock_mode:1;
154 u8 rsvd8:1; /* finish byte */ 154 u8 vbios_hotplug_support:1;
155 155
156 /* bits 3 */ 156 /* bits 3 */
157 u8 disable_smooth_vision:1; 157 u8 disable_smooth_vision:1;
158 u8 single_dvi:1; 158 u8 single_dvi:1;
159 u8 rsvd9:1; 159 u8 rotate_180:1; /* 181 */
160 u8 fdi_rx_polarity_inverted:1; 160 u8 fdi_rx_polarity_inverted:1;
161 u8 rsvd10:4; /* finish byte */ 161 u8 vbios_extended_mode:1; /* 160 */
162 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */
163 u8 panel_best_fit_timing:1; /* 160 */
164 u8 ignore_strap_state:1; /* 160 */
162 165
163 /* bits 4 */ 166 /* bits 4 */
164 u8 legacy_monitor_detect; 167 u8 legacy_monitor_detect;
@@ -167,9 +170,10 @@ struct bdb_general_features {
167 u8 int_crt_support:1; 170 u8 int_crt_support:1;
168 u8 int_tv_support:1; 171 u8 int_tv_support:1;
169 u8 int_efp_support:1; 172 u8 int_efp_support:1;
170 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ 173 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */
171 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 174 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
172 u8 rsvd11:3; /* finish byte */ 175 u8 dp_ssc_dongle_supported:1;
176 u8 rsvd11:2; /* finish byte */
173} __packed; 177} __packed;
174 178
175/* pre-915 */ 179/* pre-915 */
@@ -206,6 +210,56 @@ struct bdb_general_features {
206#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 210#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
207#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 211#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
208 212
213/* Add the device class for LFP, TV, HDMI */
214#define DEVICE_TYPE_INT_LFP 0x1022
215#define DEVICE_TYPE_INT_TV 0x1009
216#define DEVICE_TYPE_HDMI 0x60D2
217#define DEVICE_TYPE_DP 0x68C6
218#define DEVICE_TYPE_DP_DUAL_MODE 0x60D6
219#define DEVICE_TYPE_eDP 0x78C6
220
221#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
222#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
223#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
224#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
225#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
226#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
227#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
228#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
229#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
230#define DEVICE_TYPE_LVDS_SINGALING (1 << 5)
231#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
232#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
233#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
234#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
235#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
236
237/*
238 * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
239 * system, the other bits may or may not be set for eDP outputs.
240 */
241#define DEVICE_TYPE_eDP_BITS \
242 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
243 DEVICE_TYPE_MIPI_OUTPUT | \
244 DEVICE_TYPE_COMPOSITE_OUTPUT | \
245 DEVICE_TYPE_DUAL_CHANNEL | \
246 DEVICE_TYPE_LVDS_SINGALING | \
247 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
248 DEVICE_TYPE_VIDEO_SIGNALING | \
249 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
250 DEVICE_TYPE_ANALOG_OUTPUT)
251
252#define DEVICE_TYPE_DP_DUAL_MODE_BITS \
253 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
254 DEVICE_TYPE_MIPI_OUTPUT | \
255 DEVICE_TYPE_COMPOSITE_OUTPUT | \
256 DEVICE_TYPE_LVDS_SINGALING | \
257 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
258 DEVICE_TYPE_VIDEO_SIGNALING | \
259 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
260 DEVICE_TYPE_DIGITAL_OUTPUT | \
261 DEVICE_TYPE_ANALOG_OUTPUT)
262
209#define DEVICE_CFG_NONE 0x00 263#define DEVICE_CFG_NONE 0x00
210#define DEVICE_CFG_12BIT_DVOB 0x01 264#define DEVICE_CFG_12BIT_DVOB 0x01
211#define DEVICE_CFG_12BIT_DVOC 0x02 265#define DEVICE_CFG_12BIT_DVOC 0x02
@@ -226,77 +280,126 @@ struct bdb_general_features {
226#define DEVICE_WIRE_DVOB_MASTER 0x0d 280#define DEVICE_WIRE_DVOB_MASTER 0x0d
227#define DEVICE_WIRE_DVOC_MASTER 0x0e 281#define DEVICE_WIRE_DVOC_MASTER 0x0e
228 282
283/* dvo_port pre BDB 155 */
229#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 284#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
230#define DEVICE_PORT_DVOB 0x01 285#define DEVICE_PORT_DVOB 0x01
231#define DEVICE_PORT_DVOC 0x02 286#define DEVICE_PORT_DVOC 0x02
232 287
288/* dvo_port BDB 155+ */
289#define DVO_PORT_HDMIA 0
290#define DVO_PORT_HDMIB 1
291#define DVO_PORT_HDMIC 2
292#define DVO_PORT_HDMID 3
293#define DVO_PORT_LVDS 4
294#define DVO_PORT_TV 5
295#define DVO_PORT_CRT 6
296#define DVO_PORT_DPB 7
297#define DVO_PORT_DPC 8
298#define DVO_PORT_DPD 9
299#define DVO_PORT_DPA 10
300#define DVO_PORT_DPE 11 /* 193 */
301#define DVO_PORT_HDMIE 12 /* 193 */
302#define DVO_PORT_MIPIA 21 /* 171 */
303#define DVO_PORT_MIPIB 22 /* 171 */
304#define DVO_PORT_MIPIC 23 /* 171 */
305#define DVO_PORT_MIPID 24 /* 171 */
306
307#define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33
308
233/* 309/*
234 * We used to keep this struct but without any version control. We should avoid 310 * The child device config, aka the display device data structure, provides a
235 * using it in the future, but it should be safe to keep using it in the old 311 * description of a port and its configuration on the platform.
236 * code. Do not change; we rely on its size. 312 *
313 * The child device config size has been increased, and fields have been added
314 * and their meaning has changed over time. Care must be taken when accessing
315 * basically any of the fields to ensure the correct interpretation for the BDB
316 * version in question.
317 *
318 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
319 * space for the full structure below, and initialize the tail not actually
320 * present in VBT to zeros. Accessing those fields is fine, as long as the
321 * default zero is taken into account, again according to the BDB version.
322 *
323 * BDB versions 155 and below are considered legacy, and version 155 seems to be
324 * a baseline for some of the VBT documentation. When adding new fields, please
325 * include the BDB version when the field was added, if it's above that.
237 */ 326 */
238struct old_child_dev_config { 327struct child_device_config {
239 u16 handle; 328 u16 handle;
240 u16 device_type; 329 u16 device_type; /* See DEVICE_TYPE_* above */
241 u8 device_id[10]; /* ascii string */ 330
242 u16 addin_offset; 331 union {
243 u8 dvo_port; /* See Device_PORT_* above */ 332 u8 device_id[10]; /* ascii string */
244 u8 i2c_pin; 333 struct {
245 u8 slave_addr; 334 u8 i2c_speed;
246 u8 ddc_pin; 335 u8 dp_onboard_redriver; /* 158 */
247 u16 edid_ptr; 336 u8 dp_ondock_redriver; /* 158 */
248 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 337 u8 hdmi_level_shifter_value:4; /* 169 */
249 u8 dvo2_port; 338 u8 hdmi_max_data_rate:4; /* 204 */
250 u8 i2c2_pin; 339 u16 dtd_buf_ptr; /* 161 */
251 u8 slave2_addr; 340 u8 edidless_efp:1; /* 161 */
252 u8 ddc2_pin; 341 u8 compression_enable:1; /* 198 */
253 u8 capabilities; 342 u8 compression_method:1; /* 198 */
254 u8 dvo_wiring;/* See DEVICE_WIRE_* above */ 343 u8 ganged_edp:1; /* 202 */
255 u8 dvo2_wiring; 344 u8 reserved0:4;
256 u16 extended_type; 345 u8 compression_structure_index:4; /* 198 */
257 u8 dvo_function; 346 u8 reserved1:4;
258} __packed; 347 u8 slave_port; /* 202 */
348 u8 reserved2;
349 } __packed;
350 } __packed;
259 351
260/* This one contains field offsets that are known to be common for all BDB 352 u16 addin_offset;
261 * versions. Notice that the meaning of the contents contents may still change, 353 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
262 * but at least the offsets are consistent. */ 354 u8 i2c_pin;
263 355 u8 slave_addr;
264struct common_child_dev_config {
265 u16 handle;
266 u16 device_type;
267 u8 not_common1[12];
268 u8 dvo_port;
269 u8 not_common2[2];
270 u8 ddc_pin; 356 u8 ddc_pin;
271 u16 edid_ptr; 357 u16 edid_ptr;
272 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 358 u8 dvo_cfg; /* See DEVICE_CFG_* above */
273 u8 efp_routed:1;
274 u8 lane_reversal:1;
275 u8 lspcon:1;
276 u8 iboost:1;
277 u8 hpd_invert:1;
278 u8 flag_reserved:3;
279 u8 hdmi_support:1;
280 u8 dp_support:1;
281 u8 tmds_support:1;
282 u8 support_reserved:5;
283 u8 aux_channel;
284 u8 not_common3[11];
285 u8 iboost_level;
286} __packed;
287 359
360 union {
361 struct {
362 u8 dvo2_port;
363 u8 i2c2_pin;
364 u8 slave2_addr;
365 u8 ddc2_pin;
366 } __packed;
367 struct {
368 u8 efp_routed:1; /* 158 */
369 u8 lane_reversal:1; /* 184 */
370 u8 lspcon:1; /* 192 */
371 u8 iboost:1; /* 196 */
372 u8 hpd_invert:1; /* 196 */
373 u8 flag_reserved:3;
374 u8 hdmi_support:1; /* 158 */
375 u8 dp_support:1; /* 158 */
376 u8 tmds_support:1; /* 158 */
377 u8 support_reserved:5;
378 u8 aux_channel;
379 u8 dongle_detect;
380 } __packed;
381 } __packed;
382
383 u8 pipe_cap:2;
384 u8 sdvo_stall:1; /* 158 */
385 u8 hpd_status:2;
386 u8 integrated_encoder:1;
387 u8 capabilities_reserved:2;
388 u8 dvo_wiring; /* See DEVICE_WIRE_* above */
389
390 union {
391 u8 dvo2_wiring;
392 u8 mipi_bridge_type; /* 171 */
393 } __packed;
288 394
289/* This field changes depending on the BDB version, so the most reliable way to 395 u16 extended_type;
290 * read it is by checking the BDB version and reading the raw pointer. */ 396 u8 dvo_function;
291union child_device_config { 397 u8 dp_usb_type_c:1; /* 195 */
292 /* This one is safe to be used anywhere, but the code should still check 398 u8 flags2_reserved:7; /* 195 */
293 * the BDB version. */ 399 u8 dp_gpio_index; /* 195 */
294 u8 raw[33]; 400 u16 dp_gpio_pin_num; /* 195 */
295 /* This one should only be kept for legacy code. */ 401 u8 dp_iboost_level:4; /* 196 */
296 struct old_child_dev_config old; 402 u8 hdmi_iboost_level:4; /* 196 */
297 /* This one should also be safe to use anywhere, even without version
298 * checks. */
299 struct common_child_dev_config common;
300} __packed; 403} __packed;
301 404
302struct bdb_general_definitions { 405struct bdb_general_definitions {
@@ -585,23 +688,38 @@ struct bdb_driver_features {
585#define EDP_VSWING_1_2V 3 688#define EDP_VSWING_1_2V 3
586 689
587 690
588struct edp_link_params { 691struct edp_fast_link_params {
589 u8 rate:4; 692 u8 rate:4;
590 u8 lanes:4; 693 u8 lanes:4;
591 u8 preemphasis:4; 694 u8 preemphasis:4;
592 u8 vswing:4; 695 u8 vswing:4;
593} __packed; 696} __packed;
594 697
698struct edp_pwm_delays {
699 u16 pwm_on_to_backlight_enable;
700 u16 backlight_disable_to_pwm_off;
701} __packed;
702
703struct edp_full_link_params {
704 u8 preemphasis:4;
705 u8 vswing:4;
706} __packed;
707
595struct bdb_edp { 708struct bdb_edp {
596 struct edp_power_seq power_seqs[16]; 709 struct edp_power_seq power_seqs[16];
597 u32 color_depth; 710 u32 color_depth;
598 struct edp_link_params link_params[16]; 711 struct edp_fast_link_params fast_link_params[16];
599 u32 sdrrs_msa_timing_delay; 712 u32 sdrrs_msa_timing_delay;
600 713
601 /* ith bit indicates enabled/disabled for (i+1)th panel */ 714 /* ith bit indicates enabled/disabled for (i+1)th panel */
602 u16 edp_s3d_feature; 715 u16 edp_s3d_feature; /* 162 */
603 u16 edp_t3_optimization; 716 u16 edp_t3_optimization; /* 165 */
604 u64 edp_vswing_preemph; /* v173 */ 717 u64 edp_vswing_preemph; /* 173 */
718 u16 fast_link_training; /* 182 */
719 u16 dpcd_600h_write_required; /* 185 */
720 struct edp_pwm_delays pwm_delays[16]; /* 186 */
721 u16 full_link_params_provided; /* 199 */
722 struct edp_full_link_params full_link_params[16]; /* 199 */
605} __packed; 723} __packed;
606 724
607struct psr_table { 725struct psr_table {
@@ -745,81 +863,6 @@ struct bdb_psr {
745#define SWF14_APM_STANDBY 0x1 863#define SWF14_APM_STANDBY 0x1
746#define SWF14_APM_RESTORE 0x0 864#define SWF14_APM_RESTORE 0x0
747 865
748/* Add the device class for LFP, TV, HDMI */
749#define DEVICE_TYPE_INT_LFP 0x1022
750#define DEVICE_TYPE_INT_TV 0x1009
751#define DEVICE_TYPE_HDMI 0x60D2
752#define DEVICE_TYPE_DP 0x68C6
753#define DEVICE_TYPE_DP_DUAL_MODE 0x60D6
754#define DEVICE_TYPE_eDP 0x78C6
755
756#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
757#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
758#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
759#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
760#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
761#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
762#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
763#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
764#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
765#define DEVICE_TYPE_LVDS_SINGALING (1 << 5)
766#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
767#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
768#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
769#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
770#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
771
772/*
773 * Bits we care about when checking for DEVICE_TYPE_eDP
774 * Depending on the system, the other bits may or may not
775 * be set for eDP outputs.
776 */
777#define DEVICE_TYPE_eDP_BITS \
778 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
779 DEVICE_TYPE_MIPI_OUTPUT | \
780 DEVICE_TYPE_COMPOSITE_OUTPUT | \
781 DEVICE_TYPE_DUAL_CHANNEL | \
782 DEVICE_TYPE_LVDS_SINGALING | \
783 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
784 DEVICE_TYPE_VIDEO_SIGNALING | \
785 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
786 DEVICE_TYPE_ANALOG_OUTPUT)
787
788#define DEVICE_TYPE_DP_DUAL_MODE_BITS \
789 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
790 DEVICE_TYPE_MIPI_OUTPUT | \
791 DEVICE_TYPE_COMPOSITE_OUTPUT | \
792 DEVICE_TYPE_LVDS_SINGALING | \
793 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
794 DEVICE_TYPE_VIDEO_SIGNALING | \
795 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
796 DEVICE_TYPE_DIGITAL_OUTPUT | \
797 DEVICE_TYPE_ANALOG_OUTPUT)
798
799/* define the DVO port for HDMI output type */
800#define DVO_B 1
801#define DVO_C 2
802#define DVO_D 3
803
804/* Possible values for the "DVO Port" field for versions >= 155: */
805#define DVO_PORT_HDMIA 0
806#define DVO_PORT_HDMIB 1
807#define DVO_PORT_HDMIC 2
808#define DVO_PORT_HDMID 3
809#define DVO_PORT_LVDS 4
810#define DVO_PORT_TV 5
811#define DVO_PORT_CRT 6
812#define DVO_PORT_DPB 7
813#define DVO_PORT_DPC 8
814#define DVO_PORT_DPD 9
815#define DVO_PORT_DPA 10
816#define DVO_PORT_DPE 11
817#define DVO_PORT_HDMIE 12
818#define DVO_PORT_MIPIA 21
819#define DVO_PORT_MIPIB 22
820#define DVO_PORT_MIPIC 23
821#define DVO_PORT_MIPID 24
822
823/* Block 52 contains MIPI configuration block 866/* Block 52 contains MIPI configuration block
824 * 6 * bdb_mipi_config, followed by 6 pps data block 867 * 6 * bdb_mipi_config, followed by 6 pps data block
825 * block below 868 * block below
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 34c8f5600ce0..1257e15c1a03 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -118,92 +118,125 @@
118#define INTEL_IRONLAKE_M_IDS(info) \ 118#define INTEL_IRONLAKE_M_IDS(info) \
119 INTEL_VGA_DEVICE(0x0046, info) 119 INTEL_VGA_DEVICE(0x0046, info)
120 120
121#define INTEL_SNB_D_IDS(info) \ 121#define INTEL_SNB_D_GT1_IDS(info) \
122 INTEL_VGA_DEVICE(0x0102, info), \ 122 INTEL_VGA_DEVICE(0x0102, info), \
123 INTEL_VGA_DEVICE(0x0112, info), \
124 INTEL_VGA_DEVICE(0x0122, info), \
125 INTEL_VGA_DEVICE(0x010A, info) 123 INTEL_VGA_DEVICE(0x010A, info)
126 124
127#define INTEL_SNB_M_IDS(info) \ 125#define INTEL_SNB_D_GT2_IDS(info) \
128 INTEL_VGA_DEVICE(0x0106, info), \ 126 INTEL_VGA_DEVICE(0x0112, info), \
127 INTEL_VGA_DEVICE(0x0122, info)
128
129#define INTEL_SNB_D_IDS(info) \
130 INTEL_SNB_D_GT1_IDS(info), \
131 INTEL_SNB_D_GT2_IDS(info)
132
133#define INTEL_SNB_M_GT1_IDS(info) \
134 INTEL_VGA_DEVICE(0x0106, info)
135
136#define INTEL_SNB_M_GT2_IDS(info) \
129 INTEL_VGA_DEVICE(0x0116, info), \ 137 INTEL_VGA_DEVICE(0x0116, info), \
130 INTEL_VGA_DEVICE(0x0126, info) 138 INTEL_VGA_DEVICE(0x0126, info)
131 139
140#define INTEL_SNB_M_IDS(info) \
141 INTEL_SNB_M_GT1_IDS(info), \
142 INTEL_SNB_M_GT2_IDS(info)
143
144#define INTEL_IVB_M_GT1_IDS(info) \
145 INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
146
147#define INTEL_IVB_M_GT2_IDS(info) \
148 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
149
132#define INTEL_IVB_M_IDS(info) \ 150#define INTEL_IVB_M_IDS(info) \
133 INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \ 151 INTEL_IVB_M_GT1_IDS(info), \
134 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ 152 INTEL_IVB_M_GT2_IDS(info)
135 153
136#define INTEL_IVB_D_IDS(info) \ 154#define INTEL_IVB_D_GT1_IDS(info) \
137 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ 155 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
156 INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */
157
158#define INTEL_IVB_D_GT2_IDS(info) \
138 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ 159 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
139 INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
140 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ 160 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
141 161
162#define INTEL_IVB_D_IDS(info) \
163 INTEL_IVB_D_GT1_IDS(info), \
164 INTEL_IVB_D_GT2_IDS(info)
165
142#define INTEL_IVB_Q_IDS(info) \ 166#define INTEL_IVB_Q_IDS(info) \
143 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ 167 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
144 168
145#define INTEL_HSW_IDS(info) \ 169#define INTEL_HSW_GT1_IDS(info) \
146 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ 170 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
147 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
148 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
149 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ 171 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
150 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
151 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
152 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ 172 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
153 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
154 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
155 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ 173 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
156 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
157 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
158 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ 174 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
159 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
160 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
161 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ 175 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
162 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
163 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
164 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ 176 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
165 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
166 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
167 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ 177 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
168 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
169 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
170 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ 178 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
171 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
172 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
173 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ 179 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
174 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
175 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
176 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ 180 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
177 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
178 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
179 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ 181 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
180 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
181 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
182 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ 182 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
183 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
184 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
185 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ 183 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
186 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
187 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
188 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ 184 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
189 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
190 INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
191 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ 185 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
186 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
187 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
188 INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
189 INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
190
191#define INTEL_HSW_GT2_IDS(info) \
192 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
193 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
194 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
195 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
196 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
197 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
198 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
199 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
200 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
201 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
202 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
203 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
204 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
205 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
206 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
192 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ 207 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
193 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ 208 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
194 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
195 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ 209 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
196 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
197 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
198 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ 210 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
199 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
200 INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
201 INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ 211 INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
212 INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
213
214#define INTEL_HSW_GT3_IDS(info) \
215 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
216 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
217 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
218 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
219 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
220 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
221 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
222 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
223 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
224 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
225 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
226 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
227 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
228 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
229 INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
230 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
231 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
202 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ 232 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
203 INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
204 INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
205 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ 233 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
206 234
235#define INTEL_HSW_IDS(info) \
236 INTEL_HSW_GT1_IDS(info), \
237 INTEL_HSW_GT2_IDS(info), \
238 INTEL_HSW_GT3_IDS(info)
239
207#define INTEL_VLV_IDS(info) \ 240#define INTEL_VLV_IDS(info) \
208 INTEL_VGA_DEVICE(0x0f30, info), \ 241 INTEL_VGA_DEVICE(0x0f30, info), \
209 INTEL_VGA_DEVICE(0x0f31, info), \ 242 INTEL_VGA_DEVICE(0x0f31, info), \
@@ -212,17 +245,19 @@
212 INTEL_VGA_DEVICE(0x0157, info), \ 245 INTEL_VGA_DEVICE(0x0157, info), \
213 INTEL_VGA_DEVICE(0x0155, info) 246 INTEL_VGA_DEVICE(0x0155, info)
214 247
215#define INTEL_BDW_GT12_IDS(info) \ 248#define INTEL_BDW_GT1_IDS(info) \
216 INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ 249 INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
217 INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ 250 INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
218 INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ 251 INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
219 INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ 252 INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
220 INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ 253 INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
254 INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
255
256#define INTEL_BDW_GT2_IDS(info) \
257 INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
221 INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ 258 INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
222 INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ 259 INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
223 INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ 260 INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
224 INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
225 INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
226 INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ 261 INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
227 INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ 262 INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
228 263
@@ -243,7 +278,8 @@
243 INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ 278 INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
244 279
245#define INTEL_BDW_IDS(info) \ 280#define INTEL_BDW_IDS(info) \
246 INTEL_BDW_GT12_IDS(info), \ 281 INTEL_BDW_GT1_IDS(info), \
282 INTEL_BDW_GT2_IDS(info), \
247 INTEL_BDW_GT3_IDS(info), \ 283 INTEL_BDW_GT3_IDS(info), \
248 INTEL_BDW_RSVD_IDS(info) 284 INTEL_BDW_RSVD_IDS(info)
249 285
@@ -335,20 +371,22 @@
335 INTEL_KBL_GT4_IDS(info) 371 INTEL_KBL_GT4_IDS(info)
336 372
337/* CFL S */ 373/* CFL S */
338#define INTEL_CFL_S_IDS(info) \ 374#define INTEL_CFL_S_GT1_IDS(info) \
339 INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \ 375 INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
340 INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \ 376 INTEL_VGA_DEVICE(0x3E93, info) /* SRV GT1 */
377
378#define INTEL_CFL_S_GT2_IDS(info) \
341 INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ 379 INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
342 INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ 380 INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
343 INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */ 381 INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */
344 382
345/* CFL H */ 383/* CFL H */
346#define INTEL_CFL_H_IDS(info) \ 384#define INTEL_CFL_H_GT2_IDS(info) \
347 INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ 385 INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
348 INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ 386 INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
349 387
350/* CFL U */ 388/* CFL U */
351#define INTEL_CFL_U_IDS(info) \ 389#define INTEL_CFL_U_GT3_IDS(info) \
352 INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \ 390 INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
353 INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ 391 INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
354 INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \ 392 INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6598fb76d2c2..d8d10d932759 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1509,9 +1509,9 @@ struct drm_i915_perf_oa_config {
1509 __u32 n_boolean_regs; 1509 __u32 n_boolean_regs;
1510 __u32 n_flex_regs; 1510 __u32 n_flex_regs;
1511 1511
1512 __u64 __user mux_regs_ptr; 1512 __u64 mux_regs_ptr;
1513 __u64 __user boolean_regs_ptr; 1513 __u64 boolean_regs_ptr;
1514 __u64 __user flex_regs_ptr; 1514 __u64 flex_regs_ptr;
1515}; 1515};
1516 1516
1517#if defined(__cplusplus) 1517#if defined(__cplusplus)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 13:15:54 -0400