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authorPeter Griffin <peter.griffin@linaro.org>2015-03-31 03:35:07 -0400
committerTejun Heo <tj@kernel.org>2015-04-01 12:07:02 -0400
commit9a8340bfeb03c5fc20b39aa533b164844ef582f9 (patch)
tree2b0aca95b8ed88ade0de7dea11c7c544558973f4
parentb6305d62234642a37fa1a68d15e741cfc3428c45 (diff)
ahci: st: Update the ahci_st DT documentation
As part of testing ahci_st driver working on stih407 I noticed several things wrong in the DT documentation: - 1) Compatible string doesn't match the driver code 2) pwr-rst reset isn't documented (but exists in the driver) 3) some whitespace issues (spaces not tabs) Also add in a stih407 family example into the doc. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Tejun Heo <tj@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/ata/ahci-st.txt45
1 files changed, 32 insertions, 13 deletions
diff --git a/Documentation/devicetree/bindings/ata/ahci-st.txt b/Documentation/devicetree/bindings/ata/ahci-st.txt
index 133120270066..e1d01df8e3c1 100644
--- a/Documentation/devicetree/bindings/ata/ahci-st.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-st.txt
@@ -3,29 +3,48 @@ STMicroelectronics STi SATA controller
3This binding describes a SATA device. 3This binding describes a SATA device.
4 4
5Required properties: 5Required properties:
6 - compatible : Must be "st,sti-ahci" 6 - compatible : Must be "st,ahci"
7 - reg : Physical base addresses and length of register sets 7 - reg : Physical base addresses and length of register sets
8 - interrupts : Interrupt associated with the SATA device 8 - interrupts : Interrupt associated with the SATA device
9 - interrupt-names : Associated name must be; "hostc" 9 - interrupt-names : Associated name must be; "hostc"
10 - resets : The power-down and soft-reset lines of SATA IP
11 - reset-names : Associated names must be; "pwr-dwn" and "sw-rst"
12 - clocks : The phandle for the clock 10 - clocks : The phandle for the clock
13 - clock-names : Associated name must be; "ahci_clk" 11 - clock-names : Associated name must be; "ahci_clk"
14 - phys : The phandle for the PHY port 12 - phys : The phandle for the PHY port
15 - phy-names : Associated name must be; "ahci_phy" 13 - phy-names : Associated name must be; "ahci_phy"
16 14
15Optional properties:
16 - resets : The power-down, soft-reset and power-reset lines of SATA IP
17 - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
18
17Example: 19Example:
18 20
21 /* Example for stih416 */
19 sata0: sata@fe380000 { 22 sata0: sata@fe380000 {
20 compatible = "st,sti-ahci"; 23 compatible = "st,ahci";
21 reg = <0xfe380000 0x1000>; 24 reg = <0xfe380000 0x1000>;
22 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; 25 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
23 interrupt-names = "hostc"; 26 interrupt-names = "hostc";
24 phys = <&phy_port0 PHY_TYPE_SATA>; 27 phys = <&phy_port0 PHY_TYPE_SATA>;
25 phy-names = "ahci_phy"; 28 phy-names = "ahci_phy";
26 resets = <&powerdown STIH416_SATA0_POWERDOWN>, 29 resets = <&powerdown STIH416_SATA0_POWERDOWN>,
27 <&softreset STIH416_SATA0_SOFTRESET>; 30 <&softreset STIH416_SATA0_SOFTRESET>;
28 reset-names = "pwr-dwn", "sw-rst"; 31 reset-names = "pwr-dwn", "sw-rst";
29 clocks = <&clk_s_a0_ls CLK_ICN_REG>; 32 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
30 clock-names = "ahci_clk"; 33 clock-names = "ahci_clk";
34 };
35
36 /* Example for stih407 family silicon */
37 sata0: sata@9b20000 {
38 compatible = "st,ahci";
39 reg = <0x9b20000 0x1000>;
40 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
41 interrupt-names = "hostc";
42 phys = <&phy_port0 PHY_TYPE_SATA>;
43 phy-names = "ahci_phy";
44 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
45 <&softreset STIH407_SATA0_SOFTRESET>,
46 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
47 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
48 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
49 clock-names = "ahci_clk";
31 }; 50 };