diff options
| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2017-09-28 10:06:33 -0400 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-10-02 09:58:31 -0400 |
| commit | 98f7d577c882be5a4e7403b3fdd1741d1baab6b5 (patch) | |
| tree | bfc3647c8dc30344bb1a5fe96690ec59e2f5a9f2 | |
| parent | 9e7460fc325dad06d2066abdbc1f4dd49456f9a4 (diff) | |
arm64: dts: marvell: fix interrupt-map property for Armada CP110 PCIe controller
The interrupt-map property used in the description of the Marvell
Armada 7K/8K PCIe controllers has a bogus extraneous 0 that causes the
interrupt conversion to not be done properly. This causes the PCIe PME
and AER root port service drivers to fail their initialization:
[ 5.019900] genirq: Setting trigger mode 7 for irq 114 failed (irq_chip_set_type_parent+0x0/0x30)
[ 5.028821] pcie_pme: probe of 0001:00:00.0:pcie001 failed with error -22
[ 5.035687] genirq: Setting trigger mode 7 for irq 114 failed (irq_chip_set_type_parent+0x0/0x30)
[ 5.044614] aer: probe of 0001:00:00.0:pcie002 failed with error -22
This problem was introduced when the interrupt description was
switched from using the GIC directly to using the ICU interrupt
controller. Indeed, the GIC has address-cells = <1>, which requires a
parent unit address, while the ICU has address-cells = <0>.
Fixes: 6ef84a827c37 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 8263a8a504a8..f2aa2a81de4d 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | |||
| @@ -336,7 +336,7 @@ | |||
| 336 | /* non-prefetchable memory */ | 336 | /* non-prefetchable memory */ |
| 337 | 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; | 337 | 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; |
| 338 | interrupt-map-mask = <0 0 0 0>; | 338 | interrupt-map-mask = <0 0 0 0>; |
| 339 | interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; | 339 | interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; |
| 340 | interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; | 340 | interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; |
| 341 | num-lanes = <1>; | 341 | num-lanes = <1>; |
| 342 | clocks = <&cpm_clk 1 13>; | 342 | clocks = <&cpm_clk 1 13>; |
| @@ -362,7 +362,7 @@ | |||
| 362 | /* non-prefetchable memory */ | 362 | /* non-prefetchable memory */ |
| 363 | 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; | 363 | 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; |
| 364 | interrupt-map-mask = <0 0 0 0>; | 364 | interrupt-map-mask = <0 0 0 0>; |
| 365 | interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; | 365 | interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; |
| 366 | interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; | 366 | interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; |
| 367 | 367 | ||
| 368 | num-lanes = <1>; | 368 | num-lanes = <1>; |
| @@ -389,7 +389,7 @@ | |||
| 389 | /* non-prefetchable memory */ | 389 | /* non-prefetchable memory */ |
| 390 | 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; | 390 | 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; |
| 391 | interrupt-map-mask = <0 0 0 0>; | 391 | interrupt-map-mask = <0 0 0 0>; |
| 392 | interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; | 392 | interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; |
| 393 | interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; | 393 | interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; |
| 394 | 394 | ||
| 395 | num-lanes = <1>; | 395 | num-lanes = <1>; |
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index b71ee6c83668..4fe70323abb3 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | |||
| @@ -335,7 +335,7 @@ | |||
| 335 | /* non-prefetchable memory */ | 335 | /* non-prefetchable memory */ |
| 336 | 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; | 336 | 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; |
| 337 | interrupt-map-mask = <0 0 0 0>; | 337 | interrupt-map-mask = <0 0 0 0>; |
| 338 | interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; | 338 | interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; |
| 339 | interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; | 339 | interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; |
| 340 | num-lanes = <1>; | 340 | num-lanes = <1>; |
| 341 | clocks = <&cps_clk 1 13>; | 341 | clocks = <&cps_clk 1 13>; |
| @@ -361,7 +361,7 @@ | |||
| 361 | /* non-prefetchable memory */ | 361 | /* non-prefetchable memory */ |
| 362 | 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; | 362 | 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; |
| 363 | interrupt-map-mask = <0 0 0 0>; | 363 | interrupt-map-mask = <0 0 0 0>; |
| 364 | interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; | 364 | interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; |
| 365 | interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; | 365 | interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; |
| 366 | 366 | ||
| 367 | num-lanes = <1>; | 367 | num-lanes = <1>; |
| @@ -388,7 +388,7 @@ | |||
| 388 | /* non-prefetchable memory */ | 388 | /* non-prefetchable memory */ |
| 389 | 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; | 389 | 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; |
| 390 | interrupt-map-mask = <0 0 0 0>; | 390 | interrupt-map-mask = <0 0 0 0>; |
| 391 | interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; | 391 | interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; |
| 392 | interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; | 392 | interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; |
| 393 | 393 | ||
| 394 | num-lanes = <1>; | 394 | num-lanes = <1>; |
