drm/amdgpu: don't load MEC2 on topaz

Not validated.

Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

2 files changed, 5 insertions, 11 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 39fa41bcae10..87c3332f45e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -111,7 +111,6 @@ MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
-MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
 
 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
@@ -828,7 +827,8 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
-        if (adev->asic_type != CHIP_STONEY) {
+        if ((adev->asic_type != CHIP_STONEY) &&
+            (adev->asic_type != CHIP_TOPAZ)) {
                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
                 if (!err) {
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
index 966d4b2ed9da..090486c18249 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
@@ -432,7 +432,7 @@ static uint32_t iceland_smu_get_mask_for_fw_type(uint32_t fw_type)
                 case AMDGPU_UCODE_ID_CP_ME:
                         return UCODE_ID_CP_ME_MASK;
                 case AMDGPU_UCODE_ID_CP_MEC1:
-                        return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK;
+                        return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK;
                 case AMDGPU_UCODE_ID_CP_MEC2:
                         return UCODE_ID_CP_MEC_MASK;
                 case AMDGPU_UCODE_ID_RLC_G:
@@ -522,12 +522,6 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
                 return -EINVAL;
         }
 
-        if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
-                        &toc->entry[toc->num_entries++])) {
-                DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
-                return -EINVAL;
-        }
-
         if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
                         &toc->entry[toc->num_entries++])) {
                 DRM_ERROR("Failed to get firmware entry for SDMA0\n");
@@ -550,8 +544,8 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
                         UCODE_ID_CP_ME_MASK |
                         UCODE_ID_CP_PFP_MASK |
                         UCODE_ID_CP_MEC_MASK |
-                        UCODE_ID_CP_MEC_JT1_MASK |
-                        UCODE_ID_CP_MEC_JT2_MASK;
+                        UCODE_ID_CP_MEC_JT1_MASK;
+
 
         if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
                 DRM_ERROR("Fail to request SMU load ucode\n");