Merge tag 'sunxi-core-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/soc

Allwinner core changes for 4.18

The A83t, unlike the other Allwinner SoCs, cannot use PSCI because of a
silicon bug. As such, we needed to have some smp_ops in order to bringup
the various cores (and clusters) found on this SoC.

* tag 'sunxi-core-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: sun8i: smp: Add support for A83T
  ARM: sun9i: smp: Add is_a83t field
  ARM: sun9i: smp: Rename clusters's power-off
  ARM: shmobile: Convert file to use cntvoff
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: smp: Move assembly code into a file
  ARM: Allow this header to be included by assembly files

Signed-off-by: Olof Johansson <olof@lixom.net>

11 files changed, 291 insertions, 120 deletions

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO)      += locomo.o
 obj-$(CONFIG_SHARP_PARAM)       += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)       += scoop.o
+obj-$(CONFIG_SMP)               += secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM)              += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
 CFLAGS_REMOVE_mcpm_entry.o      = -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index 000000000000..53fc7bdb6c2e
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(secure_cntvoff_init)
+        .arch   armv7-a
+        /*
+         * CNTVOFF has to be initialized either from non-secure Hypervisor
+         * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+         * then it should be handled by the secure code. The CPU must implement
+         * the virtualization extensions.
+         */
+        cps     #MON_MODE
+        mrc     p15, 0, r1, c1, c1, 0           /* Get Secure Config */
+        orr     r0, r1, #1
+        mcr     p15, 0, r0, c1, c1, 0           /* Set Non Secure bit */
+        isb
+        mov     r0, #0
+        mcrr    p15, 4, r0, r0, c14             /* CNTVOFF = 0 */
+        isb
+        mcr     p15, 0, r1, c1, c1, 0           /* Set Secure bit */
+        isb
+        cps     #SVC_MODE
+        ret     lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index 000000000000..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 43c1ac696274..2109f123bdfb 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-ENTRY(shmobile_init_cntvoff)
-        /*
-         * CNTVOFF has to be initialized either from non-secure Hypervisor
-         * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-         * then it should be handled by the secure code
-         */
-        cps     #MON_MODE
-        mrc     p15, 0, r1, c1, c1, 0           /* Get Secure Config */
-        orr     r0, r1, #1
-        mcr     p15, 0, r0, c1, c1, 0           /* Set Non Secure bit */
-        instr_sync
-        mov     r0, #0
-        mcrr    p15, 4, r0, r0, c14             /* CNTVOFF = 0 */
-        instr_sync
-        mcr     p15, 0, r1, c1, c1, 0           /* Set Secure bit */
-        instr_sync
-        cps     #SVC_MODE
-        ret     lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-        bl      shmobile_init_cntvoff
+        bl      secure_cntvoff_init
         b       secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include <linux/of_fdt.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
+#include <asm/secure_cntvoff.h>
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
         void __iomem *base;
         u32 freq;
 
-        shmobile_init_cntvoff();
+        secure_cntvoff_init();
 
         if (of_machine_is_compatible("renesas,r8a7745") ||
             of_machine_is_compatible("renesas,r8a7792") ||
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
         bool
         depends on SMP
-        default MACH_SUN9I
+        default MACH_SUN9I || MACH_SUN8I
         select ARM_CCI400_PORT_CTRL
         select ARM_CPU_SUSPEND
 
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..71429aa85143 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,5 @@
 CFLAGS_mc_smp.o += -march=armv7-a
 
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 000000000000..32d76be98541
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ * Mylène Josserand <mylene.josserand@bootlin.com>
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/cputype.h>
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+        .arch   armv7-a
+        /*
+         * Enable cluster-level coherency, in preparation for turning on the MMU.
+         *
+         * Also enable regional clock gating and L2 data latency settings for
+         * Cortex-A15. These settings are from the vendor kernel.
+         */
+        mrc     p15, 0, r1, c0, c0, 0
+        movw    r2, #(ARM_CPU_PART_MASK & 0xffff)
+        movt    r2, #(ARM_CPU_PART_MASK >> 16)
+        and     r1, r1, r2
+        movw    r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff)
+        movt    r2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+        cmp     r1, r2
+        bne     not_a15
+
+        /* The following is Cortex-A15 specific */
+
+        /* ACTLR2: Enable CPU regional clock gates */
+        mrc p15, 1, r1, c15, c0, 4
+        orr r1, r1, #(0x1 << 31)
+        mcr p15, 1, r1, c15, c0, 4
+
+        /* L2ACTLR */
+        mrc p15, 1, r1, c15, c0, 0
+        /* Enable L2, GIC, and Timer regional clock gates */
+        orr r1, r1, #(0x1 << 26)
+        /* Disable clean/evict from being pushed to external */
+        orr r1, r1, #(0x1<<3)
+        mcr p15, 1, r1, c15, c0, 0
+
+        /* L2CTRL: L2 data RAM latency */
+        mrc p15, 1, r1, c9, c0, 2
+        bic r1, r1, #(0x7 << 0)
+        orr r1, r1, #(0x3 << 0)
+        mcr p15, 1, r1, c9, c0, 2
+
+        /* End of Cortex-A15 specific setup */
+        not_a15:
+
+        /* Get value of sunxi_mc_smp_first_comer */
+        adr     r1, first
+        ldr     r0, [r1]
+        ldr     r0, [r1, r0]
+
+        /* Skip cci_enable_port_for_self if not first comer */
+        cmp     r0, #0
+        bxeq    lr
+        b       cci_enable_port_for_self
+
+        .align 2
+        first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+        bl      sunxi_mc_smp_cluster_cache_enable
+        bl      secure_cntvoff_init
+        b       secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+        bl      sunxi_mc_smp_cluster_cache_enable
+        b       cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..b4037b603897 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,35 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST       BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)    BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n)  BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL (0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)         (0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)    BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL   0xf
 #define PRCM_PWROFF_GATING_REG(c)       (0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER  BIT(4)
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I    BIT(0)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I    BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n)  BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)     (0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG         0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c) (0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)    BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG             0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC0     0xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC1     0x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
+
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+static bool is_a83t;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -157,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
         reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
         writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+        if (is_a83t) {
+                /* assert cpu power-on reset */
+                reg  = readl(r_cpucfg_base +
+                             R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+                reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+                writel(reg, r_cpucfg_base +
+                       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+                udelay(10);
+        }
+
         /* Cortex-A7: hold L1 reset disable signal low */
         if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
                 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -180,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
         /* open power switch */
         sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+        /* Handle A83T bit swap */
+        if (is_a83t) {
+                if (cpu == 0)
+                        cpu = 4;
+        }
+
         /* clear processor power gate */
         reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
         reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
         writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
         udelay(20);
 
+        /* Handle A83T bit swap */
+        if (is_a83t) {
+                if (cpu == 4)
+                        cpu = 0;
+        }
+
         /* de-assert processor power-on reset */
         reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
         reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
         writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+        if (is_a83t) {
+                reg  = readl(r_cpucfg_base +
+                             R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+                reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+                writel(reg, r_cpucfg_base +
+                       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+                udelay(10);
+        }
+
         /* de-assert all processor resets */
         reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
         reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -212,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
         if (cluster >= SUNXI_NR_CLUSTERS)
                 return -EINVAL;
 
+        /* For A83T, assert cluster cores resets */
+        if (is_a83t) {
+                reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+                reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;   /* Core Reset    */
+                writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+                udelay(10);
+        }
+
         /* assert ACINACTM */
         reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
         reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
@@ -222,6 +274,16 @@ static int sunxi_cluster_powerup(unsigned int cluster)
         reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL;
         writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+        /* assert cluster cores resets */
+        if (is_a83t) {
+                reg  = readl(r_cpucfg_base +
+                             R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+                reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;
+                writel(reg, r_cpucfg_base +
+                       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+                udelay(10);
+        }
+
         /* assert cluster resets */
         reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
         reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
@@ -252,7 +314,10 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
         /* clear cluster power gate */
         reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-        reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+        if (is_a83t)
+                reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
+        else
+                reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
         writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
         udelay(20);
 
@@ -300,74 +365,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-        asm volatile (
-                "mrc    p15, 0, r1, c0, c0, 0\n"
-                "movw   r2, #" __stringify(ARM_CPU_PART_MASK & 0xffff) "\n"
-                "movt   r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-                "and    r1, r1, r2\n"
-                "movw   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0xffff) "\n"
-                "movt   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 >> 16) "\n"
-                "cmp    r1, r2\n"
-                "bne    not_a15\n"
-
-                /* The following is Cortex-A15 specific */
-
-                /* ACTLR2: Enable CPU regional clock gates */
-                "mrc p15, 1, r1, c15, c0, 4\n"
-                "orr r1, r1, #(0x1<<31)\n"
-                "mcr p15, 1, r1, c15, c0, 4\n"
-
-                /* L2ACTLR */
-                "mrc p15, 1, r1, c15, c0, 0\n"
-                /* Enable L2, GIC, and Timer regional clock gates */
-                "orr r1, r1, #(0x1<<26)\n"
-                /* Disable clean/evict from being pushed to external */
-                "orr r1, r1, #(0x1<<3)\n"
-                "mcr p15, 1, r1, c15, c0, 0\n"
-
-                /* L2CTRL: L2 data RAM latency */
-                "mrc p15, 1, r1, c9, c0, 2\n"
-                "bic r1, r1, #(0x7<<0)\n"
-                "orr r1, r1, #(0x3<<0)\n"
-                "mcr p15, 1, r1, c9, c0, 2\n"
-
-                /* End of Cortex-A15 specific setup */
-                "not_a15:\n"
-
-                /* Get value of sunxi_mc_smp_first_comer */
-                "adr    r1, first\n"
-                "ldr    r0, [r1]\n"
-                "ldr    r0, [r1, r0]\n"
-
-                /* Skip cci_enable_port_for_self if not first comer */
-                "cmp    r0, #0\n"
-                "bxeq   lr\n"
-                "b      cci_enable_port_for_self\n"
-
-                ".align 2\n"
-                "first: .word sunxi_mc_smp_first_comer - .\n"
-        );
-}
-
-static void __naked sunxi_mc_smp_secondary_startup(void)
-{
-        asm volatile(
-                "bl     sunxi_mc_smp_cluster_cache_enable\n"
-                "b      secondary_startup"
-                /* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
-                :: "i" (sunxi_mc_smp_cluster_cache_enable)
-        );
-}
+int sunxi_mc_smp_first_comer;
 
 static DEFINE_SPINLOCK(boot_lock);
 
@@ -516,7 +514,10 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
         /* gate cluster power */
         pr_debug("%s: gate cluster power\n", __func__);
         reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-        reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+        if (is_a83t)
+                reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
+        else
+                reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
         writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
         udelay(20);
 
@@ -598,8 +599,12 @@ out:
         return !ret;
 }
 
-static bool sunxi_mc_smp_cpu_can_disable(unsigned int __unused)
+static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
 {
+        /* CPU0 hotplug not handled for sun8i-a83t */
+        if (is_a83t)
+                if (cpu == 0)
+                        return false;
         return true;
 }
 #endif
@@ -637,16 +642,6 @@ static bool __init sunxi_mc_smp_cpu_table_init(void)
  */
 typedef typeof(cpu_reset) phys_reset_t;
 
-static void __init __naked sunxi_mc_smp_resume(void)
-{
-        asm volatile(
-                "bl     sunxi_mc_smp_cluster_cache_enable\n"
-                "b      cpu_resume"
-                /* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
-                :: "i" (sunxi_mc_smp_cluster_cache_enable)
-        );
-}
-
 static int __init nocache_trampoline(unsigned long __unused)
 {
         phys_reset_t phys_reset;
@@ -692,12 +687,14 @@ struct sunxi_mc_smp_nodes {
         struct device_node *prcm_node;
         struct device_node *cpucfg_node;
         struct device_node *sram_node;
+        struct device_node *r_cpucfg_node;
 };
 
 /* This structure holds SoC-specific bits tied to an enable-method string. */
 struct sunxi_mc_smp_data {
         const char *enable_method;
         int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+        bool is_a83t;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -705,6 +702,7 @@ static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
         of_node_put(nodes->prcm_node);
         of_node_put(nodes->cpucfg_node);
         of_node_put(nodes->sram_node);
+        of_node_put(nodes->r_cpucfg_node);
         memset(nodes, 0, sizeof(*nodes));
 }
 
@@ -734,11 +732,42 @@ static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
         return 0;
 }
 
+static int __init sun8i_a83t_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
+{
+        nodes->prcm_node = of_find_compatible_node(NULL, NULL,
+                                                   "allwinner,sun8i-a83t-r-ccu");
+        if (!nodes->prcm_node) {
+                pr_err("%s: PRCM not available\n", __func__);
+                return -ENODEV;
+        }
+
+        nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
+                                                     "allwinner,sun8i-a83t-cpucfg");
+        if (!nodes->cpucfg_node) {
+                pr_err("%s: CPUCFG not available\n", __func__);
+                return -ENODEV;
+        }
+
+        nodes->r_cpucfg_node = of_find_compatible_node(NULL, NULL,
+                                                       "allwinner,sun8i-a83t-r-cpucfg");
+        if (!nodes->r_cpucfg_node) {
+                pr_err("%s: RCPUCFG not available\n", __func__);
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
 static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
         {
                 .enable_method  = "allwinner,sun9i-a80-smp",
                 .get_smp_nodes  = sun9i_a80_get_smp_nodes,
         },
+        {
+                .enable_method  = "allwinner,sun8i-a83t-smp",
+                .get_smp_nodes  = sun8i_a83t_get_smp_nodes,
+                .is_a83t        = true,
+        },
 };
 
 static int __init sunxi_mc_smp_init(void)
@@ -746,6 +775,7 @@ static int __init sunxi_mc_smp_init(void)
         struct sunxi_mc_smp_nodes nodes = { 0 };
         struct device_node *node;
         struct resource res;
+        void __iomem *addr;
         int i, ret;
 
         /*
@@ -771,6 +801,8 @@ static int __init sunxi_mc_smp_init(void)
                         break;
         }
 
+        is_a83t = sunxi_mc_smp_data[i].is_a83t;
+
         of_node_put(node);
         if (ret)
                 return -ENODEV;
@@ -808,12 +840,23 @@ static int __init sunxi_mc_smp_init(void)
                 goto err_unmap_prcm;
         }
 
-        sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
-                                                "sunxi-mc-smp");
-        if (IS_ERR(sram_b_smp_base)) {
-                ret = PTR_ERR(sram_b_smp_base);
-                pr_err("%s: failed to map secure SRAM\n", __func__);
-                goto err_unmap_release_cpucfg;
+        if (is_a83t) {
+                r_cpucfg_base = of_io_request_and_map(nodes.r_cpucfg_node,
+                                                      0, "sunxi-mc-smp");
+                if (IS_ERR(r_cpucfg_base)) {
+                        ret = PTR_ERR(r_cpucfg_base);
+                        pr_err("%s: failed to map R-CPUCFG registers\n",
+                               __func__);
+                        goto err_unmap_release_cpucfg;
+                }
+        } else {
+                sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
+                                                        "sunxi-mc-smp");
+                if (IS_ERR(sram_b_smp_base)) {
+                        ret = PTR_ERR(sram_b_smp_base);
+                        pr_err("%s: failed to map secure SRAM\n", __func__);
+                        goto err_unmap_release_cpucfg;
+                }
         }
 
         /* Configure CCI-400 for boot cluster */
@@ -821,15 +864,18 @@ static int __init sunxi_mc_smp_init(void)
         if (ret) {
                 pr_err("%s: failed to configure boot cluster: %d\n",
                        __func__, ret);
-                goto err_unmap_release_secure_sram;
+                goto err_unmap_release_sram_rcpucfg;
         }
 
         /* We don't need the device nodes anymore */
         sunxi_mc_smp_put_nodes(&nodes);
 
         /* Set the hardware entry point address */
-        writel(__pa_symbol(sunxi_mc_smp_secondary_startup),
-               prcm_base + PRCM_CPU_SOFT_ENTRY_REG);
+        if (is_a83t)
+                addr = r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG;
+        else
+                addr = prcm_base + PRCM_CPU_SOFT_ENTRY_REG;
+        writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr);
 
         /* Actually enable multi cluster SMP */
         smp_set_ops(&sunxi_mc_smp_smp_ops);
@@ -838,9 +884,14 @@ static int __init sunxi_mc_smp_init(void)
 
         return 0;
 
-err_unmap_release_secure_sram:
-        iounmap(sram_b_smp_base);
-        of_address_to_resource(nodes.sram_node, 0, &res);
+err_unmap_release_sram_rcpucfg:
+        if (is_a83t) {
+                iounmap(r_cpucfg_base);
+                of_address_to_resource(nodes.r_cpucfg_node, 0, &res);
+        } else {
+                iounmap(sram_b_smp_base);
+                of_address_to_resource(nodes.sram_node, 0, &res);
+        }
         release_mem_region(res.start, resource_size(&res));
 err_unmap_release_cpucfg:
         iounmap(cpucfg_base);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 5e9602ce1573..de4b0e932f22 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/mach/arch.h>
+#include <asm/secure_cntvoff.h>
 
 static const char * const sunxi_board_dt_compat[] = {
         "allwinner,sun4i-a10",
@@ -62,7 +63,6 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
         "allwinner,sun8i-a23",
         "allwinner,sun8i-a33",
-        "allwinner,sun8i-a83t",
         "allwinner,sun8i-h2-plus",
         "allwinner,sun8i-h3",
         "allwinner,sun8i-r40",
@@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
         .dt_compat      = sun8i_board_dt_compat,
 MACHINE_END
 
+static void __init sun8i_a83t_cntvoff_init(void)
+{
+#ifdef CONFIG_SMP
+        secure_cntvoff_init();
+#endif
+}
+
+static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
+        "allwinner,sun8i-a83t",
+        NULL,
+};
+
+DT_MACHINE_START(SUN8I_A83T_CNTVOFF_DT, "Allwinner A83t board")
+        .init_early     = sun8i_a83t_cntvoff_init,
+        .init_time      = sun6i_timer_init,
+        .dt_compat      = sun8i_a83t_cntvoff_board_dt_compat,
+MACHINE_END
+
 static const char * const sun9i_board_dt_compat[] = {
         "allwinner,sun9i-a80",
         NULL,