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authorStefan Agner <stefan@agner.ch>2016-07-26 02:42:35 -0400
committerShawn Guo <shawnguo@kernel.org>2016-08-15 07:46:24 -0400
commit974a3abcffaebc5ac9da03540f1bc5440f6ae7cf (patch)
treebf39c22ad5b63ef40e8bc0787cf91c62251b82fc
parent2a8e583c09c841744a6aa17d7247bc4fd5c6dfbf (diff)
ARM: dts: imx7d: move ARM platform peripherals inside soc node
Since we have a SoC level node we should make use of it and have all nodes which are within the SoC, inside that node. This also saves an extra interrupt-parent properties. While at it, also order the Coresight nodes according to register addresses. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat
-rw-r--r--arch/arm/boot/dts/imx7d.dtsi32
-rw-r--r--arch/arm/boot/dts/imx7s.dtsi301
2 files changed, 167 insertions, 166 deletions
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 51c13cbdffb7..3d77d95bbc9d 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -52,23 +52,25 @@
52 }; 52 };
53 }; 53 };
54 54
55 etm@3007d000 { 55 soc {
56 compatible = "arm,coresight-etm3x", "arm,primecell"; 56 etm@3007d000 {
57 reg = <0x3007d000 0x1000>; 57 compatible = "arm,coresight-etm3x", "arm,primecell";
58 reg = <0x3007d000 0x1000>;
58 59
59 /* 60 /*
60 * System will hang if added nosmp in kernel command line 61 * System will hang if added nosmp in kernel command line
61 * without arm,primecell-periphid because amba bus try to 62 * without arm,primecell-periphid because amba bus try to
62 * read id and core1 power off at this time. 63 * read id and core1 power off at this time.
63 */ 64 */
64 arm,primecell-periphid = <0xbb956>; 65 arm,primecell-periphid = <0xbb956>;
65 cpu = <&cpu1>; 66 cpu = <&cpu1>;
66 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 67 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
67 clock-names = "apb_pclk"; 68 clock-names = "apb_pclk";
68 69
69 port { 70 port {
70 etm1_out_port: endpoint { 71 etm1_out_port: endpoint {
71 remote-endpoint = <&ca_funnel_in_port1>; 72 remote-endpoint = <&ca_funnel_in_port1>;
73 };
72 }; 74 };
73 }; 75 };
74 }; 76 };
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 1e90bdbe3a6e..d89587a97725 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -95,16 +95,6 @@
95 }; 95 };
96 }; 96 };
97 97
98 intc: interrupt-controller@31001000 {
99 compatible = "arm,cortex-a7-gic";
100 #interrupt-cells = <3>;
101 interrupt-controller;
102 reg = <0x31001000 0x1000>,
103 <0x31002000 0x1000>,
104 <0x31004000 0x2000>,
105 <0x31006000 0x2000>;
106 };
107
108 ckil: clock-cki { 98 ckil: clock-cki {
109 compatible = "fixed-clock"; 99 compatible = "fixed-clock";
110 #clock-cells = <0>; 100 #clock-cells = <0>;
@@ -119,195 +109,204 @@
119 clock-output-names = "osc"; 109 clock-output-names = "osc";
120 }; 110 };
121 111
122 timer { 112 soc {
123 compatible = "arm,armv7-timer"; 113 #address-cells = <1>;
124 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 114 #size-cells = <1>;
125 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 115 compatible = "simple-bus";
126 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
128 interrupt-parent = <&intc>; 116 interrupt-parent = <&intc>;
129 }; 117 ranges;
130 118
131 etr@30086000 { 119 funnel@30041000 {
132 compatible = "arm,coresight-tmc", "arm,primecell"; 120 compatible = "arm,coresight-funnel", "arm,primecell";
133 reg = <0x30086000 0x1000>; 121 reg = <0x30041000 0x1000>;
134 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 122 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
135 clock-names = "apb_pclk"; 123 clock-names = "apb_pclk";
124
125 ca_funnel_ports: ports {
126 #address-cells = <1>;
127 #size-cells = <0>;
128
129 /* funnel input ports */
130 port@0 {
131 reg = <0>;
132 ca_funnel_in_port0: endpoint {
133 slave-mode;
134 remote-endpoint = <&etm0_out_port>;
135 };
136 };
137
138 /* funnel output port */
139 port@2 {
140 reg = <0>;
141 ca_funnel_out_port0: endpoint {
142 remote-endpoint = <&hugo_funnel_in_port0>;
143 };
144 };
136 145
137 port { 146 /* the other input ports are not connect to anything */
138 etr_in_port: endpoint {
139 slave-mode;
140 remote-endpoint = <&replicator_out_port1>;
141 }; 147 };
142 }; 148 };
143 };
144 149
145 tpiu@30087000 { 150 etm@3007c000 {
146 compatible = "arm,coresight-tpiu", "arm,primecell"; 151 compatible = "arm,coresight-etm3x", "arm,primecell";
147 reg = <0x30087000 0x1000>; 152 reg = <0x3007c000 0x1000>;
148 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 153 cpu = <&cpu0>;
149 clock-names = "apb_pclk"; 154 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
155 clock-names = "apb_pclk";
150 156
151 port { 157 port {
152 tpiu_in_port: endpoint { 158 etm0_out_port: endpoint {
153 slave-mode; 159 remote-endpoint = <&ca_funnel_in_port0>;
154 remote-endpoint = <&replicator_out_port1>; 160 };
155 }; 161 };
156 }; 162 };
157 };
158 163
159 replicator { 164 funnel@30083000 {
160 /* 165 compatible = "arm,coresight-funnel", "arm,primecell";
161 * non-configurable replicators don't show up on the 166 reg = <0x30083000 0x1000>;
162 * AMBA bus. As such no need to add "arm,primecell" 167 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
163 */ 168 clock-names = "apb_pclk";
164 compatible = "arm,coresight-replicator";
165 169
166 ports { 170 ports {
167 #address-cells = <1>; 171 #address-cells = <1>;
168 #size-cells = <0>; 172 #size-cells = <0>;
169 173
170 /* replicator output ports */ 174 /* funnel input ports */
171 port@0 { 175 port@0 {
172 reg = <0>; 176 reg = <0>;
173 replicator_out_port0: endpoint { 177 hugo_funnel_in_port0: endpoint {
174 remote-endpoint = <&tpiu_in_port>; 178 slave-mode;
179 remote-endpoint = <&ca_funnel_out_port0>;
180 };
175 }; 181 };
176 };
177 182
178 port@1 { 183 port@1 {
179 reg = <1>; 184 reg = <1>;
180 replicator_out_port1: endpoint { 185 hugo_funnel_in_port1: endpoint {
181 remote-endpoint = <&etr_in_port>; 186 slave-mode; /* M4 input */
187 };
182 }; 188 };
183 };
184 189
185 /* replicator input port */ 190 port@2 {
186 port@2 { 191 reg = <0>;
187 reg = <0>; 192 hugo_funnel_out_port0: endpoint {
188 replicator_in_port0: endpoint { 193 remote-endpoint = <&etf_in_port>;
189 slave-mode; 194 };
190 remote-endpoint = <&etf_out_port>;
191 }; 195 };
196
197 /* the other input ports are not connect to anything */
192 }; 198 };
193 }; 199 };
194 };
195 200
196 etf@30084000 { 201 etf@30084000 {
197 compatible = "arm,coresight-tmc", "arm,primecell"; 202 compatible = "arm,coresight-tmc", "arm,primecell";
198 reg = <0x30084000 0x1000>; 203 reg = <0x30084000 0x1000>;
199 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 204 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
200 clock-names = "apb_pclk"; 205 clock-names = "apb_pclk";
201 206
202 ports { 207 ports {
203 #address-cells = <1>; 208 #address-cells = <1>;
204 #size-cells = <0>; 209 #size-cells = <0>;
205 210
206 port@0 { 211 port@0 {
207 reg = <0>; 212 reg = <0>;
208 etf_in_port: endpoint { 213 etf_in_port: endpoint {
209 slave-mode; 214 slave-mode;
210 remote-endpoint = <&hugo_funnel_out_port0>; 215 remote-endpoint = <&hugo_funnel_out_port0>;
216 };
211 }; 217 };
212 };
213 218
214 port@1 { 219 port@1 {
215 reg = <0>; 220 reg = <0>;
216 etf_out_port: endpoint { 221 etf_out_port: endpoint {
217 remote-endpoint = <&replicator_in_port0>; 222 remote-endpoint = <&replicator_in_port0>;
223 };
218 }; 224 };
219 }; 225 };
220 }; 226 };
221 };
222 227
223 funnel@30083000 { 228 etr@30086000 {
224 compatible = "arm,coresight-funnel", "arm,primecell"; 229 compatible = "arm,coresight-tmc", "arm,primecell";
225 reg = <0x30083000 0x1000>; 230 reg = <0x30086000 0x1000>;
226 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 231 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
227 clock-names = "apb_pclk"; 232 clock-names = "apb_pclk";
228
229 ports {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 233
233 /* funnel input ports */ 234 port {
234 port@0 { 235 etr_in_port: endpoint {
235 reg = <0>;
236 hugo_funnel_in_port0: endpoint {
237 slave-mode; 236 slave-mode;
238 remote-endpoint = <&ca_funnel_out_port0>; 237 remote-endpoint = <&replicator_out_port1>;
239 }; 238 };
240 }; 239 };
240 };
241 241
242 port@1 { 242 tpiu@30087000 {
243 reg = <1>; 243 compatible = "arm,coresight-tpiu", "arm,primecell";
244 hugo_funnel_in_port1: endpoint { 244 reg = <0x30087000 0x1000>;
245 slave-mode; /* M4 input */ 245 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
246 }; 246 clock-names = "apb_pclk";
247 };
248 247
249 port@2 { 248 port {
250 reg = <0>; 249 tpiu_in_port: endpoint {
251 hugo_funnel_out_port0: endpoint { 250 slave-mode;
252 remote-endpoint = <&etf_in_port>; 251 remote-endpoint = <&replicator_out_port1>;
253 }; 252 };
254 }; 253 };
255
256 /* the other input ports are not connect to anything */
257 }; 254 };
258 };
259 255
260 funnel@30041000 { 256 replicator {
261 compatible = "arm,coresight-funnel", "arm,primecell"; 257 /*
262 reg = <0x30041000 0x1000>; 258 * non-configurable replicators don't show up on the
263 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 259 * AMBA bus. As such no need to add "arm,primecell"
264 clock-names = "apb_pclk"; 260 */
261 compatible = "arm,coresight-replicator";
265 262
266 ca_funnel_ports: ports { 263 ports {
267 #address-cells = <1>; 264 #address-cells = <1>;
268 #size-cells = <0>; 265 #size-cells = <0>;
269 266
270 /* funnel input ports */ 267 /* replicator output ports */
271 port@0 { 268 port@0 {
272 reg = <0>; 269 reg = <0>;
273 ca_funnel_in_port0: endpoint { 270 replicator_out_port0: endpoint {
274 slave-mode; 271 remote-endpoint = <&tpiu_in_port>;
275 remote-endpoint = <&etm0_out_port>; 272 };
276 }; 273 };
277 };
278 274
279 /* funnel output port */ 275 port@1 {
280 port@2 { 276 reg = <1>;
281 reg = <0>; 277 replicator_out_port1: endpoint {
282 ca_funnel_out_port0: endpoint { 278 remote-endpoint = <&etr_in_port>;
283 remote-endpoint = <&hugo_funnel_in_port0>; 279 };
284 }; 280 };
285 };
286 281
287 /* the other input ports are not connect to anything */ 282 /* replicator input port */
283 port@2 {
284 reg = <0>;
285 replicator_in_port0: endpoint {
286 slave-mode;
287 remote-endpoint = <&etf_out_port>;
288 };
289 };
290 };
288 }; 291 };
289 };
290 292
291 etm@3007c000 { 293 intc: interrupt-controller@31001000 {
292 compatible = "arm,coresight-etm3x", "arm,primecell"; 294 compatible = "arm,cortex-a7-gic";
293 reg = <0x3007c000 0x1000>; 295 #interrupt-cells = <3>;
294 cpu = <&cpu0>; 296 interrupt-controller;
295 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 297 reg = <0x31001000 0x1000>,
296 clock-names = "apb_pclk"; 298 <0x31002000 0x1000>,
297 299 <0x31004000 0x2000>,
298 port { 300 <0x31006000 0x2000>;
299 etm0_out_port: endpoint {
300 remote-endpoint = <&ca_funnel_in_port0>;
301 };
302 }; 301 };
303 };
304 302
305 soc { 303 timer {
306 #address-cells = <1>; 304 compatible = "arm,armv7-timer";
307 #size-cells = <1>; 305 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
308 compatible = "simple-bus"; 306 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
309 interrupt-parent = <&intc>; 307 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
310 ranges; 308 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
309 };
311 310
312 aips1: aips-bus@30000000 { 311 aips1: aips-bus@30000000 {
313 compatible = "fsl,aips-bus", "simple-bus"; 312 compatible = "fsl,aips-bus", "simple-bus";
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