drm/i915/gvt: ignore unexpected pvinfo write

There is pvinfo writing come from vgpu might be unexpected, like
writing to one unknown address, GVT-g should do as reserved register
to discard any invalid write. Now GVT-g lets it write to the vreg
without prompt error message, should ignore the unexpected pvinfo
write access and leave the vreg as the default value.

For possible guest query GVT-g host feature, this returned proper
value instead of wrong guest setting.

v2: ignore unexpected pvinfo write instead of return predefined value

Fixes: e39c5add3221 ("drm/i915/gvt: vGPU MMIO virtualization")
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Weinan Li <weinan.z.li@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

1 files changed, 9 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index a6ade66349bd..25f78196b964 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1254,18 +1254,15 @@ static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
                 void *p_data, unsigned int bytes)
 {
-        u32 data;
-        int ret;
-
-        write_vreg(vgpu, offset, p_data, bytes);
-        data = vgpu_vreg(vgpu, offset);
+        u32 data = *(u32 *)p_data;
+        bool invalid_write = false;
 
         switch (offset) {
         case _vgtif_reg(display_ready):
                 send_display_ready_uevent(vgpu, data ? 1 : 0);
                 break;
         case _vgtif_reg(g2v_notify):
-                ret = handle_g2v_notification(vgpu, data);
+                handle_g2v_notification(vgpu, data);
                 break;
         /* add xhot and yhot to handled list to avoid error log */
         case _vgtif_reg(cursor_x_hot):
@@ -1282,13 +1279,19 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
         case _vgtif_reg(execlist_context_descriptor_hi):
                 break;
         case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
+                invalid_write = true;
                 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
                 break;
         default:
+                invalid_write = true;
                 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
                                 offset, bytes, data);
                 break;
         }
+
+        if (!invalid_write)
+                write_vreg(vgpu, offset, p_data, bytes);
+
         return 0;
 }