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authorBen Skeggs <bskeggs@redhat.com>2015-08-20 00:54:22 -0400
committerBen Skeggs <bskeggs@redhat.com>2015-08-27 22:40:47 -0400
commit97070f23c60869830039b216ff88230f54ef7107 (patch)
tree7f30048bec45520e755d940f68f6e35d686708e7
parentc85ee6ca79590cd51356bf24fb8936bc352138cf (diff)
drm/nouveau/pm: convert to new-style nvkm_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h23
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c88
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c9
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c14
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c80
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c69
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h15
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c23
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c23
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c23
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c51
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c69
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h29
21 files changed, 219 insertions, 400 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
index c67cea6aae4d..240855ad8c8d 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
@@ -1,11 +1,9 @@
1#ifndef __NVKM_PM_H__ 1#ifndef __NVKM_PM_H__
2#define __NVKM_PM_H__ 2#define __NVKM_PM_H__
3#define nvkm_pm(p) container_of((p), struct nvkm_pm, engine)
4#include <core/engine.h> 3#include <core/engine.h>
5 4
6struct nvkm_perfdom;
7struct nvkm_perfctr;
8struct nvkm_pm { 5struct nvkm_pm {
6 const struct nvkm_pm_func *func;
9 struct nvkm_engine engine; 7 struct nvkm_engine engine;
10 8
11 struct nvkm_object *perfmon; 9 struct nvkm_object *perfmon;
@@ -15,14 +13,13 @@ struct nvkm_pm {
15 u32 sequence; 13 u32 sequence;
16}; 14};
17 15
18extern struct nvkm_oclass *nv40_pm_oclass; 16int nv40_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
19extern struct nvkm_oclass *nv50_pm_oclass; 17int nv50_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
20extern struct nvkm_oclass *g84_pm_oclass; 18int g84_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
21extern struct nvkm_oclass *gt200_pm_oclass; 19int gt200_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
22extern struct nvkm_oclass *gt215_pm_oclass; 20int gt215_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
23extern struct nvkm_oclass *gf100_pm_oclass; 21int gf100_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
24extern struct nvkm_oclass *gf108_pm_oclass; 22int gf108_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
25extern struct nvkm_oclass *gf117_pm_oclass; 23int gf117_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
26extern struct nvkm_oclass *gk104_pm_oclass; 24int gk104_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
27extern struct nvkm_oclass gk110_pm_oclass;
28#endif 25#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 3cf15d46f9d2..c954ae4189a9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -471,7 +471,7 @@ nv40_chipset = {
471 .fifo = nv40_fifo_new, 471 .fifo = nv40_fifo_new,
472 .gr = nv40_gr_new, 472 .gr = nv40_gr_new,
473// .mpeg = nv40_mpeg_new, 473// .mpeg = nv40_mpeg_new,
474// .pm = nv40_pm_new, 474 .pm = nv40_pm_new,
475// .sw = nv10_sw_new, 475// .sw = nv10_sw_new,
476}; 476};
477 477
@@ -496,7 +496,7 @@ nv41_chipset = {
496 .fifo = nv40_fifo_new, 496 .fifo = nv40_fifo_new,
497 .gr = nv40_gr_new, 497 .gr = nv40_gr_new,
498// .mpeg = nv40_mpeg_new, 498// .mpeg = nv40_mpeg_new,
499// .pm = nv40_pm_new, 499 .pm = nv40_pm_new,
500// .sw = nv10_sw_new, 500// .sw = nv10_sw_new,
501}; 501};
502 502
@@ -521,7 +521,7 @@ nv42_chipset = {
521 .fifo = nv40_fifo_new, 521 .fifo = nv40_fifo_new,
522 .gr = nv40_gr_new, 522 .gr = nv40_gr_new,
523// .mpeg = nv40_mpeg_new, 523// .mpeg = nv40_mpeg_new,
524// .pm = nv40_pm_new, 524 .pm = nv40_pm_new,
525// .sw = nv10_sw_new, 525// .sw = nv10_sw_new,
526}; 526};
527 527
@@ -546,7 +546,7 @@ nv43_chipset = {
546 .fifo = nv40_fifo_new, 546 .fifo = nv40_fifo_new,
547 .gr = nv40_gr_new, 547 .gr = nv40_gr_new,
548// .mpeg = nv40_mpeg_new, 548// .mpeg = nv40_mpeg_new,
549// .pm = nv40_pm_new, 549 .pm = nv40_pm_new,
550// .sw = nv10_sw_new, 550// .sw = nv10_sw_new,
551}; 551};
552 552
@@ -571,7 +571,7 @@ nv44_chipset = {
571 .fifo = nv40_fifo_new, 571 .fifo = nv40_fifo_new,
572 .gr = nv44_gr_new, 572 .gr = nv44_gr_new,
573// .mpeg = nv44_mpeg_new, 573// .mpeg = nv44_mpeg_new,
574// .pm = nv40_pm_new, 574 .pm = nv40_pm_new,
575// .sw = nv10_sw_new, 575// .sw = nv10_sw_new,
576}; 576};
577 577
@@ -596,7 +596,7 @@ nv45_chipset = {
596 .fifo = nv40_fifo_new, 596 .fifo = nv40_fifo_new,
597 .gr = nv40_gr_new, 597 .gr = nv40_gr_new,
598// .mpeg = nv44_mpeg_new, 598// .mpeg = nv44_mpeg_new,
599// .pm = nv40_pm_new, 599 .pm = nv40_pm_new,
600// .sw = nv10_sw_new, 600// .sw = nv10_sw_new,
601}; 601};
602 602
@@ -621,7 +621,7 @@ nv46_chipset = {
621 .fifo = nv40_fifo_new, 621 .fifo = nv40_fifo_new,
622 .gr = nv44_gr_new, 622 .gr = nv44_gr_new,
623// .mpeg = nv44_mpeg_new, 623// .mpeg = nv44_mpeg_new,
624// .pm = nv40_pm_new, 624 .pm = nv40_pm_new,
625// .sw = nv10_sw_new, 625// .sw = nv10_sw_new,
626}; 626};
627 627
@@ -646,7 +646,7 @@ nv47_chipset = {
646 .fifo = nv40_fifo_new, 646 .fifo = nv40_fifo_new,
647 .gr = nv40_gr_new, 647 .gr = nv40_gr_new,
648// .mpeg = nv44_mpeg_new, 648// .mpeg = nv44_mpeg_new,
649// .pm = nv40_pm_new, 649 .pm = nv40_pm_new,
650// .sw = nv10_sw_new, 650// .sw = nv10_sw_new,
651}; 651};
652 652
@@ -671,7 +671,7 @@ nv49_chipset = {
671 .fifo = nv40_fifo_new, 671 .fifo = nv40_fifo_new,
672 .gr = nv40_gr_new, 672 .gr = nv40_gr_new,
673// .mpeg = nv44_mpeg_new, 673// .mpeg = nv44_mpeg_new,
674// .pm = nv40_pm_new, 674 .pm = nv40_pm_new,
675// .sw = nv10_sw_new, 675// .sw = nv10_sw_new,
676}; 676};
677 677
@@ -696,7 +696,7 @@ nv4a_chipset = {
696 .fifo = nv40_fifo_new, 696 .fifo = nv40_fifo_new,
697 .gr = nv44_gr_new, 697 .gr = nv44_gr_new,
698// .mpeg = nv44_mpeg_new, 698// .mpeg = nv44_mpeg_new,
699// .pm = nv40_pm_new, 699 .pm = nv40_pm_new,
700// .sw = nv10_sw_new, 700// .sw = nv10_sw_new,
701}; 701};
702 702
@@ -721,7 +721,7 @@ nv4b_chipset = {
721 .fifo = nv40_fifo_new, 721 .fifo = nv40_fifo_new,
722 .gr = nv40_gr_new, 722 .gr = nv40_gr_new,
723// .mpeg = nv44_mpeg_new, 723// .mpeg = nv44_mpeg_new,
724// .pm = nv40_pm_new, 724 .pm = nv40_pm_new,
725// .sw = nv10_sw_new, 725// .sw = nv10_sw_new,
726}; 726};
727 727
@@ -746,7 +746,7 @@ nv4c_chipset = {
746 .fifo = nv40_fifo_new, 746 .fifo = nv40_fifo_new,
747 .gr = nv44_gr_new, 747 .gr = nv44_gr_new,
748// .mpeg = nv44_mpeg_new, 748// .mpeg = nv44_mpeg_new,
749// .pm = nv40_pm_new, 749 .pm = nv40_pm_new,
750// .sw = nv10_sw_new, 750// .sw = nv10_sw_new,
751}; 751};
752 752
@@ -771,7 +771,7 @@ nv4e_chipset = {
771 .fifo = nv40_fifo_new, 771 .fifo = nv40_fifo_new,
772 .gr = nv44_gr_new, 772 .gr = nv44_gr_new,
773// .mpeg = nv44_mpeg_new, 773// .mpeg = nv44_mpeg_new,
774// .pm = nv40_pm_new, 774 .pm = nv40_pm_new,
775// .sw = nv10_sw_new, 775// .sw = nv10_sw_new,
776}; 776};
777 777
@@ -799,7 +799,7 @@ nv50_chipset = {
799 .fifo = nv50_fifo_new, 799 .fifo = nv50_fifo_new,
800 .gr = nv50_gr_new, 800 .gr = nv50_gr_new,
801// .mpeg = nv50_mpeg_new, 801// .mpeg = nv50_mpeg_new,
802// .pm = nv50_pm_new, 802 .pm = nv50_pm_new,
803// .sw = nv50_sw_new, 803// .sw = nv50_sw_new,
804}; 804};
805 805
@@ -824,7 +824,7 @@ nv63_chipset = {
824 .fifo = nv40_fifo_new, 824 .fifo = nv40_fifo_new,
825 .gr = nv44_gr_new, 825 .gr = nv44_gr_new,
826// .mpeg = nv44_mpeg_new, 826// .mpeg = nv44_mpeg_new,
827// .pm = nv40_pm_new, 827 .pm = nv40_pm_new,
828// .sw = nv10_sw_new, 828// .sw = nv10_sw_new,
829}; 829};
830 830
@@ -849,7 +849,7 @@ nv67_chipset = {
849 .fifo = nv40_fifo_new, 849 .fifo = nv40_fifo_new,
850 .gr = nv44_gr_new, 850 .gr = nv44_gr_new,
851// .mpeg = nv44_mpeg_new, 851// .mpeg = nv44_mpeg_new,
852// .pm = nv40_pm_new, 852 .pm = nv40_pm_new,
853// .sw = nv10_sw_new, 853// .sw = nv10_sw_new,
854}; 854};
855 855
@@ -874,7 +874,7 @@ nv68_chipset = {
874 .fifo = nv40_fifo_new, 874 .fifo = nv40_fifo_new,
875 .gr = nv44_gr_new, 875 .gr = nv44_gr_new,
876// .mpeg = nv44_mpeg_new, 876// .mpeg = nv44_mpeg_new,
877// .pm = nv40_pm_new, 877 .pm = nv40_pm_new,
878// .sw = nv10_sw_new, 878// .sw = nv10_sw_new,
879}; 879};
880 880
@@ -904,7 +904,7 @@ nv84_chipset = {
904 .fifo = g84_fifo_new, 904 .fifo = g84_fifo_new,
905 .gr = g84_gr_new, 905 .gr = g84_gr_new,
906// .mpeg = g84_mpeg_new, 906// .mpeg = g84_mpeg_new,
907// .pm = g84_pm_new, 907 .pm = g84_pm_new,
908// .sw = nv50_sw_new, 908// .sw = nv50_sw_new,
909 .vp = g84_vp_new, 909 .vp = g84_vp_new,
910}; 910};
@@ -935,7 +935,7 @@ nv86_chipset = {
935 .fifo = g84_fifo_new, 935 .fifo = g84_fifo_new,
936 .gr = g84_gr_new, 936 .gr = g84_gr_new,
937// .mpeg = g84_mpeg_new, 937// .mpeg = g84_mpeg_new,
938// .pm = g84_pm_new, 938 .pm = g84_pm_new,
939// .sw = nv50_sw_new, 939// .sw = nv50_sw_new,
940 .vp = g84_vp_new, 940 .vp = g84_vp_new,
941}; 941};
@@ -966,7 +966,7 @@ nv92_chipset = {
966 .fifo = g84_fifo_new, 966 .fifo = g84_fifo_new,
967 .gr = g84_gr_new, 967 .gr = g84_gr_new,
968// .mpeg = g84_mpeg_new, 968// .mpeg = g84_mpeg_new,
969// .pm = g84_pm_new, 969 .pm = g84_pm_new,
970// .sw = nv50_sw_new, 970// .sw = nv50_sw_new,
971 .vp = g84_vp_new, 971 .vp = g84_vp_new,
972}; 972};
@@ -997,7 +997,7 @@ nv94_chipset = {
997 .fifo = g84_fifo_new, 997 .fifo = g84_fifo_new,
998 .gr = g84_gr_new, 998 .gr = g84_gr_new,
999// .mpeg = g84_mpeg_new, 999// .mpeg = g84_mpeg_new,
1000// .pm = g84_pm_new, 1000 .pm = g84_pm_new,
1001// .sw = nv50_sw_new, 1001// .sw = nv50_sw_new,
1002 .vp = g84_vp_new, 1002 .vp = g84_vp_new,
1003}; 1003};
@@ -1030,7 +1030,7 @@ nv96_chipset = {
1030 .cipher = g84_cipher_new, 1030 .cipher = g84_cipher_new,
1031 .bsp = g84_bsp_new, 1031 .bsp = g84_bsp_new,
1032 .disp = g94_disp_new, 1032 .disp = g94_disp_new,
1033// .pm = g84_pm_new, 1033 .pm = g84_pm_new,
1034}; 1034};
1035 1035
1036static const struct nvkm_device_chip 1036static const struct nvkm_device_chip
@@ -1061,7 +1061,7 @@ nv98_chipset = {
1061 .msvld = g98_msvld_new, 1061 .msvld = g98_msvld_new,
1062 .msppp = g98_msppp_new, 1062 .msppp = g98_msppp_new,
1063 .disp = g94_disp_new, 1063 .disp = g94_disp_new,
1064// .pm = g84_pm_new, 1064 .pm = g84_pm_new,
1065}; 1065};
1066 1066
1067static const struct nvkm_device_chip 1067static const struct nvkm_device_chip
@@ -1090,7 +1090,7 @@ nva0_chipset = {
1090 .fifo = g84_fifo_new, 1090 .fifo = g84_fifo_new,
1091 .gr = gt200_gr_new, 1091 .gr = gt200_gr_new,
1092// .mpeg = g84_mpeg_new, 1092// .mpeg = g84_mpeg_new,
1093// .pm = gt200_pm_new, 1093 .pm = gt200_pm_new,
1094// .sw = nv50_sw_new, 1094// .sw = nv50_sw_new,
1095 .vp = g84_vp_new, 1095 .vp = g84_vp_new,
1096}; 1096};
@@ -1124,7 +1124,7 @@ nva3_chipset = {
1124 .mspdec = gt215_mspdec_new, 1124 .mspdec = gt215_mspdec_new,
1125 .msppp = gt215_msppp_new, 1125 .msppp = gt215_msppp_new,
1126 .msvld = gt215_msvld_new, 1126 .msvld = gt215_msvld_new,
1127// .pm = gt215_pm_new, 1127 .pm = gt215_pm_new,
1128// .sw = nv50_sw_new, 1128// .sw = nv50_sw_new,
1129}; 1129};
1130 1130
@@ -1156,7 +1156,7 @@ nva5_chipset = {
1156 .mspdec = gt215_mspdec_new, 1156 .mspdec = gt215_mspdec_new,
1157 .msppp = gt215_msppp_new, 1157 .msppp = gt215_msppp_new,
1158 .msvld = gt215_msvld_new, 1158 .msvld = gt215_msvld_new,
1159// .pm = gt215_pm_new, 1159 .pm = gt215_pm_new,
1160// .sw = nv50_sw_new, 1160// .sw = nv50_sw_new,
1161}; 1161};
1162 1162
@@ -1188,7 +1188,7 @@ nva8_chipset = {
1188 .mspdec = gt215_mspdec_new, 1188 .mspdec = gt215_mspdec_new,
1189 .msppp = gt215_msppp_new, 1189 .msppp = gt215_msppp_new,
1190 .msvld = gt215_msvld_new, 1190 .msvld = gt215_msvld_new,
1191// .pm = gt215_pm_new, 1191 .pm = gt215_pm_new,
1192// .sw = nv50_sw_new, 1192// .sw = nv50_sw_new,
1193}; 1193};
1194 1194
@@ -1218,7 +1218,7 @@ nvaa_chipset = {
1218 .mspdec = g98_mspdec_new, 1218 .mspdec = g98_mspdec_new,
1219 .msppp = g98_msppp_new, 1219 .msppp = g98_msppp_new,
1220 .msvld = g98_msvld_new, 1220 .msvld = g98_msvld_new,
1221// .pm = g84_pm_new, 1221 .pm = g84_pm_new,
1222 .sec = g98_sec_new, 1222 .sec = g98_sec_new,
1223// .sw = nv50_sw_new, 1223// .sw = nv50_sw_new,
1224}; 1224};
@@ -1249,7 +1249,7 @@ nvac_chipset = {
1249 .mspdec = g98_mspdec_new, 1249 .mspdec = g98_mspdec_new,
1250 .msppp = g98_msppp_new, 1250 .msppp = g98_msppp_new,
1251 .msvld = g98_msvld_new, 1251 .msvld = g98_msvld_new,
1252// .pm = g84_pm_new, 1252 .pm = g84_pm_new,
1253 .sec = g98_sec_new, 1253 .sec = g98_sec_new,
1254// .sw = nv50_sw_new, 1254// .sw = nv50_sw_new,
1255}; 1255};
@@ -1282,7 +1282,7 @@ nvaf_chipset = {
1282 .mspdec = gt215_mspdec_new, 1282 .mspdec = gt215_mspdec_new,
1283 .msppp = gt215_msppp_new, 1283 .msppp = gt215_msppp_new,
1284 .msvld = mcp89_msvld_new, 1284 .msvld = mcp89_msvld_new,
1285// .pm = gt215_pm_new, 1285 .pm = gt215_pm_new,
1286// .sw = nv50_sw_new, 1286// .sw = nv50_sw_new,
1287}; 1287};
1288 1288
@@ -1317,7 +1317,7 @@ nvc0_chipset = {
1317 .mspdec = gf100_mspdec_new, 1317 .mspdec = gf100_mspdec_new,
1318 .msppp = gf100_msppp_new, 1318 .msppp = gf100_msppp_new,
1319 .msvld = gf100_msvld_new, 1319 .msvld = gf100_msvld_new,
1320// .pm = gf100_pm_new, 1320 .pm = gf100_pm_new,
1321// .sw = gf100_sw_new, 1321// .sw = gf100_sw_new,
1322}; 1322};
1323 1323
@@ -1351,7 +1351,7 @@ nvc1_chipset = {
1351 .mspdec = gf100_mspdec_new, 1351 .mspdec = gf100_mspdec_new,
1352 .msppp = gf100_msppp_new, 1352 .msppp = gf100_msppp_new,
1353 .msvld = gf100_msvld_new, 1353 .msvld = gf100_msvld_new,
1354// .pm = gf108_pm_new, 1354 .pm = gf108_pm_new,
1355// .sw = gf100_sw_new, 1355// .sw = gf100_sw_new,
1356}; 1356};
1357 1357
@@ -1385,7 +1385,7 @@ nvc3_chipset = {
1385 .mspdec = gf100_mspdec_new, 1385 .mspdec = gf100_mspdec_new,
1386 .msppp = gf100_msppp_new, 1386 .msppp = gf100_msppp_new,
1387 .msvld = gf100_msvld_new, 1387 .msvld = gf100_msvld_new,
1388// .pm = gf100_pm_new, 1388 .pm = gf100_pm_new,
1389// .sw = gf100_sw_new, 1389// .sw = gf100_sw_new,
1390}; 1390};
1391 1391
@@ -1420,7 +1420,7 @@ nvc4_chipset = {
1420 .mspdec = gf100_mspdec_new, 1420 .mspdec = gf100_mspdec_new,
1421 .msppp = gf100_msppp_new, 1421 .msppp = gf100_msppp_new,
1422 .msvld = gf100_msvld_new, 1422 .msvld = gf100_msvld_new,
1423// .pm = gf100_pm_new, 1423 .pm = gf100_pm_new,
1424// .sw = gf100_sw_new, 1424// .sw = gf100_sw_new,
1425}; 1425};
1426 1426
@@ -1455,7 +1455,7 @@ nvc8_chipset = {
1455 .mspdec = gf100_mspdec_new, 1455 .mspdec = gf100_mspdec_new,
1456 .msppp = gf100_msppp_new, 1456 .msppp = gf100_msppp_new,
1457 .msvld = gf100_msvld_new, 1457 .msvld = gf100_msvld_new,
1458// .pm = gf100_pm_new, 1458 .pm = gf100_pm_new,
1459// .sw = gf100_sw_new, 1459// .sw = gf100_sw_new,
1460}; 1460};
1461 1461
@@ -1490,7 +1490,7 @@ nvce_chipset = {
1490 .mspdec = gf100_mspdec_new, 1490 .mspdec = gf100_mspdec_new,
1491 .msppp = gf100_msppp_new, 1491 .msppp = gf100_msppp_new,
1492 .msvld = gf100_msvld_new, 1492 .msvld = gf100_msvld_new,
1493// .pm = gf100_pm_new, 1493 .pm = gf100_pm_new,
1494// .sw = gf100_sw_new, 1494// .sw = gf100_sw_new,
1495}; 1495};
1496 1496
@@ -1524,7 +1524,7 @@ nvcf_chipset = {
1524 .mspdec = gf100_mspdec_new, 1524 .mspdec = gf100_mspdec_new,
1525 .msppp = gf100_msppp_new, 1525 .msppp = gf100_msppp_new,
1526 .msvld = gf100_msvld_new, 1526 .msvld = gf100_msvld_new,
1527// .pm = gf100_pm_new, 1527 .pm = gf100_pm_new,
1528// .sw = gf100_sw_new, 1528// .sw = gf100_sw_new,
1529}; 1529};
1530 1530
@@ -1556,7 +1556,7 @@ nvd7_chipset = {
1556 .mspdec = gf100_mspdec_new, 1556 .mspdec = gf100_mspdec_new,
1557 .msppp = gf100_msppp_new, 1557 .msppp = gf100_msppp_new,
1558 .msvld = gf100_msvld_new, 1558 .msvld = gf100_msvld_new,
1559// .pm = gf117_pm_new, 1559 .pm = gf117_pm_new,
1560// .sw = gf100_sw_new, 1560// .sw = gf100_sw_new,
1561}; 1561};
1562 1562
@@ -1590,7 +1590,7 @@ nvd9_chipset = {
1590 .mspdec = gf100_mspdec_new, 1590 .mspdec = gf100_mspdec_new,
1591 .msppp = gf100_msppp_new, 1591 .msppp = gf100_msppp_new,
1592 .msvld = gf100_msvld_new, 1592 .msvld = gf100_msvld_new,
1593// .pm = gf117_pm_new, 1593 .pm = gf117_pm_new,
1594// .sw = gf100_sw_new, 1594// .sw = gf100_sw_new,
1595}; 1595};
1596 1596
@@ -1626,7 +1626,7 @@ nve4_chipset = {
1626 .mspdec = gk104_mspdec_new, 1626 .mspdec = gk104_mspdec_new,
1627 .msppp = gf100_msppp_new, 1627 .msppp = gf100_msppp_new,
1628 .msvld = gk104_msvld_new, 1628 .msvld = gk104_msvld_new,
1629// .pm = gk104_pm_new, 1629 .pm = gk104_pm_new,
1630// .sw = gf100_sw_new, 1630// .sw = gf100_sw_new,
1631}; 1631};
1632 1632
@@ -1662,7 +1662,7 @@ nve6_chipset = {
1662 .mspdec = gk104_mspdec_new, 1662 .mspdec = gk104_mspdec_new,
1663 .msppp = gf100_msppp_new, 1663 .msppp = gf100_msppp_new,
1664 .msvld = gk104_msvld_new, 1664 .msvld = gk104_msvld_new,
1665// .pm = gk104_pm_new, 1665 .pm = gk104_pm_new,
1666// .sw = gf100_sw_new, 1666// .sw = gf100_sw_new,
1667}; 1667};
1668 1668
@@ -1698,7 +1698,7 @@ nve7_chipset = {
1698 .mspdec = gk104_mspdec_new, 1698 .mspdec = gk104_mspdec_new,
1699 .msppp = gf100_msppp_new, 1699 .msppp = gf100_msppp_new,
1700 .msvld = gk104_msvld_new, 1700 .msvld = gk104_msvld_new,
1701// .pm = gk104_pm_new, 1701 .pm = gk104_pm_new,
1702// .sw = gf100_sw_new, 1702// .sw = gf100_sw_new,
1703}; 1703};
1704 1704
@@ -1722,7 +1722,7 @@ nvea_chipset = {
1722 .dma = gf119_dma_new, 1722 .dma = gf119_dma_new,
1723 .fifo = gk20a_fifo_new, 1723 .fifo = gk20a_fifo_new,
1724 .gr = gk20a_gr_new, 1724 .gr = gk20a_gr_new,
1725// .pm = gk104_pm_new, 1725 .pm = gk104_pm_new,
1726// .sw = gf100_sw_new, 1726// .sw = gf100_sw_new,
1727}; 1727};
1728 1728
@@ -1758,7 +1758,6 @@ nvf0_chipset = {
1758 .mspdec = gk104_mspdec_new, 1758 .mspdec = gk104_mspdec_new,
1759 .msppp = gf100_msppp_new, 1759 .msppp = gf100_msppp_new,
1760 .msvld = gk104_msvld_new, 1760 .msvld = gk104_msvld_new,
1761// .pm = gk110_pm_new,
1762// .sw = gf100_sw_new, 1761// .sw = gf100_sw_new,
1763}; 1762};
1764 1763
@@ -1794,7 +1793,6 @@ nvf1_chipset = {
1794 .mspdec = gk104_mspdec_new, 1793 .mspdec = gk104_mspdec_new,
1795 .msppp = gf100_msppp_new, 1794 .msppp = gf100_msppp_new,
1796 .msvld = gk104_msvld_new, 1795 .msvld = gk104_msvld_new,
1797// .pm = gk110_pm_new,
1798// .sw = gf100_sw_new, 1796// .sw = gf100_sw_new,
1799}; 1797};
1800 1798
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
index b88aceb343c8..67faff5d0b52 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
@@ -29,39 +29,30 @@ gf100_identify(struct nvkm_device *device)
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0xc0: 30 case 0xc0:
31 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
32 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
33 break; 32 break;
34 case 0xc4: 33 case 0xc4:
35 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 34 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
36 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
37 break; 35 break;
38 case 0xc3: 36 case 0xc3:
39 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 37 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
40 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
41 break; 38 break;
42 case 0xce: 39 case 0xce:
43 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 40 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
44 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
45 break; 41 break;
46 case 0xcf: 42 case 0xcf:
47 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 43 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
48 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
49 break; 44 break;
50 case 0xc1: 45 case 0xc1:
51 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 46 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
52 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
53 break; 47 break;
54 case 0xc8: 48 case 0xc8:
55 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 49 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
56 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
57 break; 50 break;
58 case 0xd9: 51 case 0xd9:
59 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 52 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
60 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
61 break; 53 break;
62 case 0xd7: 54 case 0xd7:
63 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 55 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
64 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
65 break; 56 break;
66 default: 57 default:
67 return -EINVAL; 58 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
index 1ad7b217e2b8..3841dc0ac01b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
@@ -29,27 +29,21 @@ gk104_identify(struct nvkm_device *device)
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0xe4: 30 case 0xe4:
31 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
32 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
33 break; 32 break;
34 case 0xe7: 33 case 0xe7:
35 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 34 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
36 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
37 break; 35 break;
38 case 0xe6: 36 case 0xe6:
39 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 37 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
40 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
41 break; 38 break;
42 case 0xea: 39 case 0xea:
43 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 40 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
44 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
45 break; 41 break;
46 case 0xf0: 42 case 0xf0:
47 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 43 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
48 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
49 break; 44 break;
50 case 0xf1: 45 case 0xf1:
51 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 46 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
52 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
53 break; 47 break;
54 case 0x106: 48 case 0x106:
55 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 49 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index e3fdbf6ba871..08c015b0e5a1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -30,82 +30,66 @@ nv40_identify(struct nvkm_device *device)
30 case 0x40: 30 case 0x40:
31 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
32 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 32 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
33 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
34 break; 33 break;
35 case 0x41: 34 case 0x41:
36 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 35 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
37 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 36 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
38 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
39 break; 37 break;
40 case 0x42: 38 case 0x42:
41 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 39 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
42 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 40 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
43 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
44 break; 41 break;
45 case 0x43: 42 case 0x43:
46 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 43 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
47 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 44 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
48 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
49 break; 45 break;
50 case 0x45: 46 case 0x45:
51 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 47 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
52 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 48 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
53 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
54 break; 49 break;
55 case 0x47: 50 case 0x47:
56 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 51 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
57 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 52 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
58 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
59 break; 53 break;
60 case 0x49: 54 case 0x49:
61 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 55 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
62 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 56 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
63 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
64 break; 57 break;
65 case 0x4b: 58 case 0x4b:
66 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 59 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
67 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 60 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
68 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
69 break; 61 break;
70 case 0x44: 62 case 0x44:
71 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 63 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
72 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 64 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
73 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
74 break; 65 break;
75 case 0x46: 66 case 0x46:
76 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 67 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
77 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 68 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
78 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
79 break; 69 break;
80 case 0x4a: 70 case 0x4a:
81 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 71 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
82 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 72 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
83 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
84 break; 73 break;
85 case 0x4c: 74 case 0x4c:
86 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 75 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
87 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 76 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
88 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
89 break; 77 break;
90 case 0x4e: 78 case 0x4e:
91 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 79 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
92 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 80 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
93 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
94 break; 81 break;
95 case 0x63: 82 case 0x63:
96 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
97 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 84 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
98 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
99 break; 85 break;
100 case 0x67: 86 case 0x67:
101 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 87 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
102 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 88 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
103 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
104 break; 89 break;
105 case 0x68: 90 case 0x68:
106 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 91 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
107 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 92 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
108 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
109 break; 93 break;
110 default: 94 default:
111 return -EINVAL; 95 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 912bd8070db7..c285f61ffd8f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -30,66 +30,52 @@ nv50_identify(struct nvkm_device *device)
30 case 0x50: 30 case 0x50:
31 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 31 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
32 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; 32 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
33 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
34 break; 33 break;
35 case 0x84: 34 case 0x84:
36 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 35 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
37 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 36 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
38 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
39 break; 37 break;
40 case 0x86: 38 case 0x86:
41 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 39 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
42 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 40 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
43 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
44 break; 41 break;
45 case 0x92: 42 case 0x92:
46 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 43 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
47 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 44 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
48 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
49 break; 45 break;
50 case 0x94: 46 case 0x94:
51 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 47 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
52 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 48 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
53 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
54 break; 49 break;
55 case 0x96: 50 case 0x96:
56 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 51 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
57 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 52 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
58 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
59 break; 53 break;
60 case 0x98: 54 case 0x98:
61 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 55 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
62 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
63 break; 56 break;
64 case 0xa0: 57 case 0xa0:
65 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 58 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
66 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 59 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
67 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
68 break; 60 break;
69 case 0xaa: 61 case 0xaa:
70 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 62 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
71 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
72 break; 63 break;
73 case 0xac: 64 case 0xac:
74 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 65 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
75 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
76 break; 66 break;
77 case 0xa3: 67 case 0xa3:
78 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 68 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
79 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; 69 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
80 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
81 break; 70 break;
82 case 0xa5: 71 case 0xa5:
83 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 72 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
84 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
85 break; 73 break;
86 case 0xa8: 74 case 0xa8:
87 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 75 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
88 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
89 break; 76 break;
90 case 0xaf: 77 case 0xaf:
91 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 78 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
92 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
93 break; 79 break;
94 default: 80 default:
95 return -EINVAL; 81 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
index 4fadf55f51f9..1614d385fb0c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
@@ -8,4 +8,3 @@ nvkm-y += nvkm/engine/pm/gf100.o
8nvkm-y += nvkm/engine/pm/gf108.o 8nvkm-y += nvkm/engine/pm/gf108.o
9nvkm-y += nvkm/engine/pm/gf117.o 9nvkm-y += nvkm/engine/pm/gf117.o
10nvkm-y += nvkm/engine/pm/gk104.o 10nvkm-y += nvkm/engine/pm/gk104.o
11nvkm-y += nvkm/engine/pm/gk110.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
index 5b4ab63809be..0db9be202c42 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
@@ -203,13 +203,13 @@ nvkm_perfsrc_disable(struct nvkm_pm *pm, struct nvkm_perfctr *ctr)
203 * Perfdom object classes 203 * Perfdom object classes
204 ******************************************************************************/ 204 ******************************************************************************/
205static int 205static int
206nvkm_perfdom_init(struct nvkm_object *object, void *data, u32 size) 206nvkm_perfdom_init(struct nvkm_perfdom *dom, void *data, u32 size)
207{ 207{
208 union { 208 union {
209 struct nvif_perfdom_init none; 209 struct nvif_perfdom_init none;
210 } *args = data; 210 } *args = data;
211 struct nvkm_pm *pm = (void *)object->engine; 211 struct nvkm_object *object = &dom->object;
212 struct nvkm_perfdom *dom = (void *)object; 212 struct nvkm_pm *pm = dom->perfmon->pm;
213 int ret, i; 213 int ret, i;
214 214
215 nvif_ioctl(object, "perfdom init size %d\n", size); 215 nvif_ioctl(object, "perfdom init size %d\n", size);
@@ -233,13 +233,13 @@ nvkm_perfdom_init(struct nvkm_object *object, void *data, u32 size)
233} 233}
234 234
235static int 235static int
236nvkm_perfdom_sample(struct nvkm_object *object, void *data, u32 size) 236nvkm_perfdom_sample(struct nvkm_perfdom *dom, void *data, u32 size)
237{ 237{
238 union { 238 union {
239 struct nvif_perfdom_sample none; 239 struct nvif_perfdom_sample none;
240 } *args = data; 240 } *args = data;
241 struct nvkm_pm *pm = (void *)object->engine; 241 struct nvkm_object *object = &dom->object;
242 struct nvkm_perfdom *dom; 242 struct nvkm_pm *pm = dom->perfmon->pm;
243 int ret; 243 int ret;
244 244
245 nvif_ioctl(object, "perfdom sample size %d\n", size); 245 nvif_ioctl(object, "perfdom sample size %d\n", size);
@@ -257,13 +257,13 @@ nvkm_perfdom_sample(struct nvkm_object *object, void *data, u32 size)
257} 257}
258 258
259static int 259static int
260nvkm_perfdom_read(struct nvkm_object *object, void *data, u32 size) 260nvkm_perfdom_read(struct nvkm_perfdom *dom, void *data, u32 size)
261{ 261{
262 union { 262 union {
263 struct nvif_perfdom_read_v0 v0; 263 struct nvif_perfdom_read_v0 v0;
264 } *args = data; 264 } *args = data;
265 struct nvkm_pm *pm = (void *)object->engine; 265 struct nvkm_object *object = &dom->object;
266 struct nvkm_perfdom *dom = (void *)object; 266 struct nvkm_pm *pm = dom->perfmon->pm;
267 int ret, i; 267 int ret, i;
268 268
269 nvif_ioctl(object, "perfdom read size %d\n", size); 269 nvif_ioctl(object, "perfdom read size %d\n", size);
@@ -290,13 +290,14 @@ nvkm_perfdom_read(struct nvkm_object *object, void *data, u32 size)
290static int 290static int
291nvkm_perfdom_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 291nvkm_perfdom_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
292{ 292{
293 struct nvkm_perfdom *dom = nvkm_perfdom(object);
293 switch (mthd) { 294 switch (mthd) {
294 case NVIF_PERFDOM_V0_INIT: 295 case NVIF_PERFDOM_V0_INIT:
295 return nvkm_perfdom_init(object, data, size); 296 return nvkm_perfdom_init(dom, data, size);
296 case NVIF_PERFDOM_V0_SAMPLE: 297 case NVIF_PERFDOM_V0_SAMPLE:
297 return nvkm_perfdom_sample(object, data, size); 298 return nvkm_perfdom_sample(dom, data, size);
298 case NVIF_PERFDOM_V0_READ: 299 case NVIF_PERFDOM_V0_READ:
299 return nvkm_perfdom_read(object, data, size); 300 return nvkm_perfdom_read(dom, data, size);
300 default: 301 default:
301 break; 302 break;
302 } 303 }
@@ -304,9 +305,9 @@ nvkm_perfdom_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
304} 305}
305 306
306static void * 307static void *
307nvkm_perfdom_dtor(struct nvkm_object *base) 308nvkm_perfdom_dtor(struct nvkm_object *object)
308{ 309{
309 struct nvkm_perfdom *dom = nvkm_perfdom(base); 310 struct nvkm_perfdom *dom = nvkm_perfdom(object);
310 struct nvkm_pm *pm = dom->perfmon->pm; 311 struct nvkm_pm *pm = dom->perfmon->pm;
311 int i; 312 int i;
312 313
@@ -607,7 +608,7 @@ nvkm_perfmon_child_new(const struct nvkm_oclass *oclass, void *data, u32 size,
607} 608}
608 609
609static int 610static int
610nvkm_perfmon_child_get(struct nvkm_object *base, int index, 611nvkm_perfmon_child_get(struct nvkm_object *object, int index,
611 struct nvkm_oclass *oclass) 612 struct nvkm_oclass *oclass)
612{ 613{
613 if (index == 0) { 614 if (index == 0) {
@@ -621,9 +622,9 @@ nvkm_perfmon_child_get(struct nvkm_object *base, int index,
621} 622}
622 623
623static void * 624static void *
624nvkm_perfmon_dtor(struct nvkm_object *base) 625nvkm_perfmon_dtor(struct nvkm_object *object)
625{ 626{
626 struct nvkm_perfmon *perfmon = nvkm_perfmon(base); 627 struct nvkm_perfmon *perfmon = nvkm_perfmon(object);
627 struct nvkm_pm *pm = perfmon->pm; 628 struct nvkm_pm *pm = perfmon->pm;
628 mutex_lock(&pm->engine.subdev.mutex); 629 mutex_lock(&pm->engine.subdev.mutex);
629 if (pm->perfmon == &perfmon->object) 630 if (pm->perfmon == &perfmon->object)
@@ -816,24 +817,19 @@ nvkm_perfdom_new(struct nvkm_pm *pm, const char *name, u32 mask,
816 return 0; 817 return 0;
817} 818}
818 819
819int 820static int
820_nvkm_pm_fini(struct nvkm_object *object, bool suspend) 821nvkm_pm_fini(struct nvkm_engine *engine, bool suspend)
821{
822 struct nvkm_pm *pm = (void *)object;
823 return nvkm_engine_fini_old(&pm->engine, suspend);
824}
825
826int
827_nvkm_pm_init(struct nvkm_object *object)
828{ 822{
829 struct nvkm_pm *pm = (void *)object; 823 struct nvkm_pm *pm = nvkm_pm(engine);
830 return nvkm_engine_init_old(&pm->engine); 824 if (pm->func->fini)
825 pm->func->fini(pm);
826 return 0;
831} 827}
832 828
833void 829static void *
834_nvkm_pm_dtor(struct nvkm_object *object) 830nvkm_pm_dtor(struct nvkm_engine *engine)
835{ 831{
836 struct nvkm_pm *pm = (void *)object; 832 struct nvkm_pm *pm = nvkm_pm(engine);
837 struct nvkm_perfdom *dom, *next_dom; 833 struct nvkm_perfdom *dom, *next_dom;
838 struct nvkm_perfsrc *src, *next_src; 834 struct nvkm_perfsrc *src, *next_src;
839 835
@@ -848,30 +844,22 @@ _nvkm_pm_dtor(struct nvkm_object *object)
848 kfree(src); 844 kfree(src);
849 } 845 }
850 846
851 nvkm_engine_destroy(&pm->engine); 847 return pm;
852} 848}
853 849
854static const struct nvkm_engine_func 850static const struct nvkm_engine_func
855nvkm_pm = { 851nvkm_pm = {
852 .dtor = nvkm_pm_dtor,
853 .fini = nvkm_pm_fini,
856 .base.sclass = nvkm_pm_oclass_get, 854 .base.sclass = nvkm_pm_oclass_get,
857}; 855};
858 856
859int 857int
860nvkm_pm_create_(struct nvkm_object *parent, struct nvkm_object *engine, 858nvkm_pm_ctor(const struct nvkm_pm_func *func, struct nvkm_device *device,
861 struct nvkm_oclass *oclass, int length, void **pobject) 859 int index, struct nvkm_pm *pm)
862{ 860{
863 struct nvkm_pm *pm; 861 pm->func = func;
864 int ret;
865
866 ret = nvkm_engine_create_(parent, engine, oclass, true, "PPM",
867 "pm", length, pobject);
868 pm = *pobject;
869 if (ret)
870 return ret;
871
872 pm->engine.func = &nvkm_pm;
873
874 INIT_LIST_HEAD(&pm->domains); 862 INIT_LIST_HEAD(&pm->domains);
875 INIT_LIST_HEAD(&pm->sources); 863 INIT_LIST_HEAD(&pm->sources);
876 return 0; 864 return nvkm_engine_ctor(&nvkm_pm, device, index, 0, true, &pm->engine);
877} 865}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c
index 815bb0dcbf7e..6e441ddafd86 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c
@@ -158,14 +158,8 @@ g84_pm[] = {
158 {} 158 {}
159}; 159};
160 160
161struct nvkm_oclass * 161int
162g84_pm_oclass = &(struct nv40_pm_oclass) { 162g84_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
163 .base.handle = NV_ENGINE(PM, 0x84), 163{
164 .base.ofuncs = &(struct nvkm_ofuncs) { 164 return nv40_pm_new_(g84_pm, device, index, ppm);
165 .ctor = nv40_pm_ctor, 165}
166 .dtor = _nvkm_pm_dtor,
167 .init = _nvkm_pm_init,
168 .fini = _nvkm_pm_fini,
169 },
170 .doms = g84_pm,
171}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c
index 18e0ed514249..d2901e9a7808 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c
@@ -129,7 +129,6 @@ gf100_perfctr_init(struct nvkm_pm *pm, struct nvkm_perfdom *dom,
129 struct nvkm_perfctr *ctr) 129 struct nvkm_perfctr *ctr)
130{ 130{
131 struct nvkm_device *device = pm->engine.subdev.device; 131 struct nvkm_device *device = pm->engine.subdev.device;
132 struct gf100_pm_cntr *cntr = (void *)ctr;
133 u32 log = ctr->logic_op; 132 u32 log = ctr->logic_op;
134 u32 src = 0x00000000; 133 u32 src = 0x00000000;
135 int i; 134 int i;
@@ -139,8 +138,8 @@ gf100_perfctr_init(struct nvkm_pm *pm, struct nvkm_perfdom *dom,
139 138
140 nvkm_wr32(device, dom->addr + 0x09c, 0x00040002 | (dom->mode << 3)); 139 nvkm_wr32(device, dom->addr + 0x09c, 0x00040002 | (dom->mode << 3));
141 nvkm_wr32(device, dom->addr + 0x100, 0x00000000); 140 nvkm_wr32(device, dom->addr + 0x100, 0x00000000);
142 nvkm_wr32(device, dom->addr + 0x040 + (cntr->base.slot * 0x08), src); 141 nvkm_wr32(device, dom->addr + 0x040 + (ctr->slot * 0x08), src);
143 nvkm_wr32(device, dom->addr + 0x044 + (cntr->base.slot * 0x08), log); 142 nvkm_wr32(device, dom->addr + 0x044 + (ctr->slot * 0x08), log);
144} 143}
145 144
146static void 145static void
@@ -148,13 +147,12 @@ gf100_perfctr_read(struct nvkm_pm *pm, struct nvkm_perfdom *dom,
148 struct nvkm_perfctr *ctr) 147 struct nvkm_perfctr *ctr)
149{ 148{
150 struct nvkm_device *device = pm->engine.subdev.device; 149 struct nvkm_device *device = pm->engine.subdev.device;
151 struct gf100_pm_cntr *cntr = (void *)ctr;
152 150
153 switch (cntr->base.slot) { 151 switch (ctr->slot) {
154 case 0: cntr->base.ctr = nvkm_rd32(device, dom->addr + 0x08c); break; 152 case 0: ctr->ctr = nvkm_rd32(device, dom->addr + 0x08c); break;
155 case 1: cntr->base.ctr = nvkm_rd32(device, dom->addr + 0x088); break; 153 case 1: ctr->ctr = nvkm_rd32(device, dom->addr + 0x088); break;
156 case 2: cntr->base.ctr = nvkm_rd32(device, dom->addr + 0x080); break; 154 case 2: ctr->ctr = nvkm_rd32(device, dom->addr + 0x080); break;
157 case 3: cntr->base.ctr = nvkm_rd32(device, dom->addr + 0x090); break; 155 case 3: ctr->ctr = nvkm_rd32(device, dom->addr + 0x090); break;
158 } 156 }
159 dom->clk = nvkm_rd32(device, dom->addr + 0x070); 157 dom->clk = nvkm_rd32(device, dom->addr + 0x070);
160} 158}
@@ -174,35 +172,37 @@ gf100_perfctr_func = {
174 .next = gf100_perfctr_next, 172 .next = gf100_perfctr_next,
175}; 173};
176 174
177int 175static void
178gf100_pm_fini(struct nvkm_object *object, bool suspend) 176gf100_pm_fini(struct nvkm_pm *pm)
179{ 177{
180 struct nvkm_pm *pm = (void *)object;
181 struct nvkm_device *device = pm->engine.subdev.device; 178 struct nvkm_device *device = pm->engine.subdev.device;
182 nvkm_mask(device, 0x000200, 0x10000000, 0x00000000); 179 nvkm_mask(device, 0x000200, 0x10000000, 0x00000000);
183 nvkm_mask(device, 0x000200, 0x10000000, 0x10000000); 180 nvkm_mask(device, 0x000200, 0x10000000, 0x10000000);
184 return nvkm_pm_fini(pm, suspend);
185} 181}
186 182
183static const struct nvkm_pm_func
184gf100_pm_ = {
185 .fini = gf100_pm_fini,
186};
187
187int 188int
188gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 189gf100_pm_new_(const struct gf100_pm_func *func, struct nvkm_device *device,
189 struct nvkm_oclass *oclass, void *data, u32 size, 190 int index, struct nvkm_pm **ppm)
190 struct nvkm_object **pobject)
191{ 191{
192 struct gf100_pm_oclass *mclass = (void *)oclass;
193 struct nvkm_device *device = (void *)parent;
194 struct nvkm_pm *pm; 192 struct nvkm_pm *pm;
195 u32 mask; 193 u32 mask;
196 int ret; 194 int ret;
197 195
198 ret = nvkm_pm_create(parent, engine, oclass, &pm); 196 if (!(pm = *ppm = kzalloc(sizeof(*pm), GFP_KERNEL)))
199 *pobject = nv_object(pm); 197 return -ENOMEM;
198
199 ret = nvkm_pm_ctor(&gf100_pm_, device, index, pm);
200 if (ret) 200 if (ret)
201 return ret; 201 return ret;
202 202
203 /* HUB */ 203 /* HUB */
204 ret = nvkm_perfdom_new(pm, "hub", 0, 0x1b0000, 0, 0x200, 204 ret = nvkm_perfdom_new(pm, "hub", 0, 0x1b0000, 0, 0x200,
205 mclass->doms_hub); 205 func->doms_hub);
206 if (ret) 206 if (ret)
207 return ret; 207 return ret;
208 208
@@ -212,7 +212,7 @@ gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
212 mask &= ~nvkm_rd32(device, 0x022584); 212 mask &= ~nvkm_rd32(device, 0x022584);
213 213
214 ret = nvkm_perfdom_new(pm, "gpc", mask, 0x180000, 214 ret = nvkm_perfdom_new(pm, "gpc", mask, 0x180000,
215 0x1000, 0x200, mclass->doms_gpc); 215 0x1000, 0x200, func->doms_gpc);
216 if (ret) 216 if (ret)
217 return ret; 217 return ret;
218 218
@@ -222,23 +222,22 @@ gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
222 mask &= ~nvkm_rd32(device, 0x0225c8); 222 mask &= ~nvkm_rd32(device, 0x0225c8);
223 223
224 ret = nvkm_perfdom_new(pm, "part", mask, 0x1a0000, 224 ret = nvkm_perfdom_new(pm, "part", mask, 0x1a0000,
225 0x1000, 0x200, mclass->doms_part); 225 0x1000, 0x200, func->doms_part);
226 if (ret) 226 if (ret)
227 return ret; 227 return ret;
228 228
229 return 0; 229 return 0;
230} 230}
231 231
232struct nvkm_oclass * 232static const struct gf100_pm_func
233gf100_pm_oclass = &(struct gf100_pm_oclass) { 233gf100_pm = {
234 .base.handle = NV_ENGINE(PM, 0xc0), 234 .doms_gpc = gf100_pm_gpc,
235 .base.ofuncs = &(struct nvkm_ofuncs) { 235 .doms_hub = gf100_pm_hub,
236 .ctor = gf100_pm_ctor,
237 .dtor = _nvkm_pm_dtor,
238 .init = _nvkm_pm_init,
239 .fini = gf100_pm_fini,
240 },
241 .doms_gpc = gf100_pm_gpc,
242 .doms_hub = gf100_pm_hub,
243 .doms_part = gf100_pm_part, 236 .doms_part = gf100_pm_part,
244}.base; 237};
238
239int
240gf100_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
241{
242 return gf100_pm_new_(&gf100_pm, device, index, ppm);
243}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
index de6162221823..56d0344853ea 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
@@ -2,27 +2,18 @@
2#define __NVKM_PM_NVC0_H__ 2#define __NVKM_PM_NVC0_H__
3#include "priv.h" 3#include "priv.h"
4 4
5struct gf100_pm_oclass { 5struct gf100_pm_func {
6 struct nvkm_oclass base;
7 const struct nvkm_specdom *doms_hub; 6 const struct nvkm_specdom *doms_hub;
8 const struct nvkm_specdom *doms_gpc; 7 const struct nvkm_specdom *doms_gpc;
9 const struct nvkm_specdom *doms_part; 8 const struct nvkm_specdom *doms_part;
10}; 9};
11 10
12int gf100_pm_ctor(struct nvkm_object *, struct nvkm_object *, 11int gf100_pm_new_(const struct gf100_pm_func *, struct nvkm_device *,
13 struct nvkm_oclass *, void *data, u32 size, 12 int index, struct nvkm_pm **);
14 struct nvkm_object **pobject);
15
16struct gf100_pm_cntr {
17 struct nvkm_perfctr base;
18};
19 13
20extern const struct nvkm_funcdom gf100_perfctr_func; 14extern const struct nvkm_funcdom gf100_perfctr_func;
21int gf100_pm_fini(struct nvkm_object *, bool);
22
23extern const struct nvkm_specdom gf100_pm_gpc[]; 15extern const struct nvkm_specdom gf100_pm_gpc[];
24 16
25extern const struct nvkm_specsrc gf100_pbfb_sources[]; 17extern const struct nvkm_specsrc gf100_pbfb_sources[];
26extern const struct nvkm_specsrc gf100_pmfb_sources[]; 18extern const struct nvkm_specsrc gf100_pmfb_sources[];
27
28#endif 19#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c
index a4d86d1ab1b0..49b24c98a7f7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c
@@ -52,16 +52,15 @@ gf108_pm_part[] = {
52 {} 52 {}
53}; 53};
54 54
55struct nvkm_oclass * 55static const struct gf100_pm_func
56gf108_pm_oclass = &(struct gf100_pm_oclass) { 56gf108_pm = {
57 .base.handle = NV_ENGINE(PM, 0xc1), 57 .doms_gpc = gf100_pm_gpc,
58 .base.ofuncs = &(struct nvkm_ofuncs) { 58 .doms_hub = gf108_pm_hub,
59 .ctor = gf100_pm_ctor,
60 .dtor = _nvkm_pm_dtor,
61 .init = _nvkm_pm_init,
62 .fini = gf100_pm_fini,
63 },
64 .doms_hub = gf108_pm_hub,
65 .doms_gpc = gf100_pm_gpc,
66 .doms_part = gf108_pm_part, 59 .doms_part = gf108_pm_part,
67}.base; 60};
61
62int
63gf108_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
64{
65 return gf100_pm_new_(&gf108_pm, device, index, ppm);
66}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c
index a76c9283237d..9170025fc988 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c
@@ -66,16 +66,15 @@ gf117_pm_part[] = {
66 {} 66 {}
67}; 67};
68 68
69struct nvkm_oclass * 69static const struct gf100_pm_func
70gf117_pm_oclass = &(struct gf100_pm_oclass) { 70gf117_pm = {
71 .base.handle = NV_ENGINE(PM, 0xd7), 71 .doms_gpc = gf100_pm_gpc,
72 .base.ofuncs = &(struct nvkm_ofuncs) { 72 .doms_hub = gf117_pm_hub,
73 .ctor = gf100_pm_ctor,
74 .dtor = _nvkm_pm_dtor,
75 .init = _nvkm_pm_init,
76 .fini = gf100_pm_fini,
77 },
78 .doms_gpc = gf100_pm_gpc,
79 .doms_hub = gf117_pm_hub,
80 .doms_part = gf117_pm_part, 73 .doms_part = gf117_pm_part,
81}.base; 74};
75
76int
77gf117_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
78{
79 return gf100_pm_new_(&gf117_pm, device, index, ppm);
80}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c
index a236db9b7a68..07f946d26ac6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c
@@ -170,16 +170,15 @@ gk104_pm_part[] = {
170 {} 170 {}
171}; 171};
172 172
173struct nvkm_oclass * 173static const struct gf100_pm_func
174gk104_pm_oclass = &(struct gf100_pm_oclass) { 174gk104_pm = {
175 .base.handle = NV_ENGINE(PM, 0xe0), 175 .doms_gpc = gk104_pm_gpc,
176 .base.ofuncs = &(struct nvkm_ofuncs) { 176 .doms_hub = gk104_pm_hub,
177 .ctor = gf100_pm_ctor,
178 .dtor = _nvkm_pm_dtor,
179 .init = _nvkm_pm_init,
180 .fini = gf100_pm_fini,
181 },
182 .doms_gpc = gk104_pm_gpc,
183 .doms_hub = gk104_pm_hub,
184 .doms_part = gk104_pm_part, 177 .doms_part = gk104_pm_part,
185}.base; 178};
179
180int
181gk104_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
182{
183 return gf100_pm_new_(&gk104_pm, device, index, ppm);
184}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c
deleted file mode 100644
index 44df8d311070..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "gf100.h"
25
26static int
27gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
28 struct nvkm_oclass *oclass, void *data, u32 size,
29 struct nvkm_object **pobject)
30{
31 struct nvkm_pm *pm;
32 int ret;
33
34 ret = nvkm_pm_create(parent, engine, oclass, &pm);
35 *pobject = nv_object(pm);
36 if (ret)
37 return ret;
38
39 return 0;
40}
41
42struct nvkm_oclass
43gk110_pm_oclass = {
44 .handle = NV_ENGINE(PM, 0xf0),
45 .ofuncs = &(struct nvkm_ofuncs) {
46 .ctor = gk110_pm_ctor,
47 .dtor = _nvkm_pm_dtor,
48 .init = _nvkm_pm_init,
49 .fini = gf100_pm_fini,
50 },
51};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c
index e92f9c711bcc..5cf5dd536fd0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c
@@ -150,14 +150,8 @@ gt200_pm[] = {
150 {} 150 {}
151}; 151};
152 152
153struct nvkm_oclass * 153int
154gt200_pm_oclass = &(struct nv40_pm_oclass) { 154gt200_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
155 .base.handle = NV_ENGINE(PM, 0xa0), 155{
156 .base.ofuncs = &(struct nvkm_ofuncs) { 156 return nv40_pm_new_(gt200_pm, device, index, ppm);
157 .ctor = nv40_pm_ctor, 157}
158 .dtor = _nvkm_pm_dtor,
159 .init = _nvkm_pm_init,
160 .fini = _nvkm_pm_fini,
161 },
162 .doms = gt200_pm,
163}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c
index f5eae63d9f48..c9227ad41b04 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c
@@ -131,14 +131,8 @@ gt215_pm[] = {
131 {} 131 {}
132}; 132};
133 133
134struct nvkm_oclass * 134int
135gt215_pm_oclass = &(struct nv40_pm_oclass) { 135gt215_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
136 .base.handle = NV_ENGINE(PM, 0xa3), 136{
137 .base.ofuncs = &(struct nvkm_ofuncs) { 137 return nv40_pm_new_(gt215_pm, device, index, ppm);
138 .ctor = nv40_pm_ctor, 138}
139 .dtor = _nvkm_pm_dtor,
140 .init = _nvkm_pm_init,
141 .fini = _nvkm_pm_fini,
142 },
143 .doms = gt215_pm,
144}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
index a4660dc14259..4bef72a9d106 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
@@ -28,7 +28,6 @@ nv40_perfctr_init(struct nvkm_pm *pm, struct nvkm_perfdom *dom,
28 struct nvkm_perfctr *ctr) 28 struct nvkm_perfctr *ctr)
29{ 29{
30 struct nvkm_device *device = pm->engine.subdev.device; 30 struct nvkm_device *device = pm->engine.subdev.device;
31 struct nv40_pm_cntr *cntr = (void *)ctr;
32 u32 log = ctr->logic_op; 31 u32 log = ctr->logic_op;
33 u32 src = 0x00000000; 32 u32 src = 0x00000000;
34 int i; 33 int i;
@@ -37,8 +36,8 @@ nv40_perfctr_init(struct nvkm_pm *pm, struct nvkm_perfdom *dom,
37 src |= ctr->signal[i] << (i * 8); 36 src |= ctr->signal[i] << (i * 8);
38 37
39 nvkm_wr32(device, 0x00a7c0 + dom->addr, 0x00000001 | (dom->mode << 4)); 38 nvkm_wr32(device, 0x00a7c0 + dom->addr, 0x00000001 | (dom->mode << 4));
40 nvkm_wr32(device, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src); 39 nvkm_wr32(device, 0x00a400 + dom->addr + (ctr->slot * 0x40), src);
41 nvkm_wr32(device, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log); 40 nvkm_wr32(device, 0x00a420 + dom->addr + (ctr->slot * 0x40), log);
42} 41}
43 42
44static void 43static void
@@ -46,13 +45,12 @@ nv40_perfctr_read(struct nvkm_pm *pm, struct nvkm_perfdom *dom,
46 struct nvkm_perfctr *ctr) 45 struct nvkm_perfctr *ctr)
47{ 46{
48 struct nvkm_device *device = pm->engine.subdev.device; 47 struct nvkm_device *device = pm->engine.subdev.device;
49 struct nv40_pm_cntr *cntr = (void *)ctr;
50 48
51 switch (cntr->base.slot) { 49 switch (ctr->slot) {
52 case 0: cntr->base.ctr = nvkm_rd32(device, 0x00a700 + dom->addr); break; 50 case 0: ctr->ctr = nvkm_rd32(device, 0x00a700 + dom->addr); break;
53 case 1: cntr->base.ctr = nvkm_rd32(device, 0x00a6c0 + dom->addr); break; 51 case 1: ctr->ctr = nvkm_rd32(device, 0x00a6c0 + dom->addr); break;
54 case 2: cntr->base.ctr = nvkm_rd32(device, 0x00a680 + dom->addr); break; 52 case 2: ctr->ctr = nvkm_rd32(device, 0x00a680 + dom->addr); break;
55 case 3: cntr->base.ctr = nvkm_rd32(device, 0x00a740 + dom->addr); break; 53 case 3: ctr->ctr = nvkm_rd32(device, 0x00a740 + dom->addr); break;
56 } 54 }
57 dom->clk = nvkm_rd32(device, 0x00a600 + dom->addr); 55 dom->clk = nvkm_rd32(device, 0x00a600 + dom->addr);
58} 56}
@@ -74,6 +72,28 @@ nv40_perfctr_func = {
74 .next = nv40_perfctr_next, 72 .next = nv40_perfctr_next,
75}; 73};
76 74
75static const struct nvkm_pm_func
76nv40_pm_ = {
77};
78
79int
80nv40_pm_new_(const struct nvkm_specdom *doms, struct nvkm_device *device,
81 int index, struct nvkm_pm **ppm)
82{
83 struct nv40_pm *pm;
84 int ret;
85
86 if (!(pm = kzalloc(sizeof(*pm), GFP_KERNEL)))
87 return -ENOMEM;
88 *ppm = &pm->base;
89
90 ret = nvkm_pm_ctor(&nv40_pm_, device, index, &pm->base);
91 if (ret)
92 return ret;
93
94 return nvkm_perfdom_new(&pm->base, "pc", 0, 0, 0, 4, doms);
95}
96
77static const struct nvkm_specdom 97static const struct nvkm_specdom
78nv40_pm[] = { 98nv40_pm[] = {
79 { 0x20, (const struct nvkm_specsig[]) { 99 { 0x20, (const struct nvkm_specsig[]) {
@@ -95,34 +115,7 @@ nv40_pm[] = {
95}; 115};
96 116
97int 117int
98nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 118nv40_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
99 struct nvkm_oclass *oclass, void *data, u32 size,
100 struct nvkm_object **pobject)
101{ 119{
102 struct nv40_pm_oclass *mclass = (void *)oclass; 120 return nv40_pm_new_(nv40_pm, device, index, ppm);
103 struct nv40_pm *pm;
104 int ret;
105
106 ret = nvkm_pm_create(parent, engine, oclass, &pm);
107 *pobject = nv_object(pm);
108 if (ret)
109 return ret;
110
111 ret = nvkm_perfdom_new(&pm->base, "pc", 0, 0, 0, 4, mclass->doms);
112 if (ret)
113 return ret;
114
115 return 0;
116} 121}
117
118struct nvkm_oclass *
119nv40_pm_oclass = &(struct nv40_pm_oclass) {
120 .base.handle = NV_ENGINE(PM, 0x40),
121 .base.ofuncs = &(struct nvkm_ofuncs) {
122 .ctor = nv40_pm_ctor,
123 .dtor = _nvkm_pm_dtor,
124 .init = _nvkm_pm_init,
125 .fini = _nvkm_pm_fini,
126 },
127 .doms = nv40_pm,
128}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
index 08287527615c..da481abe8f7a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
@@ -1,24 +1,14 @@
1#ifndef __NVKM_PM_NV40_H__ 1#ifndef __NVKM_PM_NV40_H__
2#define __NVKM_PM_NV40_H__ 2#define __NVKM_PM_NV40_H__
3#define nv40_pm(p) container_of((p), struct nv40_pm, base)
3#include "priv.h" 4#include "priv.h"
4 5
5struct nv40_pm_oclass {
6 struct nvkm_oclass base;
7 const struct nvkm_specdom *doms;
8};
9
10struct nv40_pm { 6struct nv40_pm {
11 struct nvkm_pm base; 7 struct nvkm_pm base;
12 u32 sequence; 8 u32 sequence;
13}; 9};
14 10
15int nv40_pm_ctor(struct nvkm_object *, struct nvkm_object *, 11int nv40_pm_new_(const struct nvkm_specdom *, struct nvkm_device *,
16 struct nvkm_oclass *, void *data, u32 size, 12 int index, struct nvkm_pm **);
17 struct nvkm_object **pobject);
18
19struct nv40_pm_cntr {
20 struct nvkm_perfctr base;
21};
22
23extern const struct nvkm_funcdom nv40_perfctr_func; 13extern const struct nvkm_funcdom nv40_perfctr_func;
24#endif 14#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
index dee73af1c62f..cc5a41d4c6f2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
@@ -168,14 +168,8 @@ nv50_pm[] = {
168 {} 168 {}
169}; 169};
170 170
171struct nvkm_oclass * 171int
172nv50_pm_oclass = &(struct nv40_pm_oclass) { 172nv50_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
173 .base.handle = NV_ENGINE(PM, 0x50), 173{
174 .base.ofuncs = &(struct nvkm_ofuncs) { 174 return nv40_pm_new_(nv50_pm, device, index, ppm);
175 .ctor = nv40_pm_ctor, 175}
176 .dtor = _nvkm_pm_dtor,
177 .init = _nvkm_pm_init,
178 .fini = _nvkm_pm_fini,
179 },
180 .doms = nv50_pm,
181}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
index 889dca2e87be..d7b81cbf82b5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
@@ -1,7 +1,15 @@
1#ifndef __NVKM_PM_PRIV_H__ 1#ifndef __NVKM_PM_PRIV_H__
2#define __NVKM_PM_PRIV_H__ 2#define __NVKM_PM_PRIV_H__
3#define nvkm_pm(p) container_of((p), struct nvkm_pm, engine)
3#include <engine/pm.h> 4#include <engine/pm.h>
4 5
6int nvkm_pm_ctor(const struct nvkm_pm_func *, struct nvkm_device *,
7 int index, struct nvkm_pm *);
8
9struct nvkm_pm_func {
10 void (*fini)(struct nvkm_pm *);
11};
12
5struct nvkm_perfctr { 13struct nvkm_perfctr {
6 struct list_head head; 14 struct list_head head;
7 u8 domain; 15 u8 domain;
@@ -92,25 +100,4 @@ struct nvkm_perfmon {
92 struct nvkm_object object; 100 struct nvkm_object object;
93 struct nvkm_pm *pm; 101 struct nvkm_pm *pm;
94}; 102};
95
96#define nvkm_pm_create(p,e,o,d) \
97 nvkm_pm_create_((p), (e), (o), sizeof(**d), (void **)d)
98#define nvkm_pm_dtor(p) ({ \
99 struct nvkm_pm *c = (p); \
100 _nvkm_pm_dtor(nv_object(c)); \
101})
102#define nvkm_pm_init(p) ({ \
103 struct nvkm_pm *c = (p); \
104 _nvkm_pm_init(nv_object(c)); \
105})
106#define nvkm_pm_fini(p,s) ({ \
107 struct nvkm_pm *c = (p); \
108 _nvkm_pm_fini(nv_object(c), (s)); \
109})
110
111int nvkm_pm_create_(struct nvkm_object *, struct nvkm_object *,
112 struct nvkm_oclass *, int, void **);
113void _nvkm_pm_dtor(struct nvkm_object *);
114int _nvkm_pm_init(struct nvkm_object *);
115int _nvkm_pm_fini(struct nvkm_object *, bool);
116#endif 103#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 21:03:00 -0400