Merge branch 'net-mediatek-Add-MT7621-TRGMII-mode-support'

René van Dorst says:

====================
net: mediatek: Add MT7621 TRGMII mode support

Like many other mediatek SOCs, the MT7621 SOC and the internal MT7530
switch both supports TRGMII mode. MT7621 TRGMII speed is fix 1200MBit.

v1->v2:
 - Fix breakage on non MT7621 SOC
 - Support 25MHz and 40MHz XTAL as MT7530 clocksource
====================

Tested-by: "Frank Wunderlich" <frank-w@public-files.de>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

4 files changed, 85 insertions, 14 deletions

diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index c7d352da5448..3181e95586d6 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -428,24 +428,48 @@ static int
 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
 {
         struct mt7530_priv *priv = ds->priv;
-        u32 ncpo1, ssc_delta, trgint, i;
+        u32 ncpo1, ssc_delta, trgint, i, xtal;
+
+        xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
+
+        if (xtal == HWTRAP_XTAL_20MHZ) {
+                dev_err(priv->dev,
+                        "%s: MT7530 with a 20MHz XTAL is not supported!\n",
+                        __func__);
+                return -EINVAL;
+        }
 
         switch (mode) {
         case PHY_INTERFACE_MODE_RGMII:
                 trgint = 0;
+                /* PLL frequency: 125MHz */
                 ncpo1 = 0x0c80;
-                ssc_delta = 0x87;
                 break;
         case PHY_INTERFACE_MODE_TRGMII:
                 trgint = 1;
-                ncpo1 = 0x1400;
-                ssc_delta = 0x57;
+                if (priv->id == ID_MT7621) {
+                        /* PLL frequency: 150MHz: 1.2GBit */
+                        if (xtal == HWTRAP_XTAL_40MHZ)
+                                ncpo1 = 0x0780;
+                        if (xtal == HWTRAP_XTAL_25MHZ)
+                                ncpo1 = 0x0a00;
+                } else { /* PLL frequency: 250MHz: 2.0Gbit */
+                        if (xtal == HWTRAP_XTAL_40MHZ)
+                                ncpo1 = 0x0c80;
+                        if (xtal == HWTRAP_XTAL_25MHZ)
+                                ncpo1 = 0x1400;
+                }
                 break;
         default:
                 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
                 return -EINVAL;
         }
 
+        if (xtal == HWTRAP_XTAL_25MHZ)
+                ssc_delta = 0x57;
+        else
+                ssc_delta = 0x87;
+
         mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
                    P6_INTF_MODE(trgint));
 
@@ -507,7 +531,9 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
                         mt7530_rmw(priv, MT7530_TRGMII_RD(i),
                                    RD_TAP_MASK, RD_TAP(16));
         else
-                mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
+                if (priv->id != ID_MT7621)
+                        mt7623_trgmii_set(priv, GSW_INTF_MODE,
+                                          INTF_MODE_TRGMII);
 
         return 0;
 }
@@ -613,13 +639,13 @@ static void mt7530_adjust_link(struct dsa_switch *ds, int port,
         struct mt7530_priv *priv = ds->priv;
 
         if (phy_is_pseudo_fixed_link(phydev)) {
-                if (priv->id == ID_MT7530) {
-                        dev_dbg(priv->dev, "phy-mode for master device = %x\n",
-                                phydev->interface);
+                dev_dbg(priv->dev, "phy-mode for master device = %x\n",
+                        phydev->interface);
 
-                        /* Setup TX circuit incluing relevant PAD and driving */
-                        mt7530_pad_clk_setup(ds, phydev->interface);
+                /* Setup TX circuit incluing relevant PAD and driving */
+                mt7530_pad_clk_setup(ds, phydev->interface);
 
+                if (priv->id == ID_MT7530) {
                         /* Setup RX circuit, relevant PAD and driving on the
                          * host which must be placed after the setup on the
                          * device side is all finished.
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index 4331429969fa..bfac90f48102 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -244,6 +244,10 @@ enum mt7530_vlan_port_attr {
 
 /* Register for hw trap status */
 #define MT7530_HWTRAP                   0x7800
+#define  HWTRAP_XTAL_MASK               (BIT(10) | BIT(9))
+#define  HWTRAP_XTAL_25MHZ              (BIT(10) | BIT(9))
+#define  HWTRAP_XTAL_40MHZ              (BIT(10))
+#define  HWTRAP_XTAL_20MHZ              (BIT(9))
 
 /* Register for hw trap modification */
 #define MT7530_MHWTRAP                  0x7804
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index f27efe4110cc..066712f2e985 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -134,6 +134,28 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
         return _mtk_mdio_read(eth, phy_addr, phy_reg);
 }
 
+static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
+                                     phy_interface_t interface)
+{
+        u32 val;
+
+        /* Check DDR memory type. Currently DDR2 is not supported. */
+        regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
+        if (val & SYSCFG_DRAM_TYPE_DDR2) {
+                dev_err(eth->dev,
+                        "TRGMII mode with DDR2 memory is not supported!\n");
+                return -EOPNOTSUPP;
+        }
+
+        val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
+                ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
+
+        regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
+                           ETHSYS_TRGMII_MT7621_MASK, val);
+
+        return 0;
+}
+
 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
 {
         u32 val;
@@ -183,9 +205,17 @@ static void mtk_phy_link_adjust(struct net_device *dev)
                 break;
         }
 
-        if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
-            !mac->id && !mac->trgmii)
-                mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
+        if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && !mac->id) {
+                if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) {
+                        if (mt7621_gmac0_rgmii_adjust(mac->hw,
+                                                      dev->phydev->interface))
+                                return;
+                } else {
+                        if (!mac->trgmii)
+                                mtk_gmac0_rgmii_adjust(mac->hw,
+                                                       dev->phydev->speed);
+                }
+        }
 
         if (dev->phydev->link)
                 mcr |= MAC_MCR_FORCE_LINK;
@@ -2607,7 +2637,7 @@ static const struct mtk_soc_data mt2701_data = {
 };
 
 static const struct mtk_soc_data mt7621_data = {
-        .caps = MTK_SHARED_INT,
+        .caps = MT7621_CAPS,
         .required_clks = MT7621_CLKS_BITMAP,
         .required_pctl = false,
 };
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 85e3144f1af5..876ce6798709 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -363,6 +363,10 @@
 #define MT7622_ETH              7622
 #define MT7621_ETH              7621
 
+/* ethernet system control register */
+#define ETHSYS_SYSCFG           0x10
+#define SYSCFG_DRAM_TYPE_DDR2   BIT(4)
+
 /* ethernet subsystem config register */
 #define ETHSYS_SYSCFG0          0x14
 #define SYSCFG0_GE_MASK         0x3
@@ -377,6 +381,9 @@
 /* ethernet subsystem clock register */
 #define ETHSYS_CLKCFG0          0x2c
 #define ETHSYS_TRGMII_CLK_SEL362_5      BIT(11)
+#define ETHSYS_TRGMII_MT7621_MASK       (BIT(5) | BIT(6))
+#define ETHSYS_TRGMII_MT7621_APLL       BIT(6)
+#define ETHSYS_TRGMII_MT7621_DDR_PLL    BIT(5)
 
 /* ethernet reset control register */
 #define ETHSYS_RSTCTRL          0x34
@@ -616,6 +623,7 @@ enum mtk_eth_path {
 #define MTK_SHARED_SGMII                BIT(7)
 #define MTK_HWLRO                       BIT(8)
 #define MTK_SHARED_INT                  BIT(9)
+#define MTK_TRGMII_MT7621_CLK           BIT(10)
 
 /* Supported path present on SoCs */
 #define MTK_PATH_BIT(x)         BIT((x) + 10)
@@ -667,6 +675,9 @@ enum mtk_eth_path {
 
 #define MTK_HAS_CAPS(caps, _x)          (((caps) & (_x)) == (_x))
 
+#define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
+                      MTK_GMAC2_RGMII | MTK_SHARED_INT | MTK_TRGMII_MT7621_CLK)
+
 #define MT7622_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
                       MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
                       MTK_MUX_GDM1_TO_GMAC1_ESW | \