aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorChristian Gmeiner <christian.gmeiner@gmail.com>2017-09-24 09:15:37 -0400
committerLucas Stach <l.stach@pengutronix.de>2017-10-10 05:45:51 -0400
commit9646025ee6c340b5e5ff2e34d4ae05edc45f1dd4 (patch)
tree327de341a2cf6e9c4c6c0dd0efb02171fdbdd381
parent91a9a17b59c10237c6fd72161682353be94cf01d (diff)
drm/etnaviv: add TX perf domain
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_perfmon.c53
1 files changed, 53 insertions, 0 deletions
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
index aa7fe0b954a1..9efa933fc7b1 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
@@ -299,6 +299,59 @@ static const struct etnaviv_pm_domain doms_3d[] = {
299 &perf_reg_read 299 &perf_reg_read
300 } 300 }
301 } 301 }
302 },
303 {
304 .name = "TX",
305 .profile_read = VIVS_MC_PROFILE_TX_READ,
306 .profile_config = VIVS_MC_PROFILE_CONFIG1,
307 .nr_signals = 9,
308 .signal = (const struct etnaviv_pm_signal[]) {
309 {
310 "TOTAL_BILINEAR_REQUESTS",
311 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS,
312 &perf_reg_read
313 },
314 {
315 "TOTAL_TRILINEAR_REQUESTS",
316 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS,
317 &perf_reg_read
318 },
319 {
320 "TOTAL_DISCARDED_TEXTURE_REQUESTS",
321 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS,
322 &perf_reg_read
323 },
324 {
325 "TOTAL_TEXTURE_REQUESTS",
326 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS,
327 &perf_reg_read
328 },
329 {
330 "MEM_READ_COUNT",
331 VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT,
332 &perf_reg_read
333 },
334 {
335 "MEM_READ_IN_8B_COUNT",
336 VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT,
337 &perf_reg_read
338 },
339 {
340 "CACHE_MISS_COUNT",
341 VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT,
342 &perf_reg_read
343 },
344 {
345 "CACHE_HIT_TEXEL_COUNT",
346 VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT,
347 &perf_reg_read
348 },
349 {
350 "CACHE_MISS_TEXEL_COUNT",
351 VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT,
352 &perf_reg_read
353 }
354 }
302 } 355 }
303}; 356};
304 357