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authorBen Skeggs <bskeggs@redhat.com>2014-08-09 14:10:28 -0400
committerBen Skeggs <bskeggs@redhat.com>2014-08-09 15:28:13 -0400
commit95484b57265caa671a57efed06e322d56461774b (patch)
tree88cd74be97a4e15e0c507a6119036aac62292d80
parentf392ec4b1d92004949e5a4f4418b1fbb2582ef0d (diff)
drm/nouveau/ltc: s/ltcg/ltc/ + cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/Makefile6
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/base.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/gm100.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nvc0.c20
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nve0.c14
-rw-r--r--drivers/gpu/drm/nouveau/core/include/core/device.h2
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/ltc.h28
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h41
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/ltc/base.c80
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c (renamed from drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.c)145
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c55
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c (renamed from drivers/gpu/drm/nouveau/core/subdev/ltcg/gm107.c)101
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h58
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.h21
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c8
17 files changed, 362 insertions, 235 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 029e0555fa38..1a44d952cc3a 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -153,8 +153,10 @@ nouveau-y += core/subdev/instmem/base.o
153nouveau-y += core/subdev/instmem/nv04.o 153nouveau-y += core/subdev/instmem/nv04.o
154nouveau-y += core/subdev/instmem/nv40.o 154nouveau-y += core/subdev/instmem/nv40.o
155nouveau-y += core/subdev/instmem/nv50.o 155nouveau-y += core/subdev/instmem/nv50.o
156nouveau-y += core/subdev/ltcg/gf100.o 156nouveau-y += core/subdev/ltc/base.o
157nouveau-y += core/subdev/ltcg/gm107.o 157nouveau-y += core/subdev/ltc/gf100.o
158nouveau-y += core/subdev/ltc/gk104.o
159nouveau-y += core/subdev/ltc/gm107.o
158nouveau-y += core/subdev/mc/base.o 160nouveau-y += core/subdev/mc/base.o
159nouveau-y += core/subdev/mc/nv04.o 161nouveau-y += core/subdev/mc/nv04.o
160nouveau-y += core/subdev/mc/nv40.o 162nouveau-y += core/subdev/mc/nv40.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index e4e089b65a01..8928f7981d4a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -214,7 +214,7 @@ static const u64 disable_map[] = {
214 [NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE, 214 [NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE,
215 [NVDEV_SUBDEV_TIMER] = NV_DEVICE_V0_DISABLE_CORE, 215 [NVDEV_SUBDEV_TIMER] = NV_DEVICE_V0_DISABLE_CORE,
216 [NVDEV_SUBDEV_FB] = NV_DEVICE_V0_DISABLE_CORE, 216 [NVDEV_SUBDEV_FB] = NV_DEVICE_V0_DISABLE_CORE,
217 [NVDEV_SUBDEV_LTCG] = NV_DEVICE_V0_DISABLE_CORE, 217 [NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE,
218 [NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE, 218 [NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE,
219 [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE, 219 [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE,
220 [NVDEV_SUBDEV_VM] = NV_DEVICE_V0_DISABLE_CORE, 220 [NVDEV_SUBDEV_VM] = NV_DEVICE_V0_DISABLE_CORE,
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c b/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
index 091f3e12ffc6..377ec0b8851e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
@@ -33,7 +33,7 @@
33#include <subdev/mc.h> 33#include <subdev/mc.h>
34#include <subdev/timer.h> 34#include <subdev/timer.h>
35#include <subdev/fb.h> 35#include <subdev/fb.h>
36#include <subdev/ltcg.h> 36#include <subdev/ltc.h>
37#include <subdev/ibus.h> 37#include <subdev/ibus.h>
38#include <subdev/instmem.h> 38#include <subdev/instmem.h>
39#include <subdev/vm.h> 39#include <subdev/vm.h>
@@ -72,7 +72,7 @@ gm100_identify(struct nouveau_device *device)
72 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 72 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
73 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; 73 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
74 device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; 74 device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
75 device->oclass[NVDEV_SUBDEV_LTCG ] = gm107_ltcg_oclass; 75 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
76 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 76 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
77 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 77 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
78 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 78 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index 1d741faa6fe0..b4a2917ce555 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -33,7 +33,7 @@
33#include <subdev/mc.h> 33#include <subdev/mc.h>
34#include <subdev/timer.h> 34#include <subdev/timer.h>
35#include <subdev/fb.h> 35#include <subdev/fb.h>
36#include <subdev/ltcg.h> 36#include <subdev/ltc.h>
37#include <subdev/ibus.h> 37#include <subdev/ibus.h>
38#include <subdev/instmem.h> 38#include <subdev/instmem.h>
39#include <subdev/vm.h> 39#include <subdev/vm.h>
@@ -70,7 +70,7 @@ nvc0_identify(struct nouveau_device *device)
70 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 70 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
72 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 72 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
73 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 73 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
74 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 74 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
76 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 76 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -102,7 +102,7 @@ nvc0_identify(struct nouveau_device *device)
102 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 102 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
103 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 103 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
104 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 104 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
105 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 105 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
106 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 106 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
107 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 107 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
108 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 108 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -134,7 +134,7 @@ nvc0_identify(struct nouveau_device *device)
134 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 134 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
135 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 135 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
136 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 136 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
137 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 137 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
138 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 138 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
139 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 139 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
140 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 140 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -165,7 +165,7 @@ nvc0_identify(struct nouveau_device *device)
165 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 165 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
166 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 166 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
167 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 167 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
168 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 168 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
169 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 169 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
170 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 170 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
171 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 171 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -197,7 +197,7 @@ nvc0_identify(struct nouveau_device *device)
197 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 197 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
198 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 198 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
199 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 199 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
200 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 200 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
201 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 201 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
202 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 202 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
203 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 203 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -229,7 +229,7 @@ nvc0_identify(struct nouveau_device *device)
229 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 229 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
230 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 230 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
231 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 231 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
232 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 232 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
233 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 233 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
234 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 234 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
235 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 235 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -260,7 +260,7 @@ nvc0_identify(struct nouveau_device *device)
260 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 260 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
261 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 261 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
262 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 262 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
263 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 263 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
264 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 264 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
265 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 265 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
266 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 266 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -292,7 +292,7 @@ nvc0_identify(struct nouveau_device *device)
292 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 292 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
294 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 294 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
295 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 295 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
296 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 296 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
297 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 297 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
298 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 298 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -323,7 +323,7 @@ nvc0_identify(struct nouveau_device *device)
323 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 323 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
324 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 324 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
325 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 325 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
326 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 326 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
327 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; 327 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
328 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 328 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
329 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 329 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index 51b6af6c956a..54ec53bc6252 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -33,7 +33,7 @@
33#include <subdev/mc.h> 33#include <subdev/mc.h>
34#include <subdev/timer.h> 34#include <subdev/timer.h>
35#include <subdev/fb.h> 35#include <subdev/fb.h>
36#include <subdev/ltcg.h> 36#include <subdev/ltc.h>
37#include <subdev/ibus.h> 37#include <subdev/ibus.h>
38#include <subdev/instmem.h> 38#include <subdev/instmem.h>
39#include <subdev/vm.h> 39#include <subdev/vm.h>
@@ -70,7 +70,7 @@ nve0_identify(struct nouveau_device *device)
70 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 70 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
72 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; 72 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
73 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 73 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
74 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 74 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
76 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 76 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -103,7 +103,7 @@ nve0_identify(struct nouveau_device *device)
103 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 103 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
104 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 104 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
105 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; 105 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
106 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 106 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
107 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 107 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
108 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 108 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
109 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 109 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -136,7 +136,7 @@ nve0_identify(struct nouveau_device *device)
136 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 136 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
137 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 137 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
138 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; 138 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
139 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 139 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
140 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 140 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
141 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 141 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
142 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 142 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -187,7 +187,7 @@ nve0_identify(struct nouveau_device *device)
187 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 187 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
189 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; 189 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
190 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 190 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
191 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 191 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
192 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 192 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
193 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 193 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -220,7 +220,7 @@ nve0_identify(struct nouveau_device *device)
220 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 220 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
221 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 221 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
222 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; 222 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
223 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 223 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
224 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 224 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
225 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 225 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
226 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 226 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@@ -253,7 +253,7 @@ nve0_identify(struct nouveau_device *device)
253 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 253 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
254 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 254 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
255 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; 255 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
256 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; 256 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
257 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; 257 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
258 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 258 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
259 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 259 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h
index aa62b637c389..8743766454a5 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/device.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/device.h
@@ -29,7 +29,7 @@ enum nv_subdev_type {
29 NVDEV_SUBDEV_BUS, 29 NVDEV_SUBDEV_BUS,
30 NVDEV_SUBDEV_TIMER, 30 NVDEV_SUBDEV_TIMER,
31 NVDEV_SUBDEV_FB, 31 NVDEV_SUBDEV_FB,
32 NVDEV_SUBDEV_LTCG, 32 NVDEV_SUBDEV_LTC,
33 NVDEV_SUBDEV_IBUS, 33 NVDEV_SUBDEV_IBUS,
34 NVDEV_SUBDEV_INSTMEM, 34 NVDEV_SUBDEV_INSTMEM,
35 NVDEV_SUBDEV_VM, 35 NVDEV_SUBDEV_VM,
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h b/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h
new file mode 100644
index 000000000000..de9ac0325c6e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h
@@ -0,0 +1,28 @@
1#ifndef __NOUVEAU_LTC_H__
2#define __NOUVEAU_LTC_H__
3
4#include <core/subdev.h>
5#include <core/device.h>
6
7struct nouveau_mm_node;
8
9struct nouveau_ltc {
10 struct nouveau_subdev base;
11
12 int (*tags_alloc)(struct nouveau_ltc *, u32 count,
13 struct nouveau_mm_node **);
14 void (*tags_free)(struct nouveau_ltc *, struct nouveau_mm_node **);
15 void (*tags_clear)(struct nouveau_ltc *, u32 first, u32 count);
16};
17
18static inline struct nouveau_ltc *
19nouveau_ltc(void *obj)
20{
21 return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_LTC];
22}
23
24extern struct nouveau_oclass *gf100_ltc_oclass;
25extern struct nouveau_oclass *gk104_ltc_oclass;
26extern struct nouveau_oclass *gm107_ltc_oclass;
27
28#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h b/drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h
deleted file mode 100644
index c9c1950b7743..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h
+++ /dev/null
@@ -1,41 +0,0 @@
1#ifndef __NOUVEAU_LTCG_H__
2#define __NOUVEAU_LTCG_H__
3
4#include <core/subdev.h>
5#include <core/device.h>
6
7struct nouveau_mm_node;
8
9struct nouveau_ltcg {
10 struct nouveau_subdev base;
11
12 int (*tags_alloc)(struct nouveau_ltcg *, u32 count,
13 struct nouveau_mm_node **);
14 void (*tags_free)(struct nouveau_ltcg *, struct nouveau_mm_node **);
15 void (*tags_clear)(struct nouveau_ltcg *, u32 first, u32 count);
16};
17
18static inline struct nouveau_ltcg *
19nouveau_ltcg(void *obj)
20{
21 return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_LTCG];
22}
23
24#define nouveau_ltcg_create(p,e,o,d) \
25 nouveau_subdev_create_((p), (e), (o), 0, "PLTCG", "level2", \
26 sizeof(**d), (void **)d)
27#define nouveau_ltcg_destroy(p) \
28 nouveau_subdev_destroy(&(p)->base)
29#define nouveau_ltcg_init(p) \
30 nouveau_subdev_init(&(p)->base)
31#define nouveau_ltcg_fini(p,s) \
32 nouveau_subdev_fini(&(p)->base, (s))
33
34#define _nouveau_ltcg_dtor _nouveau_subdev_dtor
35#define _nouveau_ltcg_init _nouveau_subdev_init
36#define _nouveau_ltcg_fini _nouveau_subdev_fini
37
38extern struct nouveau_oclass *gf100_ltcg_oclass;
39extern struct nouveau_oclass *gm107_ltcg_oclass;
40
41#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
index 5a6a5027f749..946518572346 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
@@ -26,7 +26,7 @@
26#include <subdev/bios/pll.h> 26#include <subdev/bios/pll.h>
27#include <subdev/bios/rammap.h> 27#include <subdev/bios/rammap.h>
28#include <subdev/bios/timing.h> 28#include <subdev/bios/timing.h>
29#include <subdev/ltcg.h> 29#include <subdev/ltc.h>
30 30
31#include <subdev/clock.h> 31#include <subdev/clock.h>
32#include <subdev/clock/pll.h> 32#include <subdev/clock/pll.h>
@@ -425,7 +425,7 @@ extern const u8 nvc0_pte_storage_type_map[256];
425void 425void
426nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) 426nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
427{ 427{
428 struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb); 428 struct nouveau_ltc *ltc = nouveau_ltc(pfb);
429 struct nouveau_mem *mem = *pmem; 429 struct nouveau_mem *mem = *pmem;
430 430
431 *pmem = NULL; 431 *pmem = NULL;
@@ -434,7 +434,7 @@ nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
434 434
435 mutex_lock(&pfb->base.mutex); 435 mutex_lock(&pfb->base.mutex);
436 if (mem->tag) 436 if (mem->tag)
437 ltcg->tags_free(ltcg, &mem->tag); 437 ltc->tags_free(ltc, &mem->tag);
438 __nv50_ram_put(pfb, mem); 438 __nv50_ram_put(pfb, mem);
439 mutex_unlock(&pfb->base.mutex); 439 mutex_unlock(&pfb->base.mutex);
440 440
@@ -468,12 +468,12 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
468 468
469 mutex_lock(&pfb->base.mutex); 469 mutex_lock(&pfb->base.mutex);
470 if (comp) { 470 if (comp) {
471 struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb); 471 struct nouveau_ltc *ltc = nouveau_ltc(pfb);
472 472
473 /* compression only works with lpages */ 473 /* compression only works with lpages */
474 if (align == (1 << (17 - 12))) { 474 if (align == (1 << (17 - 12))) {
475 int n = size >> 5; 475 int n = size >> 5;
476 ltcg->tags_alloc(ltcg, n, &mem->tag); 476 ltc->tags_alloc(ltc, n, &mem->tag);
477 } 477 }
478 478
479 if (unlikely(!mem->tag)) 479 if (unlikely(!mem->tag))
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c
new file mode 100644
index 000000000000..c99bf3f7352f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c
@@ -0,0 +1,80 @@
1/*
2 * Copyright 2014 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "priv.h"
26
27static int
28nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n,
29 struct nouveau_mm_node **pnode)
30{
31 struct nvkm_ltc_priv *priv = (void *)ltc;
32 int ret;
33
34 ret = nouveau_mm_head(&priv->tags, 1, n, n, 1, pnode);
35 if (ret)
36 *pnode = NULL;
37
38 return ret;
39}
40
41static void
42nvkm_ltc_tags_free(struct nouveau_ltc *ltc, struct nouveau_mm_node **pnode)
43{
44 struct nvkm_ltc_priv *priv = (void *)ltc;
45 nouveau_mm_free(&priv->tags, pnode);
46}
47
48static void
49nvkm_ltc_tags_clear(struct nouveau_ltc *ltc, u32 first, u32 count)
50{
51 const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
52 struct nvkm_ltc_priv *priv = (void *)ltc;
53 const u32 limit = first + count - 1;
54
55 BUG_ON((first > limit) || (limit >= priv->num_tags));
56
57 impl->cbc_clear(priv, first, limit);
58 impl->cbc_wait(priv);
59}
60
61int
62nvkm_ltc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
63 struct nouveau_oclass *oclass, int length, void **pobject)
64{
65 const struct nvkm_ltc_impl *impl = (void *)oclass;
66 struct nvkm_ltc_priv *priv;
67 int ret;
68
69 ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PLTCG",
70 "l2c", length, pobject);
71 priv = *pobject;
72 if (ret)
73 return ret;
74
75 priv->base.base.intr = impl->intr;
76 priv->base.tags_alloc = nvkm_ltc_tags_alloc;
77 priv->base.tags_free = nvkm_ltc_tags_free;
78 priv->base.tags_clear = nvkm_ltc_tags_clear;
79 return 0;
80}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
index f2f3338a967a..f72ab8191d9d 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
@@ -25,10 +25,28 @@
25#include <subdev/fb.h> 25#include <subdev/fb.h>
26#include <subdev/timer.h> 26#include <subdev/timer.h>
27 27
28#include "gf100.h" 28#include "priv.h"
29
30void
31gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
32{
33 nv_wr32(priv, 0x17e8cc, start);
34 nv_wr32(priv, 0x17e8d0, limit);
35 nv_wr32(priv, 0x17e8c8, 0x00000004);
36}
37
38void
39gf100_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
40{
41 int c, s;
42 for (c = 0; c < priv->ltc_nr; c++) {
43 for (s = 0; s < priv->lts_nr; s++)
44 nv_wait(priv, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0);
45 }
46}
29 47
30static void 48static void
31gf100_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts) 49gf100_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
32{ 50{
33 u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400); 51 u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400);
34 u32 stat = nv_rd32(priv, base + 0x020); 52 u32 stat = nv_rd32(priv, base + 0x020);
@@ -39,17 +57,17 @@ gf100_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts)
39 } 57 }
40} 58}
41 59
42static void 60void
43gf100_ltcg_intr(struct nouveau_subdev *subdev) 61gf100_ltc_intr(struct nouveau_subdev *subdev)
44{ 62{
45 struct gf100_ltcg_priv *priv = (void *)subdev; 63 struct nvkm_ltc_priv *priv = (void *)subdev;
46 u32 mask; 64 u32 mask;
47 65
48 mask = nv_rd32(priv, 0x00017c); 66 mask = nv_rd32(priv, 0x00017c);
49 while (mask) { 67 while (mask) {
50 u32 lts, ltc = __ffs(mask); 68 u32 lts, ltc = __ffs(mask);
51 for (lts = 0; lts < priv->lts_nr; lts++) 69 for (lts = 0; lts < priv->lts_nr; lts++)
52 gf100_ltcg_lts_isr(priv, ltc, lts); 70 gf100_ltc_lts_isr(priv, ltc, lts);
53 mask &= ~(1 << ltc); 71 mask &= ~(1 << ltc);
54 } 72 }
55 73
@@ -59,52 +77,38 @@ gf100_ltcg_intr(struct nouveau_subdev *subdev)
59 nv_mask(priv, 0x000640, 0x02000000, 0x00000000); 77 nv_mask(priv, 0x000640, 0x02000000, 0x00000000);
60} 78}
61 79
62int 80static int
63gf100_ltcg_tags_alloc(struct nouveau_ltcg *ltcg, u32 n, 81gf100_ltc_init(struct nouveau_object *object)
64 struct nouveau_mm_node **pnode)
65{ 82{
66 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; 83 struct nvkm_ltc_priv *priv = (void *)object;
67 int ret; 84 int ret;
68 85
69 ret = nouveau_mm_head(&priv->tags, 1, n, n, 1, pnode); 86 ret = nvkm_ltc_init(priv);
70 if (ret) 87 if (ret)
71 *pnode = NULL; 88 return ret;
72 89
73 return ret; 90 nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
91 nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
92 nv_wr32(priv, 0x17e8d4, priv->tag_base);
93 return 0;
74} 94}
75 95
76void 96void
77gf100_ltcg_tags_free(struct nouveau_ltcg *ltcg, struct nouveau_mm_node **pnode) 97gf100_ltc_dtor(struct nouveau_object *object)
78{ 98{
79 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; 99 struct nouveau_fb *pfb = nouveau_fb(object);
80 100 struct nvkm_ltc_priv *priv = (void *)object;
81 nouveau_mm_free(&priv->tags, pnode);
82}
83 101
84static void 102 nouveau_mm_fini(&priv->tags);
85gf100_ltcg_tags_clear(struct nouveau_ltcg *ltcg, u32 first, u32 count) 103 nouveau_mm_free(&pfb->vram, &priv->tag_ram);
86{
87 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
88 u32 last = first + count - 1;
89 int p, i;
90
91 BUG_ON((first > last) || (last >= priv->num_tags));
92
93 nv_wr32(priv, 0x17e8cc, first);
94 nv_wr32(priv, 0x17e8d0, last);
95 nv_wr32(priv, 0x17e8c8, 0x4); /* trigger clear */
96 104
97 /* wait until it's finished with clearing */ 105 nvkm_ltc_destroy(priv);
98 for (p = 0; p < priv->ltc_nr; ++p) {
99 for (i = 0; i < priv->lts_nr; ++i)
100 nv_wait(priv, 0x1410c8 + p * 0x2000 + i * 0x400, ~0, 0);
101 }
102} 106}
103 107
104/* TODO: Figure out tag memory details and drop the over-cautious allocation. 108/* TODO: Figure out tag memory details and drop the over-cautious allocation.
105 */ 109 */
106int 110int
107gf100_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct gf100_ltcg_priv *priv) 111gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv)
108{ 112{
109 u32 tag_size, tag_margin, tag_align; 113 u32 tag_size, tag_margin, tag_align;
110 int ret; 114 int ret;
@@ -142,22 +146,22 @@ gf100_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct gf100_ltcg_priv *priv)
142 146
143 priv->tag_base = tag_base; 147 priv->tag_base = tag_base;
144 } 148 }
145 ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
146 149
150 ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
147 return ret; 151 return ret;
148} 152}
149 153
150static int 154int
151gf100_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 155gf100_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
152 struct nouveau_oclass *oclass, void *data, u32 size, 156 struct nouveau_oclass *oclass, void *data, u32 size,
153 struct nouveau_object **pobject) 157 struct nouveau_object **pobject)
154{ 158{
155 struct gf100_ltcg_priv *priv;
156 struct nouveau_fb *pfb = nouveau_fb(parent); 159 struct nouveau_fb *pfb = nouveau_fb(parent);
160 struct nvkm_ltc_priv *priv;
157 u32 parts, mask; 161 u32 parts, mask;
158 int ret, i; 162 int ret, i;
159 163
160 ret = nouveau_ltcg_create(parent, engine, oclass, &priv); 164 ret = nvkm_ltc_create(parent, engine, oclass, &priv);
161 *pobject = nv_object(priv); 165 *pobject = nv_object(priv);
162 if (ret) 166 if (ret)
163 return ret; 167 return ret;
@@ -170,57 +174,24 @@ gf100_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
170 } 174 }
171 priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28; 175 priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28;
172 176
173 ret = gf100_ltcg_init_tag_ram(pfb, priv); 177 ret = gf100_ltc_init_tag_ram(pfb, priv);
174 if (ret) 178 if (ret)
175 return ret; 179 return ret;
176 180
177 priv->base.tags_alloc = gf100_ltcg_tags_alloc; 181 nv_subdev(priv)->intr = gf100_ltc_intr;
178 priv->base.tags_free = gf100_ltcg_tags_free;
179 priv->base.tags_clear = gf100_ltcg_tags_clear;
180
181 nv_subdev(priv)->intr = gf100_ltcg_intr;
182 return 0;
183}
184
185void
186gf100_ltcg_dtor(struct nouveau_object *object)
187{
188 struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
189 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
190 struct nouveau_fb *pfb = nouveau_fb(ltcg->base.base.parent);
191
192 nouveau_mm_fini(&priv->tags);
193 nouveau_mm_free(&pfb->vram, &priv->tag_ram);
194
195 nouveau_ltcg_destroy(ltcg);
196}
197
198static int
199gf100_ltcg_init(struct nouveau_object *object)
200{
201 struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
202 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
203 int ret;
204
205 ret = nouveau_ltcg_init(ltcg);
206 if (ret)
207 return ret;
208
209 nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
210 nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
211 if (nv_device(ltcg)->card_type >= NV_E0)
212 nv_wr32(priv, 0x17e000, priv->ltc_nr);
213 nv_wr32(priv, 0x17e8d4, priv->tag_base);
214 return 0; 182 return 0;
215} 183}
216 184
217struct nouveau_oclass * 185struct nouveau_oclass *
218gf100_ltcg_oclass = &(struct nouveau_oclass) { 186gf100_ltc_oclass = &(struct nvkm_ltc_impl) {
219 .handle = NV_SUBDEV(LTCG, 0xc0), 187 .base.handle = NV_SUBDEV(LTC, 0xc0),
220 .ofuncs = &(struct nouveau_ofuncs) { 188 .base.ofuncs = &(struct nouveau_ofuncs) {
221 .ctor = gf100_ltcg_ctor, 189 .ctor = gf100_ltc_ctor,
222 .dtor = gf100_ltcg_dtor, 190 .dtor = gf100_ltc_dtor,
223 .init = gf100_ltcg_init, 191 .init = gf100_ltc_init,
224 .fini = _nouveau_ltcg_fini, 192 .fini = _nvkm_ltc_fini,
225 }, 193 },
226}; 194 .intr = gf100_ltc_intr,
195 .cbc_clear = gf100_ltc_cbc_clear,
196 .cbc_wait = gf100_ltc_cbc_wait,
197}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c
new file mode 100644
index 000000000000..063caf791800
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "priv.h"
26
27static int
28gk104_ltc_init(struct nouveau_object *object)
29{
30 struct nvkm_ltc_priv *priv = (void *)object;
31 int ret;
32
33 ret = nvkm_ltc_init(priv);
34 if (ret)
35 return ret;
36
37 nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
38 nv_wr32(priv, 0x17e000, priv->ltc_nr);
39 nv_wr32(priv, 0x17e8d4, priv->tag_base);
40 return 0;
41}
42
43struct nouveau_oclass *
44gk104_ltc_oclass = &(struct nvkm_ltc_impl) {
45 .base.handle = NV_SUBDEV(LTC, 0xe4),
46 .base.ofuncs = &(struct nouveau_ofuncs) {
47 .ctor = gf100_ltc_ctor,
48 .dtor = gf100_ltc_dtor,
49 .init = gk104_ltc_init,
50 .fini = _nvkm_ltc_fini,
51 },
52 .intr = gf100_ltc_intr,
53 .cbc_clear = gf100_ltc_cbc_clear,
54 .cbc_wait = gf100_ltc_cbc_wait,
55}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
index e79d0e81de40..c05333ebaff2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gm107.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
@@ -25,10 +25,28 @@
25#include <subdev/fb.h> 25#include <subdev/fb.h>
26#include <subdev/timer.h> 26#include <subdev/timer.h>
27 27
28#include "gf100.h" 28#include "priv.h"
29 29
30static void 30static void
31gm107_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts) 31gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
32{
33 nv_wr32(priv, 0x17e270, start);
34 nv_wr32(priv, 0x17e274, limit);
35 nv_wr32(priv, 0x17e26c, 0x00000004);
36}
37
38static void
39gm107_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
40{
41 int c, s;
42 for (c = 0; c < priv->ltc_nr; c++) {
43 for (s = 0; s < priv->lts_nr; s++)
44 nv_wait(priv, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0);
45 }
46}
47
48static void
49gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
32{ 50{
33 u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400); 51 u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400);
34 u32 stat = nv_rd32(priv, base + 0x00c); 52 u32 stat = nv_rd32(priv, base + 0x00c);
@@ -40,16 +58,16 @@ gm107_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts)
40} 58}
41 59
42static void 60static void
43gm107_ltcg_intr(struct nouveau_subdev *subdev) 61gm107_ltc_intr(struct nouveau_subdev *subdev)
44{ 62{
45 struct gf100_ltcg_priv *priv = (void *)subdev; 63 struct nvkm_ltc_priv *priv = (void *)subdev;
46 u32 mask; 64 u32 mask;
47 65
48 mask = nv_rd32(priv, 0x00017c); 66 mask = nv_rd32(priv, 0x00017c);
49 while (mask) { 67 while (mask) {
50 u32 lts, ltc = __ffs(mask); 68 u32 lts, ltc = __ffs(mask);
51 for (lts = 0; lts < priv->lts_nr; lts++) 69 for (lts = 0; lts < priv->lts_nr; lts++)
52 gm107_ltcg_lts_isr(priv, ltc, lts); 70 gm107_ltc_lts_isr(priv, ltc, lts);
53 mask &= ~(1 << ltc); 71 mask &= ~(1 << ltc);
54 } 72 }
55 73
@@ -59,37 +77,32 @@ gm107_ltcg_intr(struct nouveau_subdev *subdev)
59 nv_mask(priv, 0x000640, 0x02000000, 0x00000000); 77 nv_mask(priv, 0x000640, 0x02000000, 0x00000000);
60} 78}
61 79
62static void 80static int
63gm107_ltcg_tags_clear(struct nouveau_ltcg *ltcg, u32 first, u32 count) 81gm107_ltc_init(struct nouveau_object *object)
64{ 82{
65 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg; 83 struct nvkm_ltc_priv *priv = (void *)object;
66 u32 last = first + count - 1; 84 int ret;
67 int p, i;
68
69 BUG_ON((first > last) || (last >= priv->num_tags));
70 85
71 nv_wr32(priv, 0x17e270, first); 86 ret = nvkm_ltc_init(priv);
72 nv_wr32(priv, 0x17e274, last); 87 if (ret)
73 nv_wr32(priv, 0x17e26c, 0x4); /* trigger clear */ 88 return ret;
74 89
75 /* wait until it's finished with clearing */ 90 nv_wr32(priv, 0x17e27c, priv->ltc_nr);
76 for (p = 0; p < priv->ltc_nr; ++p) { 91 nv_wr32(priv, 0x17e278, priv->tag_base);
77 for (i = 0; i < priv->lts_nr; ++i) 92 return 0;
78 nv_wait(priv, 0x14046c + p * 0x2000 + i * 0x200, ~0, 0);
79 }
80} 93}
81 94
82static int 95static int
83gm107_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 96gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
84 struct nouveau_oclass *oclass, void *data, u32 size, 97 struct nouveau_oclass *oclass, void *data, u32 size,
85 struct nouveau_object **pobject) 98 struct nouveau_object **pobject)
86{ 99{
87 struct gf100_ltcg_priv *priv;
88 struct nouveau_fb *pfb = nouveau_fb(parent); 100 struct nouveau_fb *pfb = nouveau_fb(parent);
101 struct nvkm_ltc_priv *priv;
89 u32 parts, mask; 102 u32 parts, mask;
90 int ret, i; 103 int ret, i;
91 104
92 ret = nouveau_ltcg_create(parent, engine, oclass, &priv); 105 ret = nvkm_ltc_create(parent, engine, oclass, &priv);
93 *pobject = nv_object(priv); 106 *pobject = nv_object(priv);
94 if (ret) 107 if (ret)
95 return ret; 108 return ret;
@@ -102,41 +115,23 @@ gm107_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
102 } 115 }
103 priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28; 116 priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28;
104 117
105 ret = gf100_ltcg_init_tag_ram(pfb, priv); 118 ret = gf100_ltc_init_tag_ram(pfb, priv);
106 if (ret)
107 return ret;
108
109 priv->base.tags_alloc = gf100_ltcg_tags_alloc;
110 priv->base.tags_free = gf100_ltcg_tags_free;
111 priv->base.tags_clear = gm107_ltcg_tags_clear;
112
113 nv_subdev(priv)->intr = gm107_ltcg_intr;
114 return 0;
115}
116
117static int
118gm107_ltcg_init(struct nouveau_object *object)
119{
120 struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
121 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
122 int ret;
123
124 ret = nouveau_ltcg_init(ltcg);
125 if (ret) 119 if (ret)
126 return ret; 120 return ret;
127 121
128 nv_wr32(priv, 0x17e27c, priv->ltc_nr);
129 nv_wr32(priv, 0x17e278, priv->tag_base);
130 return 0; 122 return 0;
131} 123}
132 124
133struct nouveau_oclass * 125struct nouveau_oclass *
134gm107_ltcg_oclass = &(struct nouveau_oclass) { 126gm107_ltc_oclass = &(struct nvkm_ltc_impl) {
135 .handle = NV_SUBDEV(LTCG, 0xff), 127 .base.handle = NV_SUBDEV(LTC, 0xff),
136 .ofuncs = &(struct nouveau_ofuncs) { 128 .base.ofuncs = &(struct nouveau_ofuncs) {
137 .ctor = gm107_ltcg_ctor, 129 .ctor = gm107_ltc_ctor,
138 .dtor = gf100_ltcg_dtor, 130 .dtor = gf100_ltc_dtor,
139 .init = gm107_ltcg_init, 131 .init = gm107_ltc_init,
140 .fini = _nouveau_ltcg_fini, 132 .fini = _nvkm_ltc_fini,
141 }, 133 },
142}; 134 .intr = gm107_ltc_intr,
135 .cbc_clear = gm107_ltc_cbc_clear,
136 .cbc_wait = gm107_ltc_cbc_wait,
137}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h
new file mode 100644
index 000000000000..96d12a220400
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h
@@ -0,0 +1,58 @@
1#ifndef __NVKM_LTC_PRIV_H__
2#define __NVKM_LTC_PRIV_H__
3
4#include <subdev/ltc.h>
5#include <subdev/fb.h>
6
7struct nvkm_ltc_priv {
8 struct nouveau_ltc base;
9 u32 ltc_nr;
10 u32 lts_nr;
11 u32 num_tags;
12 u32 tag_base;
13 struct nouveau_mm tags;
14 struct nouveau_mm_node *tag_ram;
15};
16
17#define nvkm_ltc_create(p,e,o,d) \
18 nvkm_ltc_create_((p), (e), (o), sizeof(**d), (void **)d)
19#define nvkm_ltc_destroy(p) ({ \
20 struct nvkm_ltc_priv *_priv = (p); \
21 _nvkm_ltc_dtor(nv_object(_priv)); \
22})
23#define nvkm_ltc_init(p) ({ \
24 struct nvkm_ltc_priv *_priv = (p); \
25 _nvkm_ltc_init(nv_object(_priv)); \
26})
27#define nvkm_ltc_fini(p,s) ({ \
28 struct nvkm_ltc_priv *_priv = (p); \
29 _nvkm_ltc_fini(nv_object(_priv), (s)); \
30})
31
32int nvkm_ltc_create_(struct nouveau_object *, struct nouveau_object *,
33 struct nouveau_oclass *, int, void **);
34
35#define _nvkm_ltc_dtor _nouveau_subdev_dtor
36#define _nvkm_ltc_init _nouveau_subdev_init
37#define _nvkm_ltc_fini _nouveau_subdev_fini
38
39int gf100_ltc_ctor(struct nouveau_object *, struct nouveau_object *,
40 struct nouveau_oclass *, void *, u32,
41 struct nouveau_object **);
42void gf100_ltc_dtor(struct nouveau_object *);
43int gf100_ltc_init_tag_ram(struct nouveau_fb *, struct nvkm_ltc_priv *);
44int gf100_ltc_tags_alloc(struct nouveau_ltc *, u32, struct nouveau_mm_node **);
45void gf100_ltc_tags_free(struct nouveau_ltc *, struct nouveau_mm_node **);
46
47struct nvkm_ltc_impl {
48 struct nouveau_oclass base;
49 void (*intr)(struct nouveau_subdev *);
50 void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit);
51 void (*cbc_wait)(struct nvkm_ltc_priv *);
52};
53
54void gf100_ltc_intr(struct nouveau_subdev *);
55void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32);
56void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *);
57
58#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.h b/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.h
deleted file mode 100644
index 87b10b8412ea..000000000000
--- a/drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef __NVKM_LTCG_PRIV_GF100_H__
2#define __NVKM_LTCG_PRIV_GF100_H__
3
4#include <subdev/ltcg.h>
5
6struct gf100_ltcg_priv {
7 struct nouveau_ltcg base;
8 u32 ltc_nr;
9 u32 lts_nr;
10 u32 num_tags;
11 u32 tag_base;
12 struct nouveau_mm tags;
13 struct nouveau_mm_node *tag_ram;
14};
15
16void gf100_ltcg_dtor(struct nouveau_object *);
17int gf100_ltcg_init_tag_ram(struct nouveau_fb *, struct gf100_ltcg_priv *);
18int gf100_ltcg_tags_alloc(struct nouveau_ltcg *, u32, struct nouveau_mm_node **);
19void gf100_ltcg_tags_free(struct nouveau_ltcg *, struct nouveau_mm_node **);
20
21#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
index 2b4af9610ee9..15d41dc176ff 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
@@ -41,7 +41,7 @@ nvc0_mc_intr[] = {
41 { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ 41 { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
42 { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ 42 { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
43 { 0x01000000, NVDEV_SUBDEV_PWR }, 43 { 0x01000000, NVDEV_SUBDEV_PWR },
44 { 0x02000000, NVDEV_SUBDEV_LTCG }, 44 { 0x02000000, NVDEV_SUBDEV_LTC },
45 { 0x08000000, NVDEV_SUBDEV_FB }, 45 { 0x08000000, NVDEV_SUBDEV_FB },
46 { 0x10000000, NVDEV_SUBDEV_BUS }, 46 { 0x10000000, NVDEV_SUBDEV_BUS },
47 { 0x40000000, NVDEV_SUBDEV_IBUS }, 47 { 0x40000000, NVDEV_SUBDEV_IBUS },
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
index 668cf964e4a9..2d0988755530 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
@@ -28,7 +28,7 @@
28#include <subdev/timer.h> 28#include <subdev/timer.h>
29#include <subdev/fb.h> 29#include <subdev/fb.h>
30#include <subdev/vm.h> 30#include <subdev/vm.h>
31#include <subdev/ltcg.h> 31#include <subdev/ltc.h>
32#include <subdev/bar.h> 32#include <subdev/bar.h>
33 33
34struct nvc0_vmmgr_priv { 34struct nvc0_vmmgr_priv {
@@ -116,12 +116,12 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
116 pte <<= 3; 116 pte <<= 3;
117 117
118 if (mem->tag) { 118 if (mem->tag) {
119 struct nouveau_ltcg *ltcg = 119 struct nouveau_ltc *ltc =
120 nouveau_ltcg(vma->vm->vmm->base.base.parent); 120 nouveau_ltc(vma->vm->vmm->base.base.parent);
121 u32 tag = mem->tag->offset + (delta >> 17); 121 u32 tag = mem->tag->offset + (delta >> 17);
122 phys |= (u64)tag << (32 + 12); 122 phys |= (u64)tag << (32 + 12);
123 next |= (u64)1 << (32 + 12); 123 next |= (u64)1 << (32 + 12);
124 ltcg->tags_clear(ltcg, tag, cnt); 124 ltc->tags_clear(ltc, tag, cnt);
125 } 125 }
126 126
127 while (cnt--) { 127 while (cnt--) {