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authorGustavo A. R. Silva <garsilva@embeddedor.com>2017-05-09 11:22:21 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2017-05-10 04:09:31 -0400
commit94d7fb4982d2145c5784e33fa973ffb9ebb086ac (patch)
tree473f073151ce9440bfb70583326bba410bc4ed53
parentda98d2e13b9566ddc1e84e418ab6a86155138d9b (diff)
gpu: drm: gma500: remove dead code
Local variable use_gct is assigned to a constant value and it is never updated again. Remove this variable and the dead code it guards. Addresses-Coverity-ID: 145690 Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170509152221.GA7618@embeddedgus
-rw-r--r--drivers/gpu/drm/gma500/mdfld_tpo_vid.c51
1 files changed, 9 insertions, 42 deletions
diff --git a/drivers/gpu/drm/gma500/mdfld_tpo_vid.c b/drivers/gpu/drm/gma500/mdfld_tpo_vid.c
index d8d4170725b2..d40628e6810d 100644
--- a/drivers/gpu/drm/gma500/mdfld_tpo_vid.c
+++ b/drivers/gpu/drm/gma500/mdfld_tpo_vid.c
@@ -32,53 +32,20 @@ static struct drm_display_mode *tpo_vid_get_config_mode(struct drm_device *dev)
32 struct drm_display_mode *mode; 32 struct drm_display_mode *mode;
33 struct drm_psb_private *dev_priv = dev->dev_private; 33 struct drm_psb_private *dev_priv = dev->dev_private;
34 struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD; 34 struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
35 bool use_gct = false;
36 35
37 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 36 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
38 if (!mode) 37 if (!mode)
39 return NULL; 38 return NULL;
40 39
41 if (use_gct) { 40 mode->hdisplay = 864;
42 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo; 41 mode->vdisplay = 480;
43 mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo; 42 mode->hsync_start = 873;
44 mode->hsync_start = mode->hdisplay + 43 mode->hsync_end = 876;
45 ((ti->hsync_offset_hi << 8) | 44 mode->htotal = 887;
46 ti->hsync_offset_lo); 45 mode->vsync_start = 487;
47 mode->hsync_end = mode->hsync_start + 46 mode->vsync_end = 490;
48 ((ti->hsync_pulse_width_hi << 8) | 47 mode->vtotal = 499;
49 ti->hsync_pulse_width_lo); 48 mode->clock = 33264;
50 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) |
51 ti->hblank_lo);
52 mode->vsync_start =
53 mode->vdisplay + ((ti->vsync_offset_hi << 8) |
54 ti->vsync_offset_lo);
55 mode->vsync_end =
56 mode->vsync_start + ((ti->vsync_pulse_width_hi << 8) |
57 ti->vsync_pulse_width_lo);
58 mode->vtotal = mode->vdisplay +
59 ((ti->vblank_hi << 8) | ti->vblank_lo);
60 mode->clock = ti->pixel_clock * 10;
61
62 dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay);
63 dev_dbg(dev->dev, "vdisplay is %d\n", mode->vdisplay);
64 dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start);
65 dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);
66 dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);
67 dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);
68 dev_dbg(dev->dev, "VSE is %d\n", mode->vsync_end);
69 dev_dbg(dev->dev, "vtotal is %d\n", mode->vtotal);
70 dev_dbg(dev->dev, "clock is %d\n", mode->clock);
71 } else {
72 mode->hdisplay = 864;
73 mode->vdisplay = 480;
74 mode->hsync_start = 873;
75 mode->hsync_end = 876;
76 mode->htotal = 887;
77 mode->vsync_start = 487;
78 mode->vsync_end = 490;
79 mode->vtotal = 499;
80 mode->clock = 33264;
81 }
82 49
83 drm_mode_set_name(mode); 50 drm_mode_set_name(mode);
84 drm_mode_set_crtcinfo(mode, 0); 51 drm_mode_set_crtcinfo(mode, 0);